JP6730892B2 - Power supply control device and isolated switching power supply device - Google Patents

Description

The present invention relates to a power supply control device.

Conventionally, various flyback type insulated switching power supply devices that convert an input DC voltage into a desired DC voltage have been developed. In this insulation type switching power supply device, an output voltage is obtained on the secondary side of the transformer by switching-driving a switching element connected in series to the primary winding of the transformer. When the switching element is turned on, the transformer is charged with exciting energy, and when the switching element is turned off, the exciting energy is discharged through the diode and the smoothing capacitor arranged on the secondary side of the transformer. An example of an insulating type switching power supply device is disclosed in Patent Document 1, for example.

In addition, as a control method of the switching power supply device, a linear control method (for example, a voltage mode control method, a current mode control method) or a non-linear control method (for example, a fixed on-time method, a fixed off-time method, a hysteresis method, etc.) has been conventionally used. (Window method) is adopted.

JP, 2012-125084, A

Here, in the above flyback type insulated switching power supply device, a predetermined minimum off time is set so that the off time for turning off the switching element is not too short, and the off time is set to the minimum off time. There is a limit that does not become shorter than the time.

Further, some of the flyback type insulated switching power supply devices as described above have a function (OCP) of detecting and protecting an overcurrent of the primary side current. In such an insulating type switching power supply device, when it is detected that the primary side current has reached the overcurrent protection level (OCP level), the switching element is forcibly turned off, and from there, the minimum off time is reached. After that, the switching element was controlled to be turned on again.

While the switching element is off, the generated secondary current decreases, but in the above control, the secondary current does not decrease so much because it is turned off for a short period of the minimum off time. The primary side current that starts to flow at the next turn-on becomes large, and as soon as the primary side current rises, the overcurrent protection level is reached, and the switching element is turned off again. Therefore, there is a problem that charging on the primary side performed by turning on the switching element becomes insufficient and the rise of the output voltage of the insulating switching power supply device is delayed.

In view of the above situation, an object of the present invention is to provide a power supply control device capable of speeding up an increase in output voltage during overcurrent protection.

In order to achieve the above object, one aspect of the present invention includes a transformer including a primary winding and a secondary winding, and a switching element,
A power supply control device used for a flyback type insulated switching power supply device in which an input voltage application terminal is connected to one end of the primary winding and the switching element is connected to the other end of the primary winding. hand,
An OCP section (overcurrent protection section) that detects an overcurrent of the primary side current;
An off controller for turning off the switching element when the overcurrent is detected;
A first timer for measuring a predetermined minimum off time at a timing delayed after being turned off by the off control unit;
An on-trigger signal generation unit that generates an on-trigger signal that turns on the switching element based on a feedback signal obtained by feeding back a flyback voltage,
An on-timing determining unit that determines a timing for turning on the switching element based on the measured minimum off-time and the on-trigger signal,
Is provided (first configuration).

In the first configuration, a second timer that starts measuring a predetermined percentage of the ON time at the same timing as the first timer,
The predetermined minimum off-time measured by the first timer, and a minimum off-time setting unit that compares the time measured by the second timer and sets the longer one as the minimum off-time,
The on-timing determining unit may determine a timing for turning on the switching element based on the set minimum off-time and the on-trigger signal (second configuration).

Moreover, in the said 2nd structure, the said predetermined ratio may be 20%-80% (3rd structure).

In addition, in the third configuration, the predetermined ratio may be 50% (fourth configuration).

In any of the above second to fourth configurations, the minimum off time setting unit may be an AND circuit (fifth configuration).

In any one of the first to fifth configurations, the on-timing determining unit may be an AND circuit (sixth configuration).

In any one of the first to sixth configurations, a third timer that measures an on-time,
A first latch circuit to which the output of the third timer is input;
An OR circuit to which the output of the OCP section and the output of the third timer are input,
A second latch circuit to which the output of the OR circuit is input,
The off control unit includes the OR circuit and the second latch circuit,
The second PWM signal output from the second latch circuit is input to a driver that drives the switching element,
The first PWM signal output from the first latch circuit is input to the first timer,
The output of the on-timing determining unit may be input to the first latch circuit and the second latch circuit (seventh configuration).

An insulated switching power supply device according to another aspect of the present invention includes the power supply control device having any one of the above configurations, a switching element, and a transformer.

According to the present invention, it is possible to speed up the rise of the output voltage during overcurrent protection.

1 is an overall configuration diagram of an insulated switching power supply device according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the power supply control IC which concerns on one Embodiment of this invention. It is a figure which shows one concrete example of a structure of a timer part and a logic part. It is a figure which shows one structural example of a filter. It is a figure which shows one structural example of an on-time timer. FIG. 6 is an example of a diagram showing how the secondary current decreases when the switching element is turned off. 7 is a timing chart showing an example of each PWM signal and each timer output at the time of a transient response in which the output voltage is reduced due to a load change. 7 is a timing chart showing an example of each waveform in a comparative example using only the minimum off-time timer. It is a timing chart in the embodiment of the present invention corresponding to Drawing 8A concerning a comparative example. 7 is a timing chart showing an example of an operation at the time of overcurrent protection in the insulated switching power supply device according to the comparative example. 6 is a timing chart showing an example of an operation during overcurrent protection in the insulated switching power supply device according to the embodiment of the present invention. It is a figure which shows the structure which controls the output timing of a difference circuit. It is a waveform example of the switching voltage when the switching element is turned off. It is a whole block diagram of the insulation type switching power supply device which concerns on the modification of this invention. 9 is a timing chart showing an example of each waveform when turning off a main switching element in an insulated switching power supply device according to a modification of the present invention.

<Overall structure of isolated switching power supply>
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an overall configuration of an insulated switching power supply device 10 according to an embodiment of the present invention. The isolated switching power supply device 10 is a flyback DC/DC converter that generates an output voltage Vout from an input voltage Vin. Further, the isolated switching power supply device 10 performs adaptive on-time control as described below as a control method.

The insulated switching power supply device 10 includes a power supply control IC 1 and various discrete components (transformer Tr1, diode D2, smoothing capacitor C2, resistor R11, and resistor R12) externally attached to the power supply control IC1.

The power supply control IC 1 (power supply control device) is a main body (semiconductor device) that integrally controls the overall operation of the isolated switching power supply device 10. The power supply control IC 1 has a power supply terminal T1, a feedback terminal T2, a switching output terminal T3, a ground terminal T4, and a REF terminal T5 in order to establish an electrical connection with the outside.

The input voltage Vin, which is a DC voltage, is applied to the power supply terminal T1 and also to one end of the primary winding L1 of the transformer Tr1. The other end of the primary winding L1 is connected to the feedback terminal T2 via an externally attached resistor R11 and also connected to the switching output terminal T3. One end of the secondary winding L2 of the transformer Tr1 is connected to the anode of the diode D2. A smoothing capacitor C2 is connected between the cathode of the diode D2 and the other end of the secondary winding L2. The output voltage Vout is generated at the connection point between one end of the capacitor C2 and the cathode of the diode D2. A ground potential application terminal is connected to the ground terminal T4. One end of an external resistor R12 is connected to the REF terminal T5.

FIG. 2 is a block diagram showing the internal configuration of the power supply control IC 1. The power supply control IC 1 includes a difference circuit 11, a comparator 13, a logic unit 14, a driver 15, a timer unit 16, a filter 17, a ripple generation unit 18, an OCP unit (overcurrent protection unit) 19, and switching. The device M1 is included, and these components are integrated into one chip.

The drain of the switching element M1 composed of an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is connected to one end of the primary winding L1 via a switching output terminal T3. The source of the switching element M1 is connected to the ground potential application terminal via the ground terminal T4.

When the switching element M1 is turned on, a current flows through the primary winding L1 of the transformer Tr1 and the transformer Tr1 is charged with excitation energy. At this time, the diode D2 is off. Next, when the switching element M1 is turned off, the charged excitation energy is discharged from the secondary winding L2 of the transformer Tr1 through the diode D2 and smoothed by the smoothing capacitor C2 to generate the output voltage Vout. At this time, a current flows through the diode D2.

When the switching element M1 is off, the flyback voltage VOR represented by the following equation (1) is generated in the primary winding L1.
VOR=Np/Ns×(Vout+Vf) (1)
However, Np: number of turns of the primary winding L1, Ns: number of turns of the secondary winding L2, Vf: forward voltage of the diode D2

At this time, the switching voltage Vsw which is the drain voltage of the switching element M1 is expressed by the following equation (2).
Vsw=Vin+VOR (2)

The difference circuit 11 includes a power supply terminal T1 to which an input voltage Vin is applied, a feedback terminal T2 connected to the other end of a resistor R11 to which a switching voltage Vsw is applied to one end, and a REF terminal connected to one end of a resistor R12. Connected to T5. As a result, the difference circuit 11 converts the difference between the switching voltage Vsw and the input voltage Vin into a voltage/current by the resistor R11, and the converted current and the resistor R12 generate the REF terminal voltage VTref at the REF terminal T5. That is, the REF terminal voltage VTref is generated as a feedback signal obtained by feeding back the flyback voltage VOR. The difference circuit 11 corresponds to a feedback signal output unit.

The difference circuit 11 performs an operation of directly outputting the REF terminal voltage VTref as the output VTref2 when the switching element M11 is off, and an operation of holding the output VTref2 at a certain timing. The difference circuit 11 outputs the output VTref2 to the comparator 13.

The comparator 13 compares the output VTref2 with the reference voltage Vref having a triangular wave shape generated by the ripple generator 18, and outputs the FET ON trigger signal Tgon as a comparison result to the logic unit 14. The comparator 13 corresponds to an on-trigger signal generator.

The logic unit 14 generates the first PWM signal pwm1 and the second PWM signal pwm2. The first PWM signal pwm1 and the second PWM signal pwm2 are pulse-shaped signals and basically have the same on-duty.

The filter 17 extracts the on-duty information by filtering the first PWM signal pwm1. The filter 17 corresponds to a duty information acquisition unit. The timer unit 16 and the logic unit 14 set an on-time, which is a period during which the switching element M1 is turned on, based on the on-duty information from the filter 17. The logic unit 14 sets the second PWM signal pwm2 to Low level in order to switch the switching element M1 from ON to OFF at a timing such that the set ON time is reached.

Further, the timer unit 16 and the logic unit 14 set the minimum off-time which is the minimum value of the off-time which is the period during which the switching element M1 is turned off, based on the on-duty information from the filter 17. The logic unit 14 sets the second PWM signal pwm2 to High level in order to switch the switching element M1 from OFF to ON at the set minimum OFF time and the timing based on the FET ON trigger signal Tgon from the comparator 13.

The driver 15 generates the gate voltage GT based on the second PWM signal pwm2 generated by the logic unit 14 and applies it to the gate of the switching element M1. As a result, the switching element M1 is on/off controlled.

Further, the timer unit 16 generates a switch timing signal SWT instructing on/off timing of a switch (not shown) included in the difference circuit 11 and outputs the switch timing signal SWT to the difference circuit 11. The differential circuit 11 outputs the REF terminal voltage Vtref as the output VTref2 as it is when the switch timing signal SWT indicates ON, and holds the output VTref2 at the timing of switching from ON to OFF when instructing OFF.

<On/off time setting control>
Next, the control for setting the ON time/OFF time by the power supply control IC 1 according to the present embodiment will be described. FIG. 3 is a diagram showing a specific configuration example of the timer unit 16 and the logic unit 14.

The timer unit 16 has a minimum off time timer 161, a 1/2 on time timer 162, a minimum on time timer 163, an on time timer 164, and an inverter 165. The logic unit 14 has a first latch circuit 141, a second latch circuit 142, AND circuits 143 to 145, and an OR circuit 146. The first latch circuit 141 outputs the first PWM signal pwm1. The second latch circuit 142 outputs the second PWM signal pwm2 to the driver 15.

The first latch circuit 141 and the second latch circuit 142 are simultaneously set by the signal input to the set terminal, and are basically reset by the signal input to the reset terminal (except when the OCP unit 19 detects an overcurrent). Therefore, the first PWM signal pwm1 and the second PWM signal pwm2 are synchronized and have the same on-duty.

When the first PWM signal pwm1 rises from Low to High by setting the first latch circuit 141, that is, when the switching element M1 is turned on by the second PWM signal pwm2, the output of the inverter 165 becomes Low. The minimum on-time timer 163 and the on-time timer 164 are reset.

When the minimum on-time timer 163 is reset, it starts measuring a predetermined minimum on-time (fixed value). Here, the predetermined minimum on-time is a parameter that determines the degree of over-boosting of the output voltage Vout. When reset, the on-time timer 164 starts measuring the on-time set by the filter output voltage V1 generated by the filter 17 based on the first PWM signal pwm1.

Here, FIG. 4 is a diagram illustrating a configuration example of the filter 17. The filter 17 has a resistor R17, a capacitor C17, and resistors R171 and R172 for voltage division. An input terminal T171 to which the first PWM signal pwm1 is applied is connected to one end of the resistor R17. The other end of the resistor R17 is connected to one end of the capacitor C17 and is also connected to the first output terminal T172 where the filter output voltage V1 is generated. The other end of the capacitor C17 is connected to the ground potential application end. That is, the resistor R17 and the capacitor C17 form a low-pass filter, and the signal after passing the first PWM signal pwm1 through the low-pass filter becomes the filter output voltage V1. Therefore, the filter output voltage V1 indicates the on-duty information of the first PWM signal pwm1.

In addition, FIG. 5 is a diagram illustrating a configuration example of the on-time timer 164. The on-time timer 164 is a so-called lamp counter having a constant current circuit Ic, a capacitor C164, and a comparator CP164. A constant current circuit Ic and a capacitor C164 are connected in series between the power supply voltage Vcc and the ground potential, and the connection point is connected to the non-inverting input terminal (+) of the comparator CP164. The filter output voltage V1 is applied to the inverting input terminal (−) of the comparator CP164. The output of the comparator CP164 becomes the output of the on-time timer 164.

When the on-time timer 164 is reset, the electric charge stored in the capacitor C164 is discharged. Then, the capacitor C164 is charged by the current controlled to be constant by the constant current circuit Ic. The time t until the voltage at the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 as the reference voltage by charging the capacitor C164 is expressed by the following equation (3).
t=C×V1/I (3)
However, C: capacitance of the capacitor C164, I: constant current value

The output of the comparator CP164 is Low at the time of reset, but when the voltage at the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 after the time t has passed, the output of the comparator C164 becomes High.

The minimum on-time timer 163 can be configured by a lamp counter similar to the configuration shown in FIG. At this time, the reference voltage of the comparator, the constant current value of the constant current circuit, and the capacitance of the capacitor are appropriately set so that the time t becomes a predetermined minimum on-time.

The output of the minimum on-time timer 163 and the output of the on-time timer 164 are input to the AND circuit 145. When the outputs of the minimum on-time timer 163 and the on-time timer 165 are both High by the AND circuit 145, the output of the AND circuit 145 is High. That is, the output of the AND circuit 145 becomes High at the timing when the longer one of the predetermined minimum ON time measured by the minimum ON time timer 163 and the ON time measured by the ON time timer 164 is measured. Therefore, when the ON time is shorter than the predetermined minimum ON time, the ON time is limited to the predetermined minimum ON time. The AND circuit 145 corresponds to the off-timing determining unit.

The output of the AND circuit 145 is input to the reset terminal of the first latch circuit 141 and the OR circuit 146. The output of the OCP section 19 is also input to the OR circuit 146. The output of the OR circuit 146 is input to the second latch circuit 142. Since the output of the OCP unit 19 becomes Low in the normal state when no overcurrent is detected, both the first latch circuit 141 and the second latch circuit 142 are reset at the timing when the output of the AND circuit 145 becomes High. The OR control circuit 146 and the second latch circuit 142 constitute an OFF control section.

As a result, both the first PWM signal pwm1 and the second PWM signal pwm2 are switched to the low level, the switching element M1 is turned off by the second PWM signal pwm2, and the on time is defined.

When the first PWM signal pwm1 becomes Low level, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset. The minimum off time timer 161 starts measuring a predetermined minimum off time (fixed value) when reset. When the switching element M1 is off, the difference circuit 11 outputs the REF terminal voltage VTref as it is or holds the output. However, since the switching voltage Vsw has ringing immediately after the switching element M1 is turned off, until the ringing becomes stable. It is necessary to secure the time of, and the above-mentioned predetermined minimum off time is defined.

The minimum off time timer can be configured by a lamp counter similar to the configuration shown in FIG. At this time, the reference voltage of the comparator, the constant current value of the constant current circuit, and the capacitance of the capacitor are appropriately set so that the time t becomes a predetermined minimum off time.

When the 1/2 ON time timer 162 is reset, it starts measuring 50% of the ON time. Here, when the switching element M1 is on, the primary-side current Ip flowing through the primary winding L1 rises, and when the switching element M1 is off, the secondary-side current Is flowing through the secondary winding L2. Has a peak value obtained by multiplying the peak value of the primary side current by the turns ratio. Then, the secondary current gradually decreases with the passage of time. FIG. 6 is an example of a diagram showing how the secondary side current Is decreases when the switching element M1 is turned off. As shown in FIG. 6, the secondary side current Is gradually decreases from the peak value Ispk at the time of turning off, and becomes zero when the discharge time toff2 has elapsed. In the discharge up to 50% (1/2 toff2) of the discharge time toff2, since the discharge amount increases by the discharge amount of the area S2 with respect to the average discharge amount (area S1), efficient discharge is possible. Become. On the contrary, if the discharge time toff2 exceeds 50%, the efficiency deteriorates.

Therefore, it suffices if the discharge time (that is, the off time) can be extended to 50% of the discharge time toff2, but it is difficult to estimate because the actual discharge time toff2 depends on the transformer Tr1 and the load condition. Therefore, in the present embodiment, the off time is extended to 50% of the on time as a standard similar to 50% of the discharge time toff2.

Specifically, in the configuration of the filter 17 shown in FIG. 4, the filter output voltage V1 is divided by the resistors R171 and R172 having the same resistance value and output as the filter output voltage V2 from the second output terminal T173. As a result, the filter output voltage V2 becomes 50% of the filter output voltage V1. Then, the 1/2 on-time timer 162 is configured similarly to the configuration of the lamp counter shown in FIG. 5, and the filter output voltage V2 is applied as the reference voltage of the comparator. As a result, the 1/2 on-time timer 162 sets the output to High at the time point when 50% of the on-time is measured after being reset and the output becomes Low.

The outputs of the minimum off-time timer 161 and the 1/2 on-time timer 162 are input to the AND circuit 144. The output of the AND circuit 144 is set to High when both the outputs of the minimum off-time timer 161 and the 1/2 ON-time timer 162 are both High. That is, the longer one of the predetermined minimum off time and 50% of the on time is selected and set as the minimum off time. The AND circuit 144 corresponds to the minimum off time setting unit.

Then, the FET on-trigger signal Tgon and the output of the AND circuit 144 are input to the AND circuit 143. As a result, when both the FET on-trigger signal Tgon and the output of the AND circuit 144 become High, the output of the AND circuit 143 becomes High. That is, if the timing at which the FET on-trigger signal Tgon becomes High is after the set minimum off-time has elapsed, that timing is selected, and the timing at which the set minimum off-time has elapsed is the FET on-trigger signal Tgon. If it is after the High timing, the timing at which the minimum off time has elapsed is selected. That is, the off time is limited so as not to be shorter than the minimum off time. The AND circuit 143 corresponds to an on-timing determining unit.

The output of the AND circuit 143 is input to each set terminal of the first latch circuit 141 and the second latch circuit 142. Therefore, at the timing when the output of the AND circuit 143 is set to High, both the first latch circuit 141 and the second latch circuit 142 are set, and the first PWM signal pwm1 and the second PWM signal pwm2 are both switched to High. As a result, the switching element M1 is turned on and the off time is defined.

When the output voltage Vout decreases due to the load change, the switching element M1 is turned on so that the set minimum off time is the off time. At this time, the on-duty of the first PWM signal pwm1 becomes large, and the on-time set by the filter output voltage V1 becomes long. In this way, by performing the adaptive on-time control in which the on-time is set by using the on-duty information of the first PWM signal pwm1, the response characteristic with respect to the load fluctuation can be improved.

Here, FIG. 7 is a timing chart showing an example of each PWM signal and each timer output at the time of a transient response in which the output voltage Vout is lowered due to a load change. Note that FIG. 7 also shows the outputs of the AND circuits 145 and 144 and the FET on-trigger signal Tgon. At timing t1, both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High, and the switching element M1 is turned on. Then, both the minimum on-time timer 163 and the on-time timer 164 are reset, and the output of each timer becomes Low.

Then, when the minimum on-time timer 163 measures a predetermined minimum on-time, the output of the minimum on-time timer 163 becomes High (timing t2). After that, when the on-time timer 164 measures the on-time, the output of the on-time timer 164 is set to High (timing 3). At this timing, the output of the AND circuit 145 becomes High, so that both the first latch circuit 141 and the second latch circuit 142 are reset, the first PWM signal pwm1 and the second PWM signal pwm2 are both Low, and the switching element M1 is off. It is said that

At this time, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset, and the output of each timer becomes Low. After that, when the predetermined minimum off time is measured by the minimum off time timer 161, the output of the minimum off time timer 161 is set to High (timing t4). After that, when the 1/2 ON time timer 162 measures 50% of the ON time, the output of the 1/2 ON time timer 162 becomes High (timing t5). Here, since the timing when the FET on-trigger signal Tgon becomes High is before the timing t5, the output of the AND circuit 143 becomes High at the timing t5. As a result, the first latch circuit 141 and the second latch circuit 142 are both set, the first PWM signal pwm1 and the second PWM signal pwm2 are both High, and the switching element M1 is turned on.

In this way, 50% of the ON time that is longer than the predetermined minimum OFF time is set as the minimum OFF time, so the discharge time can be secured more than when the predetermined minimum OFF time is set as the OFF time. The transient response can be speeded up. Note that the above-mentioned predetermined ratio of 50% is an example, and if it is set to a ratio of 20% to 80%, for example, a certain effect can be obtained.

In addition, here, comparison with an embodiment in which the minimum off-timer is used to set the minimum off-time will be described with reference to FIGS. 8A and 8B. FIG. 8A is a timing chart showing an example of each waveform in the embodiment for comparison using only the minimum off-time timer. In FIG. 8A, waveform examples of the PWM signal, the output of the minimum off-timer, the primary-side current Ip, and the secondary-side current Is are shown from the top.

FIG. 8A shows a case where the output voltage Vout is lowered due to load fluctuation after the timing t11 when the PWM signal becomes High and the switching element is turned on. While the switching element is on, the primary side current Ip increases. At the timing t12 when the PWM signal becomes Low and the switching element is turned off, the minimum off-time timer is reset to start measuring a predetermined minimum off-time. At the timing t12, the primary current Ip becomes zero, and the secondary current Is is generated according to the peak value of the primary current Ip, and then decreases.

The measurement of the minimum off-time is completed at the timing t13, and the output of the minimum off-timer becomes High. Here, since the FET on-trigger signal Tgon becomes High before the timing t13 due to the decrease in the output voltage Vout, the PWM signal is set to High at the timing t13 and the switching element is turned on. Here, the secondary side current Is becomes zero, and the primary side current Ip is generated according to the value of the secondary side current Is, and increases thereafter. Then, at timing t14, the PWM signal is set to Low and the switching element is turned off. At this time, the primary side current Ip becomes zero.

FIG. 8B is a timing chart in the present embodiment, which corresponds to FIG. 8A according to the comparative example. In FIG. 8B, from the top, the first PWM signal pwm1 (and the second PWM signal pwm2), the output of the minimum off-time timer 161, the output of the 1/2 on-time timer 162, the primary side current Ip, and the secondary side current Is. A waveform example is shown.

In FIG. 8B, at the timing t12′ when the first PWM signal pwm1 is set to Low and the switching element M1 is turned off, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset, and each timer starts time measurement. To do. Here, the primary side current Ip becomes zero and decreases after the secondary side current Is is generated. In FIG. 8B, after the timing t13' at which the minimum off-time timer 161 finishes measuring the predetermined minimum off-time, the 1/2 on-time timer 162 finishes measuring 50% of the on-time at timing t14'. Here, since the FET on-trigger signal Tgon becomes High before the timing t14' due to the decrease in the output voltage Vout, the first PWM signal pwm1 is set High at the timing t14' and the switching element M1 is turned on. Here, the secondary side current Is becomes zero, and the primary side current Ip is generated according to the value of the secondary side current Is, and increases thereafter. Then, at timing t15', the first PWM signal pwm1 is set to Low, and the switching element M1 is turned off. At this time, the primary side current Ip becomes zero.

In FIG. 8B, as compared with FIG. 8A, the off time is defined at the timing when 50% of the on time that is longer than the predetermined minimum off time is measured. Therefore, by ensuring the discharge time of the secondary side, the secondary side is secured. The current Is is reduced to a lower value. As a result, the value of the primary-side current Ip generated when the switching element M1 is turned on can be lowered, so that the amount of increase change from the peak value Ippk1 of the primary-side current to the peak value Ippk2 in FIG. It is possible to suppress the amount of increase change from the peak value Ippk1′ of the primary-side current to the peak value Ippk2′ in FIG. 8B.

Further, in FIG. 8B, it can be seen that variation in the switching cycle (switching frequency) can be suppressed as compared with FIG. 8A.

The time compared with the predetermined minimum off time is not limited to the time of the predetermined ratio (for example, 50%) which is the fixed value of the on time, and the predetermined ratio may be variably controlled according to the load situation.

<Operation during overcurrent protection>
Next, the operation of the insulated switching power supply device 10 according to this embodiment during overcurrent protection will be described with reference to FIGS. 9A and 9B.

FIG. 9A is a timing chart showing an example of an operation during overcurrent protection in an insulated switching power supply device according to a comparative example for comparison with the present embodiment. In FIG. 9A, at the timing t21 when the PWM signal becomes High and the switching element is turned on, the primary-side current Ip starts to flow and then rises. Then, at timing t22 when it is detected that an overcurrent has occurred in the primary-side current Ip and the primary-side current Ip has reached a predetermined OCP level, the PWM signal is set to Low and the switching element is turned off. At this time, the primary-side current Ip becomes zero and decreases after the secondary-side current Is is generated.

At the timing t22, the minimum off-timer is reset and starts measuring a predetermined minimum off-time. Then, when the minimum off-time measurement is completed at the timing t23, the PWM signal is set to High and the switching element is turned on. At this time, the secondary side current Is becomes zero and rises after the primary side current Ip starts flowing. Then, at timing t24 when it is detected that the primary current Ip has reached the OCP level, the PWM signal is set to Low and the switching element is turned off. At this time, the primary current Ip becomes zero and the secondary current Is starts to flow.

On the other hand, in the present embodiment, the timing chart shown in FIG. 9B is shown as an example of the operation during overcurrent protection. Here, as shown in FIG. 2, in the OCP unit 19, the switching voltage Vsw, which is a voltage value obtained by multiplying the current value of the primary side current Ip by the ON resistance value of the switching element M1, reaches a predetermined reference voltage. By detecting this, the overcurrent is detected.

In FIG. 9B, at the timing t21' when the first PWM signal pwm1 and the second PWM signal pwm2 become High and the switching elements are turned on, the primary current Ip starts to flow and then increases. When the OCP unit 19 detects the overcurrent of the primary-side current Ip at the timing t22', the OCP unit 19 outputs a High output signal to the OR circuit 146 (FIG. 3). As a result, the output of the OR circuit 146 becomes High, the second latch circuit 142 is reset, the second PWM signal pwm2 is set Low, and the switching element M1 is turned off. At this time, the primary-side current Ip becomes zero and decreases after the secondary-side current Is begins to flow.

However, at timing t22′, the output of the AND circuit 145 is Low and the primary side current Ip reaches the OCP level, so the second PWM signal pwm2 is Low, but the first latch circuit 141 is not reset and the first PWM signal is not reset. The signal pwm1 maintains High. After that, at the timing t23' when the output of the AND circuit 145 becomes High, the first latch circuit 141 is reset and the first PWM signal pwm1 becomes Low. At this time, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset, and time measurement is started.

Then, after the timing t24' at which the minimum off-time timer 161 completes the measurement of the predetermined minimum off-time, the 1/2 on-time timer 162 completes the measurement of 50% of the on-time at the timing t25'. At this time, since the output voltage Vout is low due to the overcurrent state, the FET on-trigger signal Tgon has already become High. Therefore, at the timing 25', both the first latch circuit 141 and the second latch circuit 142 are set, and both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High. As a result, the switching element M1 is turned on. At this time, the secondary side current Is becomes zero, and the primary side current Ip starts to flow and then increases.

Then, at the timing t26' when the OCP unit 19 detects that the primary-side current Ip has reached the OCP level, the second PWM signal pwm2 is set to Low and the switching element M1 is turned off. At this time, the primary-side current Ip becomes zero and decreases after the secondary-side current Is begins to flow.

As described above, in the present embodiment, the switching element M1 is turned off at the timing t22′ when the overcurrent is detected, but at the subsequent timing t23′, the first PWM signal pwm1 is set to Low and the minimum off-time timers 161 and 1 are set. Since the /2 on-time timer 162 is reset, the discharge time on the secondary side is extended by the period T1 between timings t22' and t23'. Further, in the present embodiment, the 1/2 on-time timer 162 measures the period T2 longer than the predetermined minimum off-time to define the off-period, so that the discharge time is further extended.

As a result, the increase in the value at the beginning of the flow of the primary current Ip shown in FIG. 9B according to the present embodiment is higher than the amount of change ΔIp in the increase of the value at the beginning of the flow of the primary current Ip according to the comparative example. The amount of change ΔIp′ can be suppressed. In FIG. 9A, the amount of increase change ΔIp becomes large and the primary side current Ip reaches the OCP level immediately (timing t24), so that the charging time on the primary side becomes short and the rise of the output voltage becomes slow. On the other hand, in FIG. 9B, by suppressing the amount of increase change ΔIp′, the time (timing t25′ to t26′) until the primary side current Ip reaches the OCP level is lengthened, so that The charging time can be secured and the rise of the output voltage Vout can be accelerated.

<Regarding output timing control of difference circuit>
Next, output timing control of the differential circuit 11 in the insulated switching power supply device 10 according to the present embodiment will be described. As described above, the difference circuit 11 outputs the REF terminal voltage VTref as it is or holds the output when the switching element M1 is off. A configuration for controlling the output timing by the difference circuit 11 is shown in FIG. The timer unit 16 shown in FIG. 10 corresponds to a timing control unit.

The timer unit 16 shown in FIG. 10 has a minimum off time timer 1611, a 1/2 on time timer 1621, an inverter 166, an AND circuit 167, a mask period timer 168, and a latch circuit 169. Note that the timer unit 16 shown in FIG. 10 is the same as the timer unit 16 shown in FIG. 3 described above, that is, the timer unit 16 of FIG. 3 omits the configuration shown in FIG. Further has that configuration.

The minimum off-time timer 1611 measures 95% of the predetermined minimum off-time measured by the minimum off-time timer 161. The 1/2 on-time timer 1621 is configured similarly to the lamp counter shown in FIG. 5, and applies the output voltage V3 output from the filter 17 as the reference voltage of the comparator. The output voltage V3 is 95% of the output voltage V2 (FIG. 4) described above. As a result, the 1/2 ON time timer 1621 measures a time of 95% of 50% of the ON time. The ratio of 95% for the minimum off time timer 1611 and the 1/2 on time timer 1621 is an example, and other ratios may be used as long as the ratio is less than 100% (for example, a ratio of 70% or more). ).

The first PWM signal pwm1 output from the first latch circuit 141 is input to the inverter 166. The outputs of the minimum off time timer 1611, the 1/2 on time timer 1621, and the inverter 166 are input to the AND circuit 167. The output of the AND circuit 167 is input to the reset terminal of the latch circuit 169.

The mask period timer 168 measures a predetermined mask period (for example, 240 nsec). The output of the mask period timer 168 is input to the set terminal of the latch circuit 169. The output of the latch circuit 169 is input to the sample hold circuit 12 as the switch timing signal SWT.

Explaining the operation of such a configuration, when the first PWM signal pwm1 (and the second PWM signal pwm2) becomes Low and the switching element M1 is turned off, the mask period timer 168 is reset to start time measurement and output is Low. And the output of the inverter 166 becomes High. At this time, both the minimum off-time timer 1611 and the 1/2 on-time timer 1621 are reset, time measurement is started, and the output of each timer becomes Low. When each time measurement is completed, the output of each timer becomes High.

The mask period timer 168 sets the output to High when the predetermined mask period is measured. Then, the latch circuit 169 is set and the switch timing signal SWT is set to High. As a result, the switch (not shown) included in the difference circuit 11 is turned on, and the difference circuit 11 starts the operation of outputting the REF terminal voltage VTref as it is as the output VTref2.

After that, the timing at which 95% of the predetermined minimum off time is measured by the minimum off-time timer 1611 or the timing at which 95% of 50% of the on-time is further measured by the 1/2 on-time timer 1621, whichever is later The AND circuit 167 becomes High at the timing. Then, the latch circuit 169 is reset and sets the switch timing signal SWT to Low. As a result, the switch included in the difference circuit 11 is turned off, and the difference circuit 11 holds the output VTref2 at the switching timing from on to off.

Here, FIG. 11 shows a waveform example of the switching voltage Vsw when the switching element M1 is turned off. As shown in FIG. 11, immediately after the switching element M1 is turned off, ringing occurs in the switching voltage Vsw due to the leakage inductance of the primary winding L1 of the transformer Tr1. Therefore, the mask period timer 168 masks only the mask period Tmsk so that the operation of outputting the REF terminal voltage VTref as it is is not performed during the period in which ringing occurs.

When the mask period Tmsk has elapsed, the operation of directly outputting the REF terminal voltage VTref is started. Thereafter, the output is held when the longer one of the predetermined minimum off-time 95% of the time Tmin_off and the on-time 50% of the further 95% of the time T1/2on (in FIG. 11). In the example, T1/2on is longer). When Tmin_off is longer, the switching element M1 is turned on after the predetermined minimum off time has elapsed, and when T1/2on is longer, the switching element M1 is turned on after 50% of the on time has elapsed. M1 is turned on. Therefore, the output is held before the timing when the switching element M1 is turned on, so that the output can be held when the secondary current Is is flowing. That is, it is possible to prevent the output from being abnormal due to the timing at which the switching element M1 is turned on and the timing at which the output is held overlapping.

Further, the REF terminal voltage VTref is a signal obtained by feeding back the flyback voltage VOR, and the flyback voltage VOR is represented by the above formula (1). Since the forward voltage Vf of the diode D2 in the equation (1) is the error, Vf becomes smaller and the error becomes smaller as the secondary current Is approaches zero. That is, the later the time, the more appropriate the timing for holding the output. When T1/2on is longer than Tmin_off, the timing for holding the output can be later in time.

<Modifications regarding switching element>
Next, a modified example of the insulated switching power supply device according to the present embodiment described above will be described. FIG. 12 shows the configuration of an insulated switching power supply device 10' according to a modification. The insulated switching power supply device 10' shown in FIG. 12 includes a power supply control IC 1'.

The power supply control IC 1'includes a main switching element M11, a sub switching element M12, a resistor R12, and a comparator CP. In addition, in the power supply control IC 1 ′, the components other than the configuration shown in FIG. 12 are the same as those in the above-described embodiment (FIG. 2).

The main switching element M11 composed of an N-channel MOSFET is a switching element that contributes to the generation of the output voltage Vout by the isolated switching power supply device 10' when it is switching-driven. The drain (current inflow end) of the main switching element M11 is connected to the switching output terminal T3, and the source (current outflow end) is connected to the ground terminal T41.

The sub switching element M12 is composed of an N-channel MOSFET. The drain (current inflow end) of the sub switching element M12 is connected to the connection point between the drain of the main switching element M11 and the switching output terminal T3 via the resistor R12. The source (current outflow end) of the sub switching element M12 is connected to the ground terminal T42.

The output terminal of a driver (not shown) is connected to the gate (control terminal) of the main switching element M11. The gate of the switching element M11 is connected to the non-inverting input terminal (+) of the comparator CP. A predetermined threshold voltage Vth1 is applied as a reference voltage to the inverting input terminal (−) of the comparator CP. The output end of the comparator CP is connected to the gate (control end) of the sub switching element M12. The comparator CP corresponds to a voltage applying section.

Here, the operation of the configuration using the main switching element M11 and the sub switching element M12 will be described with reference to FIG. FIG. 13 is a timing chart showing an example of each waveform when turning off the main switching element M11. In FIG. 13, from the top, the gate voltage Vg11 of the main switching element M11, the gate voltage Vg12 of the sub switching element M12, the current (drain current) I11 flowing through the main switching element M11, the secondary side current Is, the switching voltage Vsw, and the sub voltage A current (drain current) I12 flowing through the switching element M12 is shown.

When the main switching element M11 is on (the sub switching element M12 is off), at timing t31, withdrawal of charges from the gate capacitance of the main switching element M11 is started by a driver (not shown) so as to turn off the main switching element M11. It Then, the gate voltage Vg11 of the main switching element M11 decreases. Then, at the timing t32 when the gate voltage Vg11 reaches the mirror voltage Vm and then drops below the mirror voltage Vm, the current I11 starts decreasing and the switching voltage Vsw starts rising. Then, when the gate voltage Vg11 reaches the threshold voltage Vth1, the output of the comparator CP becomes Low (timing t33). As a result, the extraction of charges from the gate capacitance of the sub switching element M12 is started, and the gate voltage Vg12 starts decreasing. Then, when the gate voltage Vg11 reaches the threshold voltage Vth11 of the main switching element M11, the current I11 becomes zero (timing t34).

During the period from the timing t32 to the timing t35 when the gate voltage Vg12 reaches the threshold voltage Vth12 of the sub switching element Vg12, the current I12 flows through the sub switching element M12 which is on. At timing t35, the sub switching element M12 is turned off and the current I12 stops flowing. Therefore, during the period from the timing t32 to the timing t34 when the current I11 of the main switching element M11 becomes zero, both the main switching element M11 and the sub switching element M12 are on. Then, in the period from the timing t34 to the timing t35, the main switching element M11 is off and the sub switching element M12 is on. Then, after the timing t35, both the main switching element M11 and the sub switching element M12 are turned off.

Here, the primary winding L1 of the transformer Tr1 has a leakage inductance, and when the switching element is on, a current also flows through this leakage inductance to accumulate energy, but it is coupled with other windings. There is no power transfer. Accordingly, if the sub switching element M12 is not provided, ringing is large in the switching voltage Vsw when the main switching element M11 is turned off, and a long period occurs.

Therefore, in the present embodiment, by providing the sub switching element M12 and causing the current I12 to flow through the sub switching element M12 when turning off the main switching element M11, it is possible to suppress ringing occurring in the switching voltage Vsw. FIG. 12 shows that the peak value of ringing (broken line) that occurs in the switching voltage Vsw when the sub-switching element M12 is not provided can be reduced to the peak value of the switching voltage Vsw shown by the solid line in the present embodiment. ing.

Conventionally, a snubber circuit has been used to suppress ringing, but the snubber circuit is a circuit that is difficult for the user to design, and if the design fails, the switching element may be destroyed. According to the present embodiment, it is possible to suppress ringing without using such a snubber circuit.

As described above, the threshold voltage Vth1 of the comparator CP is set between the mirror voltage Vm of the main switching element M11 and the threshold voltage Vth11 of the main switching element M11 itself, and the reason will be described. First, the current I11 flowing through the main switching element M11 decreases from when the gate voltage Vg11 falls below the mirror voltage Vm, and becomes zero when the gate voltage Vg11 reaches the threshold voltage Vth11. When the threshold voltage Vth1 is set to be equal to or higher than the mirror voltage Vm, during the period in which the gate voltage Vg11 is the threshold voltage Vth1 to the mirror voltage Vm, almost no current flows in the sub switching element M12, so that the period does not function. Become. On the other hand, when the threshold voltage Vth1 is set to be equal to or lower than the threshold voltage Vth11, the timing when the gate voltage Vg12 reaches the threshold voltage Vth12 is delayed, and the current I12 excessively flows in the sub switching element M12. Therefore, it is preferable that the threshold voltage Vth1 is lower than the mirror voltage Vm, and further, it is set between the mirror voltage Vm and the threshold voltage Vth11.

The resistor R12 is provided to limit the current I12. There is a period (timing t32 to t34) in which the sub switching element M12 is turned on when the main switching element M11 is turned on. During this period, the current flowing between the switching output terminal T3 and the ground terminals T41 and T42 is: A current flows to the side of the main switching element M11 having a low resistance, and almost no current flows to the sub switching element M12 due to the resistance R12. This is because if the current I12 is made to flow too much, the rising voltage of the switching voltage Vsw becomes abnormally low when the main switching element M11 is turned off.

Further, in the present embodiment, the main switching element M11 and the sub switching element M12 are preferably manufactured in the same process, and the main switching element M11 is larger than the sub switching element M12 (for example, 1000:1). Since they are manufactured in the same process, the main switching element M11 and the sub switching element M12 have the same variations and have the same characteristics. Therefore, the time from the start of the drop of the gate voltage until it becomes zero (or the threshold voltage of the switching element is reached) is almost the same in the main switching element M11 and the sub switching element M12, and the current I11 of the main switching element M11 is When it becomes zero, it is guaranteed that the sub-switching element M12 is on. Further, when the size of the main switching element M11 is large, a large amount of current flows in a steady ON state, the capacity of a parasitic capacitor that causes a resonance phenomenon also increases, and the effect of suppressing ringing by the sub switching element M12 increases.

Instead of using the comparator CP as described above, a delay circuit such as a filter that delays the voltage applied to the gate of the main switching element M11 and applies it to the gate of the sub switching element M12 may be used. .. For example, if the delay time elapses before the current I11 of the main switching element M11 becomes zero and the sub switching element M12 keeps ON when the current of the main switching element M11 is zero, ringing is suppressed. be able to.

<Other>
Although the embodiment of the present invention has been described above, the embodiment can be variously modified within the scope of the gist of the present invention.

For example, the switching element may be provided outside the power supply control IC instead of being provided in the power supply control IC.

The insulated switching power supply device according to the present invention is suitable for use in, for example, a solar inverter, an FA inverter, an industrial equipment inverter such as a power storage system, or the like.

INDUSTRIAL APPLICABILITY The present invention can be used, for example, in an insulated switching power supply device for an inverter.

1 Power supply control IC
10 Insulated switching power supply device Tr1 Transformer L1 Primary winding L2 Secondary winding D2 Diode C2 Smoothing capacitor T1 Power supply terminal T2 Feedback terminal T3 Switching output terminal T4 Ground terminal T5 REF terminal R11, R12 Resistance 11 Differential circuit
13 Comparator 14 Logic Section 15 Driver 16 Timer Section 17 Filter 18 Ripple Generation Section 19 OCP Section M1 Switching Element 141 First Latch Circuit 142 Second Latch Circuit 143-145 AND Circuit 146 OR Circuit 161 Minimum Off-Time Timer 162 1/2 ON Time timer 163 Minimum on-time timer 164 On-time timer 165 Inverter 166 Inverter 167 AND circuit 168 Mask period timer 169 Latch circuit 1611 Minimum off-time timer 1621 1/2 On-time timer M11 Main switching element M12 Sub-switching element R12 Resistance CP comparator T41 , T42 ground terminal

Claims (8)

A transformer including a primary winding and a secondary winding, and a switching element,
A power supply control device used for a flyback type insulated switching power supply device in which an input voltage application terminal is connected to one end of the primary winding and the switching element is connected to the other end of the primary winding. hand,
An OCP section (overcurrent protection section) that detects an overcurrent of the primary side current;
An off controller for turning off the switching element when the overcurrent is detected;
A first timer for measuring a predetermined minimum off time at a timing delayed after being turned off by the off control unit;
An on-trigger signal generation unit that generates an on-trigger signal that turns on the switching element based on a feedback signal obtained by feeding back a flyback voltage,
An on-timing determining unit that determines a timing for turning on the switching element based on the measured minimum off-time and the on-trigger signal,
A power supply control device comprising: A second timer that starts measuring a predetermined percentage of the on-time at the same timing as the first timer;
The predetermined minimum off-time measured by the first timer, and a minimum off-time setting unit that compares the time measured by the second timer and sets the longer one as the minimum off-time,
The power supply control device according to claim 1, wherein the on-timing determination unit determines a timing for turning on the switching element based on the set minimum off-time and the on-trigger signal. The power supply control device according to claim 2, wherein the predetermined ratio is 20% to 80%. The power supply control device according to claim 3, wherein the predetermined ratio is 50%. The power supply control device according to any one of claims 2 to 4, wherein the minimum off-time setting unit is an AND circuit. The power supply control device according to claim 1, wherein the on-timing determining unit is an AND circuit. A third timer that measures the on time,
A first latch circuit to which the output of the third timer is input;
An OR circuit to which the output of the OCP section and the output of the third timer are input,
A second latch circuit to which the output of the OR circuit is input,
The off control unit includes the OR circuit and the second latch circuit,
The second PWM signal output from the second latch circuit is input to a driver that drives the switching element,
The first PWM signal output from the first latch circuit is input to the first timer,
The power supply control device according to claim 1, wherein an output of the on-timing determining unit is input to the first latch circuit and the second latch circuit. An insulated switching power supply device comprising the power supply control device according to any one of claims 1 to 7, a switching element, and a transformer.

Images