JP6775365B2 - Insulated switching power supply and power supply control - Google Patents

Description

The present invention relates to an isolated switching power supply device.

Conventionally, various flyback type isolated switching power supply devices that convert an input DC voltage into a desired DC voltage have been developed. In this isolated switching power supply device, an output voltage is obtained on the secondary side of the transformer by switching driving a switching element connected in series with the primary winding of the transformer. When the switching element is turned on, the transformer is charged with exciting energy, and when the switching element is turned off, the exciting energy is discharged via a diode and a smoothing capacitor arranged on the secondary side of the transformer. An example of an isolated switching power supply device is disclosed in, for example, Patent Document 1.

Further, as a control method of the switching power supply device, a linear control method (for example, a voltage mode control method, a current mode control method) or a non-linear control method (for example, an on-time fixed method, an off-time fixed method, hysteresis) has been conventionally used. Window method) is adopted.

Japanese Unexamined Patent Publication No. 2012-125084

Here, in the flyback type isolated switching power supply device as described above, ringing may occur in the voltage applied to the switching element when the switching element is turned off due to the leakage inductance of the transformer. In order to prevent the ringing from being destroyed by exceeding the withstand voltage of the switching element, a snubber circuit is often provided to suppress the ringing.

However, the snubber circuit is a circuit that is difficult for the user to design, and if the design fails, the switching element may be destroyed.

In view of the above situation, the present invention provides an isolated switching power supply device and a power supply control device capable of suppressing ringing that occurs in the voltage applied to the switching element when the switching element is turned off without using a snubber circuit. The purpose is to provide.

In order to achieve the above object, the insulated switching power supply device according to one aspect of the present invention includes a transformer including a primary winding and a secondary winding to which an input voltage application end is connected to one end.
A main switching element in which a current inflow end is connected to the other end of the primary winding,
An auxiliary switching element to which the current inflow end is connected to the current inflow end of the main switching element,
A state in which both the main switching element and the sub-switching element are turned on, a state in which the main switching element is turned off and the sub-switching element is turned on, and a state in which both the main switching element and the sub-switching element are turned off. A voltage application unit that applies a voltage to the control end of the sub-switching element so as to transition in the order of
(First configuration).

Further, in the first configuration, the voltage application unit is a comparator.
A control end of the main switching element is connected to one input end of the comparator.
A threshold voltage of the main switching element is applied as a reference voltage to the other input end of the comparator.
The output end of the comparator may be connected to the control end of the sub-switching element (second configuration).

Further, in the second configuration, the threshold voltage may be set to a value lower than the mirror voltage of the main switching element (third configuration).

Further, in the third configuration, the threshold voltage may be set between the mirror voltage and the threshold voltage of the main switching element itself (fourth configuration).

Further, in the first configuration, the voltage application unit may be a filter that delays the voltage applied to the control end of the main switching element and applies it to the control end of the sub-switching element (fifth). Composition).

Further, in any of the first to fifth configurations, the current inflow end of the sub-switching element may be connected to the current inflow end of the main switching element via a resistance element (sixth). Constitution).

Further, in any of the first to sixth configurations, the main switching element and the sub-switching element may be manufactured in the same process (seventh configuration).

Further, in any of the first to seventh configurations, the main switching element may be larger in size than the sub-switching element (eighth configuration).

Further, the power supply control device according to another aspect of the present invention is used for an isolated switching power supply device including a transformer including a primary winding and a secondary winding in which an input voltage application end is connected to one end. It is a power control device
A main switching element in which a current inflow end is connected to the other end of the primary winding,
An auxiliary switching element to which the current inflow end is connected to the current inflow end of the main switching element, and
A voltage application unit for applying a voltage to the control end of the sub-switching element is provided so that the sub-switching element is turned off later than the main switching element (9th configuration).

Further, in the ninth configuration, a resistance element connected between the current inflow end of the main switching element and the current inflow end of the sub-switching element may be further provided (tenth configuration).

According to the present invention, it is possible to suppress ringing that occurs in the voltage applied to the switching element when the switching element is turned off without using a snubber circuit.

It is an overall block diagram of the insulation type switching power supply device which concerns on one Embodiment of this invention. It is a block diagram which shows the internal structure of the power supply control IC which concerns on one Embodiment of this invention. It is a figure which shows one specific configuration example of a timer part and a logic part. It is a figure which shows one configuration example of a filter. It is a figure which shows one configuration example of an on-time timer. It is a figure of an example which shows the state of decrease of the secondary side current when a switching element is turned off. It is a timing chart which shows an example of each PWM signal and each timer output at the time of a transient response that output voltage dropped by load fluctuation. It is a timing chart which shows each waveform example in the comparative example which uses only the minimum off time timer. It is a timing chart in the embodiment of the present invention corresponding to FIG. 8A according to a comparative example. It is a timing chart which shows an example of the operation at the time of overcurrent protection in the insulated switching power supply device which concerns on a comparative example. It is a timing chart which shows an example of the operation at the time of overcurrent protection in the insulated switching power supply device which concerns on embodiment of this invention. It is a figure which shows the structure which controls the output timing of a difference circuit. The waveform example of the switching voltage when the switching element is turned off is shown. It is an overall block diagram of the insulation type switching power supply device which concerns on the modification of this invention. It is a timing chart which shows an example of each waveform when the main switching element is turned off in the insulated switching power supply device which concerns on the modification of this invention.

<Overall configuration of isolated switching power supply>
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an overall configuration of an insulated switching power supply device 10 according to an embodiment of the present invention. The isolated switching power supply device 10 is a flyback type DC / DC converter that generates an output voltage Vout from an input voltage Vin. Further, the isolated switching power supply device 10 performs adaptive on-time control as described later as a control method.

The isolated switching power supply device 10 includes a power supply control IC1 and various discrete components (transformer Tr1, diode D2, smoothing capacitor C2, resistor R11, and resistor R12) externally attached to the power supply control IC1.

The power supply control IC 1 (power supply control device) is a main body (semiconductor device) that comprehensively controls the overall operation of the isolated switching power supply device 10. The power supply control IC 1 has a power supply terminal T1, a feedback terminal T2, a switching output terminal T3, a ground terminal T4, and a REF terminal T5 in order to establish an electrical connection with the outside.

The input voltage Vin, which is a DC voltage, is applied to the power supply terminal T1 and is also applied to one end of the primary winding L1 of the transformer Tr1. The other end of the primary winding L1 is connected to the feedback terminal T2 via an external resistor R11 and is also connected to the switching output terminal T3. One end of the secondary winding L2 of the transformer Tr1 is connected to the anode of the diode D2. A smoothing capacitor C2 is connected between the cathode of the diode D2 and the other end of the secondary winding L2. An output voltage Vout is generated at the connection point between one end of the capacitor C2 and the cathode of the diode D2. An application end of the ground potential is connected to the ground terminal T4. One end of an external resistor R12 is connected to the REF terminal T5.

FIG. 2 is a block diagram showing an internal configuration of the power supply control IC1. The power supply control IC 1 switches between the difference circuit 11, the comparator 13, the logic unit 14, the driver 15, the timer unit 16, the filter 17, the ripple generation unit 18, the OCP unit (overcurrent protection unit) 19, and the switching. It has an element M1 and is configured by integrating each of these components on one chip.

The drain of the switching element M1 composed of an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is connected to one end of the primary winding L1 via the switching output terminal T3. The source of the switching element M1 is connected to the application end of the ground potential via the ground terminal T4.

When the switching element M1 is turned on, a current flows through the primary winding L1 of the transformer Tr1, and the transformer Tr1 is charged with exciting energy. At this time, the diode D2 is off. Next, when the switching element M1 is turned off, the charged exciting energy is discharged from the secondary winding L2 of the transformer Tr1 through the diode D2, and is smoothed by the smoothing capacitor C2 to generate an output voltage Vout. At this time, a current flows through the diode D2.

When the switching element M1 is off, the flyback voltage VOR represented by the following equation (1) is generated in the primary winding L1.
VOR = Np / Ns × (Vout + Vf) (1)
However, Np: the number of turns of the primary winding L1, Ns: the number of turns of the secondary winding L2, Vf: the forward voltage of the diode D2.

At this time, the switching voltage Vsw, which is the drain voltage of the switching element M1, is represented by the following equation (2).
Vsw = Vin + VOR (2)

The difference circuit 11 includes a power supply terminal T1 to which an input voltage Vin is applied, a feedback terminal T2 connected to the other end of a resistor R11 to which a switching voltage Vsw is applied to one end, and a REF terminal to which one end of the resistor R12 is connected. Connected to T5. As a result, the difference circuit 11 converts the difference between the switching voltage Vsw and the input voltage Vin into voltage and current by the resistor R11, and the converted current and the resistor R12 generate a REF terminal voltage VTref at the REF terminal T5. That is, the REF terminal voltage VTref is generated as a feedback signal that feeds back the flyback voltage VOR. The difference circuit 11 corresponds to a feedback signal output unit.

The difference circuit 11 performs an operation of outputting the REF terminal voltage VTref as it is as an output VTref2 when the switching element M11 is off, and an operation of holding the output VTref2 at a certain timing. The difference circuit 11 outputs the output VTref 2 to the comparator 13.

The comparator 13 compares the output VTref2 with, for example, a triangular wave-shaped reference voltage Vref generated by the ripple generation unit 18, and outputs the FET on-trigger signal Tgon as the comparison result to the logic unit 14. The comparator 13 corresponds to an on-trigger signal generation unit.

The logic unit 14 generates the first PWM signal pwm1 and the second PWM signal pwm2. The first PWM signal pwm1 and the second PWM signal pwm2 are pulse signals, and the on-duty is basically the same.

The filter 17 extracts on-duty information by filtering the first PWM signal pwm1. The filter 17 corresponds to a duty information acquisition unit. The timer unit 16 and the logic unit 14 set the on-time, which is the period during which the switching element M1 is turned on, based on the on-duty information from the filter 17. The logic unit 14 sets the second PWM signal pwm2 to the Low level in order to switch the switching element M1 from on to off at a timing such that the set on time is reached.

Further, the timer unit 16 and the logic unit 14 set the minimum off time, which is the minimum value of the off time, which is the period during which the switching element M1 is turned off, based on the on-duty information from the filter 17. The logic unit 14 sets the second PWM signal pwm2 to the High level in order to switch the switching element M1 from off to on at the timing based on the set minimum off time and the FET on trigger signal Tgon from the comparator 13.

The driver 15 generates a gate voltage GT based on the second PWM signal pwm2 generated by the logic unit 14 and applies it to the gate of the switching element M1. As a result, the switching element M1 is controlled on / off.

Further, the timer unit 16 generates a switch timing signal SWT that indicates an on / off timing of a switch (not shown) included in the difference circuit 11 and outputs the switch timing signal SWT to the difference circuit 11. When the switch timing signal SWT instructs to turn on, the difference circuit 11 outputs the REF terminal voltage VTref as the output VTref2 as it is, and when instructing to turn it off, the difference circuit 11 holds the output VTref2 at the timing of switching from on to off.

<On time / off time setting control>
Next, the control for setting the on-time / off-time by the power supply control IC1 according to the present embodiment will be described. FIG. 3 is a diagram showing a specific configuration example of the timer unit 16 and the logic unit 14.

The timer unit 16 has a minimum off-time timer 161, a 1/2 on-time timer 162, a minimum on-time timer 163, an on-time timer 164, and an inverter 165. The logic unit 14 includes a first latch circuit 141, a second latch circuit 142, AND circuits 143 to 145, and an OR circuit 146. The first latch circuit 141 outputs the first PWM signal pwm1. The second latch circuit 142 outputs the second PWM signal pwm2 to the driver 15.

The first latch circuit 141 and the second latch circuit 142 are set at the same time by the signal input to the set terminal, and are basically reset at the same time (except when the overcurrent is detected by the OCP unit 19) by the signal input to the reset terminal. Therefore, the first PWM signal pwm1 and the second PWM signal pwm2 are synchronized and have the same on-duty.

When the first latch circuit 141 is set and the first PWM signal pwm1 rises from Low to High, that is, when the switching element M1 is turned on by the second PWM signal pwm2, the output of the inverter 165 becomes Low. The minimum on-time timer 163 and the on-time timer 164 are reset.

When the minimum on-time timer 163 is reset, the measurement of a predetermined minimum on-time (fixed value) is started. Here, the predetermined minimum on-time is a parameter that determines the degree of over-boosting of the output voltage Vout. When the on-time timer 164 is reset, the on-time timer 164 starts measuring the on-time set by the filter output voltage V1 generated by the filter 17 based on the first PWM signal pwm1.

Here, FIG. 4 is a diagram showing a configuration example of the filter 17. The filter 17 has a resistor R17, a capacitor C17, and resistors R171 and R172 for dividing the voltage. An input terminal T171 to which the first PWM signal pwm1 is applied is connected to one end of the resistor R17. The other end of the resistor R17 is connected to one end of the capacitor C17 and also to the first output terminal T172 where the filter output voltage V1 is generated. The other end of the capacitor C17 is connected to the end where the ground potential is applied. That is, a low-pass filter is formed from the resistor R17 and the capacitor C17, and the signal after passing the first PWM signal pwm1 through the low-pass filter becomes the filter output voltage V1. Therefore, the filter output voltage V1 indicates the on-duty information of the first PWM signal pwm1.

Further, FIG. 5 is a diagram showing a configuration example of the on-time timer 164. The on-time timer 164 is a so-called lamp counter having a constant current circuit Ic, a capacitor C164, and a comparator CP164. A constant current circuit Ic and a capacitor C164 are connected in series between the power supply voltage Vcc and the ground potential, and the connection point is connected to the non-inverting input terminal (+) of the comparator CP164. A filter output voltage V1 is applied to the inverting input terminal (−) of the comparator CP164. The output of the comparator CP164 becomes the output of the on-time timer 164.

When the on-time timer 164 is reset, the electric charge stored in the capacitor C164 is discharged. Then, the capacitor C164 is charged by the current constantly controlled by the constant current circuit Ic. The time t until the voltage at the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 as the reference voltage by charging the capacitor C164 is expressed by the following equation (3).
t = C × V1 / I (3)
However, C: the capacity of the capacitor C164, I: the constant current value

At the time of reset, the output of the comparator CP164 is Low, but when the voltage at the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 after the time t elapses, the output of the comparator C164 becomes High.

The minimum on-time timer 163 can be configured by a lamp counter similar to the configuration shown in FIG. At this time, the reference voltage of the comparator, the constant current value of the constant current circuit, and the capacity of the capacitor are appropriately set so that the time t becomes a predetermined minimum on-time.

The output of the minimum on-time timer 163 and the output of the on-time timer 164 are input to the AND circuit 145. When the outputs of the minimum on-time timer 163 and the on-time timer 165 are both set to High by the AND circuit 145, the output of the AND circuit 145 becomes High. That is, the output of the AND circuit 145 becomes High at the timing when the longer of the predetermined minimum on-time measured by the minimum on-time timer 163 and the on-time measured by the on-time timer 164 is measured. Therefore, when the on time is shorter than the predetermined minimum on time, the on time is limited to the predetermined minimum on time. The AND circuit 145 corresponds to an off-timing determination unit.

The output of the AND circuit 145 is input to the reset terminal of the first latch circuit 141 and is also input to the OR circuit 146. The output of the OCP unit 19 is also input to the OR circuit 146. The output of the OR circuit 146 is input to the second latch circuit 142. In the normal state when no overcurrent is detected, the output of the OCP unit 19 becomes Low, so that both the first latch circuit 141 and the second latch circuit 142 are reset at the timing when the output of the AND circuit 145 becomes High. The off control unit is composed of the OR circuit 146 and the second latch circuit 142.

As a result, both the first PWM signal pwm1 and the second PWM signal pwm2 are switched to the Low level, the switching element M1 is turned off by the second PWM signal pwm2, and the on time is defined.

When the first PWM signal pwm1 reaches the Low level, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset. When the minimum off time timer 161 is reset, the measurement of a predetermined minimum off time (fixed value) is started. When the switching element M1 is off, the difference circuit 11 outputs the REF terminal voltage VTref as it is or holds the output. However, since ringing occurs in the switching voltage Vsw immediately after the switching element M1 is turned off, until the ringing becomes stable. It is necessary to secure the above time, and the above-mentioned predetermined minimum off time is set.

The minimum off-time timer can be configured by a lamp counter similar to the configuration shown in FIG. At this time, the reference voltage of the comparator, the constant current value of the constant current circuit, and the capacity of the capacitor are appropriately set so that the time t becomes a predetermined minimum off time.

Further, when the 1/2 on-time timer 162 is reset, the measurement of 50% of the on-time is started. Here, when the switching element M1 is on, the primary side current Ip flowing through the primary winding L1 rises, and when the switching element M1 is turned off, the secondary side current Is flowing through the secondary winding L2. A peak value obtained by multiplying the peak value of the primary side current by the turns ratio is generated. Then, the secondary side current gradually decreases with the passage of time. FIG. 6 is a diagram showing an example of a decrease in the secondary side current Is when the switching element M1 is turned off. As shown in FIG. 6, the secondary side current Is gradually decreases from the peak value Ispk at the time of turning off, and becomes zero when the discharge time toff2 elapses. In the discharge up to 50% (1/2 toff2) of the discharge time toff2, the discharge amount increases by the discharge amount of the area S2 with respect to the average discharge amount (area S1), so that efficient discharge is possible. Become. On the contrary, if the discharge time exceeds 50% of toff2, the efficiency deteriorates.

Therefore, it is sufficient if the discharge time (that is, the off time) can be extended to 50% of the discharge time toff2, but it is difficult to estimate the actual discharge time toff2 because it depends on the transformer Tr1 and the load condition. Therefore, in the present embodiment, the off time is extended to 50% of the on time as a guideline similar to 50% of the discharge time toff2.

Specifically, in the configuration of the filter 17 shown in FIG. 4, the filter output voltage V1 is divided by the resistors R171 and R172 having the same resistance value and output from the second output terminal T173 as the filter output voltage V2. As a result, the filter output voltage V2 becomes 50% of the filter output voltage V1. Then, a 1/2 on-time timer 162 is configured in the same manner as the configuration of the lamp counter shown in FIG. 5, and the filter output voltage V2 is applied as the reference voltage of the comparator. As a result, the 1/2 on-time timer 162 sets the output to High when 50% of the on-time is measured after the output becomes Low after being reset.

The outputs of the minimum off-time timer 161 and the 1/2 on-time timer 162 are input to the AND circuit 144. The output of the AND circuit 144 is set to High when both the outputs of the minimum off-time timer 161 and the 1/2 on-time timer 162 are set to High. That is, the longer of the predetermined minimum off time and 50% of the on time is selected and set as the minimum off time. The AND circuit 144 corresponds to the minimum off time setting unit.

Then, the FET on-trigger signal Tgon and the output of the AND circuit 144 are input to the AND circuit 143. As a result, when the FET on-trigger signal Tgon and the output of the AND circuit 144 are both High, the output of the AND circuit 143 is set to High. That is, if the timing at which the FET on-trigger signal Tgon becomes High is after the above-set minimum off time has elapsed, that timing is selected, and the timing at which the above-set minimum off time has elapsed is the timing at which the FET on-trigger signal Tgon has elapsed. If it is after the high timing, the timing at which the minimum off time has elapsed is selected. That is, the off time is limited so that it is not shorter than the minimum off time. The AND circuit 143 corresponds to the on-timing determination unit.

The output of the AND circuit 143 is input to each set terminal of the first latch circuit 141 and the second latch circuit 142. Therefore, at the timing when the output of the AND circuit 143 is set to High, both the first latch circuit 141 and the second latch circuit 142 are set, and both the first PWM signal pwm1 and the second PWM signal pwm2 are switched to High. As a result, the switching element M1 is turned on and the off time is defined.

When the output voltage Vout drops due to load fluctuation, the switching element M1 is turned on so that the minimum off time set above is set as the off time. At this time, the on-duty of the first PWM signal pwm1 becomes large, and the on-time set by the filter output voltage V1 becomes long. As described above, by performing adaptive on-time control for setting the on-time using the on-duty information of the first PWM signal pwm1, the response characteristic to the load fluctuation can be improved.

Here, FIG. 7 is a timing chart showing an example of each PWM signal and each timer output at the time of a transient response in which the output voltage Vout drops due to load fluctuation. In addition, FIG. 7 also shows the outputs of the AND circuits 145 and 144, and the FET on-trigger signal Tgon. At the timing t1, both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High, and the switching element M1 is turned on. Then, both the minimum on-time timer 163 and the on-time timer 164 are reset, and the output of each timer becomes Low.

Then, when the predetermined minimum on-time is measured by the minimum on-time timer 163, the output of the minimum on-time timer 163 is set to High (timing t2). After that, when the on-time is measured by the on-time timer 164, the output of the on-time timer 164 is set to High (timing 3). At this timing, since the output of the AND circuit 145 becomes High, both the first latch circuit 141 and the second latch circuit 142 are reset, the first PWM signal pwm1 and the second PWM signal pwm2 are both set to Low, and the switching element M1 is turned off. It is said that.

At this time, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset, and the output of each timer becomes Low. After that, when a predetermined minimum off time is measured by the minimum off time timer 161, the output of the minimum off time timer 161 is set to High (timing t4). After that, when 50% of the on-time is measured by the 1/2 on-time timer 162, the output of the 1/2 on-time timer 162 is set to High (timing t5). Here, since the timing at which the FET on-trigger signal Tgon becomes High is before the timing t5, the output of the AND circuit 143 becomes High at the timing t5. As a result, both the first latch circuit 141 and the second latch circuit 142 are set, the first PWM signal pwm1 and the second PWM signal pwm2 are both set to High, and the switching element M1 is turned on.

In this way, since 50% of the on-time longer than the predetermined minimum off time is set as the minimum off time, the discharge time can be secured as compared with the case where the predetermined minimum off time is set as the off time. The transient response can be accelerated. The predetermined ratio of 50% is an example, and if it is set to a ratio of, for example, 20% to 80%, a certain effect can be obtained.

Further, here, a comparison with an embodiment in which the minimum off time is set by using only the minimum off time timer will be described with reference to FIGS. 8A and 8B. FIG. 8A is a timing chart showing each waveform example in the embodiment for comparison using only the minimum off-time timer. In FIG. 8A, examples of waveforms of the PWM signal, the output of the minimum off-time timer, the primary side current Ip, and the secondary side current Is are shown from the upper stage.

FIG. 8A shows a case where the output voltage Vout drops due to load fluctuation after the timing t11 when the PWM signal becomes High and the switching element is turned on. While the switching element is on, the primary current Ip increases. At the timing t12 when the PWM signal becomes Low and the switching element is turned off, the minimum off time timer is reset and measurement starts at a predetermined minimum off time. At the timing t12, the primary side current Ip becomes zero, the secondary side current Is is generated according to the peak value of the primary side current Ip, and then decreases.

The measurement of the minimum off time is completed at the timing t13, and the output of the minimum off time timer becomes High. Here, since the FET on-trigger signal Tgon is set to High before the timing t13 due to the decrease in the output voltage Vout, the PWM signal is set to High and the switching element is turned on at the timing t13. Here, the secondary side current Is becomes zero, the primary side current Ip is generated according to the value of the secondary side current Is, and then increases. Then, at the timing t14, the PWM signal is set to Low, and the switching element is turned off. At this time, the primary side current Ip becomes zero.

FIG. 8B is a timing chart in the present embodiment corresponding to FIG. 8A according to the comparative example. In FIG. 8B, from the top, the first PWM signal pwm1 (and the second PWM signal pwm2), the output of the minimum off-time timer 161 and the output of the 1/2 on-time timer 162, the primary side current Ip and the secondary side current Is. An example of the waveform is shown.

In FIG. 8B, at the timing t12'when the first PWM signal pwm1 is set to Low and the switching element M1 is turned off, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset, and each timer starts time measurement. To do. Here, the primary side current Ip becomes zero, and the secondary side current Is decreases thereafter. In FIG. 8B, the 1/2 on-time timer 162 completes the measurement of 50% of the on-time at the timing t14'after the timing t13'in which the minimum off-time timer 161 completes the measurement of the predetermined minimum off-time. Here, since the FET on-trigger signal Tgon is set to High before the timing t14'due to the decrease in the output voltage Vout, the first PWM signal pwm1 is set to High and the switching element M1 is turned on at the timing t14'. Here, the secondary side current Is becomes zero, the primary side current Ip is generated according to the value of the secondary side current Is, and then increases. Then, at the timing t15', the first PWM signal pwm1 is set to Low, and the switching element M1 is turned off. At this time, the primary side current Ip becomes zero.

In FIG. 8B, the off time is defined at the timing of measuring 50% of the on time longer than the predetermined minimum off time as compared with FIG. 8A. Therefore, by securing the discharge time on the secondary side, the secondary side is secured. The current Is is reduced to a lower value. As a result, the value of the primary side current Ip generated when the switching element M1 is turned on can be lowered, so that the increase change amount of the primary side current from the peak value Ippk1 to the peak value Ippk2 in FIG. 8A can be reduced. , The amount of increase change of the primary side current from the peak value Ippk1'to the peak value Ippk2' in FIG. 8B can be suppressed.

Further, in FIG. 8B, it can be seen that the fluctuation of the switching cycle (switching frequency) can be suppressed as compared with FIG. 8A.

The time to be compared with the predetermined minimum off time is not limited to the time of a predetermined ratio (for example, 50%) which is a fixed value of the on time, and the predetermined ratio may be variably controlled according to the load condition.

<Operation during overcurrent protection>
Next, the operation of the insulated switching power supply device 10 according to the present embodiment at the time of overcurrent protection will be described with reference to FIGS. 9A and 9B.

FIG. 9A is a timing chart showing an example of the operation at the time of overcurrent protection in the insulated switching power supply device according to the comparative example for comparison with the present embodiment. In FIG. 9A, at the timing t21 when the PWM signal becomes High and the switching element is turned on, the primary side current Ip starts to flow and then increases. Then, at the timing t22 when it is detected that an overcurrent occurs in the primary side current Ip and the primary side current Ip reaches a predetermined OCP level, the PWM signal is set to Low and the switching element is turned off. At this time, the primary side current Ip becomes zero, and the secondary side current Is is generated and thereafter decreases.

At the timing t22, the minimum off time timer is reset and measurement starts at a predetermined minimum off time. Then, when the minimum off time is measured at the timing t23, the PWM signal is set to High and the switching element is turned on. At this time, the secondary side current Is becomes zero and rises after the primary side current Ip starts to flow. Then, at the timing t24 when it is detected that the primary side current Ip has reached the OCP level, the PWM signal is set to Low and the switching element is turned off. At this time, the primary side current Ip becomes zero, and the secondary side current Is begins to flow.

On the other hand, in the present embodiment, the timing chart shown in FIG. 9B is used as an example of the operation during overcurrent protection. Here, as shown in FIG. 2, in the OCP unit 19, the switching voltage Vsw, which is a voltage value obtained by multiplying the current value of the primary side current Ip by the on-resistance value of the switching element M1, has reached a predetermined reference voltage. By detecting that, the overcurrent is detected.

In FIG. 9B, at the timing t21'when the first PWM signal pwm1 and the second PWM signal pwm2 become High and the switching element is turned on, the primary side current Ip increases after the start of flow. Then, when the OCP unit 19 detects the overcurrent of the primary side current Ip at the timing t22', the OCP unit 19 outputs the High output signal to the OR circuit 146 (FIG. 3). As a result, the output of the OR circuit 146 becomes High, the second latch circuit 142 is reset, the second PWM signal pwm2 is set to Low, and the switching element M1 is turned off. At this time, the primary side current Ip becomes zero and decreases after the secondary side current Is starts to flow.

However, at the timing t22', the output of the AND circuit 145 is Low, and since the primary side current Ip reaches the OCP level, the second PWM signal pwm2 becomes Low, but the first latch circuit 141 is not reset and the first PWM. The signal pwm1 maintains High. After that, at the timing t23'when the output of the AND circuit 145 becomes High, the first latch circuit 141 is reset, and the first PWM signal pwm1 becomes Low. At this time, both the minimum off time timer 161 and the 1/2 on time timer 162 are reset, and the time measurement is started.

Then, after the timing t24'when the minimum off time timer 161 completes the measurement of the predetermined minimum off time, the 1/2 on-time timer 162 completes the measurement of 50% of the on-time at the timing t25'. At this time, since the output voltage Vout is low due to the overcurrent state, the FET on-trigger signal Tgon is already High. Therefore, at the timing 25', both the first latch circuit 141 and the second latch circuit 142 are set, and both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High. As a result, the switching element M1 is turned on. At this time, the secondary side current Is becomes zero, and the primary side current Ip increases after the start of flow.

Then, at the timing t26'when the OCP unit 19 detects that the primary side current Ip has reached the OCP level, the second PWM signal pwm2 is set to Low, and the switching element M1 is turned off. At this time, the primary side current Ip becomes zero and decreases after the secondary side current Is starts to flow.

As described above, in the present embodiment, the switching element M1 is turned off at the timing t22'when the overcurrent is detected, but the first PWM signal pwm1 is set to Low at the subsequent timing t23', and the minimum off-time timers 161 and 1 are set. Since the / 2 on-time timer 162 is reset, the discharge time on the secondary side is extended by the period T1 of the timings t22'to t23'. Further, in the present embodiment, the off period is defined by measuring T2 for a period longer than the predetermined minimum off time by the 1/2 on-time timer 162, so that the discharge time is further extended.

As a result, the increase in the value at the start of the flow of the primary current Ip shown in FIG. 9A according to the comparative example increases from the amount of change ΔIp at the start of the flow of the primary current Ip shown in FIG. 9B according to the present embodiment. The amount of change ΔIp'can be suppressed. In FIG. 9A, the amount of increase change ΔIp becomes large, and the primary side current Ip reaches the OCP level immediately (timing t24), so that the charging time on the primary side becomes short and the increase of the output voltage becomes slow. On the other hand, in FIG. 9B, the time until the primary side current Ip reaches the OCP level (timing t25'to t26') is lengthened by suppressing the amount of increase change ΔIp', so that the primary side is on the primary side. The charging time can be secured and the rise of the output voltage Vout can be accelerated.

<About output timing control of differential circuit>
Next, the output timing control of the difference circuit 11 in the isolated switching power supply device 10 according to the present embodiment will be described. As described above, the difference circuit 11 outputs the REF terminal voltage VTref as it is or holds the output when the switching element M1 is off. FIG. 10 shows a configuration for controlling the output timing by the difference circuit 11. The timer unit 16 shown in FIG. 10 corresponds to a timing control unit.

The timer unit 16 shown in FIG. 10 includes a minimum off-time timer 1611, a 1/2 on-time timer 1621, an inverter 166, an AND circuit 167, a mask period timer 168, and a latch circuit 169. The timer unit 16 shown in FIG. 10 is the same as the timer unit 16 shown in FIG. 3 described above. That is, the timer unit 16 shown in FIG. 3 omits the configuration shown in FIG. Further has that configuration.

The minimum off-time timer 1611 measures 95% of the predetermined minimum off-time measured by the minimum off-time timer 161. The 1/2 on-time timer 1621 has the same configuration as the lamp counter shown in FIG. 5, and applies an output voltage V3 output by the filter 17 as a reference voltage of the comparator. The output voltage V3 is 95% of the above-mentioned output voltage V2 (FIG. 4). As a result, the 1/2 on-time timer 1621 measures an additional 95% of the on-time of 50%. The ratio of 95% for the minimum off-time timer 1611 and the 1/2 on-time timer 1621 is an example, and other ratios may be used as long as they are smaller than 100% (for example, a ratio of 70% or more). ).

The first PWM signal pwm1 output from the first latch circuit 141 is input to the inverter 166. The outputs of the minimum off-time timer 1611, the 1/2 on-time timer 1621, and the inverter 166 are input to the AND circuit 167. The output of the AND circuit 167 is input to the reset terminal of the latch circuit 169.

The mask period timer 168 measures a predetermined mask period (for example, 240 nsec). The output of the mask period timer 168 is input to the set terminal of the latch circuit 169. The output of the latch circuit 169 is input to the sample hold circuit 12 as a switch timing signal SWT.

Explaining the operation of such a configuration, when the first PWM signal pwm1 (and the second PWM signal pwm2) becomes Low and the switching element M1 is turned off, the mask period timer 168 is reset to start time measurement and the output is Low. Therefore, the output of the inverter 166 becomes High. At this time, both the minimum off-time timer 1611 and the 1/2 on-time timer 1621 are reset, time measurement is started, and the output of each timer becomes Low. When each time measurement is completed, the output of each timer becomes High.

When the mask period timer 168 measures a predetermined mask period, the output is set to High. Then, the latch circuit 169 is set, and the switch timing signal SWT is set to High. As a result, the switch (not shown) included in the difference circuit 11 is turned on, and the difference circuit 11 starts the operation of outputting the REF terminal voltage VTref as it is as the output VTref2.

After that, the later of the timing at which the minimum off-time timer 1611 measures 95% of the predetermined minimum off-time and the timing at which the 1/2 on-time timer 1621 measures an additional 95% of 50% of the on-time. At the timing of, the AND circuit 167 becomes High. Then, the latch circuit 169 is reset, and the switch timing signal SWT is set to Low. As a result, the switch included in the difference circuit 11 is turned off, and the difference circuit 11 holds the output VTref2 at the switching timing from on to off.

Here, FIG. 11 shows an example of a waveform of the switching voltage Vsw when the switching element M1 is turned off. As shown in FIG. 11, immediately after the switching element M1 is turned off, ringing occurs in the switching voltage Vsw due to the leakage inductance of the primary winding L1 of the transformer Tr1. Therefore, by masking only the mask period Tmsk with the mask period timer 168, the operation of outputting the REF terminal voltage VTref as it is is not performed during the period when ringing occurs.

When the mask period Tmsk elapses, the operation of outputting the REF terminal voltage VTref as it is is started. After that, the output is retained when the longer of the time Tmin_off of 95% of the predetermined minimum off time and the time T1 / 2on of 50% of the on time and further 95% of the on time elapses (FIG. 11). In the example, T1 / 2on is longer). When Tmin_off is longer, the switching element M1 is turned on after the timing when the predetermined minimum off time elapses, and when T1 / 2on is longer, the switching element is turned on after the timing when 50% of the on time elapses. M1 is turned on. Therefore, since the timing at which the output is held is earlier than the timing at which the switching element M1 is turned on, the output can be held when the secondary side current Is is flowing. That is, it is possible to prevent an abnormality from occurring in the output due to the overlap between the timing when the switching element M1 is turned on and the timing when the output is held.

Further, the REF terminal voltage VTref is a signal obtained by feeding back the flyback voltage VOR, and the flyback voltage VOR is represented by the above equation (1). In the equation (1), the forward voltage Vf of the diode D2 is the error, so the closer the secondary current Is is to zero, the smaller the Vf and the smaller the error. That is, the later the time, the more appropriate the timing for holding the output. When T1 / 2on is longer than Tmin_off, the timing of holding the output can be later in time.

<Modification example of switching element>
Next, a modified example of the insulated switching power supply device according to the present embodiment described above will be described. FIG. 12 shows the configuration of the insulated switching power supply device 10'according to the modified example. The isolated switching power supply device 10'shown in FIG. 12 includes a power supply control IC 1'.

The power supply control IC 1'has a configuration including a main switching element M11, a sub switching element M12, a resistor R12, and a comparator CP. In the power supply control IC 1', the components other than the configuration shown in FIG. 12 are the same as those in the above-described embodiment (FIG. 2).

The main switching element M11 composed of the N-channel MOSFET is a switching element that contributes to the generation of the output voltage Vout by the isolated switching power supply device 10'by being switched and driven. The drain (current inflow end) of the main switching element M11 is connected to the switching output terminal T3, and the source (current outflow end) is connected to the ground terminal T41.

The sub-switching element M12 is composed of an N-channel MOSFET. The drain (current inflow end) of the sub-switching element M12 is connected to the connection point between the drain of the main switching element M11 and the switching output terminal T3 via the resistor R12. The source (current outflow end) of the sub-switching element M12 is connected to the ground terminal T42.

An output terminal of a driver (not shown) is connected to the gate (control end) of the main switching element M11. The gate of the switching element M11 is connected to the non-inverting input terminal (+) of the comparator CP. A predetermined threshold voltage Vth1 is applied as a reference voltage to the inverting input terminal (−) of the comparator CP. The output end of the comparator CP is connected to the gate (control end) of the sub-switching element M12. The comparator CP corresponds to a voltage application unit.

Here, the operation of the configuration using the main switching element M11 and the sub-switching element M12 will be described with reference to FIG. FIG. 13 is a timing chart showing an example of each waveform when the main switching element M11 is turned off. In FIG. 13, from the top, the gate voltage Vg11 of the main switching element M11, the gate voltage Vg12 of the sub switching element M12, the current (drain current) I11 flowing through the main switching element M11, the secondary side current Is, the switching voltage Vsw, and the sub The current (drain current) I12 flowing through the switching element M12 is shown.

When the main switching element M11 is on (the sub-switching element M12 is off), at timing t31, a driver (not shown) starts extracting electric charge from the gate capacitance of the main switching element M11 in order to turn off the main switching element M11. To. Then, the gate voltage Vg11 of the main switching element M11 decreases. Then, after the gate voltage Vg11 reaches the mirror voltage Vm, the current I11 starts to decrease and the switching voltage Vsw starts to rise at the timing t32 when the gate voltage Vg11 falls below the mirror voltage Vm. Then, when the gate voltage Vg11 reaches the threshold voltage Vth1, the output of the comparator CP becomes Low (timing t33). As a result, the extraction of electric charge from the gate capacitance of the sub-switching element M12 is started, and the gate voltage Vg12 starts to decrease. Then, when the gate voltage Vg11 reaches the threshold voltage Vth11 of the main switching element M11, the current I11 becomes zero (timing t34).

During the period from the timing t32 to the timing t35 when the gate voltage Vg12 reaches the threshold voltage Vth12 of the sub-switching element Vg12, the current I12 flows through the sub-switching element M12 which is on. At the timing t35, the sub-switching element M12 is turned off and the current I12 stops flowing. Therefore, during the period from the timing t32 to the timing t34 when the current I11 of the main switching element M11 becomes zero, both the main switching element M11 and the sub switching element M12 are on. Then, during the period from the timing t34 to the timing t35, the main switching element M11 is off and the sub switching element M12 is on. Then, after the timing t35, both the main switching element M11 and the sub switching element M12 are turned off.

Here, the primary winding L1 of the transformer Tr1 has a leakage inductance, and when the switching element is on, a current flows through this leakage inductance and energy is stored, but it is combined with other windings. Power transfer is not performed because it is not installed. As a result, if the sub-switching element M12 is not provided, ringing will occur in the switching voltage Vsw for a long period of time when the main switching element M11 is turned off.

Therefore, in the present embodiment, the sub-switching element M12 is provided, and the current I12 is passed through the sub-switching element M12 when the main switching element M11 is turned off, so that ringing that occurs in the switching voltage Vsw can be suppressed. FIG. 12 shows that the peak value of the ringing (broken line) that occurs in the switching voltage Vsw when the sub-switching element M12 is not provided can be reduced to the peak value of the switching voltage Vsw shown by the solid line in this embodiment. ing.

Conventionally, a snubber circuit has been used to suppress ringing, but the snubber circuit is a circuit that is difficult for the user to design, and if the design fails, the switching element may be destroyed. According to this embodiment, ringing can be suppressed without using such a snubber circuit.

As described above, the threshold voltage Vth1 of the comparator CP is set between the mirror voltage Vm of the main switching element M11 and the threshold voltage Vth11 of the main switching element M11 itself, and the reason will be described. First, the current I11 flowing through the main switching element M11 decreases from the time when the gate voltage Vg11 drops below the mirror voltage Vm, and becomes zero when the gate voltage Vg11 reaches the threshold voltage Vth11. When the threshold voltage Vth1 is set to the mirror voltage Vm or higher, almost no current flows through the sub-switching element M12 during the period when the gate voltage Vg11 becomes the threshold voltage Vth1 to the mirror voltage Vm, so that the period does not function. Become. On the other hand, when the threshold voltage Vth1 is set to the threshold voltage Vth11 or less, the timing at which the gate voltage Vg12 reaches the threshold voltage Vth12 is delayed, and the current I12 excessively flows through the sub-switching element M12. Therefore, the threshold voltage Vth1 is lower than the mirror voltage Vm, and it is preferable to set the threshold voltage Vth1 between the mirror voltage Vm and the threshold voltage Vth11.

Further, the resistor R12 is provided in order to limit the current I12. There is a period (timing t32 to t34) in which the sub-switching element M12 is turned on when the main switching element M11 is on. In this period, the current flowing between the switching output terminal T3 and the ground terminals T41 and T42 is A current flows through the main switching element M11 having a low resistance, and almost no current flows through the sub-switching element M12 due to the resistance R12. This is because if the current I12 is passed too much, the rising voltage of the switching voltage Vsw becomes abnormally low when the main switching element M11 is turned off.

Further, in the present embodiment, the main switching element M11 and the sub-switching element M12 are preferably manufactured in the same process, and the main switching element M11 is larger in size than the sub-switching element M12 (for example, 1000: 1). Since they are manufactured in the same process, the main switching element M11 and the sub switching element M12 have the same variation and have the same characteristics. Therefore, the time from the start of the drop of the gate voltage to zero (or the threshold voltage of the switching element is reached) is almost the same in the main switching element M11 and the sub-switching element M12, and the current I11 of the main switching element M11 is When it reaches zero, it is guaranteed that the sub-switching element M12 is on. Further, when the size of the main switching element M11 is large, the current flowing in the steady on state is large, the capacitance of the parasitic capacitor that causes the resonance phenomenon is also large, and the effect of suppressing ringing by the sub switching element M12 is large.

Instead of the configuration using the comparator CP as described above, a delay circuit such as a filter that delays the voltage applied to the gate of the main switching element M11 and applies it to the gate of the sub-switching element M12 may be used. .. For example, if a delay time elapses before the current I11 of the main switching element M11 becomes zero and the sub-switching element M12 is kept on when the current of the main switching element M11 is zero, ringing is suppressed. be able to.

<Others>
Although the embodiments of the present invention have been described above, the embodiments can be modified in various ways within the scope of the gist of the present invention.

For example, the switching element may be provided outside the power supply control IC instead of being provided.

Further, the insulated switching power supply device according to the present invention is preferably used for, for example, an inverter for industrial equipment such as a solar inverter, an FA inverter, and a power storage system.

The present invention can be used, for example, in an isolated switching power supply device for an inverter.

1 Power control IC
10 Insulated switching power supply Tr1 Transformer L1 Primary winding L2 Secondary winding D2 Diode C2 Smoothing capacitor T1 Power supply terminal T2 Feedback terminal T3 Switching output terminal T4 Ground terminal T5 REF terminal R11, R12 Resistance 11 Difference circuit
13 Comparator 14 Logic part 15 Driver 16 Timer part 17 Filter 18 Ripple generation part 19 OCP part M1 Switching element 141 1st latch circuit 142 2nd latch circuit 143 to 145 AND circuit 146 OR circuit 161 Minimum off time timer 162 1/2 on Time timer 163 Minimum on-time timer 164 On-time timer 165 Inverter 166 Inverter 167 AND circuit 168 Mask period timer 169 Latch circuit 1611 Minimum off-time timer 1621 1/2 On-time timer M11 Main switching element M12 Sub-switching element R12 Resistance CP comparator T41 , T42 ground terminal

Claims (6)

A power supply control device used in an isolated switching power supply device including a transformer including a primary winding and a secondary winding in which an input voltage application end is connected to one end .
A main switching element in which a current inflow end is connected to the other end of the primary winding,
An auxiliary switching element to which the current inflow end is connected to the current inflow end of the main switching element,
A state in which both the main switching element and the sub-switching element are turned on, a state in which the main switching element is turned off and the sub-switching element is turned on, and a state in which both the main switching element and the sub-switching element are turned off. A voltage application unit that applies a voltage to the control end of the sub-switching element so as to transition in the order of
Equipped with a,
The voltage application unit is a comparator and is
A control end of the main switching element is connected to one input end of the comparator.
A predetermined threshold voltage is applied to the other input end of the comparator as a reference voltage.
The output end of the comparator is connected to the control end of the sub-switching element .
A power supply control device characterized in that the threshold voltage is set to a value lower than the mirror voltage of the main switching element. The power supply control device according to claim 1 , wherein the threshold voltage is set between the mirror voltage and the threshold voltage of the main switching element itself. The power supply control device according to claim 1 or 2 , wherein the current inflow end of the sub-switching element is connected to the current inflow end of the main switching element via a resistance element. The power supply control device according to any one of claims 1 to 3 , wherein the main switching element and the sub-switching element are manufactured in the same process. The power supply control device according to any one of claims 1 to 4 , wherein the main switching element is larger in size than the sub switching element. An insulated switching power supply device comprising the power supply control device according to any one of claims 1 to 5 and a transformer.

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