JP2018037614A - Circuit device - Google Patents

Circuit device Download PDF

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JP2018037614A
JP2018037614A JP2016172004A JP2016172004A JP2018037614A JP 2018037614 A JP2018037614 A JP 2018037614A JP 2016172004 A JP2016172004 A JP 2016172004A JP 2016172004 A JP2016172004 A JP 2016172004A JP 2018037614 A JP2018037614 A JP 2018037614A
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substrate
electronic component
solder
land
lands
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JP6576892B2 (en
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吉田　勇
Isamu Yoshida
勇 吉田
俊和 執行
Toshikazu Shigyo
俊和 執行
勝 鴨志田
Masaru Kamoshita
勝 鴨志田
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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Abstract

PROBLEM TO BE SOLVED: To solve such a problem that the production process of a board increases to cause increase in manufacturing cost of the board.SOLUTION: The electrode 4 of an electronic component 3 is connected with lands 2a, 2b formed on a board 1 by means of a solder 5. On the lateral face 6 between the lands 2a, 2b, solder 5 gets wet and a fillet 7 is formed. Since a path through which voids escape can also be secured from the bottom face side of the solder 5, voids of the solder 5 can be reduced. The lateral faces 6 between the lands 2a, 2b allows for soldering 5 in a shape close to NSMD structure by forming the fillet 7, and connection reliability of the electrode 4 and the land 2 can be improved. Although crack of the solder 5 progresses from the bottom face side to the side surface side of the electronic component 3, connection reliability with the solder 5 is improved because the land 2b extends to the outside of the arrangement position of the electronic component 3.SELECTED DRAWING: Figure 5

Description

本発明は、回路装置に関する。   The present invention relates to a circuit device.

基板上にチップ抵抗器などの電子部品を設置する場合には、電子部品の電極と基板のランドとの接続に、はんだが用いられる。電子部品の電極とランドとのはんだによる接続箇所には、各部材の線膨張係数の差に起因して熱疲労による応力やひずみが発生する。そのため、各部材の最も弱い箇所から破壊が発生して進行する。一般的には、はんだ内で破壊することが多い。このはんだ内での破壊を抑制し、接続の信頼性を向上する為に、電極とランドの間の距離を伸ばして、はんだの厚さを厚くする方法がある。はんだは、厚さが厚くなることにより許容変形量が増加し、熱疲労により発生する応力やひずみを低減し、接続の信頼性が向上する。   When an electronic component such as a chip resistor is installed on the substrate, solder is used to connect the electrode of the electronic component and the land of the substrate. Stresses and strains due to thermal fatigue are generated at soldered connection points between the electrodes and lands of the electronic component due to differences in the linear expansion coefficients of the respective members. Therefore, the breakage occurs and proceeds from the weakest part of each member. Generally, it often breaks in the solder. In order to suppress the breakage in the solder and improve the connection reliability, there is a method of increasing the thickness of the solder by increasing the distance between the electrode and the land. As the thickness of the solder increases, the amount of allowable deformation increases, stress and strain generated by thermal fatigue are reduced, and connection reliability is improved.

チップ抵抗器などの電子部品は、はんだの厚さを確保するのが難しい。電子部品は、部品の側面と上下面に電極が形成されている。電子部品の電極とランドとをはんだで接続すると、はんだの表面張力や電子部品の重量、ランドの形状から、はんだは電子部品の側面側の接続に多く移動するため電子部品の底面側のはんだの厚さは薄くなる傾向にある。はんだが薄くなると許容できる変形量が小さいため、各部材の線膨張係数の差に起因して熱疲労による応力やひずみではんだ内の破壊が進行しやすい。また、はんだ内の小さいボイドも破壊の進行を助けることになる。   Electronic components such as chip resistors are difficult to ensure the solder thickness. In the electronic component, electrodes are formed on the side surface and the upper and lower surfaces of the component. When the electrodes and lands of an electronic component are connected by solder, the solder moves to the connection on the side of the electronic component due to the surface tension of the solder, the weight of the electronic component, and the shape of the land. The thickness tends to be thin. Since the amount of deformation that can be tolerated is small when the solder is thin, destruction within the solder is likely to proceed due to stress and strain due to thermal fatigue due to differences in the linear expansion coefficients of the members. In addition, small voids in the solder will help the progress of destruction.

特許文献１には、はんだの接続部の信頼性を向上する技術が開示されている。この技術は、１つのランドに厚さの異なる厚肉部と薄肉部を形成し、厚肉部は少なくとも電極の直下に形成することにより、はんだの厚さを確保するものである。そして、ランドの厚肉部となる箇所にレジストマスクを形成し、エッチング処理を施すことにより薄肉部を形成し、レジストマスクを除去することにより厚肉部を形成するという工程を行う。   Patent Document 1 discloses a technique for improving the reliability of a solder connection portion. In this technique, a thick portion and a thin portion having different thicknesses are formed on one land, and the thick portion is formed at least directly below the electrode, thereby ensuring the thickness of the solder. Then, a process is performed in which a resist mask is formed at a portion to be a thick portion of the land, a thin portion is formed by performing an etching process, and a thick portion is formed by removing the resist mask.

特開２０１４−２２０３３６号公報JP 2014-220336 A

上述した特許文献１に記載の技術では、基板の製造工程が多くなり、基板の製造コストがアップするという問題があった。   The technique described in Patent Document 1 described above has a problem that the manufacturing process of the substrate increases and the manufacturing cost of the substrate increases.

本発明の第１の態様による回路装置は、電極が形成された電子部品と、前記電子部品の１つの電極に対して複数のランドが形成された基板と、前記電極と前記ランドとを接続するはんだと、を備える。
本発明の第２の態様による回路装置は、電極が形成された電子部品と、前記電子部品の１つの電極に対してランドが形成された基板と、前記電子部品と前記基板との間に設けられ、前記電子部品を前記基板から離間して固定する固定部材と、前記電極と前記ランドとを接続するはんだと、を備え、前記電子部品は、所定の搭載領域において前記基板と対向するように前記基板上に設置されており、前記ランドは、前記搭載領域の外側に配置される。 A circuit device according to a first aspect of the present invention connects an electronic component on which an electrode is formed, a substrate on which a plurality of lands are formed with respect to one electrode of the electronic component, and the electrode and the land. Solder.
A circuit device according to a second aspect of the present invention is provided with an electronic component on which an electrode is formed, a substrate on which a land is formed with respect to one electrode of the electronic component, and the electronic component and the substrate. A fixing member that fixes the electronic component apart from the substrate, and a solder that connects the electrode and the land, and the electronic component faces the substrate in a predetermined mounting region. The land is disposed on the substrate, and the land is disposed outside the mounting area.

本発明によれば、基板の製造工程を多くすることなく、基板のランドと電子部品の電極との接続信頼性を向上できる。   According to the present invention, it is possible to improve the connection reliability between the land of the substrate and the electrode of the electronic component without increasing the number of manufacturing steps of the substrate.

第１の実施形態における電子部品を設置した基板の斜視図である。It is a perspective view of the board | substrate which installed the electronic component in 1st Embodiment. 第１の実施形態における電子部品を設置した基板の断面位置を示す図である。It is a figure which shows the cross-sectional position of the board | substrate which installed the electronic component in 1st Embodiment. 第１の実施形態における電子部品を設置した基板の断面図である。It is sectional drawing of the board | substrate which installed the electronic component in 1st Embodiment. 第１の実施形態における基板の上面図である。It is a top view of the board | substrate in 1st Embodiment. 第１の実施形態における電子部品を設置した基板の拡大断面図である。It is an expanded sectional view of the board | substrate which installed the electronic component in 1st Embodiment. 第２の実施形態における基板の上面図である。It is a top view of the board | substrate in 2nd Embodiment. 第２の実施形態における基板の断面図である。It is sectional drawing of the board | substrate in 2nd Embodiment. 第３の実施形態における基板の上面図である。It is a top view of the board | substrate in 3rd Embodiment. 第３の実施形態における基板の断面図である。It is sectional drawing of the board | substrate in 3rd Embodiment. 第４の実施形態における基板の上面図である。It is a top view of the board | substrate in 4th Embodiment. 第４の実施形態における基板の断面図である。It is sectional drawing of the board | substrate in 4th Embodiment.

（第１の実施形態）
本発明による回路装置の第１の実施形態について、図１〜図５を参照して説明する。
図1は、電子部品を設置した基板の斜視図である。基板１にはランド２が形成されている。電子部品３は略長方形の本体の両端に電極４が形成されている。そして、はんだ５によってランド２と電極４は電気的に接続され、電子部品３は基板１に設置される。基板１は、プリント基板、セラミック基板、フレキシブル基板などである。 (First embodiment)
A first embodiment of a circuit device according to the present invention will be described with reference to FIGS.
FIG. 1 is a perspective view of a substrate on which electronic components are installed. A land 2 is formed on the substrate 1. The electronic component 3 has electrodes 4 formed on both ends of a substantially rectangular main body. The land 2 and the electrode 4 are electrically connected by the solder 5, and the electronic component 3 is installed on the substrate 1. The substrate 1 is a printed substrate, a ceramic substrate, a flexible substrate, or the like.

基板１に電子部品３を一つ設置した例で説明するが、基板１には多種多様な電子部品が多数設置されている。また、基板１には、各電子部品３の電極が接続されるランドが多数形成され、その各ランドを電気的に接続する配線が施されている。さらに、基板１の表面には配線を保護するレジストがあってもよい。また、基板１は片面実装基板の例で説明するが、両面実装基板もしくは多層基板であってもよい。   Although an example in which one electronic component 3 is installed on the substrate 1 will be described, a large number of various electronic components are installed on the substrate 1. In addition, a large number of lands to which the electrodes of the respective electronic components 3 are connected are formed on the substrate 1, and wirings for electrically connecting the lands are provided. Further, a resist for protecting the wiring may be provided on the surface of the substrate 1. Moreover, although the board | substrate 1 demonstrates with the example of a single-sided mounting board | substrate, a double-sided mounting board | substrate or a multilayer board | substrate may be sufficient.

ランド２の材質は、ＣｕやＡｇなどが用いられる。また、ランド２の形状で接続信頼性を向上する方法として、ＳＭＤ（Solder Mask Defined）構造をＮＳＭＤ（Non Solder Mask Defined）構造にすることが知られている。ＳＭＤ構造は、ランド２の周辺上部までレジストを設ける。一方、ＮＳＭＤ構造は、ランド２の全域にレジストが存在しない構造である。ＮＳＭＤ構造は、はんだ５がランド２の側面まで濡れることが特徴であり、はんだ５がランド２の側面まで濡れるため接続面積が増加し、熱応力を低減することにより接続信頼性が向上する。   The material of the land 2 is Cu, Ag, or the like. Further, as a method for improving the connection reliability with the shape of the land 2, it is known to change the SMD (Solder Mask Defined) structure to an NSMD (Non Solder Mask Defined) structure. In the SMD structure, a resist is provided up to the upper periphery of the land 2. On the other hand, the NSMD structure is a structure in which no resist exists in the entire land 2. The NSMD structure is characterized in that the solder 5 is wetted to the side surface of the land 2, and the solder 5 is wetted to the side surface of the land 2, so that the connection area is increased and the connection reliability is improved by reducing the thermal stress.

電極４は、メッキで作ることが多く、下地にＮｉ、Ｃｕ、もしくはＮｉとＣｕの２層からなる構造が多く、表面にＳｎ、Ｃｕ、Ａｕなどで形成されている。
基板１やランド２や電極４等の各部材の材質や構造は、用途、放熱性、電気特性、コスト、長期信頼性などの観点から決定する。 The electrode 4 is often made by plating, and has a structure composed of Ni, Cu, or two layers of Ni and Cu on the base, and is formed of Sn, Cu, Au, or the like on the surface.
The material and structure of each member such as the substrate 1, the land 2, and the electrode 4 are determined from the viewpoint of application, heat dissipation, electrical characteristics, cost, long-term reliability, and the like.

図２は、電子部品３を設置した基板１の断面位置を示す図である。断面Ａは、電子部品３の短辺の中央部であって電子部品３の長辺方向に沿った切断を示す。   FIG. 2 is a diagram showing a cross-sectional position of the substrate 1 on which the electronic component 3 is installed. The cross section A is a central portion of the short side of the electronic component 3 and shows a cut along the long side direction of the electronic component 3.

図３は、電子部品３を設置した基板１の断面図であり、図２に示す断面Ａである。
電子部品３の両端には電極４が形成されており、基板１には電子部品３の電極４に対してランド２が形成されている。電極４とランド２の間には両者を電気的に接続し、電子部品３を基板１に固定するためのはんだ５が施されている。 3 is a cross-sectional view of the substrate 1 on which the electronic component 3 is installed, and is a cross-section A shown in FIG.
Electrodes 4 are formed on both ends of the electronic component 3, and lands 2 are formed on the substrate 1 with respect to the electrodes 4 of the electronic component 3. Solder 5 is applied between the electrode 4 and the land 2 for electrically connecting the two and the electronic component 3 to the substrate 1.

図４は、基板１を上から見た上面図である。この図では、基板１上から電子部品３及びはんだ５を除いた状態で、ランド２の形状を示す。電子部品３は、図中に破線で示す搭載領域８において基板１と対向するように基板１上に設置される。ランド２は、図４に示すように、電子部品３の１つの電極に対して二つのランド２ａ、２ｂが形成されている。そして、ランド２ａの少なくとも一部分は、搭載領域８の内側に配置される。ランド２ｂは搭載領域８の外側に配置される。なお、ランド２ａ、２ｂはＮＳＭＤ構造になっており、ランド２ａ、２ｂの間の側面部６は、はんだ５が濡れる。   FIG. 4 is a top view of the substrate 1 as viewed from above. In this figure, the shape of the land 2 is shown with the electronic component 3 and the solder 5 removed from the substrate 1. The electronic component 3 is installed on the substrate 1 so as to face the substrate 1 in a mounting region 8 indicated by a broken line in the drawing. In the land 2, two lands 2 a and 2 b are formed for one electrode of the electronic component 3 as shown in FIG. 4. At least a part of the land 2 a is disposed inside the mounting area 8. The land 2 b is disposed outside the mounting area 8. The lands 2a and 2b have an NSMD structure, and the solder 5 gets wet on the side surface 6 between the lands 2a and 2b.

図５は、電子部品３を設置した基板１の拡大断面図であり、図３のＢ部分である。
電子部品３の電極４は、基板１に形成されたランド２ａ、２ｂとはんだ５によって接続される。ランド２ａ、２ｂの間の側面部６は、はんだ５が濡れてフィレット７が形成される。そのため、はんだ５の底面側からもボイドが抜ける経路を確保できるのではんだ５内のボイドを低減することができる。 FIG. 5 is an enlarged cross-sectional view of the substrate 1 on which the electronic component 3 is installed, and is a portion B of FIG.
The electrode 4 of the electronic component 3 is connected to lands 2 a and 2 b formed on the substrate 1 by solder 5. In the side surface portion 6 between the lands 2a and 2b, the solder 5 gets wet and a fillet 7 is formed. Therefore, since a path through which voids can be removed also from the bottom surface side of the solder 5 can be secured, voids in the solder 5 can be reduced.

ランド２ａ、２ｂの間の側面部６は、フィレット７を形成し、ＮＳＭＤ構造に近い形状にはんだ５を施すことができ、電極４とランド２との接続信頼性を向上することができる。また、はんだ５に亀裂が生じた場合、その亀裂は電子部品３の底面側から側面側へ進展するが、ランド２ｂが電子部品３の配置位置の外側へ伸びているので、はんだ５との接続信頼性が向上する。   The side surface portion 6 between the lands 2a and 2b forms a fillet 7, and the solder 5 can be applied in a shape close to the NSMD structure, so that the connection reliability between the electrode 4 and the land 2 can be improved. Further, when a crack occurs in the solder 5, the crack progresses from the bottom surface side to the side surface side of the electronic component 3. Reliability is improved.

（第２の実施形態）
本発明による回路装置の第２の実施形態について、図６〜図７を参照して説明する。
なお、第２の実施形態においても、第１の実施形態で図示した図１の電子部品を設置した基板の斜視図、図２の電子部品を設置した基板の断面位置を示す図、図３の電子部品を設置した基板の断面図、図５の電子部品を設置した基板の拡大断面図は同様であるので、図示およびその説明を省略する。 (Second Embodiment)
A second embodiment of the circuit device according to the present invention will be described with reference to FIGS.
Also in the second embodiment, a perspective view of the board on which the electronic component of FIG. 1 illustrated in the first embodiment is installed, a cross-sectional position of the board on which the electronic component of FIG. 2 is installed, FIG. Since the cross-sectional view of the substrate on which the electronic component is installed and the enlarged cross-sectional view of the substrate on which the electronic component in FIG.

図６は、基板１を上から見た上面図である。この図では、基板１上から電子部品３及びはんだ５を除いた状態で、ランド２の形状を示す。電子部品３は、図中に破線で示す搭載領域８において基板１と対向するように基板１上に設置される。ランド２は、図６に示すように、電子部品３の１つの電極に対して二つのランド２ａ、２ｂが形成されている。そして、ランド２ａは、搭載領域８の内側に配置され、且つ、電子部品３の短辺よりも短い。ランド２ｂは搭載領域８の外側に配置され、ランド２ａの面積よりも大きい。   FIG. 6 is a top view of the substrate 1 as viewed from above. In this figure, the shape of the land 2 is shown with the electronic component 3 and the solder 5 removed from the substrate 1. The electronic component 3 is installed on the substrate 1 so as to face the substrate 1 in a mounting region 8 indicated by a broken line in the drawing. In the land 2, two lands 2 a and 2 b are formed for one electrode of the electronic component 3 as shown in FIG. 6. The land 2 a is disposed inside the mounting area 8 and is shorter than the short side of the electronic component 3. The land 2b is disposed outside the mounting area 8, and is larger than the area of the land 2a.

図７は、図６のＣ−Ｃ’断面図である。なお、図７は、電子部品３の電極４をはんだ５でランド２ａと接続した状態の断面図である。図７に示すように、ランド２ａの面積を小さくしているので、電子部品３の底面側のはんだ５の量が少なくなる。このため、ランド２ａの位置で発生したはんだ５の亀裂は、ランド２ｂの位置のはんだ５に伝わることを遅延させることができ、接続信頼性の向上ができる。また、はんだ５の底面側からもボイドが抜ける経路を確保できるので、はんだ５のボイドを低減することができる。   FIG. 7 is a cross-sectional view taken along the line C-C ′ in FIG. 6. FIG. 7 is a cross-sectional view of the state in which the electrode 4 of the electronic component 3 is connected to the land 2 a with the solder 5. As shown in FIG. 7, since the area of the land 2a is reduced, the amount of solder 5 on the bottom side of the electronic component 3 is reduced. For this reason, the crack of the solder 5 generated at the position of the land 2a can be delayed from being transmitted to the solder 5 at the position of the land 2b, and the connection reliability can be improved. Further, since a path through which voids can be removed also from the bottom surface side of the solder 5 can be secured, voids in the solder 5 can be reduced.

（第３の実施形態）
本発明による回路装置の第３の実施形態について、図８〜図９を参照して説明する。
なお、第３の実施形態においても、基板１やランド２や電極４等の各部材の材質や構造は第１の実施形態で説明したものと同様である。 (Third embodiment)
A third embodiment of the circuit device according to the present invention will be described with reference to FIGS.
In the third embodiment, the material and structure of each member such as the substrate 1, the land 2, and the electrode 4 are the same as those described in the first embodiment.

図８は、基板１を上から見た上面図である。この図では、基板１上から電子部品３及びはんだ５を除いた状態で、ランド２の形状を示すものである。電子部品３は、図中に破線で示す搭載領域８において基板１と対向するように基板１上に設置される。ランド２は、図８に示すように、電子部品３の１つの電極に対して三つのランド２ａ、２ｂ、２ｃが形成されている。そして、ランド２ａの少なくとも一部分は、搭載領域８の内側に配置される。ランド２ｂ、２ｃは搭載領域８の外側に配置され、ランド２ｂ、２ｃは離間して配置される。   FIG. 8 is a top view of the substrate 1 as viewed from above. In this figure, the shape of the land 2 is shown with the electronic component 3 and the solder 5 removed from the substrate 1. The electronic component 3 is installed on the substrate 1 so as to face the substrate 1 in a mounting region 8 indicated by a broken line in the drawing. In the land 2, three lands 2 a, 2 b, and 2 c are formed for one electrode of the electronic component 3 as shown in FIG. 8. At least a part of the land 2 a is disposed inside the mounting area 8. The lands 2b and 2c are arranged outside the mounting area 8, and the lands 2b and 2c are arranged apart from each other.

図９は、図８のＤ−Ｄ’断面図である。なお、図９は、電子部品３の電極４をはんだ５でランド２ｂ、２ｃと接続した状態の断面図である。また、図８のＥ−Ｅ’断面図は、第１の実施形態で図示した図５の拡大断面図と同様であり、その説明を省略する。図９に示すように、ランド２ｂ、２ｃの間の側面部６には、フィレット７が形成され、ＮＳＭＤ構造ではんだ５を施すことができ、接続信頼性を向上できる。また、ランド２ｂ、２ｃの間からもボイドが抜ける経路を確保しているのではんだ５内のボイドを低減することができる。   9 is a cross-sectional view taken along the line D-D ′ of FIG. 8. FIG. 9 is a cross-sectional view of the state in which the electrode 4 of the electronic component 3 is connected to the lands 2 b and 2 c with the solder 5. 8 is the same as the enlarged sectional view of FIG. 5 illustrated in the first embodiment, and a description thereof will be omitted. As shown in FIG. 9, a fillet 7 is formed on the side surface portion 6 between the lands 2b and 2c, and solder 5 can be applied with an NSMD structure, thereby improving connection reliability. In addition, since a path through which voids come out from between the lands 2b and 2c is secured, voids in the solder 5 can be reduced.

なお、搭載領域８の外側に配置されるランド２ｂ、２ｃは、二つ設けたが、ランドを分割して三つ以上設けてもよい。この場合、各ランド間にフィレット７が各々形成されるので、更に接続信頼性を向上できる。   Although two lands 2b and 2c arranged outside the mounting area 8 are provided, three or more lands may be provided by dividing the lands. In this case, since the fillet 7 is formed between the lands, the connection reliability can be further improved.

（第４の実施形態）
本発明による回路装置の第４の実施形態について、図１０〜図１１を参照して説明する。
なお、第４の実施形態においても、第１の実施形態で図示した図１の電子部品を設置した基板の斜視図は同様であるので、図示およびその説明を省略する。また、基板１やランド２や電極４等の各部材の材質や構造は第１の実施形態で説明したものと同様である。 (Fourth embodiment)
A fourth embodiment of the circuit device according to the present invention will be described with reference to FIGS.
In the fourth embodiment as well, the perspective view of the substrate on which the electronic component of FIG. 1 illustrated in the first embodiment is installed is the same, and the illustration and description thereof are omitted. The material and structure of each member such as the substrate 1, the land 2, and the electrode 4 are the same as those described in the first embodiment.

図１０は、基板１を上から見た上面図である。この図では、基板１上から電子部品３及びはんだ５を除いた状態を図示する。電子部品３は、図中に破線で示す搭載領域８において基板１と対向するように基板１上に設置される。基板１上には、ランド２ｄが形成され、電子部品３を支持固定する固定部材９が設置されている。ランド２ｄは搭載領域８の外側に配置される。固定部材９は円筒形状で絶縁性の高いエポキシ樹脂であり、搭載領域８の略中央部に固定的に設置される。   FIG. 10 is a top view of the substrate 1 as viewed from above. This figure shows a state where the electronic component 3 and the solder 5 are removed from the substrate 1. The electronic component 3 is installed on the substrate 1 so as to face the substrate 1 in a mounting region 8 indicated by a broken line in the drawing. A land 2 d is formed on the substrate 1, and a fixing member 9 that supports and fixes the electronic component 3 is installed. The land 2 d is disposed outside the mounting area 8. The fixing member 9 is a cylindrical and highly insulating epoxy resin, and is fixedly installed at a substantially central portion of the mounting region 8.

図１１は、図１０のＦ−Ｆ’断面図である。なお、図１１は、電子部品３の電極４をはんだ５でランド２ｄと接続した状態の断面図である。電子部品３の両端には電極４が形成されており、基板１には電子部品３の電極４に対してランド２ｄが形成されている。電極４とランド２ｄの間には両者を電気的に接続し、電子部品３を基板１に固定するためのはんだ５が施されている。固定部材９は、電子部品３を基板１から離間する間隔を決定するもので、固定部材９の厚さはランド２ｄの厚さよりも大きくする。なお、固定部材９は円筒形状に限らず、電子部品３を基板１から離間するものであればその形状を問わない。
固定部材９により、電子部品３を高い位置に固定することにより、はんだ５の厚さを厚く確保することができ、接続信頼性を向上することができる。 11 is a cross-sectional view taken along the line FF ′ of FIG. FIG. 11 is a cross-sectional view of the state in which the electrode 4 of the electronic component 3 is connected to the land 2d with the solder 5. Electrodes 4 are formed on both ends of the electronic component 3, and lands 2 d are formed on the substrate 1 with respect to the electrodes 4 of the electronic component 3. Solder 5 is applied between the electrode 4 and the land 2d to electrically connect them and fix the electronic component 3 to the substrate 1. The fixing member 9 determines an interval at which the electronic component 3 is separated from the substrate 1. The thickness of the fixing member 9 is larger than the thickness of the land 2 d. The fixing member 9 is not limited to a cylindrical shape, and may be any shape as long as the electronic component 3 is separated from the substrate 1.
By fixing the electronic component 3 at a high position by the fixing member 9, the thickness of the solder 5 can be ensured thick, and the connection reliability can be improved.

なお、搭載領域８の外側に配置されるランド２ｄは、一つ設けたが、ランド２ｄを分割して二つ以上設けてもよい。この場合、第３の実施形態で説明したように、各ランド間にフィレット７が各々形成されるので、更に接続信頼性を向上できる。   Although one land 2d arranged outside the mounting area 8 is provided, two or more lands 2d may be provided by dividing the land 2d. In this case, as described in the third embodiment, since the fillets 7 are formed between the lands, connection reliability can be further improved.

以上説明した実施形態によれば、次の作用効果が得られる。
（１）第１〜第３の実施形態では、回路装置は、電極４が形成された電子部品３と、電子部品３の１つの電極４に対して複数のランド２（２ａ、２ｂ、２ｃ）が形成された基板１と、電極４とランド２とを接続するはんだ５と、を備えた。これにより、基板の製造工程を多くすることなく、基板のランドと電子部品の電極との接続信頼性を向上できる。
（２）第４の実施形態では、回路装置は、電極４が形成された電子部品３と、電子部品３の１つの電極４に対してランド２ｄが形成された基板１と、電子部品３と基板１との間に設けられ、電子部品３を基板１から離間して固定する固定部材９と、電極４とランド２ｄとを接続するはんだ５と、を備える。電子部品３は、所定の搭載領域８において基板１と対向するように基板１上に設置されており、ランド２ｄは、搭載領域８の外側に配置される。これにより、第１〜第３の実施形態と同様に、基板の製造工程を多くすることなく、基板のランドと電子部品の電極との接続信頼性を向上できる。 According to the embodiment described above, the following operational effects can be obtained.
(1) In the first to third embodiments, the circuit device includes an electronic component 3 on which the electrode 4 is formed, and a plurality of lands 2 (2a, 2b, 2c) with respect to one electrode 4 of the electronic component 3. And a solder 5 for connecting the electrode 4 and the land 2 to each other. Thereby, the connection reliability between the land of the substrate and the electrode of the electronic component can be improved without increasing the number of manufacturing steps of the substrate.
(2) In the fourth embodiment, the circuit device includes an electronic component 3 on which an electrode 4 is formed, a substrate 1 on which a land 2d is formed with respect to one electrode 4 of the electronic component 3, an electronic component 3, A fixing member 9 provided between the substrate 1 and fixing the electronic component 3 away from the substrate 1 and a solder 5 connecting the electrode 4 and the land 2d are provided. The electronic component 3 is installed on the substrate 1 so as to face the substrate 1 in a predetermined mounting area 8, and the land 2 d is disposed outside the mounting area 8. Thereby, similarly to the first to third embodiments, the connection reliability between the land of the substrate and the electrode of the electronic component can be improved without increasing the number of manufacturing steps of the substrate.

本発明は、上記の実施形態に限定されるものではなく、本発明の特徴を損なわない限り、本発明の技術思想の範囲内で考えられるその他の形態についても、本発明の範囲内に含まれる。また、上述の各実施形態を組み合わせた構成としてもよい。   The present invention is not limited to the above-described embodiment, and other forms conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention as long as the characteristics of the present invention are not impaired. . Moreover, it is good also as a structure which combined each above-mentioned embodiment.

１ 基板
２、２ａ、２ｂ、２ｃ、２ｄ ランド
３ 電子部品
４ 電極
５ はんだ
７ フィレット
９ 固定部材 1 Substrate 2, 2a, 2b, 2c, 2d Land 3 Electronic component 4 Electrode 5 Solder 7 Fillet 9 Fixing member

Claims (7)

電極が形成された電子部品と、
前記電子部品の１つの電極に対して複数のランドが形成された基板と、
前記電極と前記ランドとを接続するはんだと、を備えた回路装置。 An electronic component having electrodes formed thereon;
A substrate on which a plurality of lands are formed for one electrode of the electronic component;
A circuit device comprising solder for connecting the electrode and the land. 請求項１に記載の回路装置において、
前記電子部品は、所定の搭載領域において前記基板と対向するように前記基板上に設置されており、
前記複数のランドのうち少なくとも一つのランドは、前記搭載領域の外側に配置される回路装置。 The circuit device according to claim 1,
The electronic component is installed on the substrate so as to face the substrate in a predetermined mounting area,
At least one of the plurality of lands is a circuit device disposed outside the mounting area. 請求項２に記載の回路装置において、
前記搭載領域の外側に配置されるランドの面積は、少なくとも一部分が前記搭載領域の内側に配置されるランドの面積よりも大きい回路装置。 The circuit device according to claim 2,
A circuit device in which an area of a land arranged outside the mounting region is at least partially larger than an area of a land arranged inside the mounting region. 請求項２または請求項３に記載の回路装置において、
前記搭載領域の外側に配置されるランドを複数備える回路装置。 The circuit device according to claim 2 or claim 3,
A circuit device comprising a plurality of lands arranged outside the mounting area. 電極が形成された電子部品と、
前記電子部品の１つの電極に対してランドが形成された基板と、
前記電子部品と前記基板との間に設けられ、前記電子部品を前記基板から離間して固定する固定部材と、
前記電極と前記ランドとを接続するはんだと、を備え、
前記電子部品は、所定の搭載領域において前記基板と対向するように前記基板上に設置されており、
前記ランドは、前記搭載領域の外側に配置される回路装置。 An electronic component having electrodes formed thereon;
A substrate on which lands are formed for one electrode of the electronic component;
A fixing member provided between the electronic component and the substrate and fixing the electronic component apart from the substrate;
Solder for connecting the electrode and the land,
The electronic component is installed on the substrate so as to face the substrate in a predetermined mounting area,
The land is a circuit device arranged outside the mounting area. 請求項５に記載の回路装置において、
前記固定部材は、前記電子部品を前記基板から離間する間隔が前記ランドの厚さよりも大きくなる厚さを有する回路装置。 The circuit device according to claim 5,
The fixing device is a circuit device having a thickness such that an interval at which the electronic component is separated from the substrate is larger than a thickness of the land. 請求項５または請求項６に記載の回路装置において、
前記ランドは複数のランドよりなる回路装置。 In the circuit device according to claim 5 or 6,
The land is a circuit device comprising a plurality of lands.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150857U (en) * 1982-04-05 1983-10-08 株式会社東芝 printed wiring board
JPH044779U (en) * 1990-04-26 1992-01-16
JPH07122846A (en) * 1993-10-21 1995-05-12 Advantest Corp Soldering method of small surface mounting part
JPH07202394A (en) * 1993-12-28 1995-08-04 Matsushita Electric Ind Co Ltd Printed circuit board
JP2008060182A (en) * 2006-08-30 2008-03-13 Hitachi Ltd In-vehicle electronic circuit device
JP2009111108A (en) * 2007-10-30 2009-05-21 Nec Corp Mounting structure and mounting method of chip component
JP2012216658A (en) * 2011-03-31 2012-11-08 Tdk Corp Circuit board, packaged electronic component, and method for mounting electronic component

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150857U (en) * 1982-04-05 1983-10-08 株式会社東芝 printed wiring board
JPH044779U (en) * 1990-04-26 1992-01-16
JPH07122846A (en) * 1993-10-21 1995-05-12 Advantest Corp Soldering method of small surface mounting part
JPH07202394A (en) * 1993-12-28 1995-08-04 Matsushita Electric Ind Co Ltd Printed circuit board
JP2008060182A (en) * 2006-08-30 2008-03-13 Hitachi Ltd In-vehicle electronic circuit device
JP2009111108A (en) * 2007-10-30 2009-05-21 Nec Corp Mounting structure and mounting method of chip component
JP2012216658A (en) * 2011-03-31 2012-11-08 Tdk Corp Circuit board, packaged electronic component, and method for mounting electronic component

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