JP2018030765A - Method for manufacturing silicon single crystal wafer, method for manufacturing silicon epitaxial wafer, silicon single crystal wafer and silicon epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon single crystal wafer capable of uniformly forming a high-density BMD in the in-plane and preventing a PID from occurring, having less void-like defects and a wide DZ width and having excellent oxide film pressure resistance and outer-periphery flatness of the wafer.SOLUTION: A method for manufacturing a silicon single crystal wafer comprises the steps of: preparing a silicon single crystal having 0.01 pieces/cmor more of void-like defects having a size of 10 nm or more and less than 100 nm without detecting an oxidation induction stacking fault when performing heat treatment in an oxidative atmosphere having a nitrogen concentration of 5×10-5×10atoms/cmand two step temperatures of 1,000°C and 1,150°C and without detecting a void-like defect of 100 nm or more; slicing and polishing the silicon single crystal to be processed into a silicon single crystal wafer; and heating the silicon single crystal wafer at a temperature of 1,050°C or more and 1,350°C or less in a gas atmosphere including at least one of Hand Ar. Polishing is not performed after the heating.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a silicon single crystal wafer, a method for manufacturing a silicon epitaxial wafer, a silicon single crystal wafer, and a silicon epitaxial wafer.

  In a silicon single crystal, there are vacancy-type point defects called vacancy incorporated into the silicon single crystal during crystal growth and interstitial-silicon point defects called interstitial-silicon. Exists.

  In a silicon single crystal, the V region is a region where many voids are generated due to a shortage of silicon atoms, and the I region is an aggregate of silicon atoms or dislocation loop clusters generated due to the presence of extra silicon atoms. It is a lot of areas. In addition, a neutral region (hereinafter abbreviated as N region) in which there is little excess or deficiency of atoms exists between the V region and the I region.

  The N region is divided into an Nv region in which vacancy is dominant and an Ni region in which interstitial-silicon is dominant (see Patent Document 1). A high density BMD (Bulk Micro Defect) is formed in the Nv region. BMD is unlikely to occur in the area.

  In order to form a high-density BMD uniformly in the surface with high oxide film breakdown voltage characteristics over the entire wafer surface, it is desirable to make the entire wafer surface an Nv region, but this is technically very difficult.

Also, even if Nv region and Ni region are mixed, there is a technology to make the BMD in-plane distribution uniform by performing RTP treatment with NH ₃ gas, but because the DZ (Denuded Zone) width is insufficient, There was a problem that got worse. Further, when polishing is performed after RTP treatment with NH ₃ gas, PID (Polishing Induced Defect) is generated (see Patent Document 2), and there is a concern about an adverse effect on a state-of-the-art device.

  In addition, an epitaxial wafer using a crystal in the V-rich region has a high density BMD uniformly formed in the surface, and has a high oxide film withstand voltage characteristic, but has a lower flatness than a polished wafer, particularly in the outer peripheral region. Due to the low flatness, there is a possibility of causing a photolithography failure in the latest device. When the epitaxial film of the epitaxial wafer is thinned, the flatness of the outer peripheral region can be improved. However, when a V-rich region crystal capable of forming a high-density BMD uniformly in the plane is used as an epitaxial film growth wafer, the COP (Crystal Originated Particle) shape is reduced when the film thickness of the epitaxial film is 1 μm or less. There is a problem that LLS (Localized Light Scatters) frequently occurs because it cannot be completely erased.

  On the other hand, the nitrogen-doped crystal does not generate OSF between the N region and the OSF (Oxidation Induced Stacking Fault) region, and has a small void defect of 100 nm or less, and in many cases, 50 nm or less. There is a crystal region (hereinafter abbreviated as a microvoid defect region) (see paragraph [0012] of Patent Document 3). When crystals in this region are used, a high-density BMD can be uniformly formed in the wafer surface. However, the crystal polished wafer in this region has a problem that the oxide film pressure resistance is remarkably worse than that in the N region.

JP 2008-207991 A International Publication No. 2010/150547 Pamphlet JP 2000-053497 A

  The present invention has been made in view of the above-described problems, and can form a high-density BMD uniformly in the surface, has few void-like defects, does not generate PID, has a sufficient DZ width, and is oxidized. An object of the present invention is to provide a method for producing a silicon single crystal wafer and a silicon epitaxial wafer having good film pressure resistance characteristics and good peripheral flatness of the wafer. Another object of the present invention is to provide a silicon single crystal wafer and a silicon epitaxial wafer having the characteristics as described above.

To achieve the above object, the present invention provides a method for producing a silicon single crystal wafer,
The nitrogen concentration in the silicon single crystal is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, and the silicon single crystal is oxidized in two steps of 1000 ° C., 180 minutes, 1150 ° C., 100 minutes. When heat treatment is performed in a neutral atmosphere, oxidation-induced stacking faults are not detected inside the silicon single crystal, and void defects having a size of 100 nm or more are not detected inside the silicon single crystal. Preparing a silicon single crystal having void defects of a size less than 0.01 / cm ² or more inside the silicon single crystal;
A process of polishing and processing a silicon single crystal wafer after slicing the prepared silicon single crystal,
And heat-treating the processed silicon single crystal wafer at a temperature of 1050 ° C. or higher and 1350 ° C. or lower in a gas atmosphere containing at least one of H ₂ gas and Ar gas,
Provided is a method for manufacturing a silicon single crystal wafer, wherein the processed silicon single crystal wafer is not polished after the heat treatment at a temperature of 1050 ° C. or higher and 1350 ° C. or lower.

In this manner, nitrogen is doped to generate a microvoid defect region between the Nv region and the OSF region, and only the microvoid defect region or the microvoid defect region and the Nv region are included but the Ni region is not included. By preparing a silicon single crystal and subjecting the silicon single crystal wafer produced from the silicon single crystal to a heat treatment at a temperature of 1050 ° C. or higher and 1350 ° C. or lower in a gas atmosphere containing at least one of H ₂ gas and Ar gas, High density BMD can be formed uniformly in the surface, there are few void-like defects, no PID occurs, the DZ width is sufficiently wide, the oxide film breakdown voltage characteristics are good, and the wafer outer peripheral flatness is good. Wafers can be manufactured.

  At this time, it is preferable that the time of the heat treatment at a temperature of 1050 ° C. or more and 1350 ° C. or less is 5 seconds or more and 600 seconds or less.

  With such a heat treatment time, microvoid defects can be almost completely eliminated, the width of the DZ layer can be increased, and productivity is not reduced.

  At this time, it is preferable that the temperature increase rate to the heat processing temperature of 1050 degreeC or more and 1350 degrees C or less is 1 degree-C / sec or more.

  With such a temperature rising rate, the productivity can be reduced and a silicon single crystal wafer can be manufactured at a low cost.

  In order to achieve the above-mentioned object, the present invention produces a silicon single crystal wafer using the above-described method for producing a silicon single crystal wafer, and has a thickness on the main surface of the produced silicon single crystal wafer. Provided is a method for producing a silicon epitaxial wafer, wherein a single crystal silicon film of 1.0 μm or less is epitaxially grown.

  If a silicon epitaxial wafer is manufactured by such a method, the flatness of the outer peripheral region of the wafer is not deteriorated even though it is an epitaxial wafer, so that high-density BMD is uniformly distributed in the surface, and there are few void defects, It is possible to manufacture a silicon epitaxial wafer in which no PID is generated, the DZ width is sufficiently wide, the oxide film withstand voltage characteristic is good, and the wafer outer peripheral flatness is good.

In order to achieve the above object, the present invention is a silicon single crystal wafer,
The nitrogen concentration in the silicon single crystal wafer is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, and in a two-step oxidizing atmosphere of 1000 ° C. for 180 minutes and 1150 ° C. for 100 minutes. No oxidation-induced stacking faults were detected in the silicon single crystal wafer when the heat treatment was performed, the non-defective rate of γ mode of TDDB characteristics was 90% or more, and the number of void defects of 10 nm or more on the surface of the silicon single crystal wafer. Provided is a silicon single crystal wafer characterized by having 10 or less, 0 PID, average BMD density of bulk part of 1 × 10 ⁹ pieces / cm ³ or more, and width of DZ layer of 1.0 μm or more To do.

  Such a silicon single crystal wafer is extremely suitable as a silicon single crystal wafer for a state-of-the-art device.

In order to achieve the above object, the present invention is a silicon epitaxial wafer obtained by epitaxially growing a single crystal silicon film on a main surface of a silicon single crystal wafer,
The nitrogen concentration in the silicon single crystal wafer is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less in a two-step oxidizing atmosphere of 1000 ° C. for 180 minutes and 1150 ° C. for 100 minutes. No oxidation-induced stacking fault was detected in the silicon single crystal wafer when the heat treatment was performed, the non-defective rate of γ mode of TDDB characteristics was 90% or more, and 10 or less epi defects on the surface of the silicon epitaxial wafer were 10 or less. The silicon epitaxial wafer is characterized in that the average BMD density in the bulk portion is 1 × 10 ⁹ pieces / cm ³ or more and the ESFQRmax (edge exclusion 2 mm) is 20 nm or less.

  Such a silicon epitaxial wafer is extremely suitable as a silicon epitaxial wafer for leading-edge devices.

  According to the present invention, by performing heat treatment in a reducing gas atmosphere on a wafer prepared from a silicon single crystal doped with nitrogen, high-density BMD can be uniformly formed in the surface, and void defects are reduced. Thus, it is possible to provide a silicon single crystal wafer and a silicon epitaxial wafer in which no PID occurs, the DZ width is sufficient, the oxide film withstand voltage characteristics are good, and the wafer outer peripheral flatness is good.

It is a figure which shows the process flow of the manufacturing method of the silicon single crystal wafer of this invention. It is a figure which shows BMD density distribution (after precipitation heat processing) of the radial direction of the silicon single crystal wafer of an Example and Comparative Example 2-4.

  Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.

First, the manufacturing method of the silicon single crystal wafer of this invention is demonstrated with reference to FIG. FIG. 1 is a diagram showing a process flow of a method for producing a silicon single crystal wafer according to the present invention. In the method for producing a silicon single crystal wafer of the present invention, first, the nitrogen concentration in the silicon single crystal is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less. When the heat treatment is performed in a two-step oxidizing atmosphere of 180 minutes and 1150 ° C. for 100 minutes, oxidation-induced stacking faults are not detected inside the silicon single crystal, and void defects having a size of 100 nm or more are observed. There is a step of preparing a silicon single crystal that is not detected inside the silicon single crystal and has void-like defects having a size of 10 nm or more and less than 100 nm in the silicon single crystal of 0.01 / cm ² or more (FIG. 1). A process).

  In general, it is very difficult to produce a crystal whose entire wafer surface is only the Nv region. Therefore, in the present invention, nitrogen is doped to generate a minute void-like defect region between the Nv region and the OSF region, and only the minute void-like defect region or the minute void-like defect region and the Nv region including the Ni region are formed. A crystal that does not contain is used as a silicon single crystal.

Here, when the nitrogen concentration is less than 5 × 10 ¹¹ atoms / cm ³ , the range of the pulling speed at which the microvoid defect area is generated is very narrow, and only the microvoid defect area or the microvoid defect area It is very difficult to produce a silicon single crystal that includes the Nv region and the Ni region. In addition, when the nitrogen concentration exceeds 5 × 10 ¹⁴ atoms / cm ³ , a negative effect of nitrogen such as abnormal oxygen precipitation may occur when the wafer is heat-treated. Therefore, the nitrogen concentration is set to 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less.

In addition, the silicon single crystal used in the method for producing a silicon single crystal wafer of the present invention has oxidation-induced stacking faults when subjected to heat treatment in a two-step oxidizing atmosphere at 1000 ° C. for 180 minutes and 1150 ° C. for 100 minutes. It is not detected inside the silicon single crystal. Further, void defects having a size of 100 nm or more are not detected inside the silicon single crystal, and void defects having a size of 10 nm or more and less than 100 nm are contained in the silicon single crystal by 0.01 / cm ² or more. .

  Void defects of 100 nm or more are not detected in the microvoid defect region between the Nv region and the OSF region, but are detected when the V-rich region enters, and can be completely eliminated by a short heat treatment. Can not. Since the silicon single crystal used in the method for producing a silicon single crystal wafer of the present invention does not include void defects having a size of 100 nm or more, the void defects can be eliminated by heat treatment in a reducing gas atmosphere. . On the other hand, microvoid defects of less than 10 nm hardly pose a problem.

  The method for producing a silicon single crystal wafer according to the present invention includes a step of slicing the prepared silicon single crystal and then polishing it into a silicon single crystal wafer (step B in FIG. 1). The process of processing a silicon single crystal into a silicon single crystal wafer may generally include various steps such as lapping, etching, cleaning, and inspection in addition to slicing and polishing.

The method for producing a silicon single crystal wafer according to the present invention further includes a step of heat-treating the processed silicon single crystal wafer at a temperature of 1050 ° C. to 1350 ° C. in a gas atmosphere containing at least one of H ₂ gas and Ar gas. (Step C in FIG. 1). At this time, if the temperature of the heat treatment is less than 1050 ° C., the effect of eliminating the microvoid defects is not sufficient, and if it exceeds 1350 ° C., slip is generated in the crystal, which is not preferable. Gas used in the heat treatment atmosphere is, _{H 2} gas, a mixed gas containing _{H 2,} Ar gas, a mixed gas containing Ar, a mixed gas of _{H 2} and Ar, a mixed gas containing _{H 2} and Ar preferably, these Other rare gases may be contained therein. Moreover, some silane gas and HCl gas may be contained. However, it is not preferable that a gas that reacts with Si and forms a thin film different from the silicon crystal, such as O ₂ , N ₂ , and NH ₃ , is not preferable.

  Further, in the method for producing a silicon single crystal wafer of the present invention, the polishing process is not performed after the heat treatment at 1050 ° C. or higher and 1350 ° C. or lower (step C in FIG. 1). Since the polishing process is not performed after the heat treatment, the width of the DZ layer does not decrease and PID does not occur. Further, after the heat treatment, the silicon single crystal wafer may be cleaned.

  According to the method for manufacturing a silicon single crystal wafer of the present invention described above, high-density BMD can be formed uniformly in the surface. Further, since the fine void-like defects on the surface layer of the silicon single crystal wafer disappear by the heat treatment with the reducing gas atmosphere gas, the LLS quality is good. In addition, a sufficiently thick DZ layer is formed, and the oxide film breakdown voltage characteristic is good over the entire wafer surface. Further, the same flatness as that of the polished wafer is obtained, and the flatness of the outer peripheral region is particularly high as compared with a general epitaxial wafer. Further, PID disappears by heat treatment in a reducing gas atmosphere, and polishing is not performed after the heat treatment, so that the number of LLS is significantly smaller than that of a polished wafer using N-region crystals.

  As described above, in the method for producing a silicon single crystal wafer according to the present invention, the silicon single crystal wafer can be produced in a simple heat treatment furnace by performing a short time heat treatment with an inexpensive gas once. Moreover, since the frequency of adjustment and maintenance of the heat treatment furnace is low, the production cost can be kept lower than that of the epitaxial wafer.

  Further, the heat treatment time at a temperature of 1050 ° C. or higher and 1350 ° C. or lower is preferably 5 seconds or longer and 600 seconds or shorter. With such a heat treatment time, microvoid defects can be almost completely eliminated, the width of the DZ layer can be increased, and productivity is not reduced.

  Moreover, it is preferable that the temperature increase rate to the heat processing temperature of 1050 degreeC or more and 1350 degrees C or less is 1 degree-C / sec or more. With such a temperature rising rate, the productivity can be reduced and a silicon single crystal wafer can be manufactured at a low cost.

  Further, in the method for producing a silicon epitaxial wafer of the present invention, the high density BMD is uniformly distributed in the surface by using the above-described method for producing a silicon single crystal wafer, there are few void-like defects, no PID occurs, and the DZ width. Is manufactured, and a single crystal silicon film having a thickness of 1.0 μm or less is epitaxially grown on the main surface of the manufactured silicon single crystal wafer. If a silicon epitaxial wafer is manufactured by such a method, an epitaxial wafer having an extremely high surface quality can be manufactured. Further, although the wafer is an epitaxial wafer, the flatness of the wafer outer peripheral region is not deteriorated, so that a silicon epitaxial wafer having good oxide film pressure resistance and good wafer outer flatness can be manufactured.

In the silicon single crystal wafer of the present invention, the nitrogen concentration in the silicon single crystal wafer is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, 1000 ° C., 180 minutes and 1150 ° C., When heat treatment in a two-step oxidizing atmosphere for 100 minutes is performed, oxidation-induced stacking faults are not detected in the silicon single crystal wafer, and the non-defective rate of γ mode (intrinsic breakdown) of TDDB characteristics is 90% or more. The number of void defects of 10 nm or more on the crystal wafer surface is 10 or less, the PID is 0, the average BMD density of the bulk part is 1 × 10 ⁹ pieces / cm ³ or more, and the width of the DZ layer is 1.0 μm or more. is there. Such a silicon single crystal wafer is extremely suitable as a silicon single crystal wafer for a state-of-the-art device.

In the silicon epitaxial wafer of the present invention, the nitrogen concentration in the silicon single crystal wafer is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, 1000 ° C., 180 minutes, 1150 ° C., 100 When heat treatment is performed in a two-step oxidizing atmosphere for 2 minutes, oxidation-induced stacking faults are not detected in the silicon single crystal wafer, the non-defective ratio of γ mode of TDDB characteristics is 90% or more, and the surface of the silicon epitaxial wafer is 10 nm or more. The number of epitaxial defects is 10 or less, the average BMD density in the bulk portion is 1 × 10 ⁹ pieces / cm ³ or more, and the ESFQRmax (edge exclusion 2 mm) is 20 nm or less. Here, ESFQR (Edge site front squares range) is an index that focuses on the edge of the site flatness where the flatness is likely to deteriorate, and is derived from the reference plane obtained from the thickness distribution by the least square method. It is defined by the maximum and minimum width of the deviation. ESFQRmax is the maximum value among the plurality of ESFQRs at the wafer peripheral site. Such a silicon epitaxial wafer is extremely suitable as a silicon epitaxial wafer for leading-edge devices.

  EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.

Example 1
The nitrogen concentration in the silicon single crystal was set to 1 × 10 ¹³ atoms / cm ³ , and the oxygen concentration was set to 1 × 10 ¹⁸ atoms / cm ³ . The crystal region of the silicon single crystal was confirmed as follows. After performing precipitation heat treatment at 800 ° C. for 4 hours and 1000 ° C. for 16 hours, BMD was measured by measuring the cleaved section with MO-441 manufactured by Raytex, and the BMD density was 1 × 10 ⁷ pieces / cm 3. It was confirmed that the Ni region and the I-rich region that were ³ or less were not included. Furthermore, it was confirmed that the V-rich region having COP was not included by the FPD method. The FPD (Flow Pattern Defect) method is a method in which a sample is selectively etched to reveal defects and be evaluated. Next, this silicon single crystal was subjected to two-step heat treatment at 1000 ° C. for 180 minutes and 1150 ° C. for 100 minutes in an oxidizing atmosphere, and then selective etching was performed to measure oxidation-induced stacking faults. It was confirmed that it was not included.

The silicon single crystal was processed to produce a polished wafer, and the LLS detected at a particle counter of 13 nm or more was observed by SEM (Scanning Electron Microscope) to count the number of microvoid defects. Here, a region where a microvoid defect having a size of 10 nm or more was not detected was determined as an Nv region, and a silicon single crystal wafer composed of a microvoid defect region and an Nv region was used. The average number of microvoid defects on the 10 wafers was 178 (0.25 / cm ² ). If the ratio of the Nv region is increased, the number of microvoid defects can be reduced, but if it is less than 0.01 / cm ² , the Ni region is included, and the BMD cannot be formed uniformly in the plane.

A wafer having a diameter of 300 mm made from this silicon single crystal is put into a 600 ° C. chamber (heat treatment furnace) in an H ₂ atmosphere, heated at 5 ° C./sec, and each of 1050, 1100, 1200, 1300, 1350 ° C. Heat treatment was performed at a temperature of 180 seconds, and then RCA cleaning was performed.

  When these wafers were evaluated for oxide film withstand voltage by TDDB (Time Dependent Dielectric Breakdown) method, the yield rate of γ mode was 91 for each heat treatment temperature of 1050, 1100, 1200, 1300 and 1350 ° C. 95, 98, 98, and 98%, and the heat treatment at 1050 to 1350 ° C. all increased to 90% or more. Moreover, in any wafer, the number of void defects detected as 10 nm or more on the wafer surface was 10 or less, and no PID was detected.

Further, with respect to the wafer heat-treated at _{H 2,} 800 ° C., 4 hours and 1000 ° C., an average density of BMD was measured after performing precipitation heat treatment of 16 hours at MO-441 is 1.0 to 1.3 × 10 ^{The in-} plane uniformity of the ⁹ pieces / cm ³ and the BMD density was in the in-plane variation of 11 to 16% and 20% or less, and a high-density and highly uniform BMD quality was obtained. As an example, the BMD density distribution in the radial direction of a wafer heat-treated at 1200 ° C. is shown in FIG. ESFQRmax (edge exclusion 2 mm) was 12 to 16 nm and 20 nm or less. The DZ width is 1.5, 2.3, 3.7, 5.3, and 8.1 μm for each heat treatment temperature of 1050, 1100, 1200, 1300, and 1350 ° C., and increases as the heat treatment temperature increases. did. The above results are summarized in Table 1.

(Example 2)
An epitaxial layer having a thickness of 1 μm was formed on a silicon single crystal wafer having a diameter of 300 mm manufactured under the same conditions as those of the wafer manufactured in Example 1 and subjected to heat treatment at 1100 ° C. for 180 seconds in an H ₂ atmosphere. The non-defective product rate in the γ mode of the TDDB method was 98%, and the number of void defects (epi defects) on the epitaxial wafer surface was zero. The average density and in-plane uniformity of BMD in the bulk part were almost the same as those of the wafer in which the epitaxial layer was not formed as shown in Example 1. The DZ width was 3.4 μm and was sufficiently wide, and ESFQRmax was 17 nm and 20 nm or less. The results obtained in Example 2 are shown in Table 1.

(Comparative Example 1)
A wafer having a diameter of 300 mm polished from the same silicon single crystal as in Example 1 was put into a chamber at 600 ° C. in an H ₂ atmosphere, heated at 5 ° C./sec, and subjected to heat treatment at 1000 ° C. for 180 sec. RCA cleaning was performed. When the wafer was evaluated, the non-defective product rate in the γ mode of the TDDB method was 88% and 90% or less, 31 void defects detected as 10 nm or more on the wafer surface, and 16 PIDs. The average density and in-plane uniformity of BMD and ESFQRmax were almost the same as those heat-treated at 1050 to 1350 ° C., but the DZ width was 0.5 μm, which was 1 μm or less. The results obtained in Comparative Example 1 are shown in Table 1.

(Comparative Example 2)
A wafer having a diameter of 300 mm polished from the same silicon single crystal as in Example 1 was evaluated without heat treatment. The non-defective product rate in the γ mode of the TDDB method was 57%, which was significantly worse than that in the case of heat treatment in an H ₂ atmosphere, and 182 void defects and 92 PIDs were detected on the wafer surface. The average density and in-plane uniformity of BMD (see FIG. 2) and ESFQRmax were almost the same as those heat-treated at 1050 to 1350 ° C., but the DZ width was 0 μm. The results obtained in Comparative Example 2 are shown in Table 1.

(Comparative Example 3)
An epitaxial layer having a thickness of 3 μm was formed on a 300 mm diameter wafer polished from the same silicon single crystal as in Example 1, and evaluated. The non-defective product rate in the γ mode of the TDDB method was 98%, and the number of void defects (epi defects) on the epitaxial wafer surface was zero. The average density and in-plane uniformity of BMD in the bulk part are almost the same as those obtained by heat treatment at 1050 to 1350 ° C. (see FIG. 2), and the DZ width was 5.2 μm, but the ESFQRmax was 21 nm and 20 nm or more. Became. The results obtained in Comparative Example 3 are shown in Table 1.

(Comparative Example 4)
A polished wafer having a diameter of 300 mm was prepared using a silicon single crystal not doped with nitrogen, having an oxygen concentration of 0.9 × 10 ¹⁸ atoms / cm ³ and mixed with an Nv region and an Ni region, and was evaluated without heat treatment. The non-defective product rate in the γ mode of the TDDB method was 87% and 90% or less. No void defects on the wafer surface were detected, but 104 PIDs were detected. The average density of BMD was 2.8 × 10 ⁸ pieces / cm ³ and 1 × 10 ⁹ pieces / cm ³ or less, and the in-plane uniformity of the BMD density was extremely poor with in-plane variation of 100% (see FIG. 2). ). The results obtained in Comparative Example 4 are shown in Table 1.

(Comparative Example 5)
A silicon single crystal of the entire surface V-rich region was fabricated with a nitrogen concentration of 1 × 10 ¹³ atoms / cm ³ and an oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ in the silicon single crystal. A wafer having a diameter of 300 mm polished from this silicon single crystal was subjected to a heat treatment at 1100 ° C. in an H ₂ atmosphere, and then an epitaxial layer having a thickness of 1 μm was formed and evaluated. The non-defective product rate in the γ mode of the TDDB method was 98%. The average density and in-plane uniformity of BMD in the bulk part were almost the same as in the examples. The DZ width was 1.8 μm, and ESFQRmax was 18 nm and 20 nm or less. However, the number of void defects (epi defects) on the surface of the epitaxial wafer was very high at 247. The results obtained in Comparative Example 5 are shown in Table 1.

As described above, in Examples 1 and 2, 1) non-defective product rate in γ mode of TDDB method: 90% or more, 2) number of void defects in wafer surface: 10 or less, 3) number of PIDs: 0 4) Average density of BMD: in the range of 1.0 to 1.3 × 10 ¹⁹ pieces / cm ³ 5) In-plane uniformity of BMD density: 20% or less, 6) DZ width: 1.5 μm or more 7) ESFQRmax: All the criteria of 20 nm or less were satisfied. On the other hand, in Comparative Examples 1-5, there was no thing which satisfied all the standards.

The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

As described above, in Examples 1 and 2, 1) non-defective product rate in γ mode of TDDB method: 90% or more, 2) number of void defects in wafer surface: 10 or less, 3) number of PIDs: 0 4) Average density of BMD: in the range of 1.0 to 1.3 × 10 ⁹ pieces / cm ³ 5) In-plane uniformity of BMD density: 20% or less, 6) DZ width: 1.5 μm or more 7) ESFQRmax: All the criteria of 20 nm or less were satisfied. On the other hand, in Comparative Examples 1-5, there was no thing which satisfied all the standards.

Claims (6)

A method for producing a silicon single crystal wafer,
The nitrogen concentration in the silicon single crystal is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, and the silicon single crystal is oxidized in two steps of 1000 ° C., 180 minutes, 1150 ° C., 100 minutes. When heat treatment is performed in a neutral atmosphere, oxidation-induced stacking faults are not detected inside the silicon single crystal, and void defects having a size of 100 nm or more are not detected inside the silicon single crystal. Preparing a silicon single crystal having void defects of a size less than 0.01 / cm ² or more inside the silicon single crystal;
A process of polishing and processing a silicon single crystal wafer after slicing the prepared silicon single crystal,
And heat-treating the processed silicon single crystal wafer at a temperature of 1050 ° C. or higher and 1350 ° C. or lower in a gas atmosphere containing at least one of H ₂ gas and Ar gas,
A method for producing a silicon single crystal wafer, wherein the processed silicon single crystal wafer is not polished after the heat treatment at a temperature of 1050 ° C. or higher and 1350 ° C. or lower.   2. The method for producing a silicon single crystal wafer according to claim 1, wherein a time of the heat treatment at a temperature of 1050 ° C. to 1350 ° C. is 5 seconds to 600 seconds.   3. The method for producing a silicon single crystal wafer according to claim 1, wherein a rate of temperature rise to a heat treatment temperature of 1050 ° C. or more and 1350 ° C. or less is 1 ° C./second or more.   A silicon single crystal wafer is manufactured using the method for manufacturing a silicon single crystal wafer according to any one of claims 1 to 3, and a thickness of 1 is formed on a main surface of the manufactured silicon single crystal wafer. A method for producing a silicon epitaxial wafer, comprising epitaxially growing a single crystal silicon film having a thickness of 0.0 μm or less. A silicon single crystal wafer,
The nitrogen concentration in the silicon single crystal wafer is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, and in a two-step oxidizing atmosphere of 1000 ° C. for 180 minutes and 1150 ° C. for 100 minutes. No oxidation-induced stacking faults were detected in the silicon single crystal wafer when the heat treatment was performed, the non-defective rate of γ mode of TDDB characteristics was 90% or more, and the number of void defects of 10 nm or more on the surface of the silicon single crystal wafer. A silicon single crystal wafer characterized by having 10 or less, 0 PID, an average BMD density of a bulk portion of 1 × 10 ⁹ pieces / cm ³ or more, and a width of a DZ layer of 1.0 μm or more. A silicon epitaxial wafer obtained by epitaxially growing a single crystal silicon film on a main surface of a silicon single crystal wafer,
The nitrogen concentration in the silicon single crystal wafer is 5 × 10 ¹¹ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less in a two-step oxidizing atmosphere of 1000 ° C. for 180 minutes and 1150 ° C. for 100 minutes. No oxidation-induced stacking fault was detected in the silicon single crystal wafer when the heat treatment was performed, the non-defective rate of γ mode of TDDB characteristics was 90% or more, and 10 or less epi defects on the surface of the silicon epitaxial wafer were 10 or less. A silicon epitaxial wafer characterized in that the average BMD density in the bulk portion is 1 × 10 ⁹ pieces / cm ³ or more and the ESFQRmax (edge exclusion 2 mm) is 20 nm or less.

Images