JP2018027502A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To describe a separate processing module for security and test onto a separate area, and increase a capacity to be assigned to a game control process in a use area.SOLUTION: A processing procedure in which after an interrupt is prohibited and a flag register is saved in a stack area of a use area, a separate processing module is called and executed, and after the recovery from it, the flag register is recovered and the interrupt is allowed, is described in the use area. A processing procedure in which after a call from the use area, an internal register is saved in a stack area of a separate area, the separate processing module is then executed, and just before a recovery, the internal register saved in the stack area of the separate area is recovered, is described in the separate area.SELECTED DRAWING: Figure 4

Description

  The present invention mainly relates to revolving game machines, pachinko game machines, and the like used for the business of pachinko shops specified in Article 2, Paragraph 1 of the Law Concerning Customs Business Regulations, etc. About.

  Patent Document 1 confirms whether or not the final storage content stored in the backup RAM area is normal based on the checksum stored in the backup RAM area when the power is turned off. In such a case, a technique is described in which control is performed to restore the control state to the state before power-off based on the final stored contents.

JP 2002-95840 A

  The checksum is not the same before and after the power is cut off and it becomes abnormal. In addition to a pure failure, there may be cases where fraudulent acts are involved. Checksum check processing, etc. from the viewpoint of preventing unauthorized modification and other changes The security-related processing is essentially a regulation that combines the control area (4.5KB, etc.) and the data area (3.0KB, etc.) of the main board, that is, the main control device, in the same way as the test-related signal processing, etc. stipulated in the gaming machine rules. It can be described in another area, which is a storage area different from the used area in the capacity, and it is considered preferable to increase the capacity for game control processing that can be described in the used area. In particular, with the shift to the main AT, which is determined by the main control device, the operation of the assist time AT that informs the correct push order of the push order that has been exclusively determined by the peripheral control device so far Further savings are required.

  The object of the present invention is to perform original game control, such as security-related and test-related, other than the game control processing that controls the progress of the game while ensuring the clarity and fairness of the division of roles between the use area and the other area. It is an object of the present invention to provide a gaming machine that can appropriately describe another processing module provided for the purpose of optimization, etc., and can increase the capacity allocated to the game control processing in the use area.

The reference numerals of the drawings are illustrated in parentheses for illustration.
A use area within a predetermined capacity describing a game control process for controlling the progress of a game and another area describing another processing module (for example, E_SAMP1) that does not describe the game control process and performs a process related to security. In a gaming machine having a main CPU having a divided memory (ROM, RWM),
In the use area, interrupts are prohibited and the flag register (pair register AF) of the main CPU is saved in the use area stack area (for example, RWM addresses F1C0H to F1FFH), and then described in the separate area. A processing procedure for calling and executing another processing module (E_SAMP1), returning the flag register saved in the stack area of the used area and allowing an interrupt after returning from the other processing module (for example, another area calling process) 1), and
In the separate area, after the call from the use area, the internal registers Q, I, AF, BC, DE, HL, IX, IY, AF ′, BC ′, BC ′, DE ′, and HL ′ of the main CPU ) Is saved in the stack area (for example, RWM addresses F230H to F246H) of the other area, and thereafter, the separate processing module (E_SAMP1) is executed, and immediately before returning to the use area, the stack area of the other area A processing procedure (for example, another area processing 1) for restoring the saved internal register is described.
Here, the separate processing module may perform a process related to the test instead of or in addition to the security related process.
The internal register does not include the stack pointer SP and the program counter PC. The R register (refresh register) is excluded because it does not need to be protected.

  As a result, interrupts are prohibited during execution of another processing module described in another area, so that data in the used area is not rewritten from another area. In addition, when calling another processing module, the flag register whose value can be changed when the stack pointer is changed to properly use the stack area is saved in the stack area of the used area, and after calling from the used area, the internal register is moved to another area. Therefore, the used capacity of the stack area in the used area and the number of register save instructions in the used area can be reduced. After executing another processing module in another area, immediately before returning to the use area, the internal register saved in the stack area of another area is restored, and after returning from another process module, the flag saved in the stack area of the use area Since the register is restored, even if the contents (data) of the internal register are destroyed by the execution of the separate processing module, the identity of the internal register in the used area is maintained before and after the execution of the separate processing module. Since the internal register return processing is also described in a separate area, the number of register return instructions in the used area can be reduced. Therefore, while the number of instructions in the used area and the used capacity of the stack area can be reduced, the game control process in the used area is not affected by the execution of another processing module. Therefore, while ensuring the clarity and fairness of the division of roles between the use area and another area, other processing modules other than the game control process can be appropriately described in another area, and the capacity allocated to the game control process in the use area is appropriate. Can be increased.

In the above description, the stack pointer storing process and the restoring process indicating the stack area of the used area are described in the separate area.
This makes it possible to properly use the stack area of the used area and the stack area of the different area, and further reduce the number of instructions described in the used area.

As described above, the internal registers that are saved in the stack area of the separate area before executing the separate processing module (E_SAMP1) include table registers (AF, BC, DE, and HL registers), and this table. And back registers (AF ′, BC ′, DE ′, and HL ′ registers) that can exchange data with the registers, and the back registers are used as save registers for the front registers during interrupt processing in the use area. ing.
As a result, when interrupt processing is performed in the used area, the contents of the front register can be saved to the back register, so that the internal register can be protected quickly with a small number of steps. Since the internal registers used in the used area are saved and protected in the stack area of another area, it is possible to reliably eliminate the influence of the game control processing in the used area by executing the separate processing module. The objective can be achieved effectively.

In the above, a specific bit flag (tz) whose value changes by execution of a data transfer instruction (LD; load) is defined in the flag register (F register).
As a result, it is possible to branch by a specific bit flag whose value is changed by execution of a data transfer instruction in addition to a branch by a normal zero flag that is set to 1 when all bits are 0 as a result of operation. The branch process used in the game control process can be described with a small number of instructions, and the capacity can be saved. On the other hand, by defining such a specific bit flag, when the stack area is used properly, the contents of the flag register may change due to data transfer accompanying the change of the stack pointer. However, since the flag register is saved in the stack area of the use area before calling another area and is restored from the stack area of the use area after returning from another area, the identity of the flag register before and after execution of another processing module is Kept. Therefore, by defining the specific bit flag, it is possible to save the capacity of the game control process in the used area, and to effectively save the capacity by describing another processing module in the different area.

The perspective view of this invention gaming machine. The block diagram of the control apparatus of a gaming machine. Main CPU memory map. The program block diagram of a use area | region and another area | region.

  FIG. 1 shows a swivel game machine to which the present invention is applied. The swivel type gaming machine is generally called a pachislot machine. In 1985, after revisions to the gaming machine rules, that is, the National Public Safety Commission Regulation No. 1 on January 30, 2004 (2004), 2 It is a slot machine that conforms to the National Public Safety Commission Regulation No. 4 “Rules for Game Machine Approval and Type Approval” on May 12. Hereinafter, terms and their technical contents are in accordance with the existing game machine rules.

  The gaming machine housing 8B includes a rear cabinet 8R, a cabinet frame 8W, and door-shaped upper and lower front cabinets 8E and 8F. In the upper front cabinet 8E, a liquid crystal display device 70, a reel panel 8, an upper decoration lamp 81, a left decoration lamp 82, a right decoration lamp 83, and a liquid crystal display device that constitute an effect display device 7 that projects moving images and predetermined information in full color. Four accent decoration lamps 84 facing the corners of 70 and panel decoration lamps 85 facing the top, left and right of the reel panel 8 are provided. The lower front cabinet 8F includes an operation unit 8S, a waist panel 8P, a lower left decorative lamp 86, and a lower right decorative lamp 87. A generic name of 81 to 87 is called a decorative lamp 88. Reference numerals 91 to 94 denote speakers for outputting BGM and various sound effects, 8M denotes a medal payout opening, 8G denotes a medal tray, and 8T denotes an ashtray. Note that left and right mean left and right in the player's line of sight facing the gaming machine. The same applies hereinafter.

  The transparent display window 80 of the reel panel 8 includes a left reel 1L, a middle reel 1C, and a right reel 1R that serve as a plurality of variable display elements. A total of 21 reels 10L, 10C, and 10R are arranged on the outer periphery of the reel bands 10L, 10C, and 10R. Three consecutive frames out of symbols arranged in frames or 20 frames face through the window. Each symbol scrolls from top to bottom during normal forward rotation, including during steady rotation. A plurality of rows and a plurality of symbol display positions displayed through the window of the display window 80, that is, the three rows of the left, middle, and right reels 1L, 1C, and 1R and the upper, middle, and lower three rows respectively. At 3 × 3 = 9 symbol display positions specified by columns and stages, for example, only the middle line (left middle-middle middle-right middle) is the effective line. Note that two or more lines including other lines may be effective lines.

  The operation unit 8S includes a medal insertion slot 2 for inserting a game medal as a game medium, a jog dial JD having a push button PB and a dial DA for causing the player's operation to participate in the production, and an electromagnetic record of the storage device, that is, a credit from the credit card. A specified number necessary for the game, for example, a bet button 3 for dropping 3 (3 BET) medals, a settlement button 4 for dropping the remaining number of medals to the medal tray 8G, and variable display (rotation) of each reel 1L, 1C, 1R A start lever 5 serving as a start switch for starting the operation, a left stop button 6L serving as a stop switch provided for each of the reels 1L, 1C, and 1R and individually stopping variable display (rotation) of the corresponding reel, a middle stop button 6C, right stop button 6R, medal return button to be pressed when a medal is jammed downstream of the medal slot 2 0, and a door key hole 8K.

  The reel panel 8 has a credit display DL1 for displaying the current number of credits, a payout display DL2 for displaying the number of payout medals by winning, and is turned on every time one, two, or three medals are applied. ~ 3 lamps EL1 ~ 3, bet lamp ELb to be turned on when a winning medal can be accepted, start lamp ELs to be turned on when a start operation by the start lever 5 is possible, and lighted when a combination of symbols relating to replay is displayed The game basic lamps 30 including the replay lamp ELr to be played are provided. In addition, when the correct answer is given in the order of pressing the stop buttons 6L, 6C, 6R, the assist time AT is activated to notify the correct answer push order and the symbol to be aimed at for the push order small part that pays out the high payout medal exceeding the number of inserted medals. Inside, there are provided game effect lamps 700 constituting an effect display device 70 including a left stop lamp 71, a middle stop lamp 72, and a right stop lamp 73 that are turned on together with navigation notification on the liquid crystal display device 70.

  When the bet lamp ELb is lit, if one medal is inserted from the medal slot 2 with the hanging medal being 0, the one lamp EL1 is lit, and if one is inserted, the two lamp EL2 is lit, and one more is inserted. The three-lamp lamp EL3 is lit and reaches the specified number. When the specified number of multiplying medals is reached, the start lamp ELs is turned on, and the start operation by the start lever 5 becomes possible. If a medal is further inserted into the medal insertion slot 2 without operating the start lever 5 from the state where the prescribed number has been reached, the counter of the credit indicator DL1 is advanced and can be stored up to a predetermined upper limit of 50 sheets. Up to 50 medals paid out by winning are added to the credit, and medals paid out exceeding 50 are received by the medal tray 8G from the medal payout opening 8M.

  As shown in FIG. 2, the control device CN incorporated in the inside of the gaming machine housing 8B manages the progress of the game, and performs internal lottery, payout of medals by winning a prize, re-game operation, operation of accessory, assist time AT The main controller MC corresponding to the main board in the so-called game machine rule called the main side that executes the main game control related to the player's interest such as the operation of the game, and transmitted from the main controller MC according to the one-way communication specification And a peripheral control device SC corresponding to the peripheral board referred to as a so-called game machine rule, which receives the information to be performed and executes the effect control based on the matters determined by the main control device MC. The one-way communication specification refers to a communication specification that satisfies “not capable of receiving a signal transmitted by a peripheral board” defined in the gaming machine rules for the main board.

  The main controller MC includes an 8-bit main CPU composed of a Z80 compatible chip incorporating a read-only read-only memory ROM and a readable / writable read / write memory RWM, and is used in a system clock operating environment of 12 MHz, for example. . The main CPU applies a predetermined extended specification for gaming machines to the basic Z80 specification.

  The input port I1 of the main CPU includes index sensors 11L, 11C, and 11R (IDs) of the reels 1L, 1C, and 1R, stop buttons 6L, 6C, and 6R, a bet button 3, a settlement button 4, a start lever 5, and a medal. Signals of the insertion medal sensor 21 provided downstream of the insertion slot 2 and the payout medal sensor 23 provided at the exit of the medal payout device HP built in the gaming machine housing 8B are input. From the output port O1, the built-in LEDs 61, 62, 63 of the stop buttons 6L, 6C, 6R are connected to the reels 1L, 1C, 1R via the motor driver circuit Dr1 to the stepping motors 12L, 12C, 12R (SM), the game basic lamps 30 via the LED driver circuit Dr2, the medal blocker 22 for dropping the medals added after the reel start via the solenoid driver circuit Dr3 to the medal tray 8G, the motor driver circuit Dr4 The medal payout motor 24 of the medal payout device HP is controlled through the control.

  Each index sensor IDs detects an on-edge and an off-edge of a semicircular belt-shaped index ID (1Li, 1Ci, 1Ri) attached to the inside of each reel every half circle, and the first on-edge or off-edge is detected for all reels. After that, the stop buttons 6L, 6C, 6R can be accepted. Each stepping motor SM has a permanent magnet built-in type rotor Rm having a large number of rotor teeth on the outer periphery of the iron core, and a plurality of sets of magnetic poles having a plurality of stator teeth on the inner periphery of the magnetic pole. (A bar phase (inverted phase of A)) and D-phase (B bar phase (inverted phase of B)) windings, and a stator Sw. 1-phase excitation and 2-phase excitation for turning on one winding and other adjacent windings alternately by 1-2 phase excitation that repeats alternately every interrupt time, for example, t = 1.49 ms. The half step angle (one step angle by two-step update) is displaced by one step update, and one rotation is performed by step update 504. Further, forward rotation and reverse rotation are made possible by changing the step update direction of the excitation pulse.

  On the ROM of the main CPU, a random number value extracted from, for example, a 2-byte counter that is updated at high speed on hardware or software when the start lever 5 is operated is associated with a role within a range of 0 to 65535 that can be taken. Depending on which winning area is divided, the internal lottery means K for determining any winning combination or unfairness related to the winning, re-playing operation, the operation of the winning combination, after the operation of the start lever 5 Further, after 4.1 seconds from the start of the previous game, all reels are accelerated to the normal rotation side to reach the steady rotation speed, and each reel is individually stopped by operating the corresponding stop button. Reel control means V including a rotation stop device control means V2 that allows display of a combination of symbols corresponding to the winning combination on the active line, and if the game result is a win Transition to a medal payout means M for paying out a fixed number of medals, an automatic medal insertion means N for automatically inserting the medals for the next game in the same prescribed number if the game result is a re-game operation, a game result is in action, etc. , A game state transition means J for shifting the gaming state, a freeze lottery means W for determining whether or not a predetermined spinning effect is made to reversely rotate each reel with a predetermined probability determined for each winning combination by a predetermined freeze lottery, There is provided a turning effect execution means G for executing the turning effect related to the winning.

  Further, on the ROM of the main CPU, AT operation determining means H1 for determining the operation of the assist time AT under a predetermined operation condition associated with the internal winning combination, etc., the number of continuous games that will extend the operation of the assist time AT AT addition determining means H2 for determining the addition of the like, etc., under the predetermined additional condition associated with the internal winning combination, AT continuing management means H3 for managing the operation of the assist time AT from the end of the operation to the end of the operation, correct answer for the push order small combination The AT instruction information such as the pressing order is output to the main monitor MA constructed by borrowing the display function of the payout display DL2 managed by the main control device MC, and is also output to the liquid crystal display device 70 managed by the peripheral control device SC. Instruction information output means H4 is provided.

  The peripheral control device SC includes a sub CPU composed of a read-only read-only memory ROM attached externally and a 32-bit RISC (Reduced Instruction Set Computer) chip microcomputer having a built-in and external read / write memory RWM. For example, it is used under a system clock operating environment of about 200 MHz. Under the control of the real-time operating system RTOS (Real-Time Operating System), the sub CPU enables appropriate and efficient parallel processing of tasks by controlling the CPU time and priority assigned to tasks related to presentation display and audio. ing.

  Transmission information from the main controller MC and a signal of the jog dial JD are input to the input port I2 of the sub CPU. The transmission information from the main control device MC, that is, the reception information of the peripheral control device NC includes main-side initialization completion information, medal insertion information including operation information of the bet button 3, reel start information including operation information of the start lever 5, Winning flag information by internal lottery, operation information of stop buttons 6L, 6C, 6R, game result information, game state information, freeze and rotation effect information, AT operation information, AT instruction information, AT addition information, AT end information, error Various information such as information that is detected or determined or executed by the main controller MC is included.

  The sub CPU also functions as an I2C microcontroller, and connects the serial clock line SCL and serial data line SDA of the real-time clock RTC to the serial clock line SCL and serial data line SDA of the CPU built-in I2C. The serial clock line SCL and the serial data line SDA are each pulled up to the main operating potential vdd = 3.3V of the sub CPU via the resistor rp.

  The time data of the real-time clock RTC is written by a gaming machine manufacturer, etc. at the time of production based on the current time based on the Japanese standard or international standard clock radio wave, for example, Friday, December 25, 2015 at 15:30 It is written as 45 seconds. Thereafter, the time is continuously updated based on the reference clock by the built-in crystal resonator of the real-time clock RTC. The correction of the leap year on February 29, once every four years, is also automatically done, the major month of January 31, the minor month of January 30 or 28. The clock function of the real-time clock RTC is continuously maintained over a long period of time, for example, 10 years or longer by a backup power source BT such as a secondary battery, regardless of whether the gaming machine is powered on or off.

  On the ROM of the sub CPU, the navigation in accordance with the AT instruction information output from the AT instruction information output means H4 to the liquid crystal display device 70 or the like based on the reception information from the main controller MC, for example, the correct push order is “middle left If “right”, the navigation means X1 displays “123” or the like corresponding to the position of the stop button, and the stop button to be operated from the speakers 91 to 94 in conjunction with the display of the navigation means X1 is voiced. The voice display means X2 for notifying, the effect display means Y1 for changing and displaying the video development projected on the liquid crystal display device 70 according to the gaming state, the spinning effect, the AT period, etc., and the sound effects from the speakers 91 to 94 in conjunction with this. Sound effect output means Y2 for outputting BGM is provided.

  The I2C controller I2Cn is connected to the CPU built-in bus of the sub CPU, and the nine clocks facing the display window 80 of the serial clock line SCL and serial data line SDA of the I2C controller I2Cn are displayed on the reel bands 10L, 10C, 10R. Connected to the serial clock line SCL and serial data line SDA of the LDE driver Dr5 that controls the reel back lamps BL1 to 9 that illuminate from the back, and to the serial clock line SCL and serial data line SDA of the LED driver Dr6 that controls the decoration lamp 88 Connected to the serial clock line SCL and the serial data line SDA of the LED driver Dr7 that controls and controls the game effect lamps 700. These LED-related I2C device tasks have a higher priority than the real-time clock RTC. The serial clock line SCL and the serial data line SDA are each pulled up to the main operating potential vdd = 3.3V of the sub CPU via the resistor rp. The liquid crystal display device 70 is controlled via a VDP (Video Display Processor), an output port O2, and an LCD driver circuit Dr8. Audio from the speakers 91 to 94 is controlled via the audio IC, the output port O2, and the power amplifier circuit Dr9.

  FIG. 3 shows a memory map of the ROM and RWM of the main CPU of the main controller MC. Internal lottery means K, reel control means V, medal payout means M, medal automatic insertion means N, game state transition means J, freeze lottery means W, spinning drum effect execution means G, AT operation determination means H1, AT addition determination means H2 The program instruction code of the game control process for controlling the progress of the game by causing the AT continuation management means H3 and the AT instruction information output means H4 to function is the address 0000H in the specified capacity (control area 4.5 KB) in the used area. 11FFH, and the program data of the game control process is described in addresses 1200H to 1DF3H in the specified capacity (data area 3.0KB) in the used area.

  Other than the game control processing, responsible for security related processing from the viewpoint of preventing unauthorized modification and other changes to the unused area, the comment area, and addresses 1F00H to 2FBFH, and test related signal processing defined by the gaming machine rules The program instruction code and data of the processing module are described. A program management area, an area having no hardware area, an RWM of a use area is provided in 512 bytes of addresses F000H to F1FFH, and an RWM of another area is provided in 512 bytes of addresses F200H to F3FFH. F400H to FFFFH are areas having no hardware area. Note that the program instruction code of the game control process in the use area and the program instruction code of another process module in another area are described in an assembler language.

  Of the RWM in the used area, work areas such as timers, counters, and flags related to the used area program are secured in F000H to F13FH, and the used area stack area is secured in the F1C0H to F1FFH after the unused area. .

  Among the RWMs in another area, a work area such as a timer, a counter, a flag, etc. related to a program in another area is secured in F210H to F22FH after an unused area in F200H to F20FH, and a stack area in another area is allocated in F230H to F246H. Secured. F247H to F3FFH are unused, and F400H to FFFFH are areas where there is no area in terms of hardware.

  As shown in FIG. 4, the game control process described in the use area is an interrupt process INT1 executed every interrupt time, for example, every t = 1.49 ms, and the above-mentioned means K to H4 are collectively managed to advance one game. The game main process, and a plurality of different area call processes 1, 2,... For calling the different area processes 1, 2,. Although not shown, the use area also describes initialization processing at power-on, backup processing at power interruption, and the like. In this embodiment, the external interrupt and the non-maskable interrupt NMI are unused.

The internal registers of the main CPU used in the usage area are as follows.
1) Q register; 8-bit dedicated register with extended specifications for gaming machines. This is called a queue register.
The upper part is fixed to F0H and used for RWM access from F000H to F0FFH.
2) I register: A dedicated register that stores the upper 8 bits of the interrupt destination address.
3) A register; 8-bit accumulator used for arithmetic processing and data transfer.

4) F register: 8-bit flag register that holds the results of various operations.
s (most significant bit) is a sign flag that is set to 1 when the operation result is negative.
z is a zero flag that is set to 1 when all bits are 0 as a result of operation.
tz is a specific bit flag of an extended specification for gaming machines that is set to 1 (changes in value) when all bits are 0 by execution of a data transfer instruction (LD; load). Called the Tizet flag. Also called a second zero flag.
h is a half-carry flag that a programmer cannot be involved in.
* Is undefined.
p / v is a parity overflow flag.
n is an addition / subtraction flag that the programmer cannot participate in.
c is a carry flag that is set to 1 when a carry or borrow occurs as a result of an operation.
Note that the F register constitutes an A register and a register pair AF.

5) B, C, D, E, H, L registers; 8-bit general purpose registers.
It becomes a 16-bit register pair of BC, DE, and HL.
6) IX and IY registers; 16-bit dedicated registers for index addressing.
IXh and IYh represent the upper 8 bits, and IXl and IYl represent the lower 8 bits.
7) A ′, F ′, B ′, C ′, D ′, E ′, H ′, L ′ registers;
A, F, B, C, D, E, H, and L are back registers that can exchange data by an exchange command. A 'and F' are AF ', B' and C 'are BC', D ''AndE' are the back registers of the pair, DE ', H' and L 'are HL', respectively.

  In the interrupt processing INT1, the data in the front register AF is saved to the back register by the exchange instruction EX (step t1), and the data in the front registers BC, DE, and HL is saved by the exchange instruction EXX in the back registers BC ′, DE ′, and HL. After saving to '(step t2), various interrupt processing is executed (step t3). Various interrupt processing includes reading processing for the input port I1, motor control processing for the stepping motor SM, output management processing for the output port O1, subcommand transmission processing to the peripheral control device SC, monitoring processing for various sensors, and update of various timers. Processing, external signal output control processing to the game machine installation island side, etc. are included. After executing various interrupt processes, the data saved in the back registers BC ′, DE ′, and HL ′ by the exchange instruction EXX is restored to the front registers BC, DE, and HL (step t4), and the back register AF ′ is obtained by the exchange instruction EX. The saved data is returned to the table register AF (step t5), the interrupt is permitted (step t6), and the process returns from the interrupt process (step t7).

  In SAMP1 of another area call processing 1, interrupt is prohibited (step S1), and the register pair AF including the flag register F is moved from the bottom F1FFH of the stack area of the used area to the younger one by the “PUSH AF” instruction. Then, 2 bytes (16 bits) are saved (step S2).

  After step S2, another area process 1 is called and executed by "CALL E_SAMP1" (step S3). By executing the CALL instruction, the upper 8 bits and the lower 8 bits of the return address, that is, the address “POP AF” next to the CALL instruction are recorded in the stack area of the use area.

  After returning from the different area processing 1, the register pair AF including the flag register F saved in step S2 is returned by the “POP AF” instruction (step S4), and an interrupt is permitted (step S5).

  In E_SAMP1 of the separate area process 1 described in the separate area, the stack pointer SP indicating the stack area of the used area is saved in a storage area called EX_STCB that is secured in the RWM of the separate area (step S6), and the stack of the separate area is stored. @ SK2_ARE_BAS + 1 (= F247H), which is the next address of the bottom address of the area, is set as the initial value of the stack pointer SP (step S7). As a result, the stack area changes from the use area to another area.

  Next, instructions that define the internal registers Q, I, A, F, B, C, D, E, H, L, IX, and IY used in the usage area with the “PUSH ALL” extended specification for gaming machines. As a result, the stack area is evacuated from the bottom F246H of the stack area of another area toward the younger address (step S8), and AF and AF ′ are exchanged by the exchange instruction EX (step S9), and BC is exchanged by the exchange instruction EXX. And BC ′, DE and DE ′, and HL and HL ′ are respectively replaced (step S10), and the instructions that are defined in the extended specification for gaming machines “PUSH GPR” are collectively followed by the stuffing after the stuffing in step S8. Save to the address (step S11).

  Thereafter, predetermined different area processing 1 is executed (step S12). In this separate area processing 1, backflow / stagnation / foreign matter detection processing at the time of medal insertion, backflow / staying / foreign matter detection processing at the time of medal payout, front door open detection processing, internal random number abnormality check processing, internal lottery winning Any one of security related processes such as a setting value abnormality confirmation process, a RWM abnormality confirmation process, and a backup abnormality confirmation process, which are combinations of probabilities, or two or more combination processes are executed. In other area processing 2 and later, security related processes other than the different area processing 1 or test related signal output processing defined by the gaming machine rules are described. The separate area processes 2,... Are called from the separate area call processes 2,.

  After completion of the separate area processing 1, the register that holds the contents of the back register packed in step S11 is returned in a batch by the instruction defined in the extended specification for gaming machines called “POP GPR” (step S13) and replaced. BC ′ and BC are exchanged by instruction EXX, DE ′ and DE are exchanged, and HL ′ and HL are exchanged (step S14), and AF ′ and AF are exchanged by exchange instruction EX (step S15). The table register packed in step S8 is restored at once by the instruction defined in the extended specification for gaming machines “POP ALL” (step S16).

  Subsequently, the stack pointer SP that points to the stack area of the use area before the call of the separate area process 1 is restored from the storage area EX_STCB of the RWM of the separate area (step S17). As a result, the stack area changes from another area to a use area.

  Thereafter, the “RET” command returns to the use area (step S18). The “RET” instruction returns to the return address stored in the stack area of the use area, the stack pointer SP indicating the address of the stack area is incremented by 2, and “POP AF” in step S4 is executed.

  The instruction code of the separate area call processing 1 described in the use area is 7 bytes in total, with “DI”, “PUSH AF”, “POP AF”, “EI” each having 1 byte, and “CALL E_SAMP1” having 3 bytes. When the separate area process 1 is described with an instruction exceeding 7 bytes, the capacity of the used area can be saved for the area exceeding 7 bytes. Since the different area processing is not limited to one and is often a plurality, the number of bytes saved in each processing is at least a great saving effect in total.

  In the above embodiment, the rotating type gaming machine is exemplified, but the invention can be similarly applied to a pachinko gaming machine. Needless to say, the specific numbers and addresses in the above description are merely examples.

1L; left reel, 1C; middle reel, 1R; right reel 2; medal slot, 3; bet button, 4; checkout button 5; start lever, 6L, 6C, 6R; each stop switch 7; production display device, 70 Liquid crystal display device 8; reel panel 80; display window CN; control device MC; main control device SC; peripheral control device K; internal lottery means V; reel control means V1; ; Rotation stop device control means M; medal payout means N: medal automatic insertion means J: game state transition means W; freeze drawing means G: spinning effect execution means H1: AT operation determination means H2: AT addition determination Means H3; AT continuation management means, H4; AT instruction information output means X1; navigation means, X2; voice navigation means Y1; effect display means, Y2;

Claims (5)

It has a memory in which a use area within a predetermined capacity describing a game control process for controlling the progress of a game and a separate area describing another processing module that does not describe the game control process and performs a process related to security are provided. In gaming machines with a main CPU,
In the use area, interrupts are prohibited and the flag register of the main CPU is saved in the stack area of the use area, and then the separate processing module described in the separate area is called and executed. Describes the processing procedure for restoring the flag register saved in the stack area of the used area and allowing an interrupt,
In the separate area, after calling from the use area, the internal register of the main CPU is saved in the stack area of the separate area, and thereafter, the separate processing module is executed and immediately before returning to the use area. A gaming machine characterized in that it describes a processing procedure for restoring the internal register saved in the stack area of the different area. It has a memory in which a use area within a predetermined capacity describing a game control process for controlling the progress of a game and a separate area describing another processing module that does not describe the game control process but performs a process related to a test In gaming machines with a main CPU,
In the use area, interrupts are prohibited and the flag register of the main CPU is saved in the stack area of the use area, and then the separate processing module described in the separate area is called and executed. Describes the processing procedure for restoring the flag register saved in the stack area of the used area and allowing an interrupt,
In the separate area, after calling from the use area, the internal register of the main CPU is saved in the stack area of the separate area, and thereafter, the separate processing module is executed and immediately before returning to the use area. A gaming machine characterized in that it describes a processing procedure for restoring the internal register saved in the stack area of the different area.   The gaming machine according to claim 1 or 2, wherein a save process and a return process of a stack pointer indicating the stack area of the use area are described in the separate area.   The internal register that is saved in the stack area of the separate area before executing the separate processing module includes a front register and a back register that can exchange data with the front register, and the back register is the use area. The gaming machine according to any one of claims 1 to 3, wherein the gaming machine is used as a save register for the table register during an interrupt process.   The gaming machine according to any one of claims 1 to 4, wherein the flag register defines a specific bit flag whose value is changed by execution of a data transfer instruction.

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