JP2018023192A - Unit control device for multilevel power conversion apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in a multilevel inverter, if there is an individual difference between units, a cross-flow current may be generated, thereby varying a current duty.SOLUTION: Voltage command value correction means is provided on a prestage of cross-flow current suppression control means. The voltage command value correction means includes: first switch means for suppressing an approach of a voltage command value to zero by providing a threshold with respect to the voltage command value; second switching means for inhibiting a change of the voltage command value from a negative value to a positive value when an inclination of a triangular carrier waveform is positive; and third switch means for inhibiting a change of the voltage command value from a positive value to a negative value when the inclination of the triangular carrier waveform is negative. The voltage command value that is corrected by the voltage command value correction means is defined as a voltage command value to the cross-flow current suppression control means.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a unit parallel control device of a multi-level power conversion device, and more particularly to a control device that equalizes current duties between inverter units.

  As an example of the configuration of the multi-level power conversion device, there are a three-level inverter and a five-level inverter. FIG. 7A shows one phase of an NPC type three-level inverter. The phase voltage is generated by ON / OFF operations of switching elements T1 to T4 such as IGBTs in the inverter. Further, the ON / OFF signal of each switching element is generally generated by PWM modulation that compares a voltage command value and a carrier triangular wave (triangular wave comparison PWM method).

  In addition to the NPC type shown in FIG. 7A, the three-level inverter includes a T type shown in FIG. 7B and a flying capacitor (hereinafter referred to as FC) type shown in FIG. 7C. Patent Document 1 describes an example of an FC type three-level inverter. Table 1 shows the switching pattern of the FC type three-level inverter of FIG. 7 (c). When a zero voltage based on the N terminal is output to the output terminal O, the FC is turned on by turning ON T1 and T3 or turning ON T2 and T4. Note that the applied voltage of the capacitor C1 and the applied voltage of the capacitor C2 are equal, and VCF = Vdc1 / 2.

  There is a case where a plurality of such inverter units are arranged in parallel to constitute a power conversion device to cope with an increase in capacity. FIG. 8 shows an example in which FC type three-level inverters are arranged in parallel. At this time, if there is an individual difference between the inverter units, a difference occurs in the output current between the inverters (a cross current is generated), and the current duty varies. As a result, heat generation is concentrated on a specific inverter and the life is shortened. In the worst case, there arises a problem that the switching element is destroyed due to overcurrent or overheating. As a countermeasure, a cross current suppression reactor is connected to each inverter, but new problems such as an increase in cost, weight, and loss occur. In order to solve this problem, a method for suppressing the cross current by controlling the cross current suppressing reactor as small as possible is being studied.

  Patent Document 2 describes a method of suppressing cross current by adjusting gate timing (ON / OFF signal timing) of a switching element. In Example 9 (paragraph [0139]), NPC type or T type is described. Control for suppressing cross current in a parallel configuration of three-level inverters has been proposed.

JP2008-92651 WO2014 / 123199 JP2015-8586

  In the method of Patent Document 2, there is a problem that the cross current is increased if the switching is not performed for a long time in order to control the cross current during switching. FIG. 9 shows an operation state when the frequency is temporarily lowered in a parallel configuration of three-level inverters. Since the carrier triangular wave (carrier 1 and carrier 2 in FIG. 9) does not cross when the voltage command value Vref crosses zero, switching is not performed over one period of carrier in section A and 1.5 periods or more in section B. In the three-level inverter, when the voltage command value Vref crosses zero, there is a case where it does not cross the carrier triangular wave, and there is a possibility that the cross current will increase each time.

  Recently, a multi-level inverter exceeding three levels, such as a five-level inverter disclosed in Patent Document 3, has been proposed. When this inverter is PWM-modulated, four carrier triangular waves are used as shown in FIG. Therefore, not only the zero crossing of the voltage command value Vref but also a problem similar to FIG. When multi-level inverters exceeding three levels are configured in parallel, the cross current increases more frequently than the three levels.

  Therefore, in order to solve the above-described problems, the present invention is a multi-purpose circuit that suppresses the cross current by correcting the voltage command value so that the voltage command value and the carrier triangular wave are reliably crossed and switched within a certain period. The object is to provide a unit control device for a level power converter.

The present invention connects multi-inverter units of three or more levels in parallel, compares the voltage command value with the carrier triangular wave while equalizing the cross current duty between the inverter units by the cross current suppression control means, and switching elements in the inverter In the control device for generating the on / off signal of
A voltage command value correction means is provided in the previous stage of the cross current suppression control means,
The voltage command value correcting means is provided with threshold values (forbidden bands) −Vth to Vth for the voltage command value Vref, and first switch means for suppressing the approach of the voltage command value Vref to zero;
Second switch means for prohibiting the change of the voltage command value Vref from a negative value to a positive value when the slope of the carrier triangular wave is positive;
Third switch means for prohibiting a change of the voltage command value Vref from a positive value to a negative value when the slope of the carrier triangular wave is negative;
The voltage command value corrected by the voltage command value correcting means is used as the voltage command value to the cross current suppression control means.

The first switch means of the present invention includes a first comparator that detects that the voltage command value Vref is less than the threshold value Vth, and a second comparator that detects that the voltage command value Vref exceeds the threshold value -Vth. Has a function to output the voltage command value Vref when the voltage command value Vref is outside the range of the threshold value -Vth to Vth, and hold the previous output value when the voltage command value Vref is within the range of the threshold value -Vth to Vth,
The second switch means detects a third comparator that detects that the output of the first switch means is a positive value, and a fourth comparator that detects that the previous output value held is a negative value. And a fifth comparator that detects that the slope of the differential value of the carrier triangular wave is a positive value, and holds the output signal “1” from each of the third to fifth comparators. A function of outputting the previous output value and outputting from the first switch means when the output signal is not "1",
The third switch means detects a sixth comparator that detects that the output of the second switch means is a negative value, and a seventh comparator that detects that the previous output value held is a positive value. The previous output value held when the output signal “1” from each of the sixth and seventh comparators is negative and the slope of the differential value of the carrier triangular wave is negative is corrected. The voltage command value Vref ′ is output, and when the slope of the differential value of the carrier triangular wave is positive, the output of the second switch means is provided.

In the present invention, the multi-level inverter has three phases, and the three-phase voltage command value Vref is subtracted separately from the voltage command value Vref ′ corrected by the voltage command value correcting means, respectively, via a subtractor, The total value of the obtained calculated values is added to the three-phase voltage command value Vref separately to obtain a newly corrected three-phase voltage command value Vref ^* , and the voltage command value Vref ^* is the cross current control control means. Is a voltage command value for.

Further, according to the present invention, the voltage command value correcting means is connected in series in N-2 stages, the input of the voltage command value correcting means in the second and subsequent stages is used as the output of the voltage command value correcting means in the previous stage, and n connected in series In the voltage command value correction means of the stage, the input (voltage command value Vref-n of each stage) is the threshold value 2n / (N-1) -1-Vth <Vref-n <2n / (N-1) -1 + Vth Based on whether or not it is within the range, the output of the voltage command value correcting means at each stage is generated.
However, N is the number of multi-levels of the inverter, N ≧ 4, n = 1 ... N-2

  As described above, according to the present invention, even if the voltage command value is near zero, by always generating one switching between the vertices of the carrier triangular wave, the opportunity for performing the cross current suppression control is increased, and the cross current is reduced. Can be small.

The voltage command value correction | amendment block diagram which shows embodiment of this invention. FIG. 3 is a block diagram illustrating a cross current control control. The voltage command value correction | amendment block diagram which shows other embodiment of this invention. The voltage command value correction | amendment block diagram which shows other embodiment of this invention. The correction waveform figure of a voltage command value. The correction waveform figure of a voltage command value. In the main circuit configuration diagram (for one phase) of the 3-level inverter, (a) is NPC type, (b) is A-NPC type, and (c) FC type. The unit parallel block diagram of FC type 3 level inverter. An explanatory waveform diagram at the time of switching frequency reduction.

  Prior to the description of the embodiments, a cross current suppression control block of a multilevel power converter to which the present invention is applied will be described. FIG. 2 shows a cross current suppression control block for each phase of the inverter unit, which is installed in each phase of the inverter unit. The control block of FIG. 2 is an example applied to a three-level inverter and is the same as FIG. 12 of Patent Document 2. In this embodiment, the voltage command Vref ′ input to the cross current suppression control block is shown in FIG. It is corrected by the voltage command value correction block shown.

  In FIG. 2, the PWM modulator 21 generates gate command values Gref1 and Gref2 based on the input voltage command value Vref ′ and the carrier triangular wave Vcarry. For example, the gate command value Gref1 is a gate command value corresponding to the switching elements TN1 and TN3 shown in FIG. 8, and the gate command value Gref2 is a gate command value corresponding to the switching elements TN2 and TN4. The gate command values Gref1 and Gref2 are input to the dead time processor 24 through the corresponding delay adders DelayU1, DelayD1, DelayU2, and DelayD2, respectively, and after dead time processing is performed, gate signals G1N, G2N, G3N, and G4N are output. Is done. These gate signals become ON / OFF signals for the respective switching elements.

  The gate delay command value calculation block 23 receives the vertex detection signal of the carrier triangular wave Vcarry detected through the vertex detector 22 and the gate command values Gref1 and Gref2. In the gate delay command value calculation block 23, the buffers 32a and 32b hold the values of the gate command values Gref1 and Gref2 half a cycle before the carrier triangular wave Vcarry. I1 to I8 are integration amplifiers, SW11, SW21, SW31, SW41, SW51, SW61, SW71, and SW81 are input switches, SW12, SW22, SW32, SW42, SW52, SW62, SW72, and SW82 are output switches, and AND1 to AND8 are AND In the circuit, the output signal of the sign detector 25 is input to the AND circuits AND1 to AND4, and the output current detection value IinvUNdet of the inverter unit is positive as one of the conditions for closing the input switches SW11, SW21, SW31, SW41. I will do it. At this time, the output signal of the code detector 25 becomes “1”. Further, the inverted output signal of the sign detector 25 is input to the AND circuits AND5 to AND8, and the output current detection value IinvUNdet of the inverter unit is negative as one of the conditions for closing the input switches SW51, SW61, SW71, SW81. I will do it. At this time, the output signal of the code detector 25 becomes “0”.

  Another condition for closing the input switches SW11 and SW51 is that the gate command value Gref1 is “1”, the gate command value Gref1 before the half cycle of the carrier triangular wave Vcarry is “0”, and the gate command value before the half cycle of the carrier triangular wave Vcarry. This is a case where Gref2 is “1”. Another condition for closing the input switches SW21 and SW61 is that the gate command value Gref1 is “0”, the gate command value Gref1 before the half cycle of the carrier triangular wave Vcarry is “1”, and the gate before the half cycle of the carrier triangular wave Vcarry. This is a case where the command value Gref2 is “1”.

  Another condition for closing the input switches SW31 and SW71 is that the gate command value Gref2 is “1”, the gate command value Gref2 before the half cycle of the carrier triangular wave Vcarry is “0”, and the gate command value before the half cycle of the carrier triangular wave Vcarry. This is a case where Gref1 is “0”. Another condition for closing the input switches SW41 and SW81 is that the gate command value Gref2 is “0”, the gate command value Gref2 before the half cycle of the carrier triangular wave Vcarry is “1”, and the gate before the half cycle of the carrier triangular wave Vcarry. This is a case where the command value Gref1 is “0”.

  The condition for closing the output switches SW12, SW22, SW32, and SW42 is that the output current detection value IinvUNdet of the inverter unit is positive. The condition for closing the output switches SW52, SW62, SW72, and SW82 is that the output current detection value IinvUNdet of the inverter unit is negative.

  The adder add1 adds the outputs of the proportional amplifier P and the output switches SW12 and SW52, and inverts the sign by multiplying the addition result of the adder add1 by -1 in the multiplier mul1. The output of the multiplier mul1 becomes DelayU1 at the timing when the gate command value Gref1 rises from “0” to “1”. The adder add2 adds the outputs of the proportional amplifier P and the output switches SW22 and SW62, and the addition result of the adder add2 becomes DelayD1 when the gate command value Gref1 falls from “1” to “0”.

  The adder add3 adds the outputs of the proportional amplifier P and the output switches SW32 and SW72, and the addition result of the adder add3 is multiplied by −1 in the multiplier mul2, and the sign is inverted. The output of the multiplier mul2 becomes DelayU2 at the timing when the gate command value Gref2 rises from “0” to “1”. The adder add4 adds the outputs of the proportional amplifier P and the output switches SW42 and SW82, and the addition result of the adder add4 becomes DelayD2 when the gate command value Gref2 falls from “1” to “0”.

  In the present invention, the voltage command value Vref ′ input to the cross current suppression control block shown in FIG. 2 is a voltage command value corrected by the voltage command value correction block shown in FIG. In FIG. 1, a voltage command value Vref is an output of a control amplifier if it is a current control inverter or a voltage control inverter, and may be given in a feed forward without applying control. The voltage command value Vref is input to the comparators cmpA and cmpB and the terminal a of the switch SWA, respectively.

  The comparator cmpA detects that the voltage command value Vref is less than the set threshold value Vth, and outputs “1”. The comparator cmpB detects that the voltage command value Vref exceeds the threshold value −Vth and outputs “1”. The outputs of the comparators cmpA and cmpB are input separately to the input terminals of the AND circuit AND11. The threshold value Vth corresponds to the upper limit value of the forbidden band shown in FIG. 5, and the threshold value −Vth corresponds to the lower limit value of the forbidden band shown in FIG. The AND circuit AND11 outputs “1” for both the comparators cmpA and cmpB, and outputs “1” when −Vth <Vref <Vth is established. The switch SWA switches to the terminal b when the output of the AND circuit AND11 is “1”, and switches to the terminal a when the output is “0”.

The output of the buffer Z- ¹ for inputting the output of the switch SWA is connected to the terminal b side of the switch SWA. The switch SWA directly outputs Vref as an output signal if the voltage command value Vref is outside the range of the threshold value −Vth to Vth, and holds the previously output value if the voltage command value Vref is within the range of the threshold value −Vth to Vth. To do. The output of the switch SWA is connected to the terminal a of the switch SWB. The output of the switch SWB is connected to the terminal a of the switch SWC.

The output of the buffer Z- ¹ that inputs the output of the switch SWB is connected to the terminal b side of the switch SWB. The comparator cmpD detects that the switch SWA output is a positive value and outputs “1”. The comparator cmpC detects that the buffer value is negative and outputs “1”. Each detection value is input to the AND circuit AND12. Further, the inclination signal of the carrier triangular wave detected by the comparator cmpG is input to the AND circuit AND12. The slope signal is differentiated by a differentiator sT, and the comparator cmpG detects that the differential value (slope) is a positive value, and is input to the AND circuit AND12.

  Therefore, the AND circuit AND12 outputs “1” when all the comparators cmpC, cmpD, and cmpG output “1”, and switches the switch SWB to the terminal b side. The output signal of the switch SWB continues to output the previous negative value even if the voltage command value Vref changes from negative to positive when the slope of the carrier triangular wave is positive. If the slope of the carrier triangular wave is negative, the voltage command value Vref Is output as is.

The output of the switch SWB is connected to the terminal a of the switch SWC, and the output of the buffer Z- ¹ that receives the output of the switch SWC is connected to the terminal b of the switch SWC. The comparator cmpF detects that the switch SWB output is a negative value and outputs “1”. The comparator cmpE detects that the value of the buffer Z ⁻¹ is a positive value and outputs “1”. The AND circuit AND13 outputs “1” when the comparators cmpE and cmpF are all “1” and the differential (slope) of the carrier triangular wave is negative, and switches the switch SWC to the terminal b side. The output signal of the switch SWC continues to output the previous positive value even if the voltage command value Vref changes from positive to negative when the slope of the carrier triangular wave is negative. If the slope of the carrier triangular wave is positive, the voltage command value Vref Is output as is. The output signal of the switch SWC is input to the cross current suppression control block of FIG. 2 as a voltage command value Vref ′.

  In this embodiment, the switch and its peripheral circuit constitute three switch means. The switch SWA has forbidden bands -Vth to Vth for the voltage command value Vref so that the voltage command value Vref does not approach zero. Switch SWB prohibits the change of voltage command value Vref from a negative value to a positive value when the slope of the carrier triangular wave is positive. The switch SWC prohibits the change of the voltage command value Vref from a positive value to a negative value when the slope of the carrier triangular wave is negative.

  FIG. 5 shows the voltage command value Vref (solid line) and the corrected voltage command value Vref ′ (dotted line). Since the voltage command value Vref before correction does not cross the carrier triangular wave near zero, the period during which the voltage command value Vref is not switched is long. During this time, the means for suppressing the cross current is lost. When there is a deviation in the voltage drop of the switching element, the deviation voltage continues to be applied to the transverse current suppressing reactor during the non-switching period indicated by Gref1 and Gref2 in FIG. 5, and the transverse current increases.

  On the other hand, in this embodiment, the voltage command value Vref ′ is set to a forbidden band near zero by the correction, and when the slope of the carrier triangular wave is negative, the change of the voltage command value Vref ′ from positive to negative is prohibited. . As a result, the voltage command value Vref ′ is corrected as indicated by Gref1 ′ in FIG. 5, and at least one switching is reliably performed between the vertices of the carrier triangular wave.

According to the first embodiment, the period during which switching is not performed can be shortened, so that an increase in cross current can be prevented. The forbidden band threshold Vth needs to be set to satisfy the minimum ON pulse width that can be output by the switching element.
When the voltage command value is corrected according to the first embodiment, the number of switching increases near zero of the voltage command value and the loss increases. However, if limited to applications where the power conversion device has a high output power factor, the phase of the output voltage and the output current will be approximately equal, so the instantaneous value of the output current will be close to zero near the zero of the voltage command value. Even if the number of switching increases near zero, the output current that is cut off is small and the switching loss is small, so the increase in loss is small.

When the voltage command value is changed by the cross current suppression control using the voltage command correction block shown in FIG. 1, the output voltage distortion and the output current distortion may occur. In the second embodiment, this problem is solved.
The voltage command correction block shown in FIG. 3 is for a three-phase, three-wire, three-level inverter. VrefU is a U-phase voltage command value, VrefV is a V-phase voltage command value, and VrefW is a W-phase voltage command value. By adding / subtracting the corrected voltage command values VrefU ′, VrefV ′, VrefW ′ obtained in FIG. 1 to the voltage command values VrefU, VrefV, VrefW of each phase, new voltage command values VrefU ^* , VrefV ^* and VrefW ^* are obtained and used as the voltage command value Vref ′ to the cross current suppression control block shown in FIG.

That is, the corrected voltage command value VrefU ′ in the voltage command correction block shown in FIG. 1 is input, and the subtractor sub1 subtracts VrefU from the corrected voltage command value VrefU ′ to obtain the U-phase correction operation amount. In the subtractor sub2, VrefV is subtracted from the corrected voltage command value VrefV 'to obtain the V-phase correction manipulated variable. Further, the subtractor sub3 subtracts VrefW from the corrected voltage command value VrefW ′ to obtain the W-phase correction manipulated variable. The adder add10 adds all the correction operation amounts for each phase, and adds the addition result and the voltage command values VrefU, VrefV, and VrefW by the adders add11, add12, and add13, respectively, to obtain a new voltage command value VrefU ^* , Get VrefV ^* and VrefW ^* .

The new voltage command values VrefU ^* , VrefV ^* , and VrefW ^* obtained as described above are superimposed on distortion due to the correction operation in the phase voltage, but the line voltage is not affected by the correction. Since the influence on the external load depends only on the line voltage in the three-phase three-wire inverter, the above operation can solve the problem of output voltage distortion and output current distortion due to correction. .

  The embodiment shown in FIG. 4 is an example in which the first embodiment is applied to a multilevel inverter having four or more levels (N levels). FIG. 4 is a configuration in which the voltage command correction blocks shown in FIG. 1 are connected in N-2 stages in series, and as an example, shows a configuration diagram per stage in a configuration for a five-level inverter with three stages in series.

The voltage command value Vref is given by the output of the control amplifier or feedforward in the same manner as in the first embodiment if the first stage (n = 1), and is the output of the previous stage if the second and subsequent stages (n ≧ 2).
The comparator cmpAn detects that the voltage command value Vref-n of the n-th stage voltage command value correcting means is less than the threshold value 2n / (N−1) −1 + Vth. The comparator cmpBn detects that the voltage command value Vref exceeds the threshold value 2n / (N-1) -1-Vth and outputs “1”. Here, the threshold value Vth corresponds to the upper limit value of the forbidden band 2 shown in FIG. When both comparators cmpAn and cmpBn output "1" and 2n / (N-1) -1-Vth <Vref-n <2n / (N-1) -1 + Vth holds, AND circuit AND1n “1” is output.

The switch SWAn is switched to the terminal b side by the output “1” of the AND circuit AND11n, and is switched to the terminal a side at “0”. The output of the buffer Z- ^{1 to which} the output of the switch SWAn is input is connected to the terminal b side of the switch SWAn. If the voltage command value Vref-n is outside the range of the threshold 2n / (N-1) -1-Vth <Vref-n <2n / (N-1) -1 + Vth, the switch SWAn will use Vref as an output signal. If the voltage command value Vref-n is within the range of 2n / (N-1) -1-Vth <Vref-n <2n / (N-1) -1 + Vth, the previous output value is held. . The output of the switch SWAn is connected to the terminal a of the switch SWBn. The output of the switch SWB is connected to the terminal a of the switch SWC.

The output of the buffer Z- ¹ that inputs the output of the switch SWBn is connected to the terminal b side of the switch SWBn. The comparator cmpDn detects that the output of the switch SWAn is larger than 2n / (N−1) −1 and outputs “1”. The comparator cmpCn detects that the value of the buffer is smaller than 2n / (N−1) −1 and outputs “1”. Each detection value is input to the AND circuit AND12n. Further, the inclination signal of the carrier triangular wave detected by the comparator cmpGn is input to the AND circuit AND12n. The inclination signal is obtained by differentiating the carrier triangular wave by the differentiator sT, detecting that the differential value (inclination) is a positive value by the comparator cmpGn, outputting “1”, and input to the AND circuit AND12n.

The output signal of switch SWBn is more than the previous 2n / (N-1) -1 even if the voltage command value Vref changes to a value larger than 2n / (N-1) -1 when the slope of the carrier triangular wave is positive. If the slope of the carrier triangular wave is negative, the voltage command value Vref is output as it is, while continuing to output a smaller value (more precisely, 2n / (N-1) -1-Vth). The output signal of the switch SWBn is input to the terminal a of the switch SWCn, and is also input to the comparator cmpF1 and the buffer Z- ¹ .

The output of the buffer Z- ¹ that receives the output of the switch SWCn is connected to the terminal b side of the switch SWCn. The comparator cmpFn detects that the output of the switch SWBn is a value smaller than 2n / (N−1) −1 and outputs “1”. The comparator cmpEn detects that the value of the buffer Z ⁻¹ is larger than 2n / (N−1) −1 and outputs “1”. Each detection value is input to the AND circuit AND13n. Further, the inclination signal of the carrier triangular wave detected by the comparator cmpGn is input to the AND circuit AND13n. The comparator cmpGn detects that the slope of the differential signal from the differentiator sT is positive, outputs “1”, inverts the logic, and inputs it to the AND circuit AND13n.

  Even if the voltage command value Vref changes to a value smaller than 2n / (N-1) -1 when the slope of the carrier triangular wave is negative, the output signal of the switch SWCn is 2n / (N-1) -1 Larger than (more precisely, 2n / (N-1) -1-Vth), and if the slope of the carrier triangular wave is positive, the voltage command value Vref is output as it is. The output signal of the switch SWCn is input to the cross current control control block of FIG. 2 as the voltage command value Vref ′ if it is the final stage (n = N−2), otherwise it is the voltage command of the next stage. Input to the value correction block. FIG. 4 shows an example in which the first level is n = 1 and the second level is n = 2.

  The corrected voltage command value applicable to the multi-level inverter of 4 levels or more (N level) can be generated by the voltage command value correcting means provided with the function operating as described above. As an example, FIG. 6 shows how the voltage command value Vref is corrected in a 5-level inverter. In the 5-level inverter, since four carrier triangular waves are used for PWM modulation, correction is required not only near zero (0) in FIG. 1 but also near +0.5 and -0.5. In this embodiment, therefore, correction blocks near +0.5 and -0.5 are added by connecting the blocks shown in FIG. 1 in three stages in series.

  N in FIG. 6 represents the number of levels, and if 5 levels, N = 5. When this is input to the uppermost block B1 in FIG. 4, 2n / (N-1) -1 = 2 / (5-1) -1 = -0.5, and the switch SWA1 in the uppermost B1 has a voltage command value Vref. Forbidden bands -0.5-Vth to -0.5 + Vth are provided, and the voltage command value Vref is not close to -0.5. The forbidden band 3 shown in FIG. 6 corresponds to the forbidden band here.

In the switch SWB1, when the slope of the carrier triangular wave is positive, the voltage command value Vref is prohibited from changing from a value smaller than −0.5 to a value larger than −0.5.
In the switch SWC1, when the slope of the carrier triangular wave is negative, the voltage command value Vref is prohibited from changing from a value larger than −0.5 to a value smaller than −0.5.
Block B1 operates as described above.

  The middle block B2 has 2n / (N-1) -1 = 4 / 4-1 = 0, and has the same configuration and operation as FIG. The forbidden band 2 shown in FIG. 6 corresponds to the forbidden band here.

  The lowermost block B3 substitutes n = 3 and N = 5 to 2n / (N-1) -1 = 0.5, and corrects the voltage command value Vref near 0.5. The forbidden band 1 shown in FIG. 6 corresponds to the forbidden band here.

  By setting the number of levels to N and substituting n = 1 to N-2 and making N-2 stages of similar blocks in series, a voltage command value correction block corresponding to an arbitrary number of levels can be configured. . However, since the number of switching elements to be used increases as the number of levels increases, it is necessary to expand the cross current control block of FIG. 2 so that the number of integrating amplifiers is twice the number of switching elements.

  Further, the third embodiment can be combined with the second embodiment. In the second embodiment, the target is a three-level inverter, but it can be applied even if the level is four or more. In this case, for example, in the case of 5 levels, it is necessary to make corrections at 0.5 and -0.5 in addition to 0, and it is necessary to apply after confirming that the timings at which corrections are required do not overlap in all phases.

  According to the third embodiment, even when multi-level inverters of four levels or more are connected in parallel, by always generating one switching between the vertices of the carrier triangular wave, the opportunity for performing the cross current suppression control is increased. The current can be reduced.

copA ~ copG ... Comparator
SWA to SWC ... switch
AND11 to AND13 ... AND circuit
sT ... Differentiator
Z ^-1 … buffer
sub1 to sub3 ...: Subtractor
add10 ～ add13… Adder

Claims (4)

Multi-inverter units of 3 levels or more are connected in parallel, and the cross-current current suppression control means equalizes the cross-current duty between the inverter units, compares the voltage command value with the carrier triangular wave, and turns on / off the switching elements in the inverter. In a control device that generates a signal,
A voltage command value correction means is provided in the previous stage of the cross current suppression control means,
The voltage command value correcting means is provided with threshold values (forbidden bands) −Vth to Vth for the voltage command value Vref, and first switch means for suppressing the approach of the voltage command value Vref to zero;
Second switch means for prohibiting the change of the voltage command value Vref from a negative value to a positive value when the slope of the carrier triangular wave is positive;
Third switch means for prohibiting a change of the voltage command value Vref from a positive value to a negative value when the slope of the carrier triangular wave is negative;
A unit control device for a multilevel power converter, wherein the voltage command value corrected by the voltage command value correction means is used as a voltage command value for the cross current suppression control means. The first switch means includes a first comparator that detects that the voltage command value Vref is less than the threshold value Vth, and a second comparator that detects that the voltage command value Vref exceeds the threshold value -Vth. It has a function to output the voltage command value Vref when the voltage command value Vref is outside the range of the threshold value -Vth to Vth, and hold the previous output value when it is within the range of the threshold value -Vth to Vth,
The second switch means detects a third comparator that detects that the output of the first switch means is a positive value, and a second comparator that detects that the previous output value held is a negative value. 4 and a fifth comparator for detecting that the slope of the differential value of the carrier triangular wave is a positive value, and the output signal “1” from each of the third to fifth comparators A function of outputting the held previous output value and outputting from the first switch means when the output signal is not "1";
The third switch means detects a sixth comparator for detecting that the output of the second switch means is a negative value, and a first comparator for detecting that the previous output value held is a positive value. The previous output value held when the output signal “1” from each of the sixth and seventh comparators is negative and the slope of the differential value of the carrier triangular wave is negative. 2. The multilevel according to claim 1, further comprising a function of outputting the output of the second switch means when the corrected voltage command value Vref 'is output and the slope of the differential value of the carrier triangular wave is positive. Unit controller for power converter. The multi-level inverter has three phases, and the three-phase voltage command value Vref is subtracted separately from the voltage command value Vref ′ corrected by the voltage command value correcting means, respectively, via a subtractor, and obtained calculated values Is added to the three-phase voltage command value Vref separately to obtain each corrected three-phase voltage command value Vref ^* , and the voltage command value Vref ^* is the voltage command value for the cross current suppression control means. The unit control device for a multilevel power conversion device according to claim 1 or 2, wherein the unit control device is a multilevel power conversion device. The voltage command value correction means is connected in series N-2, the input of the voltage command value correction means in the second and subsequent stages is used as the output of the voltage command value correction means in the previous stage, and the voltage command in the nth stage connected in series. In the value correction means, is the input (voltage command value Vref-n at each stage) within the range of threshold 2n / (N-1) -1-Vth <Vref-n <2n / (N-1) -1 + Vth 4. The unit control device for a multi-level power conversion device according to claim 1, wherein the output of the voltage command value correction means at each stage is generated based on whether or not.
Where N is the number of multi-level inverters, N ≧ 4, n = 1 ... N-2

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