JP2018022906A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit ringing occurring when being switched off and reduce surge voltage, and which can inhibit malfunction caused by rising of gate voltage VGS when being switched off and reduce the problem to increase switching loss.SOLUTION: A semiconductor device 100 includes: a gate electrode 126 which is arranged in a trench 122 and opposed to a p-type base region 116 at a part of a sidewall via a gate insulation film 124; a shield electrode 130 which is arranged in the trench 122 and lies between the gate electrode and the trench bottom; and an electrical insulation region 128 in the trench, which stretches between the gate electrode and the shield electrode and stretches along sidewalls and the bottom of the trench to separate the shield electrode from the sidewalls and the bottom. The shield electrode has a high-resistance region 130a lying on the side of an n+ drain region 112 and a low-resistance region 130b lying on the side of the gate electrode.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  Conventionally, a semiconductor device having a so-called shield gate structure is known (for example, see Patent Document 1). As shown in FIG. 20A, a conventional semiconductor device 900 includes a semiconductor substrate 910 including an n + -type drain region 912, an n − -type drift region 914, a p-type base region 916, and an n + -type source region 918, and a semiconductor substrate. Formed in 910, having a bottom adjacent to n-type drift region 914 and a side wall adjacent to p-type base region 916 and n-type drift region 914, and formed in stripes when viewed in plan A trench 922, a gate electrode 926 disposed in the trench 922 and opposed to the p-type base region 916 through the gate insulating film 924 at the side wall portion, disposed in the trench 922, and gate electrode 926 and the bottom of the trench 922, and spread between the gate electrode 926 and the shield electrode 930. An insulating region 928 in the trench 922 that extends along the sidewalls and bottom of the trench 922 and separates the shield electrode 930 from the sidewalls and bottom; and a source region 918 and a shield electrode 930 formed above the semiconductor substrate 910. And a drain electrode 936 formed adjacent to the n + -type drain region 912.

According to the conventional semiconductor device 900, since the shield electrode 930 is provided in the trench 922 and positioned between the gate electrode 926 and the bottom of the trench 922, the gate-drain capacitance C _GD (FIG. As a result, the gate charge current amount and the gate discharge current amount are reduced, and the switching speed can be increased. Further, the distance from the corner portion of the trench 922 where the electric field concentration is likely to occur to the gate electrode 926 can be increased, and further, the electric field can be relaxed in the electrically insulating region 928, so that the withstand voltage can be increased.

Japanese Patent No. 4790908

  However, the inventors' research has revealed that in the conventional semiconductor device 900, ringing or high surge voltage may occur when the switch is turned off. Therefore, the present inventor considered using a high-resistance shield electrode (for example, a shield electrode having a higher resistance than the source electrode and the gate electrode) as the shield electrode (see FIG. 2A). In this way, due to the high internal resistance of the shield electrode, the potential change of the drain electrode can be moderated when the switch is turned off, thereby suppressing the ringing that occurs when the switch is turned off and reducing the surge voltage. It becomes.

However, when a high-resistance shield electrode is used as the shield electrode as described above, a potential difference is generated along the wiring of the shield electrode in the latter half of the switching period, so that the gate-source capacitance C _GS (see FIG. 20). This also applies to FIG. 2), and the gate voltage V _GS rises, and a problem (see reference numeral A in FIG. 2B) that a malfunction (self-turn-on) is likely to occur occurs. Moreover, the problem that the switching loss increases due to the slow switching speed (see FIG. 2B) occurs.

  On the other hand, when a shield electrode having a low resistance is used as the shield electrode (see FIG. 3A), the potential change of the drain electrode cannot be moderated when the switch is turned off. The effect that the voltage can be reduced cannot be obtained (see FIG. 3B).

Accordingly, the present invention has been made to solve these problems, and can suppress ringing that occurs when the switch is turned off, reduce the surge voltage, and the gate voltage V _GS rises when the switch is turned off. An object of the present invention is to provide a semiconductor device capable of suppressing malfunction (self-turn-on) that occurs due to the above problem and reducing the problem of increased switching loss.

[1] A semiconductor device of the present invention includes a first conductivity type drain region, a first conductivity type drift region adjacent to the drain region, a second conductivity type base region adjacent to the drift region, and the base A semiconductor substrate including a first conductivity type source region adjacent to the region; a bottom formed in the semiconductor substrate; adjacent to the drift region; and a sidewall adjacent to the base region and the drift region; A trench formed in a stripe shape when viewed in plan, a gate electrode disposed in the trench and facing the base region through a gate insulating film at a portion of the side wall, and disposed in the trench And a shield electrode located between the gate electrode and the bottom of the trench, and extending between the gate electrode and the shield electrode, and further An electrically insulating region in the trench and extending above the semiconductor substrate, extending along the side wall and the bottom of the trench and separating the shield electrode from the side wall and the bottom; and the source region and the shield A semiconductor device comprising a source electrode electrically connected to an electrode and a drain electrode formed adjacent to the drain region, wherein the shield electrode is a high resistance region located on the drain region side, And it has the low resistance area | region located in the said gate electrode side, It is characterized by the above-mentioned.

  The above-described high resistance region is referred to as a first region located on the drain region side and having a first resistance along the longitudinal direction of the shield electrode, and the above-described low resistance region is disposed on the gate electrode side. It can be said that the second region is located and has a second resistance higher than the first resistance along the longitudinal direction of the shield electrode.

[2] In the semiconductor device of the present invention, both the high resistance region and the low resistance region are made of the same semiconductor material containing impurities, and the impurity concentration of the low resistance region is higher than the impurity concentration of the high resistance region. High is preferred.

[3] In the semiconductor device of the present invention, the high resistance region and the low resistance region are made of different materials, and the electrical resistivity of the material constituting the low resistance region is the electrical resistance of the material constituting the high resistance region. Preferably it is lower than the resistivity.

[4] In the semiconductor device of the present invention, the high resistance region and the low resistance region are made of the same material, and the low resistance region is cut when cut along a plane perpendicular to the stripe longitudinal direction of the shield electrode. The area is preferably larger than the cross-sectional area of the high resistance region when cut along a plane perpendicular to the longitudinal direction of the shield electrode.

[5] In the semiconductor device of the present invention, it is preferable that the high resistance region and the low resistance region are located in contact with each other.

[6] In the semiconductor device of the present invention, it is preferable that the high resistance region and the low resistance region are located at positions separated from each other via the electrically insulating region.

[7] In the semiconductor device of the present invention, the electrically insulating region sandwiched between the high resistance region and the low resistance region of the electrically insulating region partially has an opening, The high resistance region and the low resistance region are preferably in partial contact with each other through the opening.

[8] In the semiconductor device of the present invention, the low resistance region is preferably thinner than the high resistance region.

[9] In the semiconductor device of the present invention, the high resistance region is preferably thinner than the low resistance region.

According to the semiconductor device of the present invention, the shield electrode includes a shield electrode having a high resistance region located on the drain region side and a low resistance region located on the gate electrode side (see FIG. 1A). In the high resistance region, the resistance value of the resistor Ra (see FIG. 4) in the region is higher than the resistance value of the resistor Rb (see FIG. 4). Therefore, ringing that occurs when the switch is turned off can be suppressed and the surge voltage can be reduced (see FIG. 1B). In the low resistance region, the resistance value of the resistor Rb (see FIG. 4) in the region is lower than the resistance value of the resistor Ra (see FIG. 4), so that the potential difference generated along the wiring of the shield electrode is reduced. Therefore, it is possible to suppress malfunction (self-turn-on) that occurs due to the rise of the gate voltage V _{GS in} the latter half of the switching period (see reference numeral A in FIG. 1B). In addition, the presence of the low resistance region can increase the switching speed (see FIG. 1B), thereby preventing an increase in switching loss.

1 is a diagram for explaining a semiconductor device 100 according to a first embodiment. 1A is a cross-sectional view of the semiconductor device 100, and FIG. 1B is a diagram illustrating a response waveform when the semiconductor device 100 is switched off. FIG. 10 is a diagram for explaining a semiconductor device 100a according to Comparative Example 1. 2A is a cross-sectional view of the semiconductor device 100a, and FIG. 2B is a diagram illustrating a response waveform when the semiconductor device 100a is switched off. FIG. 10 is a diagram for explaining a semiconductor device 100b according to Comparative Example 2. FIG. 3A is a cross-sectional view of the semiconductor device 100b, and FIG. 3B is a diagram illustrating a response waveform when the semiconductor device 100b is switched off. FIG. 3 is a diagram for explaining the operation and effect of the semiconductor device 100 according to the first embodiment. 4A is a diagram in which parasitic resistance and parasitic capacitance are added to the cross-sectional view of the semiconductor device 100, and FIG. 4B is an equivalent circuit diagram of the semiconductor device 100. 6 is a view for explaining a method of manufacturing the semiconductor device 100 according to the first embodiment. FIG. FIG. 5A to FIG. 5D are process diagrams. 6 is a view for explaining a method of manufacturing the semiconductor device 100 according to the first embodiment. FIG. FIG. 6A to FIG. 6D are process diagrams. 6 is a view for explaining a method of manufacturing the semiconductor device 100 according to the first embodiment. FIG. Fig.7 (a)-FIG.7 (d) are each process drawing. 6 is a view for explaining a method of manufacturing the semiconductor device 100 according to the first embodiment. FIG. FIG. 8A to FIG. 8D are process diagrams. FIG. 6 is a cross-sectional view of a semiconductor device 101 according to a second embodiment. FIG. 6 is a cross-sectional view of a semiconductor device 102 according to a third embodiment. FIG. 11 is a diagram for explaining a semiconductor device 103 according to Modification 1. 11A is a cross-sectional view of the semiconductor device 103, and FIG. 11B is a cross-sectional view taken along line BB in FIG. 11A. 10 is a cross-sectional view of a semiconductor device 104 according to Modification 2. FIG. 10 is a cross-sectional view of a semiconductor device 105 according to Modification 3. FIG. FIG. 10 is a cross-sectional view of a semiconductor device 106 according to Modification 4. 10 is a cross-sectional view of a semiconductor device 107 according to Modification 5. FIG. FIG. 6 is a view for explaining another method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining another method for manufacturing the semiconductor device 100 according to the first embodiment. FIGS. 16A to 16D and FIGS. 17A to 17C are process diagrams. 16 and 17, the same steps as those shown in FIGS. 5 to 8 are not shown. FIG. 10 is a view for explaining still another method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining another method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 18A to FIG. 18D and FIG. 19A to FIG. 19D are process diagrams. 18 and 19, the same steps as those shown in FIGS. 5 to 8 are not shown. It is sectional drawing of the conventional semiconductor device 900. FIG. 20A is a diagram in which parasitic resistance and parasitic capacitance are added to the cross-sectional view of the semiconductor device 900, and FIG. 20B is an equivalent circuit diagram of the semiconductor device 900.

  Hereinafter, a semiconductor device of the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
1. Semiconductor Device As shown in FIG. 1A, the semiconductor device according to the first embodiment includes an n + -type drain region (first conductivity type drain region) 112 and an n − -type drift region adjacent to the n + -type drain region 112 ( A first conductivity type drift region) 114, a p-type base region (second conductivity type base region) 116 adjacent to the n − -type drift region 114, and an n + type source region (first contact) adjacent to the p-type base region 116. A semiconductor substrate 110 including a source region 118 of one conductivity type, a bottom formed in the semiconductor substrate 110 and adjacent to the n − type drift region 114, and adjacent to the p type base region 116 and the n − type drift region 114. A trench 122 formed in a stripe shape in plan view, and disposed in the trench 122, with the gate insulating film 124 interposed between the side walls. A gate electrode 126 facing the p-type base region 116, a shield electrode 130 disposed in the trench 122 and positioned between the gate electrode 126 and the bottom of the trench 122, and the gate electrode 126 and the shield electrode 130. And an insulating region 128 in the trench 122 that extends along the sidewall and bottom of the trench 122 and separates the shield electrode 130 from the sidewall and bottom, and is formed above the semiconductor substrate 110. A source electrode 134 electrically connected to the source region 118 and the shield electrode 130 and a drain electrode 136 formed adjacent to the drain region 112 are provided.
The semiconductor device 100 according to the first embodiment is a power MOSFET.

  In the semiconductor device 100 according to the first embodiment, the shield electrode 130 includes the high resistance region 130a located on the drain region 112 side and the low resistance region 130b located on the gate electrode 126 side. The high resistance region 130a and the low resistance region 130b are both made of the same semiconductor material containing impurities, and the impurity concentration of the low resistance region 130b is higher than the impurity concentration of the high resistance region 130a. In addition, the high resistance region 130a and the low resistance region 130b are located in contact with each other.

The thickness of the n + -type drain region 112 is 50 μm to 500 μm (eg, 350 μm), and the impurity concentration of the n + -type drain region 112 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (eg, 1 × 10 ¹⁹ cm). ^-3 ). The thickness of the n − type drift region 114 is 10 μm to 50 μm (for example, 15 μm), and the impurity concentration of the n − type drift region 114 is 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ (for example, 1 × 10 ¹⁵ cm ⁻³ ). The thickness of the p-type base region 116 is 2 μm to 10 μm (for example, 5 μm), and the impurity concentration of the p-type base region 116 is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ (for example, 1 × 10 ¹⁷ cm). ^-3 ).

The depth of the trench 122 is 4 μm to 20 μm (for example, 10 μm), and the pitch of the trench 122 is 3 μm to 15 μm (for example, 10 μm).
The gate insulating film 124 is made of, for example, a silicon dioxide film formed by a thermal oxidation method, and the thickness of the gate insulating film 124 is 20 nm to 200 nm (for example, 100 nm).
The gate electrode 126 is made of, for example, low-resistance polysilicon formed by a CVD method, and the thickness of the gate electrode 126 is 2 μm to 10 μm (for example, 5 μm).

  As described above, the shield electrode 130 is disposed in the trench 122 and located between the gate electrode 126 and the bottom of the trench 122. The high resistance region 130a is made of, for example, high resistance polysilicon formed by a CVD method, and the thickness of the high resistance region 130a is 1 μm to 4 μm (for example, 3 μm). The low resistance region 130a is made of, for example, low resistance polysilicon formed by a CVD method, and the thickness of the low resistance region 130b is 0.5 μm to 2 μm (for example, 1 μm).

  The distance between the shield electrode 130 and the gate electrode 126 is 1 μm to 3 μm (for example, 2 μm), and the distance between the shield electrode 130 and the bottom of the trench 122 is 1 μm to 3 μm (for example, 2 μm). The space | interval with a side wall is 1 micrometer-3 micrometers (for example, 2 micrometers).

The depth of the n + -type source region 118 is 1 μm to 3 μm (for example, 2 μm), and the impurity concentration of the n + -type source region 118 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ¹⁹ cm). ^-3 ).
The depth of the p + -type contact region 120 is 1 μm to 3 μm (for example, 2 μm), and the impurity concentration of the p-type contact region 126 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ¹⁹ cm). ^-3 ).
The interlayer insulating film 132 is made of, for example, a silicon dioxide film formed by a CVD method, and the thickness of the interlayer insulating film 132 is 0.5 μm to 3 μm (for example, 1 μm).

The source electrode 134 is made of, for example, an Al film or an Al alloy film (for example, an AlSi film), and the thickness of the source electrode 130 is 1 μm to 10 μm (for example, 3 μm).
The drain electrode 136 is formed of a laminated film in which Ti, Ni, and Au are laminated in this order, and the thickness of the drain electrode 136 is 0.2 μm to 1.5 μm (for example, 1 μm).

2. Effects of Semiconductor Device According to the semiconductor device 100 according to the first embodiment, the shield electrode 130 includes the high resistance region 130a located on the drain region 112 side and the low resistance region 130b located on the gate electrode 126 side as shield electrodes. (See FIG. 1A), in the high resistance region 130a, the resistance value of the resistor Ra (see FIG. 4) in the region is higher than the resistance value of the resistor Rb (see FIG. 4). Therefore, the potential change of the drain electrode at the time of switch-off can be moderated, so that ringing generated at the time of switch-off can be suppressed and the surge voltage can be reduced (see FIG. 1B). Further, in the low resistance region 130b, since the resistance value of the resistor Rb (see FIG. 4) in the region is lower than the resistance value of the resistor Ra (see FIG. 4), a potential difference generated along the wiring of the shield electrode 130. Therefore, it is possible to suppress malfunction (self-turn-on) that occurs due to the rise of the gate voltage V _{GS in} the latter half of the switching period (see symbol A in FIG. 1B). In addition, the presence of the low resistance region 130b can increase the switching speed (see FIG. 1B), thereby preventing an increase in switching loss.

  Further, according to the semiconductor device 100 according to the first embodiment, as the shield electrode 130, both the high resistance region 130a and the low resistance region 130b are made of the same semiconductor material containing impurities, and the impurity concentration of the low resistance region 130b is high. Since the shield electrode higher than the impurity concentration of the resistance region 130a is provided, the electrical resistivity of the high resistance region 130a and the low resistance region 130b can be set to a desired value relatively easily by setting the impurity doping amount to an appropriate value. Can be set to a value.

  Further, according to the semiconductor device 100 according to the first embodiment, the shield electrode 130 includes the shield electrode positioned at the position where the high resistance region 130a and the low resistance region 130b are in contact with each other. As can be seen, the shield electrode structure can be formed relatively easily.

3. Manufacturing Method of Semiconductor Device The semiconductor device 100 according to the first embodiment can be manufactured by a manufacturing method (a manufacturing method of a semiconductor device according to the first embodiment) having the following manufacturing process.

(1) Semiconductor Substrate Preparation Step As shown in FIGS. 5A to 5C, an n + type drain region 112, an n − type drift region 114 adjacent to the n + type drain region 112, and an n − type drift region 114. A semiconductor substrate 110 including a p-type base region 116 adjacent to the p-type base region 116, an n + -type source region 118 adjacent to the p-type base region 116, and a p + -type contact region 120 is prepared.

(2) Trench Formation Step Thereafter, as shown in FIG. 5D, a mask M3 is formed on the surface of the semiconductor substrate 110, and the n − type drift layer 114 is formed from the surface of the p-type base region 116 using the mask M as a mask. The trench 122 is formed to reach The depth of the trench 122 is, for example, 11 μm.

(3) First Electrical Insulating Region Formation Step Thereafter, as shown in FIG. 6A, a silicon oxide film 128 ′ is formed on the inner surface of the trench 122 and the surface of the semiconductor substrate 110 by a thermal oxidation method. Are the bottom and side walls of the electrically insulating region 128. In the first electrically insulating region forming step, the silicon oxide film 128 ′ at the bottom is formed thick by CVD, and then the silicon oxide film 128 ′ at the sidewall is formed by thermal oxidation. It is good.

(4) High Resistance Region Formation Step Thereafter, as shown in FIG. 6B, a high resistance polysilicon film 130a ′ is formed in the trench 122 and on the surface of the semiconductor substrate 110 by the CVD method. As shown in (c), the high resistance polysilicon film 130a ′ is etched back, leaving a high resistance polysilicon film 130a ′ having a predetermined thickness on the bottom of the electrically insulating region 128 inside the trench 122. The high resistance polysilicon film 130a ′ is removed. As a result, a high resistance region 130 a is formed on the bottom of the electrically insulating region 128 inside the trench 122.

(5) Low Resistance Region Formation Step Thereafter, as shown in FIG. 6D, a low resistance polysilicon film 130b ′ is formed in the trench 122 and on the surface of the semiconductor substrate 110 by the CVD method.
Thereafter, the low resistance polysilicon film 130b ′ is etched back to remove the low resistance polysilicon film 130b ′ while leaving the low resistance polysilicon film 130b ′ having a predetermined thickness on the high resistance region 130a inside the trench 122. To do. As a result, the low resistance region 130b is formed on the high resistance region 130a inside the trench 122, and as a whole, the shield electrode 130 including the high resistance region 130a and the low resistance region 130b is formed (see FIG. 7A). . The shield electrode 130 is formed such that a part or all of the shield electrode 130 is positioned deeper than the bottom of the p-type base region 116.

(6) Second Electrical Insulating Region Formation Step Thereafter, a silicon oxide film having a predetermined thickness is formed on the low resistance region 130b inside the trench 122 by CVD, and this is used as the top of the electrical insulating region 128. (See FIG. 7B.)

(7) Gate Insulating Film Forming Step Thereafter, as shown in FIG. 7C, the silicon oxide film 128 ′ formed at the site where the gate insulating film 124 is formed is removed by wet etching. Thereafter, as shown in FIG. 7D, a silicon oxide film 124 ′ is formed on the surface of the semiconductor substrate 110 and a portion where the insulating film 124 is formed on the inner surface of the trench 122 by a thermal oxidation method. The gate insulating film 124 is used.

(8) Gate Electrode Formation Step Thereafter, as shown in FIG. 8A, a low-resistance polysilicon film 126 ′ is formed from the surface side of the semiconductor substrate 110 so as to fill the trench 122. Thereafter, as shown in FIG. 8B, the low resistance polysilicon film 126 ′ is etched back, and the low resistance polysilicon film 126 ′ is left only in the trench 122. The upper part of the film 126 ′ is removed. As a result, a final gate electrode 126 is formed on the inner peripheral surface of the trench 122.

(9) Interlayer Insulating Film Forming Step Thereafter, the silicon oxide film 124 ′ on the surface of the semiconductor substrate 110 is removed, and then a PSG film is formed from the surface side of the semiconductor substrate 110 by a vapor phase method. The thermal oxide film of silicon and the PSG film are removed by etching, leaving a predetermined portion on the upper part of the film. As a result, an interlayer insulating film 132 is formed on the gate electrode 126 as shown in FIG.

(10) Source and Drain Electrode Formation Step Thereafter, as shown in FIG. 8D, a source electrode 134 is formed so as to cover the semiconductor substrate 110 and the interlayer insulating film 132, and a drain is formed on the surface of the n + type drain layer 112. An electrode 136 is formed.

  By performing the above steps, the semiconductor device 100 according to the first embodiment can be manufactured.

[Embodiment 2]
The semiconductor device 101 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the shield electrode is different from that of the semiconductor device 100 according to the first embodiment. That is, as shown in FIG. 9, in the semiconductor device 102 according to the second embodiment, the high resistance region 130a and the low resistance region 130b are made of different materials, and the electrical resistivity of the material constituting the low resistance region 130b is high. It is lower than the electrical resistivity of the material constituting the resistance region 130a (see FIG. 9).

  As a material constituting the high resistance region 130a, for example, high resistance polysilicon formed by a CVD method can be used. For the low resistance region 130b, a refractory metal (for example, W, Mo, Ta, Nb, etc.) or other metal (for example, Cu, etc.) can be used.

As described above, the semiconductor device 101 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in the configuration of the shield electrode, but the high resistance region 130a positioned on the drain region 112 side as the shield electrode, Since the shield electrode 130 having the low resistance region 130b located on the gate electrode 126 side is provided (see FIG. 9), in the high resistance region 130a, as in the case of the semiconductor device 100 according to the first embodiment, Since the resistance value of the resistor Ra (see FIG. 4) in the region is higher than the resistance value of the resistor Rb (see FIG. 4), the potential change of the drain electrode at the time of switch-off can be moderated. Ringing that occurs when the switch is turned off can be suppressed and the surge voltage can be reduced. Further, in the low resistance region 130b, since the resistance value of the resistor Rb (see FIG. 4) in the region is lower than the resistance value of the resistor Ra (see FIG. 4), a potential difference generated along the wiring of the shield electrode 130. And the malfunction (self-turn-on) that occurs due to the rise of the gate voltage V _{GS in} the second half of the switching period can be suppressed. In addition, the presence of the low resistance region 130b can increase the switching speed, thereby preventing an increase in switching loss.

  In addition, according to the semiconductor device 101 according to the second embodiment, as the shield electrode 130, the high resistance region 130a and the low resistance region 130b are made of different materials, and the electrical resistivity of the material constituting the low resistance region 130b is high resistance. Since the shield electrode lower than the electrical resistivity of the material constituting the region 130a is provided, the electrical resistance of the high resistance region 130a and the low resistance region 130b can be selected by appropriately selecting the material of the high resistance region 130a and the low resistance region 130b. The rate can be selected from a wide range.

[Embodiment 3]
The semiconductor device according to the third embodiment has basically the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the shield electrode is different from that of the semiconductor device 100 according to the first embodiment. That is, as shown in FIG. 10, in the semiconductor device 102 according to the third embodiment, the high resistance region 130 a and the low resistance region 130 b are located at positions separated from each other via the electrically insulating region 128.

  The interval between the high resistance region 130a and the low resistance region 130b can be set as appropriate, but can be set to 1 μm, for example.

As described above, the semiconductor device 102 according to the third embodiment is different from the semiconductor device 100 according to the first embodiment in the configuration of the shield electrode, but as a shield electrode, the high resistance region 130a positioned on the drain region 112 side, Since the shield electrode 130 having the low resistance region 130b located on the gate electrode 126 side is provided (see FIG. 10), the resistance in the high resistance region 130a is similar to that in the semiconductor device 100 according to the first embodiment. Since Ra (see FIG. 4) becomes high, the potential change of the drain electrode when the switch is turned off can be moderated, thereby suppressing the ringing generated when the switch is turned off and reducing the surge voltage. In addition, since the resistance Rb (see FIG. 4) is low in the low resistance region 130b, a potential difference generated along the wiring of the shield electrode 130 can be reduced, and the gate-source capacitance _CGS is reduced to reduce the gate. By reducing the source coupling, it is possible to suppress malfunction (self-turn-on) that occurs due to the rise of the gate voltage V _{GS in} the second half of the switching period. In addition, the presence of the low resistance region 130b can increase the switching speed, thereby reducing the problem of increasing the switching loss.

  In addition, according to the semiconductor device 102 according to the third embodiment, the shield electrode 130 includes the shield electrode positioned at a position where the high resistance region 130a and the low resistance region 130b are separated from each other via the electrically insulating region 128. In the high resistance region 130a, since it becomes difficult to be influenced by the low resistance region 130b, the potential change of the drain electrode at the time of switching off can be made more gradual, and ringing generated at the time of switching off can be further reduced. It is possible to suppress the surge voltage and further reduce the surge voltage.

  As mentioned above, although this invention was demonstrated based on said embodiment, this invention is not limited to said embodiment. The present invention can be implemented in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) In the first embodiment, for example, high resistance polysilicon formed by the CVD method is used as the high resistance region 130a, and low resistance polysilicon formed by, for example, the CVD method is used as the low resistance region 130b. However, the present invention is not limited to this. You may use materials other than these.

(2) In the second embodiment, for example, high resistance polysilicon formed by a CVD method is used as the high resistance region 130a, and a refractory metal (for example, W, Mo, Ta, Nb, etc.) is used as the low resistance region 130b. .) And other metals (for example, Cu, etc.) are used, but the present invention is not limited to this. You may use materials other than these.

(3) In the third embodiment, the shield electrode 130 is used as the shield electrode. The shield electrode 130 is located at a position where the high resistance region 130a and the low resistance region 130b are separated from each other via the electrically insulating region 128. As shown in b), the electrically insulating region 128 sandwiched between the high resistance region 130a and the low resistance region 130b of the electrically insulating region 128 partially has an opening 138 as a shield electrode. Alternatively, a shield electrode having a structure in which the high resistance region 130a and the low resistance region 130b are partially in contact with each other through the opening 138 may be used (Modification 1).

With such a configuration, by setting the size, pitch, and the like of the openings 138 as described above, it is possible to reduce ringing and surge voltage generated at the time of switching off, and in the latter half of the switching period. The effect of preventing malfunction (self-turn-on) and an increase in switching loss that occur due to the rise of V _GS can be realized in a well-balanced manner.

(4) In the first embodiment, as the shield electrode, both the high resistance region 130a and the low resistance region 130b are made of the same semiconductor material containing impurities, and the impurity concentration of the low resistance region 130b is the impurity of the high resistance region 130a. The shield electrode having a higher concentration is used. In the second embodiment, the high resistance region 130a and the low resistance region 130b are made of different materials as the shield electrode, and the electrical resistivity of the material constituting the low resistance region 130b is high. Although the shield electrode lower than the electrical resistivity of the material constituting the resistance region 130a is used, the present invention is not limited to this. For example, as shown in FIG. 12, the high resistance region 130a and the low resistance region 130b are made of the same material, and are substantially parallel to the stripe longitudinal direction of the shield electrode 130 (the longitudinal direction of the trench formed in the stripe shape). A shield electrode having a shape in which the cross-sectional area of the low-resistance region 130b when cut along a plane perpendicular to the longitudinal direction of the shield electrode is larger than the cross-sectional area of the high-resistance region 130a when cut along the same plane (Modifications 2 and 3; see FIGS. 12 and 13).

  Even with this configuration, a shield electrode having a high resistance region (high resistance region 130a) located on the drain region 112 side and a low resistance region (low resistance region 130b) located on the gate electrode 126 side can be obtained. Thus, the semiconductor device 100 according to the first embodiment has the effect. In this case, the shield electrode 130 may have various cross-sectional shapes such as an inverted triangle, an inverted pentagon, a baseball home base shape, and a push pin shape.

(5) Although the power MOSFET is taken as an example of the semiconductor device 100 in the first embodiment, the present invention is not limited to this. The present invention can be variously applied to devices other than the power MOSFET without departing from the spirit of the present invention.

(6) In the first embodiment, the high resistance region 130a and the low resistance region 130b are set to the same thickness, but the present invention is not limited to this. The low resistance region 130b may be thinner than the high resistance region 130a (Modification 4; see FIG. 14), and the low resistance region 130b may be thinner than the high resistance region 130a (Modification 5). 15).

  In the case of the modified example 4, it is possible to increase the effect of reducing ringing and surge voltage generated when the switch is turned off. In the case of the modified example 5, it is possible to increase the effect of preventing malfunction (self-turn-on) and an increase in switching loss caused by VGS rising in the latter half of the switching period.

(7) The semiconductor device 100 according to the first embodiment can be manufactured by a method different from the method described in the first embodiment. For example, as shown in FIGS. 16 and 17, the n + type source region 118 and the p + type contact region 120 may be formed after the shield electrode 130 and the gate electrode 126 are formed. Further, for example, as shown in FIGS. 18 and 19, after the shield electrode 130 and the gate electrode 126 are formed, the n + -type source region 118, the p-type base region 116, and the p + -type contact region 120 may be formed. Good.

  100, 100a, 100b, 101, 102, 103, 104, 105, 106, 107 ... semiconductor device, 110 ... semiconductor substrate, 112 ... n + type drain region, 114 ... n- type drift region, 116 ... p type base region, 118 ... n + type source region, 120 ... p + type contact region, 122 ... trench, 124 ... gate insulating film, 126 ... gate electrode, 128 ... electrically insulating region, 130 ... shield electrode, 130a ... high resistance region, 130b ... low Resistance region, 132 ... interlayer insulating film, 134 ... source electrode, 136 ... drain electrode, 138 ... opening, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 ... mask

  The present invention relates to a method for manufacturing a semiconductor device.

Claims (9)

A drain region of the first conductivity type, a drift region of the first conductivity type adjacent to the drain region, a base region of the second conductivity type adjacent to the drift region, and a source of the first conductivity type adjacent to the base region A semiconductor substrate including a region;
A trench formed in the semiconductor substrate, having a bottom adjacent to the drift region, and a side wall adjacent to the base region and the drift region, and formed in a stripe shape in plan view;
A gate electrode disposed in the trench and facing the base region via a gate insulating film at a portion of the side wall;
A shield electrode disposed in the trench and located between the gate electrode and the bottom of the trench;
An electrically insulating region in the trench extending between the gate electrode and the shield electrode, further extending along the sidewall and the bottom of the trench and separating the shield electrode from the sidewall and the bottom; ,
A source electrode formed above the semiconductor substrate and electrically connected to the source region and the shield electrode;
A drain electrode formed adjacent to the drain region, and a semiconductor device comprising:
The semiconductor device, wherein the shield electrode has a high resistance region located on the drain region side and a low resistance region located on the gate electrode side. The semiconductor device according to claim 1,
Both the high resistance region and the low resistance region are made of the same semiconductor material containing impurities, and the impurity concentration of the low resistance region is higher than the impurity concentration of the high resistance region. The semiconductor device according to claim 1,
The high resistance region and the low resistance region are made of different materials, respectively, and the electrical resistivity of the material constituting the low resistance region is lower than the electrical resistivity of the material constituting the high resistance region apparatus. The semiconductor device according to claim 1,
The high resistance region and the low resistance region are each made of the same material, and the cross-sectional area of the low resistance region when cut along a plane perpendicular to the stripe longitudinal direction of the shield electrode is perpendicular to the longitudinal direction of the shield electrode. A semiconductor device characterized in that it is larger than the cross-sectional area of the high resistance region when cut by a flat surface. In the semiconductor device according to claim 1,
The semiconductor device, wherein the high resistance region and the low resistance region are located in contact with each other. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the high resistance region and the low resistance region are located at positions separated from each other via the electrically insulating region. The semiconductor device according to claim 6.
Of the electrically insulating region, the electrically insulating region sandwiched between the high resistance region and the low resistance region partially has an opening,
The high resistance region and the low resistance region are in partial contact with each other through the opening. The semiconductor device according to claim 2 or 3,
The semiconductor device characterized in that the low resistance region is thinner than the high resistance region. The semiconductor device according to claim 2 or 3,
The semiconductor device, wherein the high resistance region is thinner than the low resistance region.

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