JP2017539121A5 - - Google Patents

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JP2017539121A5
JP2017539121A5 JP2017522343A JP2017522343A JP2017539121A5 JP 2017539121 A5 JP2017539121 A5 JP 2017539121A5 JP 2017522343 A JP2017522343 A JP 2017522343A JP 2017522343 A JP2017522343 A JP 2017522343A JP 2017539121 A5 JP2017539121 A5 JP 2017539121A5
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power mode
access terminal
power
frame structure
request
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JP2017539121A (ja
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JP2017522343A 2014-10-31 2015-10-30 低電力スケジューリング Active JP6585170B2 (ja)

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US201462073520P 2014-10-31 2014-10-31
US62/073,520 2014-10-31
US14/927,174 US10405278B2 (en) 2014-10-31 2015-10-29 Low power scheduling
US14/927,174 2015-10-29
PCT/US2015/058252 WO2016070004A1 (en) 2014-10-31 2015-10-30 Low power scheduling

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JP2017539121A JP2017539121A (ja) 2017-12-28
JP2017539121A5 true JP2017539121A5 (enExample) 2018-11-15
JP6585170B2 JP6585170B2 (ja) 2019-10-02

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US (3) US10405278B2 (enExample)
EP (2) EP3213563B1 (enExample)
JP (2) JP6585170B2 (enExample)
KR (2) KR102318708B1 (enExample)
CN (1) CN107113725B (enExample)
WO (1) WO2016070004A1 (enExample)

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