JP2017535967A - フリップダイの組立方法、製造方法、装置及び電子機器 - Google Patents

フリップダイの組立方法、製造方法、装置及び電子機器 Download PDF

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JP2017535967A
JP2017535967A JP2017528196A JP2017528196A JP2017535967A JP 2017535967 A JP2017535967 A JP 2017535967A JP 2017528196 A JP2017528196 A JP 2017528196A JP 2017528196 A JP2017528196 A JP 2017528196A JP 2017535967 A JP2017535967 A JP 2017535967A
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substrate
flip die
flip
die
attaching
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JP6398008B2 (ja
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スウ、クアンボ
ワン、チョウ
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ゴルテック．インク
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

本発明は、フリップダイの組立方法、製造方法、装置及び電子機器を開示する。フリップダイの組み立てに用いられる該方法は、フリップダイをレーザー透明性の第１基板に仮結合させることと、接合突起を受け基板における接続パッドに位置合わせすることと、第１基板からフリップダイを剥離するために、第１基板側からレーザーで第１基板を照射することと、フリップダイを受け基板に付着させることにより、組み立てを完了させることと、を含み、前記フリップダイの接合突起はフリップダイの第１基板に対向する側に位置する。本発明により、より速い組み立て速度に達することができる。本発明により、より小さいチップサイズを実現することができる。本発明により、より低いチップ高さを実現することができる。

Description

本発明は、電子デバイスの製造分野に関し、より具体的には、フリップダイを組み立てる方法、フリップダイ装置を製造する方法、フリップダイ装置及びフリップダイ装置を含む電子機器に関する。
従来のフリップチップのパッケージ技術では、ピックアップヘッドを用いる方式により、パッケージされていないダイを受け基板に組み立てる。例えば、電子分野において、一般的に、既に製作を完了したが、パッケージされていないデバイスをダイ（ｄｉｅ）と称し、パッケージされたデバイスをチップと称する。パッケージされていないデバイスは、例えば、半導体デバイスであってもよい。明らかに説明するために、本明細書において、既に製作を完了したが、パッケージされていないフリップデバイス（パッケージされていないフリップチップ）をフリップダイと称し、パッケージされたフリップデバイスをフリップチップと称する。
図１Ａ〜１Ｅは、ピックアップヘッドを用いてダイを受け基板に組み立てる一例を示している。
図１Ａに示すように、ピックアップヘッド１０１によりダイ１０２をピックアップする。ダイ１０２はフリップ構造であり、その接合突起１０３は片側に位置する。図１Ｂに示すように、ダイ１０２の接合突起１０３にフラックス１０４を塗布する。続いて、図１Ｃに示すように、ダイ１０２を受け基板１０５に配置する。図１Ｄに示すように、リフロー処理により、接合突起１０３を受け基板１０５に接合させる。図１Ｄにおいて、さらに配分器１０６によりアンダーフィル剤１０７をダイ１０２の底部に加える。図１Ｅに示すように、アンダーフィル剤１０７を硬化させ、それによりダイの受け基板への組み立てを完了させる。
本発明の発明者は、従来技術の組立方法において、一般的にはダイを１個ずつピックアップし配置することを理解すべきである。そのため、大型のダイアレイ／マトリックスの組立（例えば、ディスプレイに用いられるマイクロ発光ダイオードアレイ）に対して、このような方式は時間がかかる。一般的に、ピックアップヘッドの方式により、１時間に最大で数千ユニット、例えば、約２０００ユニットを組み立てることができる。このような組み立て速度は、続いてコストの問題を引き起こす。
また、本発明の発明者は、さらに、ピックアップと配置方式の特性に制限されているため、処理されたダイのサイズが限定されていることを理解すべきである。例えば、ピックアップ可能なダイのサイズは１５０μｍ以上である。
本発明の１つの目的は、フリップダイを組み立てるための新しい技術的解決手段を提供することである。
本発明の一実施例によれば、フリップダイをレーザー透明性の第１基板に仮結合させることと、接合突起を受け基板における接続パッドに位置合わせすることと、第１基板からフリップダイを剥離するために、第１基板側からレーザーで第１基板を照射することと、フリップダイを受け基板に付着させ、組み立てを完了させることとを含む、フリップダイを組み立てるための方法を提供し、前記フリップダイの接合突起はフリップダイの第１基板に対向する側に位置する。
好ましくは、前記方法は、さらに、一側に接合突起を有するデバイスウェハを形成することを含む。好ましくは、前述のフリップダイをレーザー透明性の第１基板に仮結合させるステップは、さらに、他側においてデバイスウェハを第１基板に仮結合させることと、フリップダイを形成するために、デバイスウェハを分割することと、を含む。
好ましくは、前記方法は、さらに、剥離に用いられる既知の良好なデバイスを特定するために、第１基板におけるフリップダイを検出することを含む。
好ましくは、接合突起を受け基板における接続パッドに位置合わせするステップは、さらに、第１基板を反転することを含む。
好ましくは、レーザースクライブ、機械工具によるスクライブ又はエッチングによって、前述のデバイスウェハを分割するステップを実行する。
好ましくは、前記接合突起は半田突起である。好ましくは、前述のフリップダイを受け基板に付着させるステップは、さらに、フラックスによりフリップダイを受け基板に付着させることを含む。
好ましくは、前述のフリップダイを受け基板に付着させるステップは、さらに、重力の作用により、フリップダイを受け基板に付着させることを含む。
好ましくは、前述のフリップダイを受け基板に付着させるステップは、さらに、静電力の作用により、フリップダイを受け基板に付着させることを含む。
好ましくは、前記接続パッドに電圧を印加することによって前記静電力を印加する。
好ましくは、前記フリップダイは磁気材料を含み、前述のフリップダイを受け基板に付着させるステップは、さらに、電磁力の作用により、フリップダイを受け基板に付着させることを含む。
好ましくは、前記接合突起は半田突起であり、前記方法は、さらに、フリップダイを受け基板に接合させるために、半田突起をリフロー処理することと、フリップチップの底部を充填することと、を含む。
好ましくは、前述のフリップダイを受け基板に付着させるステップは、さらに、異方性導電層によりフリップダイを受け基板に付着させることを含む。好ましくは、前記方法は、さらに、フリップダイを受け基板に接合させるために、異方性導電層を処理することを含む。
好ましくは、異方性導電層は、異方性導電膜、異方性導電ペースト及び異方性導電テープの少なくとも１つである。
好ましくは、フリップダイは、仮結合層によりレーザー透明性の第１基板に仮結合され、前記方法は、さらに、仮結合層を除去することを含む。
本発明の別の実施例によれば、本発明による方法を用いてフリップダイを受け基板に組み立てることを含む、フリップダイ装置を製造するための方法を提供する。
本発明の別の実施例によれば、本発明による方法を用いて製造されたフリップダイ装置を提供する。
本発明の別の実施例によれば、本発明によるフリップダイ装置を含む電子機器を提供する。
また、当業者であれば、従来技術には多くの問題が存在するが、本発明の各実施例または請求項の技術的解決手段は１つまたは複数の面のみから改善することができ、従来技術又は背景技術に挙げられた全ての技術的問題を同時に解決する必要がないことを理解すべきである。当業者であれば、１つの請求項に言及されていない内容を該請求項を限定するものとしてはならないことを理解すべきである。
以下、図面を参照して本発明の例示的な実施例を詳細に説明し、よって本発明のその他の特徴及び利点は明らかになる。
図面は明細書に結び付けられ明細書の一部となり本発明の実施例を示し、その説明とともに本発明の原理を解釈するのに用いられる。
従来技術のフリップダイを組み立てる一例を示す。 従来技術のフリップダイを組み立てる一例を示す。 従来技術のフリップダイを組み立てる一例を示す。 従来技術のフリップダイを組み立てる一例を示す。 従来技術のフリップダイを組み立てる一例を示す。 本発明の方法による一例示的な実施例を示すフローチャートである。 本発明によるフリップダイを組み立てるための一例を示す。 本発明によるフリップダイを組み立てるための一例を示す。 本発明によるフリップダイを組み立てるための一例を示す。 本発明によるフリップダイを組み立てるための一例を示す。 本発明によるフリップダイを組み立てるための一例を示す。 本発明によるフリップダイを組み立てるための別の例を示す。
以下、図面を参照して本発明の様々な例示的な実施例を詳細に説明する。注意すべきことは、別途具体的な説明がない限り、これらの実施例に記載の部品とステップの相対的な配置、数式及び数値は本発明の範囲を限定するものではない。
以下、少なくとも１つの例示的な実施例に対する説明は、実質的には解釈的なものに過ぎず、本発明及びその応用又は使用を限定するものではない。
かかる分野の一般的な技術者の公知の技術、方法及び装置については詳しく検討しないかも知れないが、適切な場合、前記技術、方法及び装置は明細書の一部と見なされるべきである。
ここで例示し検討される全ての例において、任何なる具体的な値は例示的なものに過ぎず、限定するためのものではないと解釈されるべきである。そのため、例示的な実施例のその他の例は異なる値を有することができる。
注意すべきことは、類似する記号とアルファベットは以下の図面において類似する項目を示すため、ある項目がある図面において定義された場合、後の図面において更に検討する必要がない。
以下、図面を参照して本発明の実施例と実例を説明する。
図２は本発明によるフリップダイを組み立てるための方法の一例示的な実施例を示すフローチャートである。
図２に示すように、ステップＳ２０１０において、フリップダイをレーザー透明性の第１基板に仮結合させる。フリップダイの接合突起はフリップダイの第１基板に対向する側に位置し、受け基板に取り付けられる。第１基板は、例えばサファイア基板である。
例えば、事前に一側に接合突起を有するデバイスウェハを形成してもよい。デバイスウェハの他側においてデバイスウェハを第１基板に仮結合させる。第１基板において、フリップダイを形成するために、デバイスウェハを分割する。例えば、レーザースクライブ、機械工具によるスクライブ又はエッチングにより前記ウェハを分割してもよい。
一例において、さらに、剥離に用いられる既知の良好なデバイスを特定するために、第１基板におけるフリップダイを検出してもよい。第１基板（受け基板ではなく）においてフリップダイを検出することができるため、選択的にレーザーを照射することにより既知の良好なデバイスのみを受けデバイスに組み立てることができる。この面で、本発明は有利である。
ステップＳ２０２０において、接合突起を受け基板における接続パッドに位置合わせする。
例えば、フリップダイの接合突起を接続パッドに位置合わせするために、第１基板を反転してもよい。
ステップＳ２０３０において、第１基板からフリップダイを剥離するために、第１基板側からレーザーで第１基板を照射する。
レーザー剥離技術は、一般的に半導体デバイスを形成するのに用いられる。従来技術には、まだレーザー剥離技術をダイの組立に応用する技術的解決手段がない。これは、レーザー剥離技術を半導体製造に応用する技術が新しい技術であるからである。また、一般的に、ダイの形成とダイの組立は２つの異なる技術であると考えられる。例えば、ダイの形成過程において、レーザー剥離プロセスの後、さらに、半導体ウェハに対して、その他の処理、例えば、様々な層、電極を形成する等を行う。ところが、例えば、ダイの組み立てにとって、ダイは一般的に仕上げられたチップである。
ステップＳ２０４０において、フリップダイを受け基板に付着させる。
例えば、前記接合突起が半田突起である場合、フラックスによりフリップダイを受け基板に付着させることができる。この場合、ステップＳ２０３０の前にステップＳ２０４０を実行することができる。
例えば、さらに、重力の作用により、フリップダイを受け基板に付着させてもよい。例えば、レーザーによりフリップダイを第１基板から剥離する時、重力の作用により、フリップダイは受け基板に落下し、又は残される。
例えば、さらに、静電力の作用により、フリップダイを受け基板に付着させてもよい。例えば、前記接続パッドに電圧を印加することによって前記静電力を印加する。
例えば、前記フリップダイは磁気材料を含み（例えば、接合突起は磁気材料を含む）、さらに、電磁力の作用により、フリップダイを受け基板に付着させてもよい。例えば、適切な電磁界を提供するために、受け基板側に磁気材料を設置する。
本発明において、接合突起が半田突起である場合、フリップダイを受け基板に接合させるために、半田突起をリフロー処理し、フリップチップの底部をアンダーフィルしてもよい。
例えば、本発明において、さらに、異方性導電層によりフリップダイを受け基板に付着させることができる。続いて、フリップダイを受け基板に接合させるために、異方性導電層を処理してもよい。例えば、異方性導電層は、異方性導電膜、異方性導電ペースト及び異方性導電テープの少なくとも１つであってもよい。
例えば、フリップダイは、仮結合層によりレーザー透明性の第１基板に仮結合させてもよい。この場合、フリップダイを剥離した後、さらに、フリップダイから仮結合層を除去することができる。ところが、当業者であれば、仮結合層は全ての場合に必ず必要なものではないことを理解すべきである。例えば、第１基板に仮結合される部分はフリップダイの一部であってもよい。
明らかに、上記説明により、当業者は、前述において順番通りにステップＳ２０１０、Ｓ２０２０、Ｓ２０３０及びＳ２０４０を挙げたが、上記順番に従わず前記ステップを実行してもよい。例えば、レーザーで第１基板を照射する（Ｓ２０３０）前にフリップダイを受け基板に付着させてもよい（Ｓ２０４０）。そして、レーザーで第１基板を照射する（Ｓ２０３０）前にフリップダイを受け基板に接合させてもよい。
該別の実施例において、本発明は、さらに、フリップダイ装置を製造するための方法を含む。該製造方法は、フリップダイ装置を形成するために、本発明によるフリップダイを組み立てるための方法を用いてフリップダイを受け基板に組み立てることを含む。前記受け基板は、例えば、ディスプレイパネル又は表示基板である。前記フリップダイ装置は、例えばディスプレイ装置である。
該別の実施例において、本発明は、さらに、フリップダイ装置、例えば、ディスプレイ装置又はパッケージされたチップを含む。前記実施例によるフリップダイ装置を製造するための方法を用いて前記フリップダイ装置を製造することができる。本発明によるフリップダイ装置は、従来技術のサイズよりも小さいダイを含むことができる。
該別の実施例において、本発明は、さらに、電子機器を含む。該電子機器は、本発明によるフリップダイ装置を含む。該電子機器は、例えば、携帯電話、タブレットＰＣ、テレビ、プリンターなどであってもよい。
本発明の技術的解決手段において、ピックアップヘッドを用いる従来技術に比べて、本発明の技術的解決手段能は、サイズのより小さいデバイスを組み立てることができる。例えば、本発明により、１５０μｍより小さい（例えば、１０μｍ）のフリップダイを組み立てることができる。即ち、本発明により、より小さいチップサイズを実現することができる。
好ましくは、第１基板に直接ウェハを形成することができるため、従来技術により組み立てられたデバイスに比べて、本発明を利用して組み立てられたフリップダイはより薄くなる。即ち、本発明により、より低いチップ高さを実現することができる。
好ましくは、本発明により、例えば、１時間に２０００００ユニットを組み立てる速度に達することができる。そのため、ピックアップヘッドを用いる従来技術に比べて、本発明の組立速度はより速く、そのためコストもより低い。
本発明の発明者は、従来技術にはまだレーザー剥離をダイの組み立てに応用する技術的解決手段がないことを発見した。そして、当業者は、このような技術的解決手段による技術的効果をまだ意識していない。言い換えれば、当業者は、まだ、この面で改善する任何なる動力がない。
以下、図３Ａ〜３Ｅを参照して、本発明によるフリップダイを組み立てるための例を説明する。
図３Ａに示すように、仮結合層２０３によりデバイスウェハ２０１をレーザー透明性の第１基板（例えば、サファイア基板）２０４に仮結合させる。デバイスウェハ２０１は、第１基板の反対側に接合突起２０２を有する。
図３Ｂに示すように、例えば、レーザースクライブ、機械工具によるスクライブ又はエッチング（例えば、ドライエッチング又はウェットエッチング）によりデバイスウェハ２０１をフリップダイ２０５に分割する。
既知の良好なデバイスを特定するために、第１基板におけるフリップダイ２０５をテストすることができ、受け基板に組み立てる。
図３Ｃに示すように、第１基板２０４を反転する。続いて、接合突起２０２を受け基板２０７における接続パッド２０６に位置合わせする。レーザー２０８により選択的にフリップダイ２０５を照射することによって、フリップダイ２０５を剥離する。
この例において、レーザーを照射する前にフリップダイ２０５を受け基板２０７に付着させてもよい。さらに、レーザーを照射する前にフリップダイ２０５を受け基板２０７に接合させてもよい。
図３Ｄに示すように、第１基板２０４を持ち上げ、フリップダイ２０５を受け基板２０７に残す。
接合突起が半田突起である場合、リフローによりフリップダイ２０５を受け基板２０７に接合させることができる。
図３Ｅに示すように、アンダーフィル剤２０９でフリップダイ２０５の底部を充填することができる。続いて、アンダーフィル剤２０９を硬化させる。
以下、図４を参照して、本発明によるフリップダイを組み立てるための別の例を説明する。
図４に示す例において、異方性導電層３１０によりフリップダイ２０５と受け基板２０７を接合させる。図４では、図３Ａ〜３Ｅにおける類似するステップを省略している。
既に実例を通じて本発明の幾つかの特定の実施例を詳細に説明したが、当業者であれば、以上の実例は説明するためのものに過ぎず、本発明の範囲を制限するためのものではないことを理解すべきである。当業者であれば、本発明の範囲と趣旨を逸脱しない限り、上記実施例を修正することができることを理解すべきである。本発明の範囲は、添付の特許請求の範囲により制限される。

Claims (17)

  1. フリップダイの組み立てに用いられる方法であって、
    フリップダイをレーザー透明性の第１基板に仮結合させることと、
    接合突起を受け基板における接続パッドに位置合わせすることと、
    第１基板からフリップダイを剥離するために、第１基板側からレーザーで第１基板を照射することと、
    フリップダイを受け基板に付着させることにより、組み立てを完了させることと、
    を含み、
    前記フリップダイの接合突起はフリップダイの第１基板に対向する側に位置する、
    ことを特徴とする方法。
  2. さらに、一側に接合突起を有するデバイスウェハを形成することを含み、
    前述のフリップダイをレーザー透明性の第１基板に仮結合させるステップは、さらに、
    デバイスウェハの他側においてデバイスウェハを第１基板に仮結合させることと、
    フリップダイを形成するために、デバイスウェハを分割することと、
    を含む、ことを特徴とする請求項１に記載の方法。
  3. さらに、剥離に用いられる既知の良好なデバイスを特定するために、第１基板におけるフリップダイを検出することを含む、ことを特徴とする請求項１又は２に記載の方法。
  4. 接合突起を受け基板における接続パッドに位置合わせするステップは、さらに、第１基板を反転させることを含む、ことを特徴とする請求項１又は２に記載の方法。
  5. レーザースクライブ、機械工具によるスクライブ又はエッチングによって、前述のデバイスウェハを分割するステップを実行する、ことを特徴とする請求項２に記載の方法。
  6. 前記接合突起は半田突起であり、前述のフリップダイを受け基板に付着させるステップは、さらに、フラックスによりフリップダイを受け基板に付着させることを含む、ことを特徴とする請求項１に記載の方法。
  7. 前述のフリップダイを受け基板に付着させるステップは、さらに、重力の作用により、フリップダイを受け基板に付着させることを含む、ことを特徴とする請求項１に記載の方法。
  8. 前述のフリップダイを受け基板に付着させるステップは、さらに、静電力の作用により、フリップダイを受け基板に付着させることを含む、ことを特徴とする請求項１に記載の方法。
  9. 前記接続パッドに電圧を印加することによって前記静電力を印加する、ことを特徴とする請求項８に記載の方法。
  10. 前記フリップダイは磁気材料を含み、前述のフリップダイを受け基板に付着させるステップは、さらに、電磁力の作用により、フリップダイを受け基板に付着させることを含む、ことを特徴とする請求項１に記載の方法。
  11. 前記接合突起は半田突起であり、前記方法は、さらに、
    フリップダイを受け基板に結合させるために、半田突起をリフロ―処理することと、
    フリップチップの底部をアンダーフィルすることと、
    を含むことを特徴とする請求項１に記載の方法。
  12. 前述のフリップダイを受け基板に付着させるステップは、さらに、
    異方性導電層によりフリップダイを受け基板に付着させることを含み、
    前記方法は、さらに、
    フリップダイを受け基板に接合させるために、異方性導電層を処理することを含む、
    ことを特徴とする請求項１に記載の方法。
  13. 異方性導電層は、異方性導電膜、異方性導電ペースト及び異方性導電テープの少なくとも１つである、ことを特徴とする請求項１２に記載の方法。
  14. フリップダイは仮結合層により第１基板に仮結合され、
    前記方法は、さらに、仮結合層を除去することを含む、
    ことを特徴とする請求項１に記載の方法。
  15. フリップダイ装置を製造するための方法であって、
    請求項１に記載の方法を用いてフリップダイを受け基板に組み立てることを含む、
    ことを特徴とする方法。
  16. 請求項１５に記載の方法により製造される、ことを特徴とするフリップダイ装置。
  17. 請求項１６に記載のフリップダイ装置を含む、ことを特徴とする電子機器。
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