JP2017516234A - 次の読取りアドレスプリフェッチングによるメモリ容量圧縮および／またはメモリ帯域幅圧縮を利用するメモリコントローラ、ならびに関連するプロセッサベースシステムおよび方法 - Google Patents

次の読取りアドレスプリフェッチングによるメモリ容量圧縮および／またはメモリ帯域幅圧縮を利用するメモリコントローラ、ならびに関連するプロセッサベースシステムおよび方法 Download PDF

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JP2017516234A
JP2017516234A JP2016568009A JP2016568009A JP2017516234A JP 2017516234 A JP2017516234 A JP 2017516234A JP 2016568009 A JP2016568009 A JP 2016568009A JP 2016568009 A JP2016568009 A JP 2016568009A JP 2017516234 A JP2017516234 A JP 2017516234A
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memory
cache
data
controller
compressed
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JP2017516234A5 (enExample
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マテウス・コーネリス・アントニウス・アドリアヌス・ヘディーズ
ナタラジャン・ヴァイディアナタン
コリン・ビートン・ヴェリリ
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クアルコム，インコーポレイテッド
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
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    • G06F2212/60—Details of cache memory
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    • G—PHYSICS
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    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2016568009A 2014-05-21 2015-05-21 次の読取りアドレスプリフェッチングによるメモリ容量圧縮および／またはメモリ帯域幅圧縮を利用するメモリコントローラ、ならびに関連するプロセッサベースシステムおよび方法 Pending JP2017516234A (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201462001545P 2014-05-21 2014-05-21
US62/001,545 2014-05-21
US201462092326P 2014-12-16 2014-12-16
US201462092409P 2014-12-16 2014-12-16
US62/092,409 2014-12-16
US62/092,326 2014-12-16
US14/716,108 US9740621B2 (en) 2014-05-21 2015-05-19 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
US14/716,108 2015-05-19
PCT/US2015/031885 WO2015179591A1 (en) 2014-05-21 2015-05-21 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods

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JP2017516234A true JP2017516234A (ja) 2017-06-15
JP2017516234A5 JP2017516234A5 (enExample) 2018-06-14

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US (1) US9740621B2 (enExample)
EP (1) EP3146435A1 (enExample)
JP (1) JP2017516234A (enExample)
CN (1) CN106462495B (enExample)
WO (1) WO2015179591A1 (enExample)

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US9740621B2 (en) 2017-08-22
US20150339237A1 (en) 2015-11-26
CN106462495B (zh) 2019-06-04
CN106462495A (zh) 2017-02-22
WO2015179591A1 (en) 2015-11-26

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