CN106462495B - 存储器控制器以及基于处理器的系统和方法 - Google Patents

存储器控制器以及基于处理器的系统和方法 Download PDF

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Publication number
CN106462495B
CN106462495B CN201580026261.3A CN201580026261A CN106462495B CN 106462495 B CN106462495 B CN 106462495B CN 201580026261 A CN201580026261 A CN 201580026261A CN 106462495 B CN106462495 B CN 106462495B
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memory
data
cache
controller
pmd
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CN106462495A (zh
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马托伊斯·科内利斯·安东尼乌斯·阿德里安努·黑德斯
纳塔拉詹·瓦伊迪安阿坦
科兰·比顿·韦里利
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Qualcomm Inc
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Qualcomm Inc
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
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    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
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    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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    • G—PHYSICS
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
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    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
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    • G—PHYSICS
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    • G06F2212/1044—Space efficiency improvement
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    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1056—Simplification
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/602—Details relating to cache prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201580026261.3A 2014-05-21 2015-05-21 存储器控制器以及基于处理器的系统和方法 Expired - Fee Related CN106462495B (zh)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201462001545P 2014-05-21 2014-05-21
US62/001,545 2014-05-21
US201462092409P 2014-12-16 2014-12-16
US201462092326P 2014-12-16 2014-12-16
US62/092,409 2014-12-16
US62/092,326 2014-12-16
US14/716,108 US9740621B2 (en) 2014-05-21 2015-05-19 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
US14/716,108 2015-05-19
PCT/US2015/031885 WO2015179591A1 (en) 2014-05-21 2015-05-21 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods

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CN106462495A CN106462495A (zh) 2017-02-22
CN106462495B true CN106462495B (zh) 2019-06-04

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US (1) US9740621B2 (enExample)
EP (1) EP3146435A1 (enExample)
JP (1) JP2017516234A (enExample)
CN (1) CN106462495B (enExample)
WO (1) WO2015179591A1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9740621B2 (en) * 2014-05-21 2017-08-22 Qualcomm Incorporated Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
US10838862B2 (en) 2014-05-21 2020-11-17 Qualcomm Incorporated Memory controllers employing memory capacity compression, and related processor-based systems and methods
US10503661B2 (en) 2014-05-21 2019-12-10 Qualcomm Incorporated Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system
US9652384B2 (en) * 2014-12-16 2017-05-16 Intel Corporation Apparatus, system and method for caching compressed data
JP6605323B2 (ja) 2015-12-24 2019-11-13 ルネサスエレクトロニクス株式会社 半導体装置、データ処理システム及び半導体装置の制御方法
US10191850B2 (en) 2016-03-31 2019-01-29 Qualcomm Incorporated Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system
US10067706B2 (en) 2016-03-31 2018-09-04 Qualcomm Incorporated Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system
US10176090B2 (en) * 2016-09-15 2019-01-08 Qualcomm Incorporated Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems
US10126979B2 (en) 2016-10-04 2018-11-13 Qualcomm Incorporated Bus encoding using metadata
US10061698B2 (en) 2017-01-31 2018-08-28 Qualcomm Incorporated Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
WO2018165939A1 (en) * 2017-03-16 2018-09-20 Intel Corporation Flash data compression decompression method and apparatus
US10169246B2 (en) * 2017-05-11 2019-01-01 Qualcomm Incorporated Reducing metadata size in compressed memory systems of processor-based systems
CN108268381B (zh) * 2017-12-15 2021-12-24 中国航空工业集团公司西安飞行自动控制研究所 一种安全实现数据快速寻址的方法
US11449428B2 (en) * 2018-06-19 2022-09-20 Western Digital Technologies, Inc. Enhanced read-ahead capability for storage devices
US11086534B2 (en) 2018-06-28 2021-08-10 Apple Inc. Memory data distribution based on communication channel utilization
US10664325B1 (en) * 2018-09-06 2020-05-26 Rockwell Collins, Inc. System for limiting shared resource access in multicore system-on-chip (SoC)
SE544272C2 (en) * 2018-11-14 2022-03-22 Zeropoint Tech Ab Accessing compressed computer memory
US10606775B1 (en) * 2018-12-28 2020-03-31 Micron Technology, Inc. Computing tile
CN109857463B (zh) * 2019-01-30 2020-12-01 上海兆芯集成电路有限公司 加速压缩方法以及加速压缩装置
US11010059B2 (en) * 2019-07-30 2021-05-18 EMC IP Holding Company LLC Techniques for obtaining metadata and user data
TWI739227B (zh) * 2019-12-03 2021-09-11 智成電子股份有限公司 避免多餘記憶體存取的系統單晶片模組
US11422934B2 (en) 2020-07-14 2022-08-23 Micron Technology, Inc. Adaptive address tracking
US11409657B2 (en) 2020-07-14 2022-08-09 Micron Technology, Inc. Adaptive address tracking
US12147341B2 (en) 2020-08-06 2024-11-19 Alibaba Group Holding Limited Memory controller prioritizing writing compressed data
US11507516B2 (en) * 2020-08-19 2022-11-22 Micron Technology, Inc. Adaptive cache partitioning
CN114168495B (zh) * 2020-09-10 2025-09-23 桑迪士克科技股份有限公司 存储设备的增强的预读能力
CN114428764B (zh) * 2022-01-26 2024-04-02 重庆紫光华山智安科技有限公司 文件写入方法、系统、电子设备及可读存储介质
US12379841B2 (en) 2022-09-20 2025-08-05 Samsung Electronics Co., Ltd. Systems and methods for performing data compression in memory
US20250293704A1 (en) * 2024-03-14 2025-09-18 Qualcomm Incorporated Bandwidth Compressed Data Movement and Footprint Compression

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110055456A1 (en) * 2009-08-26 2011-03-03 Phison Electronics Corp. Method for giving read commands and reading data, and controller and storage system using the same
US20130138867A1 (en) * 2011-11-30 2013-05-30 International Business Machines Corporation Storing Multi-Stream Non-Linear Access Patterns in a Flash Based File-System

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2831602B2 (ja) 1995-01-13 1998-12-02 富士通株式会社 圧縮データ管理装置及び圧縮データ管理方法
US5696927A (en) 1995-12-21 1997-12-09 Advanced Micro Devices, Inc. Memory paging system and method including compressed page mapping hierarchy
JPH09259040A (ja) * 1996-03-25 1997-10-03 Sharp Corp キャッシュメモリ装置
US6353871B1 (en) 1999-02-22 2002-03-05 International Business Machines Corporation Directory cache for indirectly addressed main memory
US6523102B1 (en) 2000-04-14 2003-02-18 Interactive Silicon, Inc. Parallel compression/decompression system and method for implementation of in-memory compressed cache improving storage density and access speed for industry standard memory subsystems and in-line memory modules
US7047382B2 (en) 2000-11-29 2006-05-16 Quickshift, Inc. System and method for managing compression and decompression and decompression of system memory in a computer system
US6735673B2 (en) 2002-01-10 2004-05-11 Hewlett-Packard Development Company, L.P. Apparatus and methods for cache line compression
US6640283B2 (en) 2002-01-16 2003-10-28 Hewlett-Packard Development Company, L.P. Apparatus for cache compression engine for data compression of on-chip caches to increase effective cache size
US6944740B2 (en) 2002-03-27 2005-09-13 International Business Machines Corporation Method for performing compressed I/O with memory expansion technology
US6795897B2 (en) 2002-05-15 2004-09-21 International Business Machines Corporation Selective memory controller access path for directory caching
US6981119B1 (en) 2002-08-29 2005-12-27 Advanced Micro Devices, Inc. System and method for storing performance-enhancing data in memory space freed by data compression
US7512750B2 (en) 2003-12-31 2009-03-31 Intel Corporation Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
US7225297B2 (en) * 2004-05-28 2007-05-29 International Business Machines Corporation Compressed cache lines incorporating embedded prefetch history data
US7636813B2 (en) 2006-05-22 2009-12-22 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers
US8122216B2 (en) 2006-09-06 2012-02-21 International Business Machines Corporation Systems and methods for masking latency of memory reorganization work in a compressed memory system
US7975109B2 (en) 2007-05-30 2011-07-05 Schooner Information Technology, Inc. System including a fine-grained memory and a less-fine-grained memory
US8595437B1 (en) 2008-11-21 2013-11-26 Nvidia Corporation Compression status bit cache with deterministic isochronous latency
US8341380B2 (en) 2009-09-22 2012-12-25 Nvidia Corporation Efficient memory translator with variable size cache line coverage
US8539163B1 (en) 2010-12-17 2013-09-17 Amazon Technologies, Inc. Speculative reads
US10031850B2 (en) * 2011-06-07 2018-07-24 Sandisk Technologies Llc System and method to buffer data
WO2012168960A1 (en) 2011-06-07 2012-12-13 Hitachi, Ltd. Semiconductor storage apparatus and method of controlling semiconductor storage apparatus
KR101888074B1 (ko) 2012-01-09 2018-08-13 삼성전자주식회사 저장 장치 및 불휘발성 메모리 장치, 그리고 그것의 동작 방법
US8751830B2 (en) 2012-01-23 2014-06-10 International Business Machines Corporation Memory address translation-based data encryption/compression
US8830716B2 (en) 2012-09-29 2014-09-09 Intel Corporation Intelligent far memory bandwith scaling
CN104133780B (zh) * 2013-05-02 2017-04-05 华为技术有限公司 一种跨页预取方法、装置及系统
CN107608912B (zh) * 2013-08-20 2020-10-16 华为技术有限公司 内存物理地址查询方法和装置
US10503661B2 (en) 2014-05-21 2019-12-10 Qualcomm Incorporated Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system
US10838862B2 (en) 2014-05-21 2020-11-17 Qualcomm Incorporated Memory controllers employing memory capacity compression, and related processor-based systems and methods
US9740621B2 (en) * 2014-05-21 2017-08-22 Qualcomm Incorporated Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
US10372613B2 (en) * 2014-05-30 2019-08-06 Sandisk Technologies Llc Using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device
KR20160104387A (ko) * 2015-02-26 2016-09-05 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
JP2017072981A (ja) * 2015-10-07 2017-04-13 富士通株式会社 情報処理装置、キャッシュ制御方法およびキャッシュ制御プログラム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110055456A1 (en) * 2009-08-26 2011-03-03 Phison Electronics Corp. Method for giving read commands and reading data, and controller and storage system using the same
US20130138867A1 (en) * 2011-11-30 2013-05-30 International Business Machines Corporation Storing Multi-Stream Non-Linear Access Patterns in a Flash Based File-System

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WO2015179591A1 (en) 2015-11-26
US9740621B2 (en) 2017-08-22
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CN106462495A (zh) 2017-02-22
EP3146435A1 (en) 2017-03-29

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