WO2015179591A1 - Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods - Google Patents

Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods Download PDF

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Publication number
WO2015179591A1
WO2015179591A1 PCT/US2015/031885 US2015031885W WO2015179591A1 WO 2015179591 A1 WO2015179591 A1 WO 2015179591A1 US 2015031885 W US2015031885 W US 2015031885W WO 2015179591 A1 WO2015179591 A1 WO 2015179591A1
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Prior art keywords
memory
cache
data
controller
compressed
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Ceased
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PCT/US2015/031885
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English (en)
French (fr)
Inventor
Mattheus Cornelis Antonius Adrianus HEDDES
Natarajan Vaidhyanathan
Colin Beaton Verrilli
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Qualcomm Inc
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Qualcomm Inc
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Priority to EP15728287.2A priority Critical patent/EP3146435A1/en
Priority to CN201580026261.3A priority patent/CN106462495B/zh
Priority to JP2016568009A priority patent/JP2017516234A/ja
Publication of WO2015179591A1 publication Critical patent/WO2015179591A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
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    • G06F2212/25—Using a specific main memory architecture
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/602—Details relating to cache prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • MEMORY CONTROLLERS EMPLOYING MEMORY CAPACITY AND/OR BANDWIDTH COMPRESSION WITH NEXT READ ADDRESS PREFETCHING, AND RELATED PROCESSOR-BASED SYSTEMS AND
  • FIG. 2 is a schematic diagram of a SOC that includes an exemplary CPU- based system having a plurality of CPUs and a memory controller employing memory capacity and/or memory bandwidth compression;
  • Figure 7 is a schematic diagram of an exemplary free list buffer that can be employed in a page-based or line-based buffer memory capacity compression scheme, including in Figures 4-6;
  • Figure 10 is a flowchart illustrating an exemplary process of the compressed memory controller in Figure 3 translating a PA to an allocated DB within an allocated data page (DP) in Figure 9 according to the hybrid line/page-based buffer memory capacity compression scheme in Figure 8 for a memory access;
  • Figure 11 A illustrates an example of the SOC in Figure 3 that additionally includes an optional L4 cache to compensate for performance loss due to address translation in the compressed memory controller;
  • aspects disclosed in the detailed description include memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods.
  • memory controllers are employed that can provide memory capacity compression.
  • a next read address prefetching scheme may be combined with a memory bandwidth compression scheme and/or a memory capacity compression scheme.
  • the next read address prefetching scheme can be used by a memory controller to speculatively prefetch data from system memory at another address beyond the currently accessed address.
  • the next read address to be prefetched from system or main memory can be stored as metadata in association with compressed memory data stored in compressed memory, since there may be left over space in a memory block that holds compressed memory data in the compressed memory.
  • the compressed controller 50 can perform any number of compression techniques and algorithms to provide memory capacity and/or bandwidth compression.
  • Local memory 52 is provided for data structures and other information needed by the compressed controller 50 to perform such compression techniques and algorithms.
  • the local memory 52 provided in the form of a static random access memory (SRAM) 54 in this example, is also provided in the compressed memory controller 36 to store data structures and other information needed by the compressed controller 50 to perform compression techniques and algorithms.
  • SRAM static random access memory
  • the local memory 52 is of sufficient size to be used for data structures and other data storage that may be needed for the compressed controller 50 to perform compression techniques and algorithms.
  • the additional internal memory 56 is external to the compressed memory controller 36, such as on a different semiconductor die for example, the memory access latency to the additional internal memory 56 may be greater than to the local memory 52, although an increased size of the additional internal memory 56 may allow for enhanced compression and/or a larger number of CPUs 16(1), 16(2) and/or hardware threads per CPU 16 to be accommodated.
  • Each of the resources provided for memory capacity and/or bandwidth compression in the compressed memory controller 36 in Figure 3, including the local memory 52 and the additional internal memory 56 can be used individually or in conjunction with each other to achieve the desired balance among resources and area, power consumption, increased memory capacity through memory capacity compression, and increased performance through memory bandwidth compression. Memory capacity and memory bandwidth compression can be enabled or disabled, as desired.
  • the compressed memory controller 36 can be configured to assign a PA to other PBAs in another PB pool 62(1)-62(Q). This functionality may be provided as part of a background task by the compressed memory controller 36. Depletion means that the available PBs in a particular PB pool 62(1)-62(Q) drops below a threshold, because it may be desired to assign a PA to other PBAs in another PB pool 62(1)-62(Q) before there are no remaining PBs available in a given PB pool 62(1)-62(Q).

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
PCT/US2015/031885 2014-05-21 2015-05-21 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods Ceased WO2015179591A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP15728287.2A EP3146435A1 (en) 2014-05-21 2015-05-21 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
CN201580026261.3A CN106462495B (zh) 2014-05-21 2015-05-21 存储器控制器以及基于处理器的系统和方法
JP2016568009A JP2017516234A (ja) 2014-05-21 2015-05-21 次の読取りアドレスプリフェッチングによるメモリ容量圧縮および／またはメモリ帯域幅圧縮を利用するメモリコントローラ、ならびに関連するプロセッサベースシステムおよび方法

Applications Claiming Priority (8)

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US201462001545P 2014-05-21 2014-05-21
US62/001,545 2014-05-21
US201462092409P 2014-12-16 2014-12-16
US201462092326P 2014-12-16 2014-12-16
US62/092,409 2014-12-16
US62/092,326 2014-12-16
US14/716,108 US9740621B2 (en) 2014-05-21 2015-05-19 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
US14/716,108 2015-05-19

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WO (1) WO2015179591A1 (enExample)

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