JP2017224724A - Method for manufacturing light-emitting diode chip and light-emitting diode chip - Google Patents

Method for manufacturing light-emitting diode chip and light-emitting diode chip Download PDF

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JP2017224724A
JP2017224724A JP2016119052A JP2016119052A JP2017224724A JP 2017224724 A JP2017224724 A JP 2017224724A JP 2016119052 A JP2016119052 A JP 2016119052A JP 2016119052 A JP2016119052 A JP 2016119052A JP 2017224724 A JP2017224724 A JP 2017224724A
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wafer
emitting diode
transparent substrate
back surface
diode chip
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卓 岡村
Taku Okamura
卓 岡村
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Disco Corp
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Disco Abrasive Systems Ltd
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Priority to JP2016119052A priority Critical patent/JP2017224724A/en
Priority to TW106115658A priority patent/TW201812884A/en
Priority to KR1020170072668A priority patent/KR102164309B1/en
Priority to CN201710436981.8A priority patent/CN107527986B/en
Publication of JP2017224724A publication Critical patent/JP2017224724A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0058Processes relating to semiconductor body packages relating to optical field-shaping elements

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a light-emitting diode chip capable of obtaining sufficient luminance, and the light-emitting diode chip.SOLUTION: A method for manufacturing a light-emitting diode chip comprises: a wafer preparing step of preparing a wafer which includes a laminate layer in which a plurality of semiconductor layers containing a light-emitting layer are formed on a transparent substrate for crystal growth, and in which an LED circuit is formed in each of the regions partitioned by a plurality of division schedule lines mutually crossing a surface of the laminate layer; a wafer rear surface processing step of forming a plurality of recesses or first grooves corresponding to each LED circuit on a rear surface of the wafer; a transparent substrate processing step of forming a plurality of second grooves corresponding to each LED circuit of the wafer on a surface of the transparent substrate; an integrating step of forming an integrated wafer by sticking the surface of the transparent substrate to the rear surface of the wafer; and a dividing step of dividing the integrated wafer into individual light-emitting diode chips by cutting the wafer together with the transparent substrate along the division schedule lines.SELECTED DRAWING: Figure 4

Description

本発明は、発光ダイオードチップの製造方法及び発光ダイオードチップに関する。   The present invention relates to a light emitting diode chip manufacturing method and a light emitting diode chip.

サファイア基板、GaN基板、SiC基板等の結晶成長用基板の表面にn型半導体層、発光層、p型半導体層が複数積層された積層体層が形成され、この積層体層に交差する複数の分割予定ラインによって区画された領域に複数のLED(Light Emitting Diode)等の発光デバイスが形成されたウエーハは、分割予定ラインに沿って切断されて個々の発光デバイスチップに分割され、分割された発光デバイスチップは携帯電話、パソコン、照明機器等の各種電気機器に広く利用されている。   A stacked body layer in which a plurality of n-type semiconductor layers, light-emitting layers, and p-type semiconductor layers are stacked is formed on the surface of a crystal growth substrate such as a sapphire substrate, a GaN substrate, or a SiC substrate. A wafer in which a plurality of light emitting devices such as LEDs (Light Emitting Diodes) are formed in a region partitioned by the planned division line is cut along the planned division line and divided into individual light emitting device chips, and the divided light emission Device chips are widely used in various electric devices such as mobile phones, personal computers, and lighting devices.

発光デバイスチップの発光層から出射される光は等方性を有しているため、結晶成長用基板の内部にも照射されて基板の裏面及び側面からも光が出射する。然し、基板の内部に照射された光のうち空気層との界面での入射角が臨界角以上の光は界面で全反射されて基板内部に閉じ込められ、基板から外部に出射されることがないから発光デバイスチップの輝度の低下を招くという問題がある。   Since the light emitted from the light emitting layer of the light emitting device chip is isotropic, the light is emitted also to the inside of the crystal growth substrate, and the light is also emitted from the back and side surfaces of the substrate. However, of the light irradiated to the inside of the substrate, light whose incident angle at the interface with the air layer is greater than the critical angle is totally reflected at the interface and confined inside the substrate, and is not emitted outside from the substrate. Therefore, there is a problem that the luminance of the light emitting device chip is lowered.

この問題を解決するために、発光層から出射された光が基板の内部に閉じ込められるのを抑制するために、基板の裏面に透明部材を貼着して輝度の向上を図るようにした発光ダイオード(LED)が特開2014−175354号公報に記載されている。   In order to solve this problem, a light emitting diode in which a transparent member is attached to the back surface of the substrate to improve the luminance in order to prevent light emitted from the light emitting layer from being confined inside the substrate. (LED) is described in Japanese Patent Application Laid-Open No. 2014-175354.

特開2014−175354号公報JP 2014-175354 A

然し、特許文献1に開示された発光ダイオードでは、基板の裏面に透明部材を貼着することにより輝度が僅かに向上したものの十分な輝度が得られないという問題がある。   However, the light emitting diode disclosed in Patent Document 1 has a problem that sufficient luminance cannot be obtained although the luminance is slightly improved by sticking a transparent member to the back surface of the substrate.

本発明はこのような点に鑑みてなされたものであり、その目的とするところは、十分な輝度が得られる発光ダイオードチップの製造方法及び発光ダイオードチップを提供することである。   The present invention has been made in view of these points, and an object of the present invention is to provide a method of manufacturing a light-emitting diode chip and a light-emitting diode chip that can obtain sufficient luminance.

請求項1記載の発明によると、発光ダイオードチップの製造方法であって、結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれLED回路が形成されたウエーハを準備するウエーハ準備工程と、該ウエーハの裏面に各LED回路に対応して複数の凹部又は第1の溝を形成するウエーハ裏面加工工程と、透明基板の表面に該ウエーハの各LED回路に対応して複数の第2の溝を形成する透明基板加工工程と、該ウエーハ裏面加工工程及び該透明基板加工工程を実施した後、該ウエーハの裏面に該透明基板の表面を貼着して一体化ウエーハを形成する一体化工程と、該ウエーハを該分割予定ラインに沿って該透明基板とともに切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、を備えたことを特徴とする発光ダイオードチップの製造方法が提供される。   According to invention of Claim 1, it is a manufacturing method of a light emitting diode chip | tip, Comprising: It has a laminated body layer in which the several semiconductor layer containing a light emitting layer was formed on the transparent substrate for crystal growth, This laminated body layer A wafer preparation step of preparing a wafer in which LED circuits are formed in each region partitioned by a plurality of division lines intersecting each other on the surface of the wafer, and a plurality of recesses or corresponding to each LED circuit on the back surface of the wafer A wafer back surface processing step for forming a first groove, a transparent substrate processing step for forming a plurality of second grooves on the surface of the transparent substrate corresponding to each LED circuit of the wafer, the wafer back surface processing step, After performing the transparent substrate processing step, an integrated step of forming the integrated wafer by sticking the surface of the transparent substrate to the back surface of the wafer, and the transparent substrate along the line to be divided LED chip production method of which is characterized in that and a dividing step of dividing the integrated wafer into individual light emitting diode chips is provided by cutting with.

好ましくは、透明基板加工工程において形成される第2の溝の断面形状は、三角形状、四角形状、又は半円形状の何れかである。好ましくは、ウエーハ裏面加工工程において形成される凹部又は第1の溝は、切削ブレード、エッチング、サンドブラスト、レーザーの何れかで形成され、透明基板加工工程において形成される第2の溝は、切削ブレード、エッチング、サンドブラスト、レーザーの何れかで形成される。   Preferably, the cross-sectional shape of the second groove formed in the transparent substrate processing step is any one of a triangular shape, a quadrangular shape, and a semicircular shape. Preferably, the recess or the first groove formed in the wafer back surface processing step is formed by any one of a cutting blade, etching, sand blast, and laser, and the second groove formed in the transparent substrate processing step is a cutting blade. , Etching, sandblasting, or laser.

好ましくは、該透明基板は、透明セラミックス、光学ガラス、サファイア、透明樹脂の何れかで形成され、該一体化工程において該透明基板は透明接着剤でウエーハに接着される。   Preferably, the transparent substrate is formed of any one of transparent ceramics, optical glass, sapphire, and transparent resin, and in the integration step, the transparent substrate is bonded to the wafer with a transparent adhesive.

請求項5記載の発明によると、発光ダイオードチップであって、表面にLED回路が形成され裏面に凹部又は第1の溝が形成された発光ダイオードと、該発光ダイオードの裏面に貼着された透明部材と、を備え、該透明部材の該発光ダイオードとの貼着面には第2の溝が形成されている発光ダイオードチップが提供される。   According to invention of Claim 5, it is a light emitting diode chip | tip, Comprising: The light emitting diode in which the LED circuit was formed in the surface, and the recessed part or the 1st groove | channel was formed in the back surface, and the transparent stuck on the back surface of this light emitting diode And a light emitting diode chip in which a second groove is formed on a surface of the transparent member to which the light emitting diode is attached.

本発明の発光ダイオードチップは、LEDの裏面に貼着された透明部材の表面に第2の溝が形成されているので、透明部材の表面積が増大することに加え、LEDの発光層から照射され透明部材に入射する光が該凹部又は該第1の溝並びに第2の溝部分で複雑に屈折するため、透明部材から光が出射する際に透明部材と空気層との界面での入射角が臨界角以上の光の割合が減少し、透明部材から出射される光の量が増大して発光ダイオードチップの輝度が向上する。   In the light-emitting diode chip of the present invention, the second groove is formed on the surface of the transparent member adhered to the back surface of the LED, so that the surface area of the transparent member is increased and the LED light-emitting layer is irradiated. Since light incident on the transparent member is refracted in a complicated manner in the concave portion or the first groove and the second groove portion, the incident angle at the interface between the transparent member and the air layer is reduced when light is emitted from the transparent member. The ratio of light above the critical angle is decreased, the amount of light emitted from the transparent member is increased, and the luminance of the light emitting diode chip is improved.

光デバイスウエーハの表面側斜視図である。It is a surface side perspective view of an optical device wafer. 図2(A)は切削ブレードによるウエーハの裏面加工工程を示す斜視図、図2(B)〜図2(D)は形成された溝形状を示す断面図である。FIG. 2A is a perspective view illustrating a wafer back surface processing step using a cutting blade, and FIGS. 2B to 2D are cross-sectional views illustrating the formed groove shape. 図3(A)はウエーハの裏面に形成された第1の方向に伸長する複数の溝を有するウエーハの裏面側斜視図、図3(B)はウエーハの裏面に形成された第1の方向及び第1の方向に直交する第2の方向に伸長する複数の溝が形成されたウエーハの裏面側斜視図である。3A is a perspective view of the back surface side of the wafer having a plurality of grooves extending in the first direction formed on the back surface of the wafer, and FIG. 3B is a diagram illustrating the first direction formed on the back surface of the wafer and FIG. It is a back surface side perspective view of a wafer in which a plurality of grooves extended in the 2nd direction which intersects perpendicularly with the 1st direction were formed. 図4(A)はウエーハの裏面にマスクを貼着する様子を示す斜視図、図4(B)はウエーハの裏面に複数の穴を有するマスクが貼着された状態の斜視図、図4(C)〜図4(E)はウエーハの裏面に形成された凹部の形状を示すウエーハの部分的斜視図である。4A is a perspective view showing a state where a mask is attached to the back surface of the wafer, FIG. 4B is a perspective view of a state where a mask having a plurality of holes is attached to the back surface of the wafer, FIG. FIGS. 4C to 4E are partial perspective views of the wafer showing the shape of the recesses formed on the back surface of the wafer. 図5(A)はレーザービームによりウエーハの裏面に溝を形成する様子を示す斜視図、図5(B)は溝形状を示すウエーハの部分断面図、図5(C)はレーザービームによりウエーハの裏面に円形凹部を形成する様子を示す斜視図、図5(D)は形成された円形の凹部を示すウエーハの部分斜視図である。5A is a perspective view showing a state in which a groove is formed on the back surface of the wafer by a laser beam, FIG. 5B is a partial sectional view of the wafer showing the groove shape, and FIG. 5C is a sectional view of the wafer by the laser beam. FIG. 5 (D) is a partial perspective view of the wafer showing the formed circular recess. 図6(A)は透明基板加工工程を示す斜視図、図6(B)〜図6(D)は形成された溝形状を示す断面図である。FIG. 6A is a perspective view showing a transparent substrate processing step, and FIGS. 6B to 6D are cross-sectional views showing the formed groove shape. 図7(A)は表面に第1の方向に伸長する複数の溝を有する透明基板をウエーハの裏面に貼着して一体化する一体化工程を示す斜視図、図7(B)は一体化ウエーハの斜視図である。FIG. 7A is a perspective view showing an integration process in which a transparent substrate having a plurality of grooves extending in the first direction on the front surface is attached to the back surface of the wafer and integrated, and FIG. It is a perspective view of a wafer. 第1の方向及び第1の方向に直交する第2の方向に伸長する複数の溝を表面に有する透明基板をウエーハの裏面を貼着して一体化する一体化工程を示す斜視図である。It is a perspective view which shows the integration process which sticks the back surface of a wafer and integrates the transparent substrate which has the some groove | channel extended in the 2nd direction orthogonal to a 1st direction and a 1st direction on the surface. 一体化ウエーハをダイシングテープを介して環状フレームで支持する支持工程を示す斜視図である。It is a perspective view which shows the support process which supports an integrated wafer with a cyclic | annular flame | frame via a dicing tape. 一体化ウエーハを発光ダイオードチップに分割する分割工程を示す斜視図である。It is a perspective view which shows the division | segmentation process which divides | segments an integrated wafer into a light emitting diode chip. 分割工程終了後の一体化ウエーハの斜視図である。It is a perspective view of the integrated wafer after completion | finish of a division | segmentation process. 図12(A)〜図12(C)は本発明実施形態に係る発光ダイオードチップの斜視図である。12 (A) to 12 (C) are perspective views of the light emitting diode chip according to the embodiment of the present invention.

以下、本発明の実施形態を図面を参照して詳細に説明する。図1を参照すると、光デバイスウエーハ(以下、単にウエーハと略称することがある)11の表面側斜視図が示されている。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a front side perspective view of an optical device wafer 11 (hereinafter sometimes simply referred to as a wafer) 11.

光デバイスウエーハ11は、サファイア基板13上に窒化ガリウム(GaN)等のエピタキシャル層(積層体層)15が積層されて構成されている。光デバイスウエーハ11は、エピタキシャル層15が積層された表面11aと、サファイア基板13が露出した裏面11bとを有している。   The optical device wafer 11 is configured by laminating an epitaxial layer (laminated body layer) 15 such as gallium nitride (GaN) on a sapphire substrate 13. The optical device wafer 11 has a front surface 11a on which an epitaxial layer 15 is stacked and a back surface 11b on which the sapphire substrate 13 is exposed.

ここで、本実施形態の光デバイスウエーハ11では、結晶成長用基板としてサファイア基板13を採用しているが、サファイア基板13に替えGaN基板又はSiC基板等を採用するようにしてもよい。   Here, in the optical device wafer 11 of the present embodiment, the sapphire substrate 13 is employed as the crystal growth substrate. However, a GaN substrate or a SiC substrate may be employed instead of the sapphire substrate 13.

積層体層(エピタキシャル層)15は、電子が多数キャリアとなるn型半導体層(例えば、n型GaN層)、発光層となる半導体層(例えば、InGaN層)、正孔が多数キャリアとなるp型半導体層(例えば、p型GaN層)を順にエピタキシャル成長させることにより形成される。   The stacked body layer (epitaxial layer) 15 includes an n-type semiconductor layer (for example, an n-type GaN layer) in which electrons are majority carriers, a semiconductor layer (for example, an InGaN layer) that is a light emitting layer, and a p in which holes are majority carriers. It is formed by epitaxially growing a type semiconductor layer (for example, a p-type GaN layer) in this order.

サファイア基板13は例えば100μmの厚みを有しており、積層体層15は例えば5μmの厚みを有している。積層体層15に複数のLED回路19が格子状に形成された複数の分割予定ライン17によって区画されて形成されている。ウエーハ11は、LED回路19が形成された表面11aと、サファイア基板13が露出した裏面11bとを有している。   The sapphire substrate 13 has a thickness of 100 μm, for example, and the laminate layer 15 has a thickness of 5 μm, for example. A plurality of LED circuits 19 are defined on the laminate layer 15 by a plurality of division lines 17 formed in a lattice pattern. The wafer 11 has a front surface 11a on which the LED circuit 19 is formed and a back surface 11b on which the sapphire substrate 13 is exposed.

本発明実施形態の発光ダイオードチップの製造方法によると、まず図1に示すような光デバイスウエーハ11を準備するウエーハ準備工程を実施する。更に、ウエーハ11の裏面11bにLED回路19に対応して複数の溝3を形成するウエーハ裏面加工工程を実施する。   According to the light emitting diode chip manufacturing method of the embodiment of the present invention, first, a wafer preparation step for preparing an optical device wafer 11 as shown in FIG. 1 is performed. Further, a wafer back surface processing step for forming a plurality of grooves 3 corresponding to the LED circuits 19 on the back surface 11 b of the wafer 11 is performed.

このウエーハ裏面加工工程は、例えば、よく知られた切削装置を用いて実施する。図2(A)に示すように、切削装置の切削ユニット10は、スピンドルハウジング12と、スピンドルハウジング12中に回転可能に挿入された図示しないスピンドルと、スピンドルの先端に装着された切削ブレード14とを含んでいる。   This wafer back surface processing step is performed using, for example, a well-known cutting device. As shown in FIG. 2A, the cutting unit 10 of the cutting apparatus includes a spindle housing 12, a spindle (not shown) rotatably inserted into the spindle housing 12, and a cutting blade 14 attached to the tip of the spindle. Is included.

切削ブレード14の切り刃は、例えば、ダイヤモンド砥粒をニッケルメッキで固定した電鋳砥石で形成されており、その先端形状は三角形状、四角形状、又は半円形状をしている。   The cutting blade of the cutting blade 14 is formed of, for example, an electroformed grindstone in which diamond abrasive grains are fixed by nickel plating, and the tip shape thereof is triangular, quadrangular, or semicircular.

切削ブレード14の概略上半分はブレードカバー(ホイールカバー)16で覆われており、ブレードカバー16には切削ブレード14の奥側及び手前側に水平に伸長する一対の(1本のみ図示)クーラーノズル18が配設されている。   The upper half of the cutting blade 14 is covered with a blade cover (wheel cover) 16, and the blade cover 16 is a pair of cooler nozzles (only one is shown) extending horizontally toward the back side and the near side of the cutting blade 14. 18 is arranged.

ウエーハ11の裏面11bに複数の溝3を形成するウエーハ裏面加工工程では、ウエーハ11の表面11aを図示しない切削装置のチャックテーブルで吸引保持する。そして、切削ブレード14を矢印R方向に高速回転させながらウエーハ11の裏面11bに所定深さ切り込み、図示しないチャックテーブルに保持されたウエーハ11を矢印X1方向に加工送りすることにより、第1の方向に伸長する溝3を切削により形成する。   In the wafer back surface processing step of forming a plurality of grooves 3 on the back surface 11b of the wafer 11, the surface 11a of the wafer 11 is sucked and held by a chuck table of a cutting device (not shown). Then, the cutting blade 14 is cut at a predetermined depth into the back surface 11b of the wafer 11 while rotating the cutting blade 14 at a high speed in the direction of arrow R, and the wafer 11 held on a chuck table (not shown) is processed and fed in the direction of arrow X1 to obtain the first direction. Grooves 3 that are elongated to each other are formed by cutting.

ウエーハ11を矢印X1方向に直交する方向にウエーハ11の分割予定ライン17のピッチずつ割り出し送りしながら、ウエーハ11の裏面11bを切削して、図3(A)に示すように、第1の方向に伸長する複数の溝3を次々と形成する。   As shown in FIG. 3 (A), the back surface 11b of the wafer 11 is cut while indexing and feeding the wafer 11 in the direction orthogonal to the arrow X1 direction by the pitch of the division line 17 of the wafer 11. A plurality of grooves 3 extending in succession are formed one after another.

図3(A)に示すように、ウエーハ11の裏面11bに形成する複数の溝3は一方向にのみ伸長する形態であってもよいし、或いは、図3(B)に示すように、第1の方向及び該第1の方向に直交する第2の方向に伸長する複数の溝3をウエーハ11の裏面11bに形成するようにしてもよい。   As shown in FIG. 3 (A), the plurality of grooves 3 formed on the back surface 11b of the wafer 11 may extend only in one direction, or as shown in FIG. A plurality of grooves 3 extending in the first direction and the second direction orthogonal to the first direction may be formed on the back surface 11 b of the wafer 11.

ウエーハ11の裏面11bに形成する溝は、図2(B)に示すような断面三角形状の溝3、又は図2(C)に示すような断面四角形状の溝3A、又は図2(D)に示すような断面半円形状の溝3Bの何れであってもよい。   The groove formed on the back surface 11b of the wafer 11 is a groove 3 having a triangular cross section as shown in FIG. 2 (B), or a groove 3A having a square cross section as shown in FIG. 2 (C), or FIG. 2 (D). Any of the grooves 3B having a semicircular cross section as shown in FIG.

ウエーハ11の裏面11bに切削により複数の溝3,3A,3Bを形成する実施形態に替えて、ウエーハ11の裏面11bにLED回路19に対応して複数の凹部を形成するようにしてもよい。この実施形態では、図4(A)に示すように、ウエーハ11のLED回路19に対応した複数の穴4を有するマスク2を使用する。   Instead of the embodiment in which the plurality of grooves 3, 3 </ b> A, 3 </ b> B are formed on the back surface 11 b of the wafer 11 by cutting, a plurality of recesses may be formed on the back surface 11 b of the wafer 11 corresponding to the LED circuit 19. In this embodiment, as shown in FIG. 4A, a mask 2 having a plurality of holes 4 corresponding to the LED circuit 19 of the wafer 11 is used.

図4(B)に示すように、マスク2の穴4をウエーハ11の各LED回路19に対応させてウエーハ11の裏面11bに貼着する。そして、ウェットエッチング又はプラズマエッチングによりウエーハ11の裏面11bに、図4(C)に示すように、マスク2の穴4の形状に対応した三角形状の凹部5を形成する。   As shown in FIG. 4B, the holes 4 of the mask 2 are attached to the back surface 11 b of the wafer 11 so as to correspond to the LED circuits 19 of the wafer 11. Then, a triangular recess 5 corresponding to the shape of the hole 4 of the mask 2 is formed on the back surface 11b of the wafer 11 by wet etching or plasma etching, as shown in FIG.

マスク2の穴4の形状を四角形状、又は円形状に変更することにより、ウエーハ11の裏面11bに図4(D)に示すような四角形状の凹部5Aを形成するか、図4(E)に示すようなウエーハ11の裏面11bに円形状の凹部5Bを形成するようにしてもよい。   By changing the shape of the hole 4 of the mask 2 to a square shape or a circular shape, a rectangular recess 5A as shown in FIG. 4D is formed on the back surface 11b of the wafer 11, or FIG. A circular recess 5B may be formed on the back surface 11b of the wafer 11 as shown in FIG.

本実施形態の変形例として、ウエーハ11の裏面11bにマスク2を貼着した後、サンドブラスト加工を実施することにより、ウエーハ11の裏面11bに、図4(C)に示すような三角形状の凹部5、又は図4(D)に示すような四角形状の凹部5A、又は図4(E)に示すような円形状凹部5Bを形成するようにしてもよい。   As a modification of the present embodiment, a triangular recess as shown in FIG. 4C is formed on the back surface 11b of the wafer 11 by pasting the mask 2 on the back surface 11b of the wafer 11 and then performing sandblasting. 5 or a rectangular recess 5A as shown in FIG. 4D, or a circular recess 5B as shown in FIG. 4E.

ウエーハ11の裏面11bにLED回路19に対応した複数の溝又は複数の凹部を形成するのに、レーザー加工装置を利用するようにしてもよい。レーザー加工による第1実施形態では、図5(A)に示すように、ウエーハ11に対して吸収性を有する波長(例えば、266nm)のレーザービームを集光器(レーザーヘッド)24からウエーハ11の裏面11bに照射しながら、ウエーハ11を保持した図示しないチャックテーブルを矢印X1方向に加工送りすることにより、第1の方向に伸長する溝7をウエーハ11の裏面11bにアブレーションにより形成する。   In order to form a plurality of grooves or a plurality of recesses corresponding to the LED circuit 19 on the back surface 11 b of the wafer 11, a laser processing apparatus may be used. In the first embodiment by laser processing, as shown in FIG. 5A, a laser beam having a wavelength (for example, 266 nm) having an absorptivity with respect to the wafer 11 is applied from the condenser (laser head) 24 to the wafer 11. A groove table 7 extending in the first direction is formed on the back surface 11b of the wafer 11 by ablation by processing and feeding a chuck table (not shown) holding the wafer 11 in the direction of the arrow X1 while irradiating the back surface 11b.

ウエーハ11を矢印X1方向に直交する方向にウエーハ11の分割予定ライン17のピッチずつ割り出し送りしながら、ウエーハ11の裏面11bをアブレーション加工して、第1の方向に伸長する複数の溝7を次々と形成する。溝7の断面形状は、例えば図5(B)に示すような、半円形状であってもよいし、他の形状であってもよい。   A plurality of grooves 7 extending in the first direction are successively formed by ablating the back surface 11b of the wafer 11 while indexing and feeding the wafer 11 in the direction orthogonal to the arrow X1 direction by the pitch of the division lines 17 of the wafer 11. And form. The cross-sectional shape of the groove 7 may be a semicircular shape as shown in FIG. 5B, for example, or may be another shape.

代替実施形態として、図5(C)に示すように、集光器24からウエーハ11に対して吸収性を有する波長(例えば、266nm)のパルスレーザービームを間欠的に照射して、ウエーハ11の裏面11bにLED回路19に対応した複数の凹部9を形成するようにしてもよい。凹部9の形状は、通常はレーザービームのスポット形状に対応した図5(D)に示すような円形状となる。   As an alternative embodiment, as shown in FIG. 5C, a pulse laser beam having a wavelength (for example, 266 nm) having an absorptivity is intermittently irradiated from the condenser 24 to the wafer 11 to You may make it form the some recessed part 9 corresponding to the LED circuit 19 in the back surface 11b. The shape of the recess 9 is usually a circle as shown in FIG. 5D corresponding to the spot shape of the laser beam.

ウエーハ裏面加工工程を実施した後、又は実施する前に、ウエーハ11の裏面11bに貼着する透明基板21の表面21aにLED回路19に対応して複数の溝を形成する透明基板加工工程を実施する。   After performing the wafer back surface processing step, or before performing the wafer back surface processing step, the transparent substrate processing step of forming a plurality of grooves corresponding to the LED circuit 19 on the front surface 21a of the transparent substrate 21 to be attached to the back surface 11b of the wafer 11 is performed. To do.

この透明基板加工工程は、例えば、よく知られた切削装置を用いて実施する。透明基板21の表面21aに複数の溝23を形成する透明基板加工工程では、透明基板21を図示しない切削装置のチャックテーブルで吸引保持する。   This transparent substrate processing step is performed using, for example, a well-known cutting device. In the transparent substrate processing step of forming the plurality of grooves 23 on the surface 21a of the transparent substrate 21, the transparent substrate 21 is sucked and held by a chuck table of a cutting device (not shown).

そして、切削ブレード14を矢印R方向に高速回転させながら透明基板21の表面21aに所定深さ切り込み、図示しないチャックテーブルに保持された透明基板21を矢印X1方向に加工送りすることにより、第1の方向に伸長する溝23を切削により形成する。   Then, the cutting blade 14 is cut at a predetermined depth into the surface 21a of the transparent substrate 21 while rotating at a high speed in the arrow R direction, and the transparent substrate 21 held on the chuck table (not shown) is processed and fed in the arrow X1 direction. Grooves 23 extending in the direction of are formed by cutting.

透明基板21を矢印X1方向に直交する方向にウエーハ11の分割予定ライン17のピッチずつ割り出し送りしながら、透明基板21の表面21aを切削して、図6に示すように、第1の方向に伸長する複数の溝23を次々と形成する。   The surface 21a of the transparent substrate 21 is cut while indexing and feeding the transparent substrate 21 in the direction orthogonal to the direction of the arrow X1 by the pitch of the division lines 17 of the wafer 11, and in the first direction as shown in FIG. A plurality of extending grooves 23 are formed one after another.

図7(A)に示すように、透明基板21の表面21aに形成する複数の溝23は一方向にのみ伸長する形態であってもよいし、或いは、図8に示すように、第1の方向及び該第1の方向に直交する第2の方向に伸長する複数の溝23を透明基板21の表面21aに形成するようにしてもよい。   As shown in FIG. 7A, the plurality of grooves 23 formed on the surface 21a of the transparent substrate 21 may be extended only in one direction. Alternatively, as shown in FIG. A plurality of grooves 23 extending in the direction and the second direction orthogonal to the first direction may be formed on the surface 21 a of the transparent substrate 21.

透明基板21の表面21aに形成する溝は、図6(B)に示すような断面三角形状の溝23、又は図6(C)に示すような断面四角形状の溝23A、又は図6(D)に示すような断面半円形状の溝23Bの何れであってもよい。   The groove formed on the surface 21a of the transparent substrate 21 is a groove 23 having a triangular cross section as shown in FIG. 6B, or a groove 23A having a square cross section as shown in FIG. 6C, or FIG. Any of the grooves 23B having a semicircular cross section as shown in FIG.

透明基板21は、透明樹脂、光学ガラス、サファイア、透明セラミックスの何れかから形成される。本実施形態では、光学ガラスに比べて耐久性のあるポリカーボネイト、アクリル等の透明樹脂から透明基板21を形成した。尚、溝を形成する方法として、サンドブラスト、エッチング、レーザーを用いてもよい。   The transparent substrate 21 is formed from any one of transparent resin, optical glass, sapphire, and transparent ceramics. In the present embodiment, the transparent substrate 21 is formed from a transparent resin such as polycarbonate or acrylic that is more durable than optical glass. As a method for forming the groove, sand blasting, etching, or laser may be used.

透明基板21の表面21aに複数の溝23,23A,23Bを形成する透明基板加工工程を実施した後、ウエーハ11の裏面11bに透明基板21を貼着して一体化ウエーハ25を形成する一体化工程を実施する。   Integration of forming the integrated wafer 25 by performing the transparent substrate processing step of forming the plurality of grooves 23, 23 </ b> A, 23 </ b> B on the front surface 21 a of the transparent substrate 21 and then sticking the transparent substrate 21 to the back surface 11 b of the wafer 11. Perform the process.

この一体化工程では、図7(A)に示すように、表面21aに第1の方向に伸長する複数の溝23が形成された透明基板21の表面に、ウエーハ11の裏面11bを透明接着剤により接着して、図7(B)に示すように、ウエーハ11と透明基板21とを一体化して一体化ウエーハ25を形成する。   In this integration step, as shown in FIG. 7A, the back surface 11b of the wafer 11 is attached to the surface of the transparent substrate 21 having a plurality of grooves 23 extending in the first direction on the surface 21a. As shown in FIG. 7B, the wafer 11 and the transparent substrate 21 are integrated to form an integrated wafer 25.

代替実施形態として、透明基板21の表面21aに第1の方向及びこの第1の方向に直交する第2の方向に伸長する複数の溝23を有する透明基板21の表面21aに、図8に示すように、ウエーハ11の裏面11bを透明接着剤により接着して、ウエーハ11と透明基板21とを一体化するようにしてもよい。ここで、透明基板21の表面21aに形成した溝23のピッチはウエーハ11の分割予定ライン17のピッチに対応する。   As an alternative embodiment, a surface 21a of a transparent substrate 21 having a plurality of grooves 23 extending in a first direction and a second direction orthogonal to the first direction is shown in FIG. As described above, the wafer 11 and the transparent substrate 21 may be integrated by bonding the back surface 11b of the wafer 11 with a transparent adhesive. Here, the pitch of the grooves 23 formed on the surface 21 a of the transparent substrate 21 corresponds to the pitch of the division lines 17 of the wafer 11.

一体化工程を実施した後、図9に示すように、一体化ウエーハ25の透明基板21を外周部が環状フレームFに貼着されたダイシングテープTに貼着してフレームユニットを形成し、一体化ウエーハ25をダイシングテープTを介して環状フレームFで支持する支持工程を実施する。   After performing the integration step, as shown in FIG. 9, the transparent substrate 21 of the integrated wafer 25 is attached to a dicing tape T whose outer peripheral portion is attached to the annular frame F to form a frame unit. A supporting step of supporting the wafer 25 with the annular frame F via the dicing tape T is performed.

支持工程を実施した後、フレームユニットを切削装置に投入し、切削装置で一体化ウエーハ25を切削して個々の発光ダイオードチップに分割する分割ステップを実施する。この分割ステップについて、図10を参照して説明する。   After carrying out the supporting process, the frame unit is put into a cutting device, and the dividing step of cutting the integrated wafer 25 with the cutting device and dividing it into individual light emitting diode chips is carried out. This division step will be described with reference to FIG.

分割ステップでは、一体化ウエーハ25をフレームユニットのダイシングテープTを介して切削装置のチャックテーブル20で吸引保持し、環状フレームFは図示しないクランプでクランプして固定する。   In the dividing step, the integrated wafer 25 is sucked and held by the chuck table 20 of the cutting device via the dicing tape T of the frame unit, and the annular frame F is clamped and fixed by a clamp (not shown).

そして、切削ブレード14を矢印R方向に高速回転させながら切削ブレード14の先端がダイシングテープTに届くまでウエーハ11の分割予定ライン17に切り込み、クーラーノズル18から切削ブレード14及びウエーハ11の加工点に向かって切削液を供給しつつ、一体化ウエーハ25を矢印X1方向に加工送りすることにより、ウエーハ11の分割予定ライン17に沿ってウエーハ11及び透明基板21を切断する切断溝27を形成する。   Then, while rotating the cutting blade 14 in the direction of arrow R at high speed, the cutting blade 14 is cut into the division line 17 of the wafer 11 until the tip of the cutting blade 14 reaches the dicing tape T. From the cooler nozzle 18 to the processing point of the cutting blade 14 and the wafer 11. The cutting groove 27 for cutting the wafer 11 and the transparent substrate 21 is formed along the division line 17 of the wafer 11 by processing and feeding the integrated wafer 25 in the direction of the arrow X1 while supplying the cutting fluid.

切削ユニット10をY軸方向に割り出し送りしながら、第1の方向に伸長する分割予定ライン17に沿って同様な切断溝27を次々と形成する。次いで、チャックテーブル20を90°回転してから、第1の方向に直交する第2の方向に伸長する全ての分割予定ライン17に沿って同様な切断溝27を形成して、図11に示す状態にすることで、一体化ウエーハ25を図12(A)に示すような発光ダイオードチップ31に分割する。   While indexing and feeding the cutting unit 10 in the Y-axis direction, similar cutting grooves 27 are formed one after another along the planned dividing line 17 extending in the first direction. Next, after the chuck table 20 is rotated by 90 °, similar cutting grooves 27 are formed along all the planned dividing lines 17 extending in the second direction orthogonal to the first direction, as shown in FIG. By setting the state, the integrated wafer 25 is divided into light-emitting diode chips 31 as shown in FIG.

上述した実施形態では、一体化ウエーハ25を個々の発光ダイオードチップ31に分割するのに切削装置を使用しているが、ウエーハ11及び透明基板21に対して透過性を有する波長のレーザービームを分割予定ライン13に沿ってウエーハ11に照射して、ウエーハ11及び透明基板21の内部に厚み方向に複数層の改質層を形成し、次いで、一体化ウエーハ25に外力を付与して、改質層を分割起点に一体化ウエーハ25を個々の発光ダイオードチップ31に分割するようにしてもよい。   In the embodiment described above, the cutting device is used to divide the integrated wafer 25 into the individual light emitting diode chips 31. However, the laser beam having a wavelength that is transmissive to the wafer 11 and the transparent substrate 21 is divided. Irradiate the wafer 11 along the planned line 13 to form a plurality of modified layers in the thickness direction inside the wafer 11 and the transparent substrate 21, and then apply an external force to the integrated wafer 25 to modify the wafer. The integrated wafer 25 may be divided into individual light emitting diode chips 31 using the layers as division starting points.

図12(A)に示された発光ダイオードチップ31は、表面にLED回路19を有するLED13Aの裏面に透明部材21Aが貼着されている。更に、ウエーハ11の裏面11bに凹部5又は溝3が形成されており、透明部材21Aの表面に溝23が形成されている。   The light emitting diode chip 31 shown in FIG. 12A has a transparent member 21A attached to the back surface of the LED 13A having the LED circuit 19 on the front surface. Further, the recess 5 or the groove 3 is formed on the back surface 11b of the wafer 11, and the groove 23 is formed on the surface of the transparent member 21A.

従って、図12(A)に示す発光ダイオードチップ31では、透明部材21Aの表面に溝23が形成されているため、透明部材21Aの表面積が増大する。更に、発光ダイオードチップ31のLED回路19から出射され、透明部材21Aに入射する光の一部は、ウエーハ11の裏面11bに形成された凹部5又は溝3、更に透明部材21Aの表面に形成された溝23部分で屈折されてから透明部材21Aに進入する。   Therefore, in the light-emitting diode chip 31 shown in FIG. 12A, the groove 23 is formed on the surface of the transparent member 21A, so the surface area of the transparent member 21A increases. Further, a part of the light emitted from the LED circuit 19 of the light emitting diode chip 31 and incident on the transparent member 21A is formed on the concave portion 5 or the groove 3 formed on the back surface 11b of the wafer 11 and further on the surface of the transparent member 21A. The light enters the transparent member 21A after being refracted by the groove 23 portion.

よって、透明部材21Aから外部に屈折して出射する際、透明部材21Aと空気層との界面での入射角が臨界角以上となる光の割合が減少し、透明部材21Aから出射される光の量が増大し、発光ダイオードチップ31の輝度が向上する。   Therefore, when the light is refracted and emitted from the transparent member 21A to the outside, the ratio of the light whose incident angle at the interface between the transparent member 21A and the air layer is greater than the critical angle is reduced, and the light emitted from the transparent member 21A is reduced. The amount increases, and the luminance of the light emitting diode chip 31 is improved.

図12(B)に示す発光ダイオードチップ31Aでは、LED13Aの裏面に凹部5又は溝3が形成されているのに加えて、LED13Aの裏面に表面に断面四角形状の溝23Aを有する透明部材21Aが透明な接着剤により接着されている。   In the light emitting diode chip 31A shown in FIG. 12B, in addition to the recess 5 or the groove 3 being formed on the back surface of the LED 13A, the transparent member 21A having a groove 23A having a square cross section on the front surface on the back surface of the LED 13A. It is bonded with a transparent adhesive.

本実施形態の発光ダイオードチップ31Aでも、図12(A)に示した発光ダイオードチップ31と同様に、LED回路19から出射され透明部材21Aに入射する光の一部は、LED13Aの裏面に形成された凹部5又は溝3及び透明部材21Aの表面に形成された溝23A部分で屈折されてから透明部材21Aに進入する。   Also in the light emitting diode chip 31A of the present embodiment, a part of the light emitted from the LED circuit 19 and incident on the transparent member 21A is formed on the back surface of the LED 13A, similarly to the light emitting diode chip 31 shown in FIG. The light enters the transparent member 21A after being refracted by the recessed portion 5 or groove 3 and the groove 23A formed on the surface of the transparent member 21A.

従って、透明部材21Aから外部に出射する際、透明部材21Aと空気層との界面での入射角が臨界角以上となる光の割合が減少し、透明部材21Aから出射される光の量が増大し、発光ダイオードチップ31Aの輝度が向上する。   Therefore, when the light is emitted from the transparent member 21A to the outside, the ratio of light whose incident angle at the interface between the transparent member 21A and the air layer is equal to or greater than the critical angle is reduced, and the amount of light emitted from the transparent member 21A is increased. As a result, the luminance of the light emitting diode chip 31A is improved.

図12(C)を参照すると、更に他の実施形態の発光ダイオードチップ31Bの斜視図が示されている。本実施形態の発光ダイオードチップ31Bでは、LED13Aの裏面に凹部5又は溝3が形成されていると共に、透明部材21Aの表面に断面四角形の溝23Aが互いに直交する方向に形成されている。   Referring to FIG. 12C, a perspective view of a light emitting diode chip 31B of still another embodiment is shown. In the light emitting diode chip 31B of the present embodiment, the recess 5 or the groove 3 is formed on the back surface of the LED 13A, and the grooves 23A having a square cross section are formed on the surface of the transparent member 21A in a direction perpendicular to each other.

従って、LED回路19から出射されて透明部材21Aに入射する光の内、LED13Aの裏面に形成された凹部5又は溝3及び透明部材21Aの表面に形成された溝23A部分で屈折して入射する光の量が増大する。   Accordingly, the light emitted from the LED circuit 19 and incident on the transparent member 21A is refracted and incident on the concave portion 5 or the groove 3 formed on the back surface of the LED 13A and the groove 23A portion formed on the surface of the transparent member 21A. The amount of light increases.

従って、透明部材21Aと空気層との界面での入射角が臨界角以上となる光の量が減少するため、透明部材21Aから外部に出射される光の量が増大し、発光ダイオードチップ31Dの輝度が向上する。   Accordingly, since the amount of light whose incident angle at the interface between the transparent member 21A and the air layer is equal to or greater than the critical angle is decreased, the amount of light emitted from the transparent member 21A is increased, and the light emitting diode chip 31D Brightness is improved.

図12(A)〜図12(C)に示した実施形態では、透明部材21Aが断面三角形状の溝23又は断面四角形状の溝23Aを有しているが、透明部材21Aが図6(D)に示した断面半円形状の溝23Bを有する場合についても同様な効果がある。   In the embodiment shown in FIGS. 12A to 12C, the transparent member 21A has the groove 23A having a triangular cross section or the groove 23A having a square cross section, but the transparent member 21A is shown in FIG. The same effect is obtained when the groove 23B having a semicircular cross section shown in FIG.

2 マスク
3,3A,3B 溝
4 穴
5,5A,5B 凹部
7 溝
9 凹部
10 切削ユニット
11 光デバイスウエーハ(ウエーハ)
13 サファイア基板
14 切削ブレード
15 積層体層
17 分割予定ライン
19 LED回路
21 透明基板
21A 透明部材
23,23A,23B 溝
25 一体化ウエーハ
27 切断溝
31,31A,31B 発光ダイオードチップ
2 Mask 3, 3A, 3B Groove 4 Hole 5, 5A, 5B Recess 7 Groove 9 Recess 10 Cutting unit 11 Optical device wafer (wafer)
13 Sapphire substrate 14 Cutting blade 15 Laminate layer 17 Line to be divided 19 LED circuit 21 Transparent substrate 21A Transparent member 23, 23A, 23B Groove 25 Integrated wafer 27 Cutting groove 31, 31A, 31B Light emitting diode chip

Claims (5)

発光ダイオードチップの製造方法であって、
結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれLED回路が形成されたウエーハを準備するウエーハ準備工程と、
該ウエーハの裏面に各LED回路に対応して複数の凹部又は第1の溝を形成するウエーハ裏面加工工程と、
透明基板の表面に該ウエーハの各LED回路に対応して複数の第2の溝を形成する透明基板加工工程と、
該ウエーハ裏面加工工程及び該透明基板加工工程を実施した後、該ウエーハの裏面に該透明基板の表面を貼着して一体化ウエーハを形成する一体化工程と、
該ウエーハを該分割予定ラインに沿って該透明基板とともに切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、
を備えたことを特徴とする発光ダイオードチップの製造方法。
A method of manufacturing a light emitting diode chip,
Each of the regions has a laminate layer in which a plurality of semiconductor layers including a light emitting layer are formed on a transparent substrate for crystal growth, and is divided into a plurality of division lines intersecting each other on the surface of the laminate layer. A wafer preparation step of preparing a wafer on which an LED circuit is formed;
A wafer back surface processing step for forming a plurality of recesses or first grooves corresponding to each LED circuit on the back surface of the wafer;
A transparent substrate processing step of forming a plurality of second grooves corresponding to each LED circuit of the wafer on the surface of the transparent substrate;
An integration step of forming an integrated wafer by sticking the surface of the transparent substrate to the back surface of the wafer after performing the wafer back surface processing step and the transparent substrate processing step;
A dividing step of cutting the wafer along with the transparent substrate together with the transparent substrate to divide the integrated wafer into individual light emitting diode chips;
A method for producing a light-emitting diode chip, comprising:
該透明基板加工工程で形成される前記第2の溝の断面形状は三角形状、四角形状、半円形状の何れかである請求項1記載の発光ダイオードチップの製造方法。   The method of manufacturing a light-emitting diode chip according to claim 1, wherein a cross-sectional shape of the second groove formed in the transparent substrate processing step is any one of a triangular shape, a square shape, and a semicircular shape. 該ウエーハ裏面加工工程において、前記凹部又は前記第1の溝は切削ブレード、エッチング、サンドブラスト、レーザーの何れかで形成され、
該透明基板加工工程において、前記第2の溝は切削ブレード、エッチング、サンドブラスト、レーザーの何れかで形成される請求項1記載の発光ダイオードチップの製造方法。
In the wafer back surface processing step, the recess or the first groove is formed by any one of a cutting blade, etching, sand blast, and laser,
2. The method of manufacturing a light-emitting diode chip according to claim 1, wherein in the transparent substrate processing step, the second groove is formed by any one of a cutting blade, etching, sand blasting, and laser.
該透明基板は、透明セラミックス、光学ガラス、サファイア、透明樹脂の何れかで形成され、該一体化工程において該透明基板は透明接着剤を使用して該ウエーハに貼着される請求項1記載の発光ダイオードチップの製造方法。   The transparent substrate is formed of any one of transparent ceramics, optical glass, sapphire, and transparent resin, and the transparent substrate is attached to the wafer using a transparent adhesive in the integration step. Manufacturing method of light emitting diode chip. 発光ダイオードチップであって、
表面にLED回路が形成され裏面に凹部又は第1の溝が形成された発光ダイオードと、
該発光ダイオードの裏面に貼着された透明部材と、を備え、
該透明部材の該発光ダイオードとの貼着面には第2の溝が形成されている発光ダイオードチップ。
A light emitting diode chip,
A light emitting diode in which an LED circuit is formed on the front surface and a recess or a first groove is formed on the back surface;
A transparent member attached to the back surface of the light emitting diode,
A light emitting diode chip in which a second groove is formed on a surface of the transparent member attached to the light emitting diode.
JP2016119052A 2016-06-15 2016-06-15 Method for manufacturing light-emitting diode chip and light-emitting diode chip Pending JP2017224724A (en)

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