JP2017220957A - Solid-state imaging element and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve S/N ratio at the time of reading out with high sensitivity while enabling enlargement of a dynamic range.SOLUTION: An element 4 includes: a plurality of pixel blocks BL having one photoelectric conversion part PD, a first node Pa, and one transfer switch which transfers electric charges to the first node Pa from the photoelectric conversion part PD provided corresponding to one photoelectric conversion part PD; two first switch parts SWA which electrically connect and cut off among the first node Pa of one pixel block BL, a first node Pa of the other one pixel block BL, and two second nodes Pb respectively corresponding to these two first nodes Pa; a second switch part SWB which electrically connects and cuts off between two second nodes Pb; and two third switch parts RST which supply predetermined potential VDD to two second nodes Pb, respectively.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

  In Patent Document 1 below, a plurality of pixels, each of which includes at least two pixels including (a) a photodetector, (b) a charge-voltage conversion region that forms a floating capacitance section, and (c) an input section to an amplifier. And a solid-state imaging device including a connection switch that selectively connects the charge-voltage conversion regions.

Special table 2008-546313 gazette

  In the conventional solid-state imaging device, by turning on the connection switch and connecting the charge-voltage conversion regions to each other, the number of saturated electrons in the entire connected charge-voltage conversion region is expanded, so that the dynamic range is increased. Can be enlarged.

  In the conventional solid-state imaging device, the charge-voltage conversion capacity is reduced and the charge-voltage conversion coefficient is increased by turning off the connection switch and separating the charge-voltage conversion region from other charge-voltage conversion regions. Therefore, the SN ratio at the time of high sensitivity reading becomes high.

  However, in the conventional solid-state imaging device, even when the connection switch is turned off, the SN ratio at the time of high-sensitivity readout cannot be increased so much.

  The present invention has been made in view of such circumstances, a solid-state imaging device capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and imaging using the same. An object is to provide an apparatus.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect is provided corresponding to one photoelectric conversion unit, a first node, and the one photoelectric conversion unit, and transfers charges from the photoelectric conversion unit to the first node. A plurality of pixel blocks having one transfer switch, two second nodes respectively corresponding to the first node of one pixel block and the first node of one other pixel block; Two first nodes electrically connecting and disconnecting the first node of the one pixel block and the first node and the two second nodes of the other one pixel block, respectively; A switch unit, a second switch unit that electrically connects and disconnects the two second nodes, and two third switch units that respectively supply a predetermined potential to the two second nodes; With It is intended.

  The pixel block may have only one photoelectric conversion unit and be configured by one pixel, or may have two or more photoelectric conversion units and be configured by a plurality of pixels. Good. This is the same for each aspect described later.

  In the solid-state imaging device according to the second aspect, in the first aspect, each of the pixel blocks includes a plurality of the photoelectric conversion units and the transfer switches.

  In the first or second aspect, the solid-state imaging device according to the third aspect is configured so that, in the first operation mode, the first node of the one pixel block and the second node corresponding to the first node. The first switch unit that electrically connects and disconnects is temporarily turned on only when the potential of the first node of the one pixel block is reset, and the first switch unit of the one pixel block is turned on. The first switch is configured such that the third switch section that supplies the predetermined potential to the second node corresponding to a node is turned on at least when the potential of the first node of the one pixel block is reset. And a control unit for controlling each of the third switch units.

  The solid-state imaging device according to a fourth aspect is the solid-state imaging device according to the third aspect, wherein the control unit is configured so that the first node of the one pixel block and the second node corresponding to the first node The first switch unit that electrically connects and disconnects the first switch unit is turned on, the second switch unit is turned off, and the second node corresponding to the first node of the one pixel block The first switch unit, the second switch unit, and the second switch unit that supply the predetermined potential to the first node are turned on only when the potential of the first node of the one pixel block is reset. And the third switch unit.

  The solid-state imaging device according to a fifth aspect is the solid-state imaging device according to the third or fourth aspect, wherein the control unit is configured to correspond to the first node of the one pixel block and the first node corresponding thereto in the third operation mode. The first switch that electrically connects and disconnects between two nodes is turned on, the second switch is turned on, and corresponds to the first node of the one pixel block Each of the first switch units, so that the third switch unit that supplies the predetermined potential to the second node is turned on only when the potential of the first node of the one pixel block is reset. The second switch unit and the third switch units are controlled.

  In the first or second aspect, the solid-state imaging device according to the sixth aspect includes the first node of three or more pixel blocks of the plurality of pixel blocks, and the three or more of the first nodes. Three or more first switch units for electrically connecting and disconnecting three or more second nodes respectively corresponding to one node. The above second nodes are connected in a daisy chain by a plurality of the second switch units, and three or more third switch units for supplying the predetermined potential to the three or more second nodes, respectively. It is provided.

  The solid-state imaging device according to a seventh aspect is the solid-state imaging device according to the sixth aspect, wherein the first node of one pixel block of the three or more pixel blocks and the corresponding one in the first operation mode. The first switch that electrically connects and disconnects with the second node is only when the potential of the first node of the one pixel block among the three or more pixel blocks is reset. The third switch unit that turns on once and supplies the predetermined potential to the second node corresponding to the first node of the one pixel block of the three or more pixel blocks, The first switch units and the third switches are turned on at least when the potential of the first node of the one pixel block among the three or more pixel blocks is reset. Those having a control unit for controlling the switch unit.

  The solid-state imaging device according to an eighth aspect is the seventh aspect, wherein the control unit includes the first node of one pixel block of the three or more pixel blocks in the second operation mode. The first switch unit that electrically connects and disconnects the second node corresponding to the second node is turned on, and the first pixel block of the one or more of the three or more pixel blocks is turned on. The second switch unit electrically connected to the second node corresponding to the node is turned off, and the first pixel block among the three or more pixel blocks is The third switch unit that supplies the predetermined potential to the second node corresponding to the node resets the potential of the first node of the one pixel block among the three or more pixel blocks. of To turn on, the respective first switch unit, the controls the respective second switching unit and the respective third switch unit.

  In the seventh or eighth aspect, the solid-state imaging device according to a ninth aspect is the first of the pixel blocks of the three or more pixel blocks in the third operation mode. The first switch unit that electrically connects and disconnects the node between the second node and the second node corresponding to the second node is turned on, and the one pixel block of the three or more pixel blocks is turned on. The second switch unit electrically connected to the second node corresponding to the first node is turned on, and the one of the three or more pixel blocks is the one of the pixel blocks. The third switch section that supplies the predetermined potential to the second node corresponding to the first node is configured such that the potential of the first node of the one pixel block among the three or more pixel blocks is Reset To turn only when the respective first switching section, the controls the respective second switching unit and the respective third switch unit.

  An imaging apparatus according to a tenth aspect includes the solid-state imaging element according to any one of the first to ninth aspects.

  An imaging apparatus according to an eleventh aspect is a solid-state imaging device according to the third, fourth, fifth, seventh, eighth, or ninth aspect, and control for switching each operation mode according to a set value of ISO sensitivity. Means.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to expand a dynamic range, the solid-state image sensor which can improve the S / N ratio at the time of highly sensitive reading, and an imaging device using the same can be provided.

1 is a schematic block diagram schematically showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. FIG. 2 is an enlarged circuit diagram illustrating the vicinity of four pixel blocks in FIG. 1. FIG. 4 is a schematic plan view schematically showing the vicinity of three pixel blocks in FIG. 3. FIG. 5 is an enlarged schematic plan view showing the vicinity of one pixel block in FIG. 4. 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2. 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2. 6 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. 6 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. 6 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor by a comparative example. FIG. 10 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 9. It is a circuit diagram which shows schematic structure of the solid-state image sensor of the electronic camera by the 2nd Embodiment of this invention.

  Hereinafter, a solid-state imaging device and an imaging apparatus according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram schematically showing the electronic camera 1 according to the first embodiment of the present invention.

  The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera. However, the imaging apparatus according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. The present invention can be applied to various imaging devices such as an electronic camera and an electronic camera such as a video camera that captures moving images.

  A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 3 for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 4 is arranged.

  The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. In normal main shooting (during still image shooting) or the like, the imaging control unit 5 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after, for example, a so-called global reset that resets all pixels simultaneously. The solid-state image sensor 4 is controlled. In the electronic viewfinder mode or moving image shooting, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a predetermined reading operation while performing a so-called rolling electronic shutter, for example. At these times, as will be described later, the imaging controller 5 controls the solid-state imaging device 4 so as to perform a read operation in each operation mode described later according to the ISO sensitivity setting value. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12 and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set by the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

  When the CPU 9 in the electronic camera 1 is instructed by the operation unit 14 to operate in the electronic viewfinder mode, moving image shooting, normal normal shooting (still image shooting), or the like, the CPU 9 drives the imaging control unit 5 accordingly. At this time, the lens controller 3 appropriately adjusts the focus and the aperture. The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. A digital image signal from the solid-state imaging device 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a during moving image shooting. In the case of normal main shooting (during still image shooting) or the like, the CPU 9 processes the digital image signal from the solid-state imaging device 4 by the digital signal processing unit 6 and stores it in the memory 7, and then the operation unit 14. The image processing unit 13 or the image compression unit 12 performs a desired process based on the above command, outputs the processed signal to the recording unit 11 and records it on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 in FIG. FIG. 3 is an enlarged circuit diagram showing the vicinity of four pixel blocks BL sequentially arranged in the column direction in FIG. FIG. 4 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL in FIG. FIG. 5 is an enlarged schematic plan view showing the vicinity of one pixel block BL in FIG. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS type solid-state imaging device, but is not limited thereto, and may be configured as, for example, another XY address type solid-state imaging device.

  As shown in FIGS. 2 to 4, the solid-state imaging device 4 includes a pixel block BL arranged in a two-dimensional matrix in N rows and M columns and having two pixels PX (PXA, PXB), respectively, and a first block described later. The first transistor SWA as the first switch unit that electrically connects and disconnects between the node Pa and the corresponding second node Pb, and the two second nodes Pb are electrically connected. And a second transistor SWB as a second switch section to be disconnected, a reset transistor RST as a third switch section for supplying a power supply voltage VDD as a predetermined potential to the second node Pb, a vertical scanning circuit 21, The control lines 22 to 27 provided for each row of the pixel block BL and the corresponding pixel PX (pixel block B) provided for each column of the pixel PX (for each column of the pixel block BL). A plurality of (M) vertical signal lines 28 that receive signals from the vertical signal lines 28, a constant current source 29 provided for each vertical signal line 28, and a column amplifier 30 provided corresponding to each vertical signal line 28, A CDS circuit (correlated double sampling circuit) 31, an A / D converter 32, and a horizontal readout circuit 33 are provided.

  The column amplifier 30 may be an analog amplifier or a so-called switched capacitor amplifier. Further, the column amplifier 30 is not necessarily provided.

  For convenience of drawing, FIG. 2 shows M = 2, but the number of columns M is actually a larger arbitrary number. Further, the number N of rows is not limited. When distinguishing the pixel block BL for each row, the pixel block BL in the j-th row is indicated by a symbol BL (j). This also applies to other elements and control signals described later. 2 and 3 show pixel blocks BL (n−1) to BL (n + 2) in the (n−1) th to n + 2th rows over four rows.

  In the drawing, the pixel of the pixel block BL is distinguished from the lower pixel in FIGS. 2 and 3 by PXA and the upper pixel in FIGS. 2 and 3 is PXB. When the description is made without distinction, the description may be made with the reference numeral PX attached to both. In the drawings, the photodiode of the pixel PXA is identified by PDA, and the photodiode of the pixel PXB is identified by PDB. However, when the description is made without distinguishing both, the PD is denoted by PD. May explain. Similarly, the transfer transistor of the pixel PXA is denoted by TXA and the transfer transistor of the pixel PXB is denoted by TXB. The two are distinguished from each other. There is a case. In the present embodiment, the photodiodes PD of the pixels PX are arranged in 2N rows and M columns in a two-dimensional matrix.

  In the present embodiment, each pixel PX is a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and a transfer switch that transfers charges from the photodiode PD to the first node Pa. Transfer transistor TX.

  In the present embodiment, the plurality of pixels PX form a pixel block BL for every two pixels PX (PXA, PXB) in which the photodiodes PD are sequentially arranged in the column direction. As shown in FIGS. 2 and 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL include one set of first node Pa, amplification transistor AMP, and selection transistor. Share SEL. A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa and the reference potential, and the charge transferred to the first node Pa is converted into a voltage by the capacitance. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the first node Pa. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are provided for each pixel PX without being shared by the two pixels PX (PXA, PXB). 2 and 3, n indicates a row of the pixel block BL. For example, a pixel block BL in the first row is constituted by the pixel PX (PXA) in the first row and the pixel PX (PXB) in the second row, and the pixel PX (PXA) in the third row and the pixel PX in the fourth row. (PXB) constitutes the pixel block BL in the second row.

  For example, the transfer transistor TXA (n) of the pixel block BL (n) transfers charge from the photodiode PDA (n) to the first node Pa (n), and the transfer transistor TXB (n) is the photodiode PDB (n ) To the first node Pa (n). A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa (n) and the reference potential, and the charge transferred to the first node Pa (n) is converted into a voltage by the capacitance. The The amplification transistor AMP (n) outputs a signal corresponding to the potential of the first node Pa (n). The same applies to the rows of other pixel blocks BL.

  In the present invention, for example, the pixel block BL may be configured for each of three or more pixels PX in which the photodiodes PD are sequentially arranged in the column direction.

  Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light of different color components are arranged in a predetermined color array on the light incident side of the photodiode PD of each pixel PX. (For example, a Bayer array). The pixel PX outputs an electrical signal corresponding to each color by color separation with a color filter.

  The first transistor SWA (n) constitutes a first switch unit that electrically connects and disconnects between the first node Pa (n) and the corresponding second node Pb (n). ing. Such a first switch unit can be configured by combining a plurality of switches such as transistors, but in order to simplify the structure, a single first transistor SWA is used as in the present embodiment. (N) is preferable. The same applies to the other first transistors SWA.

  Each second transistor SWB includes a second node Pb corresponding to the first node Pa of the one pixel block BL and the other of the two pixel blocks BL adjacent to each other in the column direction among the pixel blocks BL. The second switch unit is configured to be electrically connected to and disconnected from the second node Pb corresponding to the first node Pa of the pixel block BL. Thus, in the present embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy chain by a plurality of the second switch portions. The second switch portion as described above can be configured by combining a plurality of switches such as a plurality of transistors. However, in order to simplify the structure, a single second transistor is used as in the present embodiment. It is preferable to use SWB.

  For example, the second transistor SWB (n) includes the second node Pb (n) corresponding to the first node Pa (n) of the pixel block BL (n) in the nth row and the pixel in the n−1th row. The block BL (n−1) is provided so as to be electrically connected to and disconnected from the second node Pb (n−1) corresponding to the first node Pa (n−1) of the block BL (n−1). This also applies to the other second transistors SWB.

  The reset transistor RST (n) constitutes a third switch unit that supplies the power supply voltage VDD as a predetermined potential to the second node Pb (n). Although such a third switch unit can be configured by combining a plurality of switches such as transistors, in order to simplify the structure, a single reset transistor RST (n ) Is preferable. The same applies to the other reset transistors RST.

  2 and 3, VDD is a power supply potential. In the present embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWA, SWB are all nMOS transistors.

  The gate of the transfer transistor TXA is commonly connected to the control line 26 for each row, and a control signal φTXA is supplied from the vertical scanning circuit 21 to the gate. The gate of the transfer transistor TXB is commonly connected to the control line 25 for each row, and a control signal φTXB is supplied from the vertical scanning circuit 21 to the gate. The gates of the reset transistors RST are commonly connected to the control line 24 for each row, and a control signal φRST is supplied from the vertical scanning circuit 21 there. The gates of the selection transistors SEL are connected in common to the control line 23 for each row, and a control signal φSEL is supplied from the vertical scanning circuit 21 there. The gates of the first transistors SWA are commonly connected to the control line 22 for each row, and a control signal φSWA is supplied from the vertical scanning circuit 21 to the first transistor SWA. The gates of the second transistors SWB are commonly connected to the control line 27 for each row, and a control signal φSWB is supplied from the vertical scanning circuit 21 to the gate. For example, the control signal φTXA (n) is supplied to the gate of the transfer transistor TXA (n), the control signal φTXB (n) is supplied to the gate of the transfer transistor TXB (n), and the gate of the reset transistor RST (n). Is supplied with the control signal φRST (n), the gate of the selection transistor SEL (n) is supplied with the control signal φSEL (n), and the gate of the first transistor SWA (n) is supplied with the control signal φSWA (n). And a control signal φSWB (n) is supplied to the gate of the second transistor SWB (n).

  Each transistor TXA, TXB, RST, SEL, SWA, SWB is turned on when the corresponding control signal φTXA, φTXB, φRST, φSEL, φSWA, φSWB is high level (H), and is low level (L). Turn off.

  The vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB for each row of the pixel block BL under the control of the imaging control unit 5 in FIG. The first transistor SWA and the second transistor SWB are controlled to realize a still image reading operation, a moving image reading operation, and the like. In this control, for example, a read operation in each operation mode, which will be described later, is performed according to the set value of the ISO sensitivity. By this control, the signal (analog signal) of the pixel PX in the corresponding column is supplied to each vertical signal line 28.

  In the present embodiment, the vertical scanning circuit 21 constitutes a control unit that switches each operation mode to be described later according to a command (control signal) from the imaging control unit 5 in FIG.

  The signal read out to the vertical signal line 28 is amplified by the column amplifier 30 for each column, and further optical signals (signals including optical information photoelectrically converted by the pixels PX) and dark signals (light After being subjected to processing for obtaining a difference from the signal (difference signal including a noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 32, and the digital signal is held in the A / D converter 32. Is done. The digital image signal held in each A / D converter 32 is horizontally scanned by a horizontal readout circuit 33, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ).

  The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and when φDARKC is at a high level (H), The output signal is sampled as a dark signal, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1. When φSIGC is H, the output signal of the column amplifier 30 is converted into an optical signal. Sampling as Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and optical signal based on the clock and pulse from the timing generation circuit. As the configuration of the CDS circuit 31, a known configuration can be adopted.

  Here, the structure of the pixel block BL will be described with reference to FIGS. In practice, a color filter, a microlens, and the like are disposed above the photodiode PD, but are omitted in FIGS. 4 and 5, the layout of the power supply line, the ground line, the control lines 22 to 27, etc. is omitted.

  In the present embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL such as a photodiode PD is arranged in the P-type well. Yes. In FIG. 5, reference numerals 41 to 50 denote N-type impurity diffusion regions that are part of the above-described transistors. Reference numerals 61 to 67 denote gate electrodes of the respective transistors made of polysilicon. The diffusion regions 42 and 50 are regions to which the power supply voltage VDD is applied by a power supply line (not shown).

  The photodiodes PDA (n) and PDB (n) include an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (see FIG. It is an embedded photodiode made of (not shown). The photodiodes PDA (n) and PDB (n) photoelectrically convert incident light and store the generated charges in the charge storage layer.

  The transfer transistor TXA (n) is an nMOS transistor having a charge storage layer of the photodiode PDA (n) as a source, a diffusion region 41 as a drain, and a gate electrode 61 as a gate. The transfer transistor TXB (n) is an nMOS transistor having the charge storage layer of the photodiode PDB (n) as a source, the diffusion region 41 as a drain, and the gate electrode 62 as a gate. The diffusion region 41 is provided between the photodiode PDA (n) and the photodiode PDB (n). The diffusion region 41 is also used as a diffusion region serving as the drain of the transfer transistor TXA (n) and a diffusion region serving as the drain of the transfer transistor TXB (n). The gate electrode 61 of the transfer transistor TXA (n) is disposed on the photodiode PDA (n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB (n) is disposed on the photodiode PDB (n) side of the diffusion region 41.

  The amplification transistor AMP (n) is an nMOS transistor having the diffusion region 42 as a drain, the diffusion region 43 as a source, and the gate electrode 63 as a gate. The selection transistor SEL (n) is an nMOS transistor having the diffusion region 43 as a drain, the diffusion region 44 as a source, and the gate electrode 64 as a gate. The diffusion region 44 is connected to the vertical signal line 28.

  The first transistor SWA (n) is an nMOS transistor having the diffusion region 45 as a source, the diffusion region 46 as a drain, and the gate electrode 65 as a gate. The second transistor SWB (n) is an nMOS transistor having the diffusion region 47 as a drain, the diffusion region 48 as a source, and the gate electrode 66 as a gate. The reset transistor RST (n) is an nMOS transistor having the diffusion region 49 as a source, the diffusion region 50 as a drain, and the gate electrode 67 as a gate.

  The gate electrode 63 and the diffusion regions 41 and 45 of the pixel block BL (n) are electrically connected to each other by the wiring 71 (n) to be conductive. In the present embodiment, the first node Pa (n) corresponds to the wiring 71 (n) and the entire portion that is electrically connected to and conductive with respect to the wiring 71 (n).

  The drain diffusion region 46 of the first transistor SWA (n), the drain diffusion region 47 of the second transistor SWB (n), the source diffusion region 49 of the reset transistor RST (n), and the source of the second transistor SWB (n + 1) The diffusion regions 48 are electrically connected to each other by the wiring 72 (n) to be conductive. The second node Pb (n) corresponds to the wiring 72 (n) and the entire portion that is electrically connected to and conductive with the wiring 72 (n). The same applies to other first transistors SWA, other second transistors SWB, and other reset transistors RST.

  The structure of the pixel block BL other than the nth row is the same as the structure of the pixel block BL (n) in the nth row. The structure of the first transistor SWA other than the first transistor SWA (n) is similar to the structure of the first transistor SWA (n) described above. The structure of the connection transistor SWB other than the second transistor SWB (n) is the same as the structure of the connection transistor SWB (n) described above. The structures of the reset transistors RST other than the reset transistor RST (n) are the same as the structure of the reset transistor RST (n) described above.

  2 to 5, CC (n) is a capacitance between the first node Pa (n) and the reference potential when the first transistor SWA (n) is off. The capacitance value of the capacitor CC (n) is Cfd1. CD (n) is a reference to the wiring 72 (n) when the first transistor SWA (n), the second transistor SWB (n), SWB (n + 1), and the reset transistor RST (n) are off. It is the capacity between the potential. Let Cfd2 be the capacitance value of the capacitance CD (n). The same applies to other first transistors SWA, other second transistors SWB, and other reset transistors RST.

  The capacitance CC (n) includes the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region of the first transistor SWA (n), and the amplification transistor AMP (n). The capacitance of the gate electrode 63 and the wiring capacitance of the wiring 71 (n) are configured, and the total of these capacitance values becomes the capacitance value Cfd1 of the capacitance CC (n). The same applies to the rows of other pixel blocks BL. Note that the drain diffusion region 47 of the second transistor SWB (n) and the source diffusion region 49 of the reset transistor RST (n) do not become components of the capacitor CC (n), and accordingly, the capacitance of the capacitor CC (n). The value Cfd1 becomes smaller.

  Here, the value of the channel capacitance when the first transistor SWA is on and the value of the channel capacitance when the second transistor SWB is on are both Csw. Usually, the capacitance value Csw is smaller than the capacitance values Cfd1 and Cfd2.

  Now, paying attention to the pixel block BL (n), the first transistor SWA (n) is turned off (that is, the on-state transistor among the first transistors SWA and the second transistors SWB is the first one). And a capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is a capacitance CC (n). It becomes. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1. This state is a state other than when the first node Pa (n) is reset during a period T2 in FIG. 6 showing a first operation mode to be described later (φSWA (n) is L in the period T2 in FIG. 6). Corresponds to the period state).

  When the first transistor SWA (n) is turned on by focusing on the pixel block BL (n), the first transistor SWA and the second transistor SWB other than the first transistor SWA (n) are turned on. Are not electrically connected to the first node Pa (n) (here, specifically, the second transistors SWB (n), SWB (n + 1) Is off), the capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is the capacitance CD (n) and the first transistor with respect to the capacitance CC (n). The channel capacity when SWA (n) is turned on is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2. This state corresponds to a state of a period T2 in FIG. 7 showing a second operation mode described later.

  Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, among the first transistors SWA and the second transistors SWB, If the transistors other than the transistors SWA (n) and SWB (n + 1) are not electrically connected to the first node Pa (n) (here, specifically, the transistor SWB). (If (n), SWA (n + 1), SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is the capacitance CD (n), The capacitance CD (n + 1) and the channel capacitance when the transistors SWA (n) and SWB (n + 1) are turned on are added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 2 × Cfd2 + 2 × Csw≈Cfd1 + 2 × Cfd2. This state corresponds to a state of a period T2 in FIG. 8 showing a 3A operation mode to be described later.

  Furthermore, paying attention to the pixel block BL (n), when the first transistors SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, the first transistors SWA and the second transistors SWA (n + 1) are turned on. Of the transistors SWB, transistors other than the transistors SWA (n), SWA (n + 1), and SWB (n + 1) must be in an electrically connected state with respect to the first node Pa (n). Here, specifically, if the transistors SWB (n) and SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is relative to the capacitance CC (n). Capacitance CD (n), capacitance CD (n + 1), capacitance CC (n + 1) and channel capacitance when the transistors SWA (n), SWA (n + 1) and SWB (n + 1) are turned on are added. The things. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 + 2 × Cfd2 + 3 × Csw≈2 × Cfd1 + 2 × Cfd2. This state corresponds to a state of a period T2 in FIG. 9 showing a 3B operation mode to be described later.

  Further, focusing on the pixel block BL (n), when the first transistor SWA (n) and the second transistors SWB (n + 1) and SWB (n + 2) are turned on, the first transistors SWA and the second transistors SWB (n + 1) and SWB (n + 2) are turned on. Of the transistors SWB, transistors in the on state other than the transistors SWA (n), SWB (n + 1), and SWB (n + 2) are not electrically connected to the first node Pa (n) ( Here, specifically, if the transistors SWA (n + 1), SWA (n + 2), SWB (n), and SWB (n + 3) are off), the charge-voltage conversion capacity of the first node Pa (n) is For the capacitor CC (n), the capacitor CD (n), the capacitor CD (n + 1), the capacitor CD (n + 2), and the transistors SWA (n), SWB (n + 1), SWB (n + 2) The obtained by adding the channel capacity when on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 3 × Cfd2 + 3 × Csw≈Cfd1 + 3 × Cfd2. This state corresponds to a state of a period T2 in FIG. 10 showing a 3C operation mode to be described later.

  As described above, if there is no on-state transistor electrically connected to the first node Pa (n) among the first transistors SWA and the second transistors SWB, the first node Pa ( Since the capacitance value of the charge voltage conversion capacitor n) becomes the minimum capacitance value Cfd1, and the charge voltage conversion coefficient by the charge voltage conversion capacitor is increased, reading at the highest SN ratio is possible.

  On the other hand, among the first transistors SWA and the second transistors SWB, the number of ON-state transistors electrically connected to the first node Pa (n) is increased to one or more desired numbers. If so, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) can be increased to a desired value and a large amount of signal charge can be handled, so that the number of saturated electrons can be increased. it can. Thereby, the dynamic range can be expanded.

  The first node Pa (n) of the pixel block BL (n) has been described above, but the same applies to the first nodes Pa of other pixel blocks BL.

  FIG. 6 is a timing chart showing a first operation mode of the solid-state imaging device 4 shown in FIG. In the first operation mode, each pixel block BL is sequentially selected for each row, and the first node Pa of the selected pixel block BL among the first transistors SWA and the second transistors SWB is applied to the first node Pa. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected in a state where there is no on-state transistor electrically connected to the transistor (a state where the charge-voltage conversion capacitance of the first node Pa is minimum). This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read for each row. In the example illustrated in FIG. 6, signals of all the pixels PXA and PXB are read out. However, the present invention is not limited to this. For example, thinning out reading that reads out pixel rows may be performed. This also applies to each example shown in FIGS. 7 to 10 described later.

  In FIG. 6, the pixel block BL (n-1) in the (n-1) th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixels in the (n + 1) th row in the period T3. This shows a situation where the block BL (n + 1) is selected. Since the operation when the pixel block BL of any row is selected is the same, only the operation when the pixel block BL (n) of the n-th row is selected will be described here.

  The exposure of the photodiodes PDA (n) and PDB (n) has already been completed in the predetermined exposure period before the start of the period T2. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time during normal main shooting (still image shooting), and during electronic viewfinder mode or movie shooting. This is performed by a so-called rolling electronic shutter operation. Immediately before the start of the period T2, all the transistors SEL, RST, TXA, TXB, SWA, SWB are turned off.

  In the period T2, φSEL (n) in the nth row is set to H, the selection transistor SEL (n) in the pixel block BL (n) in the nth row is turned on, and the pixel block BL (n) in the nth row is turned on. Selected. Further, in the period T2, φRST (n) in the n-th row is set to H, and the reset transistor RST (n) is turned on. However, the reset transistor RST (n) does not necessarily have to be turned on over the entire period T2, and φRST (n) is used when the first node Pa (n) is reset (that is, φSWA ( Only the H period (n) may be set to H.

  ΦSWA (n) is set to H and the first transistor SWA (n) in the n-th row is temporarily turned on for a certain period (at the time of resetting the first node Pa (n)) immediately after the start of the period T2. . At this time, since φRST (n) is set to H and the reset transistor RST (n) is turned on, it passes through the reset transistor RST (n) in the on state and the first transistor SWA (n) in the on state. Thus, the potential of the first node Pa (n) is once reset to the power supply potential VDD.

  Thereafter, when the first transistor SWA (n) is turned off, it is electrically connected to the first node Pa (n) of the selected pixel block BL (n) among the transistors SWA and SWB. There is no on-state transistor. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1, which is the minimum.

  The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time t1 in the period T2, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the n-th row. A signal amplified later by the column amplifier 30 via the selection transistor SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXA (n) is set to H and the transfer transistor TXA (n) in the n-th row is turned on for a certain period from time t2 thereafter in period T2. As a result, the signal charge accumulated in the photodiode PDA (n) of the pixel block BL (n) in the nth row is transferred to the charge-voltage conversion capacitor of the first node Pa (n). The potential of the first node Pa (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n), excluding noise components.

  At a subsequent time t3 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor A signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is further sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t1 and the optical signal sampled in a certain time from time t3. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  Then, during a certain period (at the time of resetting the first node Pa (n)) from the time point t4 in the period T2, φSWA (n) is set to H and the first transistor SWA (n) in the n-th row is once turned on. To be. At this time, since φSEL (n) is set to H and the reset transistor RST (n) is turned on, it passes through the reset transistor RST (n) in the on state and the first transistor SWA (n) in the on state. Thus, the potential of the first node Pa (n) is once reset to the power supply potential VDD.

  Thereafter, when the first transistor SWA (n) is turned off, it is electrically connected to the first node Pa (n) of the selected pixel block BL (n) among the transistors SWA and SWB. There is no on-state transistor. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1, which is the minimum.

  The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time point t5 in the period T2, and the potential appearing at the first node Pa (n) is amplified by the n-th amplification transistor AMP (n). A signal amplified later by the column amplifier 30 via the selection transistor SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXB (n) is set to H and the transfer transistor TXB (n) in the n-th row is turned on for a certain period from time t6 thereafter in period T2. As a result, the signal charge accumulated in the photodiode PDB (n) of the pixel block BL (n) in the nth row is transferred to the charge-voltage conversion capacitor of the first node Pa (n). The potential of the first node Pa (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n), excluding noise components.

  At a subsequent time t7 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the n-th row, and then the selection transistor A signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is further sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t5 and the optical signal sampled in a certain time from time t7. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  As described above, in the first operation mode, the transistor SWA and SWB are selected because there is no transistor in the on state that is electrically connected to the first node Pa of the selected pixel block BL. In addition, since the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the pixel block BL is minimized and the charge-voltage conversion coefficient by the charge-voltage conversion capacitance is increased, reading with the highest SN ratio is possible. For example, when the ISO sensitivity setting value is the highest, the imaging control unit 5 instructs to perform the first operation mode.

  FIG. 7 is a timing chart showing a second operation mode of the solid-state imaging device 4 shown in FIG. In the second operation mode, each pixel block BL is sequentially selected for each row, and one on-state transistor SWA is selected from each first transistor SWA and each second transistor SWB. In a state of being electrically connected to the first node Pa of the pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on sequentially, and each of the selected pixel blocks BL is selected. It is an example of the operation | movement which reads the signal of photodiode PDA, PDB sequentially for every line.

  In FIG. 7, similarly to FIG. 6, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The second operation mode shown in FIG. 7 is different from the first operation mode shown in FIG. 6 in the following point.

  In the second operation mode shown in FIG. 7, in a period T2 in which the pixel block BL (n) in the n-th row is selected, φSWA (n) is set to H and φSWB (n), φSWB (n + 1) is set to L. The first transistor SWA (n) is turned on and the second transistors SWB (n) and φSWB (n + 1) are turned off. Thus, in the period T2, one of the transistors SWA and SWB that is in the on state is turned on by the first transistor SW (here, the first transistor SWA (n)) of the selected pixel block BL (n). The first node Pa (n) is electrically connected. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2, which is one step larger than that in the first operation mode shown in FIG.

  In the second operation mode shown in FIG. 7, while φSWA (n) is set to H and the first transistor SWA (n) is turned on, the first node Pa (n) is reset. Only at the time (a certain period immediately after the start of the period T2 and a certain period from the time point t4 in the period T2), φRST (n) is set to H and the reset transistor RST (n) is turned on. As a result, the potential of the first node Pa (n) is appropriately reset.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the second operation mode, one of the transistors SWA and SWB and the first transistor SWA in the on state are electrically connected to the first node Pa of the selected pixel block BL. Since they are connected, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL is increased by one level, and the number of saturated electrons in the charge-voltage conversion capacitance of the first node Pa is increased by one level. Can be enlarged. Thereby, the dynamic range can be expanded by one step. For example, when the ISO sensitivity setting value is one step smaller than the highest value, the imaging control unit 5 instructs the second operation mode to be performed.

  FIG. 8 is a timing chart showing a 3A operation mode of the solid-state imaging device 4 shown in FIG. The third A operation mode is one of the third operation modes. In the third operation mode, each pixel block BL is sequentially selected for each row, and an electrical connection is made between the first node Pa of the selected pixel block BL and the corresponding second node Pb. The first transistor SWA to be connected to and disconnected from is turned on, and the second transistor SWB electrically connected to the second node Pb corresponding to the first node Pa of the selected pixel block BL is turned on. The reset transistor RST that supplies the power supply potential VDD to the second node Pb corresponding to the first node Pa of the selected pixel block BL resets the first node Pa of the selected pixel block BL. The transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on sequentially in a state in which they are turned on only when Diodes PDA, a an example of a sequential operation for reading signal PDB for each row. In the third operation mode, in the third operation mode, one first transistor SWA in the on state and one second transistor in the on state with respect to the first node Pa of the selected pixel block BL. This is an example of an operation in which the transistor SWB is electrically connected.

  In FIG. 8, similarly to FIG. 6, the pixel block BL (n-1) in the (n-1) th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The difference between the 3A operation mode shown in FIG. 8 and the first operation mode shown in FIG. 6 is as follows.

  In the operation mode 3A shown in FIG. 8, in the period T2 during which the pixel block BL (n) in the n-th row is selected, φSWA (n) and φSWB (n + 1) are set to H and φSWA (n + 1), φSWB (N), φSWB (n + 2) are set to L, the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, and the first transistor SWA (n + 1) and the second transistor SWB are turned on. (N), SWB (n + 2) is turned off. Thus, in the period T2, one of the transistors SWA and SWB is turned on, the first transistor SWA in the on state (here, the first transistor SWA (n)) and one second transistor SWB in the on state ( Here, the second transistor SWB (n + 1)) is electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2, which is two steps larger than the first operation mode shown in FIG.

  In the operation mode 3A shown in FIG. 8, φSWA (n) is set to H and the first transistor SWA (n) is turned on, while the first node Pa (n) is reset. Only at the time (a certain period immediately after the start of the period T2 and a certain period from the time point t4 in the period T2), φRST (n) is set to H and the reset transistor RST (n) is turned on. As a result, the potential of the first node Pa (n) is appropriately reset. This is the same for the 3B operation mode shown in FIG. 9 and the 3C operation mode shown in FIG.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the third operation mode, one of the transistors SWA and SWB is turned on by the first transistor SWA in the on state and the second transistor SWB in the on state of the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by two levels, and the charge of the first node Pa The number of saturated electrons in the voltage conversion capacity can be increased by two stages. Thereby, the dynamic range can be expanded by two stages. For example, when the ISO sensitivity setting value is a value that is two steps smaller than the highest value, the imaging control unit 5 instructs to perform the third A operation mode.

  FIG. 9 is a timing chart showing a 3B operation mode of the solid-state imaging device 4 shown in FIG. In the third operation mode, in the third operation mode, with respect to the first node Pa of the selected pixel block BL, the two first transistors SWA in the on state and the one second in the on state. This is an example of an operation in which the transistor SWB is electrically connected.

  9, similarly to FIG. 4, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 is selected. FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The difference between the third mode of operation shown in FIG. 9 and the first mode of operation shown in FIG. 4 is as follows.

  In the operation mode 3B shown in FIG. 9, φSWA (n), φSWA (n + 1) and φSWB (n + 1) are set to H and φSWB in the period T2 in which the pixel block BL (n) in the n-th row is selected. (N), φSWB (n + 2) are set to L, the first transistors SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, and the second transistors SWB (n), SWB (n + 2) is turned off. Accordingly, in the period T2, two of the transistors SWA and SWB, the first transistor SWA in the on state (here, the first transistors SWA (n) and SWA (n + 1)) and the first transistor in the on state. The second transistor SWB (here, the second transistor SWB (n + 1)) is electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 + 2 × Cfd2 + 3 × Csw≈2 × Cfd1 + 2 × Cfd2, and the first operation mode shown in FIG. Compared to, it will be three steps larger.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the third B operation mode, two on-state first transistors SWA and one on-state second transistor SWB among the transistors SWA and SWB are connected to the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three levels, and the charge of the first node Pa The number of saturated electrons in the voltage conversion capacity can be increased by three levels. As a result, the dynamic range can be expanded by three levels. For example, when the ISO sensitivity setting value is a value that is three steps smaller than the highest value, the imaging control unit 5 instructs to perform the third B operation mode.

  FIG. 10 is a timing chart showing the 3C operation mode of the solid-state imaging device 4 shown in FIG. In the third C operation mode, each pixel block BL is sequentially selected for each row, and one of the first transistors SWA and 2 of the first transistors SWA and the second transistors SWB is turned on. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected while the two second transistors SWB in the on state are electrically connected to the first node Pa of the selected pixel block BL. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read for each row.

  Similarly to FIG. 6, in FIG. 10, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 is selected. FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The third C operation mode shown in FIG. 10 is different from the first operation mode shown in FIG. 4 in the following point.

  In the 3C operation mode shown in FIG. 10, φSWA (n), φSWB (n + 1), φSWB (n + 2) are set to H and φSWA in the period T2 in which the pixel block BL (n) in the n-th row is selected. (N + 1), φSWA (n + 2), φSWB (n), φSWB (n + 3) are set to L, and the first transistor SWA (n) and the second transistors SWB (n + 1), SWB (n + 2) are turned on. At the same time, the first transistors SWA (n + 1) and SWA (n + 2) and the second transistors SWB (n) and SWB (n + 3) are turned off. Thus, in the period T2, one of the transistors SWA and SWB is turned on, the first transistor SWA in the on state (here, the first transistor SWA (n)) and the two second transistors SWB in the on state ( Here, the second transistors SWB (n + 1) and SWB (n + 2)) are electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 3 × Cfd2 + 3 × Csw≈Cfd1 + 3 × Cfd2, which is more than the first operation mode shown in FIG. Increase by 3 levels.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  In this way, in the 3C operation mode, one of the transistors SWA and SWB, one on-state first transistor SWA and two on-state second transistors SWB are included in the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three levels, and the charge of the first node Pa The number of saturated electrons in the voltage conversion capacity can be increased by three levels. As a result, the dynamic range can be expanded by three levels. For example, when the ISO sensitivity setting value is three steps lower than the highest value, the imaging control unit 5 instructs to perform the second operation mode.

  Here, a solid-state image sensor according to a comparative example compared with the solid-state image sensor 4 in the present embodiment will be described. FIG. 11 is a circuit diagram showing the vicinity of three pixel blocks BL of the solid-state imaging device according to this comparative example, and corresponds to FIG. FIG. 12 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 11, and corresponds to FIGS. 11 and 12, elements that are the same as or correspond to those in FIGS. 3, 4, and 5 are denoted by the same reference numerals, and redundant description thereof is omitted. In FIG. 12, reference numerals are not assigned to the diffusion regions and the gate electrodes, but those reference numerals are the same as those in FIG. 5, so refer to FIG. 5 as necessary.

  This comparative example is different from the present embodiment in the points described below. In this comparative example, the first and second transistors SWA and SWB and the wirings 71 and 72 are removed, and instead, a first connection transistor SWa, a second connection transistor SWb, and wirings 97 and 98 are provided. Yes. In this comparative example, the node P corresponding to the first node Pa exists, but the node corresponding to the second node Pb does not exist. Furthermore, in the present embodiment, the source of the reset transistor RST is not connected to the first node Pa but is connected to the second node Pb, whereas in this comparative example, the source of the reset transistor RST is the node Connected to P.

  In this comparative example, for each two pixel blocks BL adjacent to each other in the column direction among the pixel blocks BL, the first pixel block BL is connected between the node P of one pixel block BL and the node P of the other pixel block BL. The connection transistor SWa and the second connection transistor SWb are provided in series. For example, between the node P (n) of the pixel block BL (n) in the nth row and the node P (n + 1) of the pixel block BL in the n + 1th row, the first connection transistor SWa (n) and the second The connecting transistor SWb (n) is provided in series.

  In this comparative example, the gate electrode of the amplification transistor AMP (n) of the pixel block BL (n), the drain diffusion region of the transfer transistors TXA (n) and TXB (n), and the source diffusion of the first connection transistor SWa (n) The region, the drain diffusion region of the second connection transistor SWb (n−1), and the source diffusion region of the reset transistor RST (n) are electrically connected to each other by the wiring 97 (n) and are conductive. The node P (n) corresponds to the wiring 97 (n) and the entire portion that is electrically connected to and conductive with the wiring 97 (n). This also applies to the other pixel blocks BL.

  In this comparative example, the two connection transistors SWa and SWb provided in series between the two nodes P are connected by the wiring 98. For example, the drain diffusion region of the first connection transistor SWa (n) and the source diffusion region of the second connection transistor SWb (n) are electrically connected by the wiring 98 (n).

  In FIGS. 11 and 12, CA (n) is a capacitance between the node P (n) and the reference potential when the connection transistors SWa (n) and SWb (n−1) are off. Let the capacitance value of the capacitor CA (n) be Cfd1 '. CB (n) indicates a capacitance between the wiring 72 (n) and the reference potential when the connection transistors SWa (n) and SWb (n) are off. The same applies to the rows of other pixel blocks BL.

  The capacitor CA (n) includes the capacitance of the drain diffusion region of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region of the reset transistor RST (n), and the capacitance of the first connection transistor SWa (n). A capacitance of the source diffusion region, a capacitance of the drain diffusion region of the second connection transistor SWb (n−1), a capacitance of the gate electrode of the amplification transistor AMP (n), and a wiring capacitance of the wiring 97 (n) The sum of these capacitance values is the capacitance value Cfd1 ′ of the capacitance CA (n). The same applies to the rows of other pixel blocks BL.

  On the other hand, the capacitance CC (n) in this embodiment is equal to the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n) and the capacitance of the first transistor SWA (n) as described above. The capacitance of the source diffusion region, the capacitance of the gate electrode of the amplification transistor AMP (n), and the wiring capacitance of the wiring 71 (n) are the sum of those capacitance values and the capacitance value Cfd1 of the capacitor CC (n). It has become.

  Therefore, the capacitance value Cfd1 of the capacitor CC (n) in the present embodiment is larger than the capacitance value Cfd1 ′ of the capacitor CA (n) in this comparative example, and the drain diffusion region of the second connection transistor SWb (n−1). And the capacitance of the source diffusion region of the reset transistor RST (n) (that is, two transistor diffusion capacitances) become smaller.

  In this comparative example, paying attention to the pixel block BL (n), when both of the coupling transistors SWa (n) and SWb (n−1) are turned off, the capacitance (charge) between the node P (n) and the reference potential. Voltage conversion capacity) becomes the capacity CA (n), the capacitance value of the charge-voltage conversion capacity at the node P (n) becomes the minimum Cfd1 ′, and the charge-voltage conversion coefficient by the charge-voltage conversion capacity increases, so that the highest SN The ratio can be read out. Further, in this comparative example, if the number of on-state coupled transistors electrically connected to the node P (n) among the respective coupled transistors SWa and SWb is increased to one or more desired numbers, Since the capacitance value of the charge-voltage conversion capacitance of the node P (n) can be increased to a desired value and a large amount of signal charge can be handled, the number of saturated electrons can be increased. Thereby, the dynamic range can be expanded.

  As described above, the minimum capacitance value Cfd1 of the charge-voltage conversion capacitance of the first node Pa (n) in the present embodiment is the minimum capacitance value of the charge-voltage conversion capacitance of the node P (n) in this comparative example. It is smaller than Cfd1 ′ by two transistor diffusion capacitors. Therefore, according to the present embodiment, the charge-voltage conversion coefficient is further increased as compared with this comparative example, and reading at a higher SN ratio is possible.

  In the present embodiment, the second transistor SWB is provided between all the two second nodes Pb sequentially adjacent in the column direction. However, the present invention is not necessarily limited to this. For example, between r second nodes Pb arranged in the column direction (r is an integer of 2 or more) and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb, The second transistor SWB may be left open without being provided. In this case, the smaller the number of r, the smaller the maximum number of the predetermined number in the second operation mode and the degree of expansion of the dynamic range decreases. However, the SN at the time of high-sensitivity reading compared to the comparative example is reduced. The ratio can be improved. Further, for example, between s second nodes Pb arranged in the column direction (s is an integer of 1 or more) and a second node Pb adjacent to the second node Pb on the lower side in the figure. May be short-circuited electrically without providing the second transistor SWB. Further, for example, between u second nodes Pb arranged in the column direction (u is an integer of 1 or more) and a second node Pb adjacent to the second node Pb on the lower side in the figure. Only the second transistor SWB is provided, while the second node Pb other than u pieces arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb are provided. You may short-circuit electrically.

  In this embodiment, the capacitance value of the capacitor CD may be set to a value within a range of ± 20% with respect to the capacitance value of the capacitor CC by providing an adjustment capacitor in the wiring 72 or the like. The value may be within a range of ± 10% with respect to the capacitance value. These points are the same for the second embodiment described later.

  Each of the operation examples illustrated in FIGS. 6 to 10 is an example of an operation of reading the signal charge of the photodiode PD of each pixel PX without mixing with the signal charge of the photodiode PD of the other pixel PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed and read with the signal charge of the photodiode PD of another pixel PX of the same color.

  For example, the first transistor SWA (n−1), SWA (n), SWA (n + 1) and the second transistor SWB (n), SWB (n + 1) are turned on and the first node Pa (n−1) is turned on. , Pa (n), Pa (n + 1) are connected to each other, and TXA (n-1), TXA (n), TXA (n + 1) are turned on at the same time, the three of the same color in the case of assuming the Bayer arrangement etc. First signal charges of the photodiodes PDA (n−1), PDA (n), and PDA (n−1) of the pixels PXA (n−1), PXA (n), and PXA (n−1) are connected to each other. The nodes Pa (n−1), Pa (n), and Pa (n + 1) are averaged, and the same color three-pixel mixed readout function can be realized. At this time, the second transistors SWB (n−2) and SWB (n + 2) are turned off and are electrically connected to the first nodes Pa (n−1), Pa (n) and Pa (n + 1). The charge-voltage conversion capacitance value at the connected first nodes Pa (n−1), Pa (n), Pa (n + 1) by minimizing the number of first or second transistors in the ON state And the same color three-pixel mixed readout can be performed with the highest SN ratio. On the other hand, in addition to the first transistors SWA (n−1), SWA (n), SWA (n + 1) and the second transistors SWB (n), SWB (n + 1), each first transistor SWA and each second transistor If one or more of the transistors SWB are electrically connected to the first nodes Pa (n−1), Pa (n), Pa (n + 1), Depending on the number, the charge-voltage conversion capacitance value at the connected first nodes Pa (n−1), Pa (n), Pa (n + 1) increases, and the dynamic range of the same color three-pixel mixed readout is expanded. Can do.

[Second Embodiment]
FIG. 13 is a circuit diagram showing a schematic configuration of the solid-state imaging device 84 of the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. 13, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment is different from the first embodiment in that the photodiode PDB and the transfer transistor TXB are removed from each pixel block BL in the first embodiment. The pixel block BL is a pixel PXA. However, in the present embodiment, the density in the column direction of the photodiode PDA is double the density in the column direction of the photodiode PDA in the first embodiment, and the photodiode in the fourth embodiment is The density in the column direction of the entire PDA and PDB is the same. In the present embodiment, n indicates the row of the pixel block BL and simultaneously indicates the row of the pixel PXA.

  In other words, in the first embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is one. Pixel PX (PXA). In the first embodiment, two pixels PX (PXA, PXB) belonging to the pixel block BL share one set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. On the other hand, in the present embodiment, each pixel PX (in this embodiment, only PXA) has a set of first node Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL. doing.

  Basically, the description of the first embodiment is applicable as the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of this embodiment is omitted here.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained.

  As mentioned above, although each embodiment and modification of this invention were demonstrated, this invention is not limited to these.

4 solid-state imaging device BL pixel block PX pixel PD photodiode TXA, TXB transfer transistor Pa first node Pb second node AMP amplification transistor SWA first transistor SWB second transistor RST reset transistor (third transistor)

Claims (1)

A plurality of pixel blocks having one photoelectric conversion unit, a first node, and one transfer switch provided corresponding to the one photoelectric conversion unit and transferring charges from the photoelectric conversion unit to the first node When,
Two second nodes respectively corresponding to the first node of one of the pixel blocks and the first node of the other one of the pixel blocks;
Two firsts electrically connecting and disconnecting the first node of the one pixel block and the first node and the two second nodes of the other one pixel block, respectively. Switch part of
A second switch unit for electrically connecting and disconnecting the two second nodes;
Two third switch units for supplying predetermined potentials to the two second nodes,
A solid-state imaging device comprising:

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