JP2017216488A - Linear distortion improvement circuit of DAC - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that conversion error occurs due to mismatch of output resistance of a logic circuit, wiring resistance, or the resistance constituting a DAC, and the DAC generates linear distortion.SOLUTION: A DAC input is estimated by inputting a DAC input to simulated input multiple regression operation. The estimated DAC input is inputted to simulated DAC multiple regression operation, thus obtaining an estimate of DAC output. The DAC input is changed so that the DAC output estimate becomes a target value, and then the simulated input multiple regression operation and simulated DAC multiple regression operation are executed repeatedly. When the DAC output estimate satisfies the target value by this repetition, this input is employed as the input of the DAC thus improving distortion of the DAC.SELECTED DRAWING: Figure 1

Description

The present invention relates to a method for improving linear distortion of digital / analog conversion (hereinafter referred to as DAC).

DAC has conversion error due to mismatch of resistors that constitute DAC, output resistance and wiring resistance of logic circuit. DAC causes linear distortion (differential nonlinearity error (DNL), integral nonlinearity) due to this conversion error. (INL: Integral Nonlinearity). An example of a method for improving the linear distortion of a conventional DAC will be described. There is known a method of improving linear distortion by inputting a digital input to a DAC and a correction memory, conversion-corrected by a correction memory, and inputting a corrected value to the DAC (for example,
reference).

Further, as a method for improving the linear distortion of the DAC, the DAC output is converted from analog to digital (hereinafter referred to as ADC), the ADC output and the digital input are calculated, and the output of the DAC distortion storage using the calculated output and the digital input as an address. And a digital input are added and input to a DAC is known to improve linear distortion (for example,
reference).

As a method for improving the linear distortion of a similar DAC, a method is known in which an error is calculated from a simulated DAC multiple regression equation of a DAC and a target DAC, and the linear distortion is corrected by increasing / decreasing the DAC input by this error ( For example,
reference). Although this linear distortion correction is similar to the present invention, the difference from the present invention is that in the conventional invention, only the simulated DAC multiple regression equation is used and the simulated input multiple regression equation is not performed. Due to this difference, a large difference appears in the error between the actually measured value and the estimated value. Error pp of measured value and estimated value using simulated input multiple regression equation and simulated DAC multiple regression equation of the present invention pp = 10.82 uV, error of measured value and estimated value of simulated DAC multiple regression equation of conventional invention only pp = 7908.6 uV Thus, the error between the actually measured value and the estimated value of the present invention is improved 731 times compared to the conventional invention. FIG. 7 is a diagram of errors between actually measured values and estimated values of the present invention / conventional invention.

JP 2000-244317 (DA converter) JP-A-5-191280 JP 2013-118466 (DAC linear distortion correction circuit)

The cause of the linear distortion of the DAC may be the output resistance of the logic circuit, the mismatch of the resistance of the R-2R ladder 10, and the wiring resistance of the ladder. It is the output resistance of the logic circuit that most affects this linear distortion. FIG. 2 is a circuit diagram of a DAC (8-bit R-2R ladder type). The output resistance of the logic circuit 13 differs depending on the low level and the high level. The low level output resistance is 80Ω, and the high level output resistance is 100Ω. The switch S1 is a switch in which 80Ω is selected when the voltage AIN (0) of the power supply V0 is low level and 100Ω is selected when the voltage AIN (0) is high level. Similarly, the switches S2 to S8 are switches in which 80Ω is selected when the voltages AIN (1) to AIN (7) of the power sources V1 to V7 are at a low level, and 100Ω is selected when the voltages are at a high level.

V0 to V7 in FIG. 2 are power supplies that generate 0V and 3.3V, and the bias power supply 11 is −3.3V. Table 1 shows the relationship of the DAC output voltage OUTm (actually measured value) assuming that the voltages of the power sources V0 to V7 are AIN (0), AIN (1),..., AIN (7). Table 1 shows DAC input AIN and bit expanded voltage values AIN (0), AIN (1),..., AIN (7). The distortion in Equation 2 is a voltage value obtained by subtracting the DAC output OUTm (actually measured value) by the regression equation OUTg in Equation 1.

A regression equation OUTg between the DAC input AIN and the DAC output OUTm is shown in Equation 1. The regression coefficient is -0.0493811 (V / LSB), and the regression constant is 6.541027 (V). The calculation formula of the DAC output distortion is shown in Formula 2.

The IN and Y axes are DAC output distortion, and the scale interval of 0.04938 V corresponds to 1 LSB. The distortion is maximized at 127 to 128 when the MSB of the DAC input AIN is switched.

The present invention is intended to solve such conversion error (linear distortion) of the conventional DAC, and aims to improve the linear distortion of the DAC.

In order to achieve the above object, the present invention inputs the output AIN + E of the comparison operation 5 to the simulated input multiple regression equation operation 6 simulating the input / output of the DAC 1 including the logic circuit 13 of FIG. 0),... X (7)). This X is input to the simulated DAC multiple regression equation calculation 2, and an estimated value OUTe of the DAC output is calculated. The output AIN + E of the comparison operation 5 is corrected so that the estimated value OUTe becomes the target DAC output value OUTt of the target DAC operation 3 (Equation 3). This correction loop is performed a plurality of times so that the output E of the error calculation 4 is less than the allowable value. The linear distortion of the DAC 1 is improved by inputting the AIN + E below the allowable value to the DAC 1.

Table 2 shows the DAC input AIN, the actual output voltage Xm (0),... Xm (7) of the logic circuit 13 in FIG. 2, and the actual DAC output OUTm. The switches S1 to S8 are switches in which 80Ω is selected when the voltages AIN (0) to AIN (7) of the power sources V0 to V7 are low level, and 100Ω is selected when the voltages AIN (0) to AIN (7) are high level. The voltages Xm (0),... Xm (7) are connected to the input resistances R8 to R1 of the DAC1, and affect each other depending on the combination of the voltages AIN (0),. For example, when AIN = 0 and x (0) = 0.000V, when AIN = 2, Xm (0) is 20.8 mV. Thus, Xm (0) is affected by AIN (1) to AIN (7).

The simulated input multiple regression equation calculation 6 determines x (0) to x (7) from Equation 5 to Equation 12. In the simulated DAC multiple regression equation calculation 2, the values of x (0) to x (7) are input to Equation 13 to obtain the estimated DAC output OUTe.
Formula 4 is a multiple regression equation with x (1) to x (7) as explanatory variables and x (0) as an objective variable. x (0) has a low level and a high level, and a multiple regression equation of Formula 4 is created as x (0_0) and x (0_1), respectively.

Similarly, x (1) has a low level and a high level, and x (1_0) and x (1_1) are respectively made, and a multiple regression equation is made up to x (7_0) and x (7_1).

In the first line of Formula 5, when AIN (0) is 0.5 V or less, the second and third lines are the multiple regression equations of the low level of x (0), and the fifth and sixth lines are the high level of the regression of x (0). In the regression equation, x (0) to x (7) on the right side of the equation are replaced with AIN (0) to AIN (7) in order to simplify the calculation. Similarly, Equation 6 is a multiple regression equation of x (1), Equation 7 is x (2), and Equation 12 is x (7).

The simulated input multiple regression equation calculation 6 determines x (0) to x (7) in Equations 5 to 12, and the simulated DAC multiple regression equation calculation 2 inputs x (0) to x (7) into Equation 13, Obtain the DAC output OUTe estimate. The X axis in FIG. 4 is the DAC input AIN, and the Y axis is the error between the actual measurement value OUTm and the estimated value OUTe. The error between the actually measured value OUTm and the estimated value OUTe is 10.6 uV at the maximum, and the LSB of DAC1 is 49.4 mV, which is 1/46660 of 1LSB. The error between the actually measured value and the estimated value has a sufficient margin, and the accuracy is maintained even if the estimated value of Equation 13 is used instead of the actually measured value.

When the multiple regression equation OUTe of Equation 13 and the target DAC output OUTt of Equation 3 are compared and the difference is greater than or equal to the allowable value, the input AIN + E is input to Equations 5 to 12, and x (0) to x (7) obtain. The comparison between the estimated output OUTe of Expression 13 and the target DAC output OUTt of Expression 3 is repeated, and when this difference E is less than the allowable value, the input AIN + E is input to the DAC 1 to improve the distortion of the output of the DAC 1.

In the conventional DAC linear distortion correction, the DAC linear distortion is corrected with reference to the correction memory. However, in recent years, the number of bits has increased due to the higher accuracy of the DAC, and the capacity of the correction memory has increased. The time to write distortion correction data in the correction memory can no longer be ignored.

The present invention has the following effects. The output resistance of the logic circuit 13 fluctuates the inputs x (0), x (1),..., X (7) of the DAC 1 and greatly affects the linear distortion of the DAC. The fluctuations of the inputs x (0), x (1),..., X (7) are estimated from Expressions 5-12.

Input x (0) to x (7) of Expressions 5 to 12 to Expression 13 to calculate the estimated output OUTe of the DAC.

The difference between the calculated output OUTe and the DAC target output (Formula 3) OUTt (estimated output-target output) is set as error E, DAC input AIN + error E is converted to DAC input, and DAC input AIN + E is input into Formula 13 Then, the DAC estimation output is calculated again. This calculation is repeated until the error E becomes equal to or less than the allowable value A. Input AIN + E whose error is less than or equal to the allowable value to DAC1, and obtain a DAC output that is less than or equal to the allowable value of error.

By performing the correction according to the present invention, a highly accurate DAC can be easily obtained without adjusting the DAC ladder resistance, offset, and the like.

Block circuit of “DAC linear distortion improvement circuit” showing an embodiment of the present invention Circuit diagram of DAC (8-bit R-2R ladder type) DAC input vs. DAC output distortion Error between measured value and estimated value Number of corrections and distortion pp Distortion of DAC output before and after correction Error between measured and estimated values of the present invention / conventional invention

The DAC input AIN is input to the DAC target DAC calculation 3 in FIG. 1 to obtain the DAC output target value OUTt. In the first comparison operation 5, E = 0 is set, and the output AIN + E is AIN. In this AIN, x (0) to x (7) are determined by Equations 5 to 12 of the simulated input multiple regression equation 6. In the simulated DAC multiple regression equation calculation 2, the values of x (0) to x (7) are input to Equation 13 to obtain the estimated DAC output OUTe. The error calculation 4 calculates the difference E between OUTe and OUTt, and the comparison calculation 5 calculates AIN + E. If difference E and allowable value A are E> A, AIN + E is determined as x (0) to x (7) by simulated input multiple regression equation calculation 6, and simulated DAC multiple regression equation calculation 2 is x (0) to x (7 ) Is input to Equation 13 to obtain the first DAC output estimated value OUTe1. In error calculation 4, the difference E1 between OUTe1 and OUTt is calculated. In comparison operation 5, AIN + E1 is calculated. If difference E1 and allowable value A are E1> A, AIN + E1 is input to simulated input multiple regression equation 6, x (0) to x (7) is determined, and simulated DAC weight is determined. Input to the regression equation calculation 2 to obtain the second DAC output estimated value OUTe2. This is repeated until E ≦ A. When E ≦ A, AIN + E is input to the DAC 1 through the logic circuit 13 to obtain the DAC output OUT.

When the DAC input AIN = 125, the DAC output target value OUTt = 0.148138V is obtained by the target DAC calculation 3, and the DAC output estimated value OUTe1 = 0.271646V is obtained by the first simulated DAC multiple regression equation calculation 2. OUTe1-OUTt = 0.123508V, OUTe1-OUTt is input-converted (Equation 14) by error calculation 4, and E1 = 3 is obtained.

Since the allowable value A = 1 and the difference E1 and the allowable value A are E1> A, the comparison operation 5 inputs AIN + E1 = 128 to the simulated DAC multiple regression equation operation 2 to obtain the DAC output estimated value OUTe2 = 0.314285V. OUTe2-OUTt = 0.166147V, OUTe2-OUTt is input-converted by the error calculation 4 (Formula 14), and E2 = 3 is obtained.

Since the difference E2 and the allowable value A are E2> A, the comparison operation 5 inputs AIN + E1 + E2 = 131 to the simulated DAC multiple regression equation operation 2, and obtains the DAC output estimated value OUTe3 = 0.51628V.
OUTe3-OUTt = 0.00349V, and OUTe3-OUTt is input-converted (Equation 14) by error calculation 4 to obtain E3 = 0.

Since the difference E3 and the allowable value A are E3 ≦ A, the comparison operation 5 inputs AIN + E1 + E2 + E3 = 131 through the logic circuit 13 and inputs it to the DAC1, and outputs OUT = 0.151628V.

FIG. 5 shows the number of corrections and distortion pp (peak to peak). The X axis is the number of corrections, and the Y axis is the distortion pp. FIG. 3 shows the first correction, and the distortion pp is 200.5 mV. The distortion pp saturates to 57.8 mVpp or lower after the third correction (49.4 mV / LSB).

FIG. 6 shows the DAC1 output distortion before and after correction. The X axis is AIN, and the Y axis is strain (0.0247 V / div). The distortion before correction is gray and is 0.2005 Vpp (same as FIG. 3), and the distortion after correction is black and is improved to 0.0603 Vpp.

The input AIN + E of the simulated input multiple regression equation calculation 6 is bit-expanded, selects the low level and the high level, and calculates x (0) to x (7) (Equation 4 to Equation 12). When x (0) to x (7) voltage cannot be measured by DAC or the like, X = AIN is set, and the values of x (0) to x (7) are explanatory variables of “1” or “0”, DAC output OUTe Can be calculated as a simulated DAC calculation formula (Formula 13).

The present invention relates to a DA converter that converts a high-precision digital signal into an analog signal in the fields of communication equipment, measuring equipment, acoustic equipment, automatic test equipment, deflection systems for electron beam lithography equipment, and the like. This facilitates accuracy.

1 DAC
2 Simulated DAC multiple regression equation calculation 3 Target DAC calculation 4 Error calculation 5 Comparison calculation 6 Simulated input multiple regression equation calculation 10 R-2R ladder 11 Bias power supply 12 OP amplifier 13 Logic circuit

Claims (1)

In an N-bit DAC that receives a digital AIN {AIN (N−1),..., AIN (0)} (N: 0, 1,...) And outputs an analog value OUT,
Simulated input multiple regression equation computing means for simulating the voltage of AIN that fluctuates according to the input bit pattern with the formula of X {X (N−1),..., X (0)}, and computation of the simulated input multiple regression equation computing means Simulated DAC multiple regression equation calculation means for simulating the DAC output OUTe having X {X (N-1),..., X (0)} obtained in step S1 as an expression, the input AIN of the N-bit DAC and the target The target DAC calculating means in which the DAC output OUTt is expressed by OUTt = proportional coefficient * AIN, the subtracting means for subtracting the DAC output OUTe of the simulated DAC multiple regression equation calculating means and the target DAC calculating means output OUTt, and the subtracting means output E When the comparison means for comparing the allowable value with the subtracting means output E exceeds the allowable value,
The comparison means output AIN + E is input to the simulated input multiple regression equation calculating means, the output X is input to the simulated DAC multiple regression equation calculating means, and the output and the target DAC calculating means output are input to the subtracting means. When the output of the subtracting means is not more than the allowable value in the loop means and the loop means, the output of the comparing means is repeated to the N-bit DAC. A linear distortion improving circuit for DAC characterized by inputting AIN + E

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