TW201310918A - Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof - Google Patents

Abstract

A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method comprises the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of the capacitor-under-test according to the digital bits.

Description

Gradual approximation analog to digital converter and method for correcting capacitance mismatch

The present invention relates to a gradual approximation analog to digital converter, and more particularly to a gradual approximation analog to digital converter for a correction capacitor mismatch and a method thereof.

In integrated circuits, the matching of capacitance values is often an important design consideration. Such as analog to digital converter (ADC) and switch-capacitor circuit, it is possible to limit the performance of the circuit due to the capacitance mismatch caused by the process offset, thus causing the circuit to fail to function. The level of design.

Please refer to the first figure, which is a schematic diagram of a conventional octet approximation register ADC (SAR ADC). As shown in the first figure, the progressive approximation analog to digital converter 1 comprises two sets of symmetric digital to analog converters (DACs) 11, 13 respectively formed by a capacitor array (C7-C0). In operation, first, the comparator 15 samples and compares the differential input signals Vip, Vin, and the progressive approximation control logic (SAR) 17 switches the switches S _7p , S _7n according to the comparison result of the comparator 15 to control the capacitor C7. Contact potential. Due to the change of the contact potential, the two sets of digital to analog converters 11, 13 will generate a new potential, and the comparator 15 will sequentially compare the digits to the output of the analog converters 11, 13, by the progressive approximation control logic 17 Corresponding digits B1-B8 are parsed based on the comparison result of the comparator 15.

The resolved digit bit Bi will produce a digital output based on the capacitance Ci of the binary specific gravity. Please refer to the second A picture, taking the three-bit progressive approximation analog-to-digital converter as an example. Under the ideal capacitance pairing, the capacitor array C3-C0 has a binary weight, and its capacitance value should be 4C, 2C, respectively. C, C. After parsing the bit bits B3-B1, the digital output Dout can be generated by the formula (1).

Dout = 4*B3+2*B2+B1 ............ (1)

However, the process offset may cause the capacitance value of the capacitor C3 to be not equal to 4C, as shown in the second B diagram. Therefore, the output output calculated using the error weight is incorrect, which may cause the original system to fail to operate normally. In order to reduce the problem of capacitor mismatch, the capacitance value of the capacitor array is usually increased, but this consumes a lot of power and reduces the speed of the entire progressive approximation to the digital converter.

Therefore, for the integrated circuit design, it is urgent to propose a circuit that can compensate or correct the capacitance mismatch caused by the process offset under the use of a relatively small unit of capacitance, so that the design circuit is effective. Can and accuracy.

In view of the above, one of the objects of embodiments of the present invention is to provide a gradual approximation analog-to-digital converter capable of compensating or correcting for a capacitance mismatch caused by a process offset using a relatively small unit of capacitance. Make the design circuit use its original performance and precision.

The present invention discloses a progressive approximation analog to digital converter (SAR ADC) that corrects a capacitance mismatch, and includes a first digital to analog converter (DAC), a progressive approximation control logic (SAR), and a comparator. And a digital correction circuit. The first digit to analog converter includes a first capacitor array having a binary weight and at least two first compensation capacitors, wherein the first compensation capacitor is binary scaled. The gradual approximation control logic circuit is configured to select a capacitor from the first capacitor array as a capacitor-under-test, and then control a junction end of the first capacitor array and a junction potential of the first compensation capacitor end point. And generating a first comparison voltage of the first digit to the analog converter. The comparator is coupled between the first digit to the analog converter and the gradual approximation control logic circuit for outputting a comparison result according to the first comparison voltage and a second comparison voltage. The digital correction circuit is coupled to the gradual approximation control logic circuit. The progressive approximation control logic controls a series of comparisons according to the comparison result to output a series of corresponding digits. The digital correction circuit then calculates a correction value based on the digits to correct the capacitance of the capacitor to be tested.

The invention further discloses a capacitance mismatch correction method for a progressive approximation analog to digital converter comprising at least one capacitor array. The calibration method includes the following steps: first, configuring at least two compensation capacitors, and selecting a capacitor from the capacitor array as a capacitor-under-test; and then controlling a capacitor end point and a compensation capacitor of the capacitor array a contact potential of the terminal, and outputting a first comparison voltage according to the determined contact potential; thereafter, controlling a series of comparisons according to the first comparison voltage and a second comparison voltage to output a series of corresponding digits Finally, a correction value is calculated according to the digits to correct the capacitance of the capacitor to be tested.

First, please refer to the third figure, which is a circuit diagram of a gradual approximation analog-to-digital converter (SAR ADC) 3 for correcting a capacitance mismatch according to an embodiment of the present invention. As shown in the third figure, it includes a first digit to analog converter (DAC) 31, a second digit to analog converter 33, a comparator 35, a progressive approximation control logic (SAR) 37, and a Digital correction circuit 39. The first digit to analog converter 31 includes a first capacitor array C7-C0 and at least two first compensation capacitors C _2C , C _1C . Similarly, the second digit to analog converter 33 includes a second capacitor array (C7-C0) and at least two second compensation capacitors _C2C , _C1C . Ideally, the capacitance values of the first capacitor array C7-C0 and the second capacitor array C7-C0 are binary weights: C7=2C6=4C5=8C4=16C3=32C2=64C1=64C0.

The comparator 35 has a non-inverting (positive) input and an inverting input for receiving and comparing the output of the first digit to the analog converter 31 and the second digit to the analog converter 33, respectively. The gradual approximation control logic circuit 37 is used to control the capacitance end point of the capacitor array C7-C0 and the junction potential of the compensation capacitor C _2C and C _1C end points, and parse the corresponding digit according to the comparison result of the comparator 35. Bits B1-B8. The digital correction circuit 37 is coupled to the progressive approximation control circuit 37 for correcting and integrating the bit bits B1-BN to output a complete N-bit digital code (N is the resolution of the ADC).

In order to correct the capacitance mismatch, before the normal operation gradually approaches the analog to digital converter 3, the mechanism proposed by the present invention must be used to find the actual weight of the capacitor array C7-C0 so that the correct digital output can be resolved later. Please refer to the fourth figure. For convenience of description, the capacitance C3-C0 in the first digit to the analog converter 31 is taken as an example. In a specific example, the first compensation capacitors C _2C and C _1C may be disposed after the capacitor C0, and the capacitance values thereof are 2C and C. First, a capacitor to be measured, such as capacitor C3, must be determined first. Assuming that the actual capacitance of capacitor C3 has been shifted to 2.5C instead of ideal 4C, as shown in the fourth figure, the mechanism proposed by the present invention should be able to Correction.

In a sample phase, the progressive approximation control logic circuit 37 resets the first capacitor array C7-C0 and the first compensation capacitors C _2C and C _1C to a common mode voltage V _cm and is connected by The switch controls the capacitor (the capacitor to be tested) C3 is coupled to a positive reference voltage VR. The capacitance of the second digit to the analog converter 33, C7-C0 and the compensation capacitors _C2C , _C1C , operate symmetrically with the first digit to the analog converter 31, so the capacitance of the second digit to the analog converter 33 (capacitance to be measured) The C3 is controlled to be coupled to a negative reference voltage (-VR).

After completing the sampling phase, please refer to the fifth A-five F map, and then enter a series of comparison stages. In the first comparison phase, the gradually approaching control logic circuit 37 controls the capacitor C3 to be coupled to the common mode voltage _Vcm . Due to the change in junction potential, the redistributed charge produces a new potential (first comparison voltage Com_ip) at the non-inverting input of comparator 35. The first comparison voltage Com_ip at this stage is equal to 2.5C*(V _cm -VR)/C _tot . In short, the common mode voltage V _cm is set to a value of 0, and then the first comparison voltage Com_ip becomes -2.5C*VR/C _tot , where C _tot represents all capacitors C7-C0 and compensation capacitor C _2C , C _1C capacitance value. Since the current first comparison voltage Com_ip is a negative value (that is, the current first comparison voltage Com_ip is smaller than the comparison voltage of the inverting input terminal (second comparison voltage)), the comparison result output by the comparator 35 is logic 0. Wherein, the gradual approximation control logic circuit 37 also controls the second digit to the junction of the second capacitor array C7-C0 of the analog converter 33 and the junction potential of the compensation capacitors C _2C and C _1C to generate a second The second comparison voltage of the digital to analog converter 33. In the sampling phase and the successive comparison phase, the second digit to analog converter 33 operates symmetrically with the first digit to analog converter 31.

In order to control the difference between the first comparison voltage Com_ip and the second comparison voltage to gradually approach 0, the gradual approximation control logic circuit 37 sequentially controls the junction potential of the capacitor according to the comparison result of the previous stage. Therefore, when entering the second comparison phase, the gradually approaching control logic circuit 37 controls the capacitor C2 to be coupled to the positive reference voltage VR to increase the first comparison voltage Com_ip. The first comparison voltage Com_ip at this stage is equal to (-2.5C*VR+2*VR)/C _tot , during which the capacitance of the second digit to the analog converter 33 is controlled to be coupled to the negative reference voltage (-VR). And the second comparison voltage at the inverting input of comparator 35 will be equal to 0.5 C*VR/C _tot . Since the first comparison voltage Com_ip is currently a negative value (that is, the current first comparison voltage Com_ip is smaller than the comparison voltage of the inverting input terminal (second comparison voltage)), the comparison result output by the comparator 35 is logic 0, gradually approaching The value of the bit B1 parsed by the type control logic circuit 37 based on the comparison result is zero.

Then, entering the third comparison phase, since the first comparison voltage Com_ip of the upper stage is still negative, the gradually approaching control logic circuit 37 controls the capacitor C1 to be coupled to the positive reference voltage VR to increase the first comparison voltage Com_ip. The comparison first voltage Com_ip at this stage is equal to (-0.5C*VR+1*VR)/C _tot , during which the capacitance C1 of the second digit to the analog converter 33 is controlled to be coupled to the negative reference voltage (-VR). And the second comparison voltage at the inverting input of comparator 35 will be equal to -0.5C*VR/C _tot . The first comparison voltage Com_ip at this stage is a positive value (that is, the current first comparison voltage Com_ip is greater than the second comparison voltage of the inverting input terminal), so the comparison result output by the comparator 35 is logic 1, and the gradual approximation control The value of the bit B2 parsed by the logic circuit 37 is 1.

The first comparison voltage Com_ip of the previous stage is a positive value, so in the fourth comparison phase, the gradual approximation control logic circuit 37 controls the capacitor C0 to be coupled to the negative reference voltage VR to lower the comparison voltage first Com_ip. The first comparison voltage Com_ip at this stage is equal to (0.5C*VR-1*VR)/C _tot , during which the capacitance C0 of the second digit to the analog converter 33 is controlled to be coupled to the positive reference voltage VR, and the comparator 35 The second comparison voltage at the inverting input will be equal to 0.5C*VR/C _tot . The first comparison voltage Com_ip at this stage is a negative value (that is, the current first comparison voltage Com_ip is smaller than the second comparison voltage of the inverting input terminal), so the comparison result output by the comparator 35 is logic 0, and the gradual approximation control The value of the bit B3 parsed by the logic circuit 37 based on the comparison result is zero.

Similarly, in the fifth comparison phase, the gradual approximation control logic circuit 37 controls the compensation capacitor C _{2C to be} coupled to the positive reference voltage VR to increase the first comparison voltage Com_ip. The first comparison voltage Com_ip at this stage is equal to (-0.5C*VR+2*VR)/C _tot ), during which the compensation capacitance C _{2C of the} second digit to the analog converter 33 is controlled to be coupled to the negative reference voltage (- VR), and the second comparison voltage at the inverting input of comparator 35 will be equal to -1.5C*VR/C _tot . The third comparison voltage Com_ip at this stage is positive (that is, the current first comparison voltage Com_ip is greater than the second comparison voltage of the inverting input), so the comparison result of the comparator 35 output is logic 1, and the gradual approximation control The value of the bit B4 parsed by the logic circuit 37 is 1.

Finally, in the sixth comparison phase, the gradual approximation control logic circuit 37 controls the compensation capacitor C _{1C to be} coupled to the negative reference voltage VR to lower the first comparison voltage Com_ip. The first comparison voltage Com_ip at this stage is equal to (1.5C*VR-1*VR)/C _tot , during which the compensation capacitance C _{1C of the} second digit to analog converter 33 is controlled to be coupled to the positive reference voltage VR and compared The second comparison voltage at the inverting input of the device 35 will be equal to -0.5 C*VR/C _tot . The third comparison voltage Com_ip at this stage is positive (that is, the current first comparison voltage Com_ip is greater than the second comparison voltage of the inverting input), so the comparison result of the comparator 35 output is logic 1, and the gradual approximation control The value of the bit B5 parsed by the logic circuit 37 based on the comparison result is 1.

After a series of comparisons, the progressive approximation control logic circuit 37 parses a series of corresponding digits B5-B1, as shown in the sixth figure. The digital correction circuit 39 calculates a correction value (index) based on the following judgment formulas (2), (3) to correct the capacitance value of the capacitance C3.

If B4=B5=!B3e index=-(2*B1+B2) ...... (2)
If B1=B2=!B3e index=-(2*B4+B5) ...... (3)

The example proposed by the embodiment of the present invention conforms to the judgment rule (2), and thus the calculated correction value index is (-1). The digital correction circuit 39 adds the ideal capacitance value (= 4C) of the capacitor C3 to the correction value index (= -1 C) to obtain the actual (or estimated) capacitance value of the capacitor C3 (4C - 1 C = 3 C). In this way, the digital correction circuit 39 can multiply the analyzed digital bit Bi by the weight of the corrected capacitance by using equation (4) to generate the digital output Dout. It is worth mentioning that in some cases, the corrected capacitance value will have an error of 0.5C with the actual capacitance value, but overall the accuracy of the circuit is improved.

Dout=3*B3+2*B2+B1 ...... (4)

After correcting the capacitance value of the capacitor C3, the above calibration step can be repeated to correct the capacitor C4, so that the capacitance of the smaller capacitance value is sequentially corrected to the capacitance of the larger capacitance value until all the capacitors are corrected, so as to obtain each The correction value of the capacitor. The corrected value of the capacitor is used to obtain the actual weight of the capacitor itself. Therefore, the digital correction circuit can obtain a more accurate digital output Dout according to the actual weight (capacitance value) of the corresponding capacitor. In practice, the correction mechanism is performed before the analogy to digital converter 3 converts the analog signal to a digital code.

In a specific embodiment, the compensation capacitors C _2C and C _1C are binary scaled, and the more the compensation capacitors C _2C and C _1C are, the larger the correction range of the capacitor to be tested is. For example, if two compensation capacitors are set, the correction value index ranges from -4 to 4; and if five compensation capacitors are set, the correction value index ranges from –(2 ⁵ -1)to to (2 ⁵ Between -1), and so on.

Finally, please refer to the seventh figure, which is a flowchart of the capacitor mismatch correction method according to an embodiment of the present invention. It should be noted that, for the sake of streamlining the description, the seventh figure only shows the operation flow of the first digit to analog converter 31, and the second digit to analog converter 33 is symmetric with the first digit to analog converter 31 as described above. Operation. The method is for the gradual approximation analog to digital converter 3 of the third figure, which additionally adds compensation capacitors C _2C , C _1C after the capacitor array C7-C0.

First, in step S701, the first capacitor to be tested, such as capacitor C3, to be corrected is determined from the capacitor array C7-C0. Then, entering the sampling phase, the gradually approaching control logic circuit 37 resets the capacitor array C7-C0 and the compensation capacitors C _2C and C _1C to the common mode voltage V _cm , and controls the capacitance to be tested to be coupled to the positive reference voltage VR (step S703). ). Then, in step S705, a series of comparison stages is entered, wherein, in the first comparison phase, the gradual approximation control logic circuit 37 controls the capacitance to be tested to be coupled to the common mode voltage _Vcm , and the digital to analog converter 31 is The determined contact potential outputs the first comparison voltage Com_ip (step S707).

In step S709, the comparator 35 determines whether the first comparison voltage Com_ip is a positive value, and if so, the output comparison result is logic 1, and the gradual approximation control logic circuit 37 controls the next capacitor (C2) of the capacitor to be tested to be coupled to A positive reference voltage (step S711). If the comparator 35 determines that the first comparison voltage Com_ip is a negative value, the output comparison result is logic 0, and the gradual approximation control logic circuit 37 controls the next capacitor (C2) to be coupled to the negative reference voltage (-VR) (step S713).

In step S715, it is judged whether or not all comparison phases have been completed. If no, the process returns to step S707 to continue the comparison. If a series of comparison phases have been completed, the progressive approximation control logic circuit 37 outputs the corresponding digit bits B1-B5 based on the comparison result each time (step S717). In step S719, the digit correction circuit 39 calculates the correction value index for correcting the capacitance value of the capacitance to be measured by using the parsed digits B1-B5 according to the equations (2) and (3).

In step S721, it is determined whether all capacitors having a larger capacitance value than the first capacitor to be tested are corrected. If not, in step S723, the next capacitor to be tested (ie, C4) is selected, and the process returns to step S703, and the above-mentioned correction operation is repeated until all the capacitors are corrected. When all the capacitors are corrected, in step S725, the digit correction circuit 39 adds the capacitance value of each capacitor to be tested to the corresponding correction value index to obtain the weight of each capacitor to be tested. Finally, in step S727, the digit correction circuit 39 multiplies the parsed digits B1-BN by the weight of the corrected capacitance to obtain the digit output Dout during the analog/digital conversion.

According to the above embodiment, the calibration capacitor mismatching gradually approximating the analog-to-digital converter and the method thereof are based on adding a small capacitance value compensation capacitor to the digital-to-analog converter, and using the mechanism proposed by the present invention. Find the actual weight of the capacitor array, and then compensate or correct the capacitance mismatch caused by the process offset, and make the design circuit play the original performance and accuracy.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

Conventional knowledge

1. . . Gradually approximating analog to digital converters

11. . . First digit to analog converter

13. . . Second digit to analog converter

C7-C0. . . Capacitor array

VR. . . Positive reference voltage

Vcm. . . Common mode voltage

15. . . Comparators

17. . . Gradual approximation control logic

B1-B8. . . Digit

S _7p , S _6p , S _5p , S _4p , S _3p , S _2p , S _1p , S _0p . . . switch

S _7n , S _6n , S _5n , S _4n , S _3n , S _2n , S _1n , S _0n . . . switch

this invention

3. . . Gradually approximating analog to digital converters

31. . . First digit to analog converter

33. . . Second digit to analog converter

C7-C0. . . Capacitor array

C _2C , C _1C . . . Compensation capacitor

VR. . . Positive reference voltage

Vcm. . . Common mode voltage

35. . . Comparators

37. . . Gradual approximation control logic

39. . . Digital correction circuit

B1-B8. . . Digit

Dout. . . Digital output

S _7p , S _6p , S _5p , S _4p , S _3p , S _2p , S _1p , S _0p . . . switch

S _7n , S _6n , S _5n , S _4n , S _3n , S _2n , S _1n , S _0n . . . switch

S701-S727. . . step

The first figure is a schematic diagram of a conventional octet gradual approximation analog to digital converter (SAR ADC).
The second A diagram is a circuit diagram of a conventional capacitor array with ideal capacitance pairing.
The second B diagram is a circuit diagram of a capacitor array in which the conventional capacitors are not paired.
The third figure is a circuit diagram of a gradual approximation analog to digital converter of a correction capacitor mismatch according to an embodiment of the present invention.
The fourth figure is a schematic diagram of the operation of the progressive approximation analog capacitor to the digital converter in the sampling phase according to an embodiment of the present invention.
The fifth to fifth F diagrams are schematic diagrams of the operation of the gradual approximation analog-to-digital converter of the correction capacitor mismatch in the comparison phase according to an embodiment of the present invention.
The sixth graph shows the resolved digits.
FIG. 7 is a flow chart showing a method for correcting a capacitance mismatch according to an embodiment of the present invention.

3. . . Gradually approximating analog to digital converters

31. . . First digit to analog converter

33. . . Second digit to analog converter

C7-C0. . . Capacitor array

C _2C , C _1C . . . Compensation capacitor

VR. . . Positive reference voltage

Vcm. . . Common mode voltage

35. . . Comparators

37. . . Gradual approximation control logic

39. . . Digital correction circuit

B1-B8. . . Digit

Dout. . . Digital output

S _7p , S _6p , S _5p , S _4p , S _3p , S _2p , S _1p , S _0p . . . switch

S _7n , S _6n , S _5n , S _4n , S _3n , S _2n , S _1n , S _0n . . . switch

Claims (15)

A gradual approximation analog-to-digital converter (SAR ADC) that corrects for capacitor mismatch and includes:
a first digital to analog converter (DAC) comprising a first capacitor array and at least two first compensation capacitors, wherein the capacitance value of the first capacitor array has a binary weight, and the first compensation capacitors Binary scaled;
a progressive approximation control logic (SAR) for selecting a capacitor from the first capacitor array as a capacitor-under-test, and then controlling a capacitance end point of the first capacitor array and the a first compensation capacitor terminal contact potential, and accordingly generating the first digit to a first comparison voltage of the analog converter;
a comparator coupled between the first digit to the analog converter and the progressive approximation control logic circuit, the comparator outputting a comparison result according to the first comparison voltage and a second comparison voltage; and a digital correction a circuit coupled to the gradual approximation control logic circuit;
The progressive approximation control logic circuit controls a series of comparisons according to the comparison result to output a series of corresponding digits, and the digit correction circuit calculates a correction value according to the digits to correct the to-be-corrected Measure the capacitance of the capacitor.

A progressive approximation analog to digital converter of a correction capacitor mismatch as described in claim 1 wherein the gradual approximation control logic resets the first capacitor array and the sample phase The first compensation capacitor is a common mode voltage, and the capacitor to be tested is coupled to a first reference voltage.

The gradual approximation analog to digital converter of the correction capacitor mismatch according to claim 2, wherein the gradual approximation control logic controls the junction potential of the capacitor according to the comparison result in a series of comparison phases, The gap between the first comparison voltage and the second comparison voltage is controlled to gradually approach zero.

A progressive approximation analog to digital converter of a correction capacitor mismatch as described in claim 3, wherein the gradual approximation control logic controls the comparison based on the comparison output of the comparator during the series of comparison phases A capacitor is coupled to the first reference voltage or a second reference voltage.

The gradual approximation analog-to-digital converter of the correction capacitor mismatch as described in claim 4, wherein the gradual approximation control logic circuit controls the capacitance to be tested to be coupled to the common mode during the first comparison phase Voltage.

The gradual approximation analog to the digital converter of the correction capacitor mismatch as described in claim 5, wherein the digital correction circuit determines that if B4=B5=!B3, the correction value is calculated=-(2*B1+B2 And, if it is judged that B1 = B2 = ! B3, the correction value = (2 * B4 + B5) is calculated, where B1 - B5 are the digits.

The gradual approximation analog to digital converter of the correction capacitor mismatch according to claim 6 of the patent application scope, wherein the digital correction circuit adds the ideal capacitance value of the capacitor to be tested to the correction value to obtain the capacitance value of the capacitor to be tested. The weight.

The gradual approximation analog to digital converter of the correction capacitor mismatch as described in claim 7 is corrected from the capacitance of the smaller capacitance value to the capacitance of the larger capacitance value, and the digital correction circuit will These digits are multiplied by the weight of each corrected capacitance to obtain a digital output during the analog/digital conversion.

The gradual approximation analog-to-digital converter of the correction capacitor mismatch as described in claim 3 of the patent application includes:
a second digit to analog converter (DAC), comprising a second capacitor array and at least two second compensation capacitors, wherein the capacitance value of the second capacitor array has a binary weight;
The gradual approximation control logic circuit controls a junction end of the capacitance end of the second capacitor array and the second compensation capacitor end point, and accordingly generates the second comparison of the second digit to the analog converter The voltage, and during the sampling phase and the series of comparison phases, the second digit to analog converter operates symmetrically with the first digit to analog converter.

A capacitance mismatch correction method for gradually approximating an analog to digital converter, the gradual approximation analog to digital converter comprising at least one capacitor array, the method comprising:
Forming at least two compensation capacitors;
Selecting a capacitor from the capacitor array as a capacitor-under-test;
Controlling a capacitance end of the capacitor array and a junction potential of the compensation capacitor terminals;
Outputting a first comparison voltage according to the determined contact potential;
Outputting a comparison result according to the first comparison voltage and a second comparison voltage;
Controlling a series of comparisons according to the comparison result to output a series of corresponding digits; and calculating a correction value according to the digits to correct the capacitance of the capacitor to be tested.

The method for correcting a capacitance mismatch according to claim 10, wherein the step of controlling the potential of the contact comprises:
During a sampling phase, the capacitor array and the compensation capacitors are reset to a common mode voltage, and the capacitor to be tested is coupled to a first reference voltage; and in a series of comparison stages, the capacitor is controlled according to the comparison result. The junction potential is controlled to gradually approach the difference between the first comparison voltage and the second comparison voltage.

The capacitor mismatch correction method according to claim 11, wherein the step of outputting the comparison result according to the first comparison voltage and the second comparison voltage includes:
Determining that if the first comparison voltage is greater than the second comparison voltage, the comparison result of the output is logic 1; and determining that if the first comparison voltage is less than the second comparison voltage, the comparison result of the output is logic 0.

The method for correcting a capacitance mismatch according to claim 12, wherein the step of controlling the series of comparisons comprises:
Controlling, according to the comparison result, a next capacitor of the capacitor to be tested is coupled to the first reference voltage or a second reference voltage;

The capacitor mismatch correction method according to claim 13, wherein the step of calculating the correction value includes:
If it is judged that B4=B5=!B3, the correction value is calculated=-(2*B1+B2);
Determining if the B1=B2=!B3, calculating the correction value=(2*B4+B5); and adding the ideal capacitance value of the capacitance to be tested to the correction value to obtain the weight of the capacitance to be tested;
Where B1-B5 are the digits.

The capacitor mismatch correction method described in claim 14 of the patent application scope further includes:
The capacitance from the smaller capacitance value is sequentially corrected to the capacitance of the larger capacitance value; and the digits are multiplied by the weight of each corrected capacitance to obtain a digital output.