CN111064468B - Calibration method and calibration system - Google Patents
Calibration method and calibration system Download PDFInfo
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- CN111064468B CN111064468B CN201811206734.XA CN201811206734A CN111064468B CN 111064468 B CN111064468 B CN 111064468B CN 201811206734 A CN201811206734 A CN 201811206734A CN 111064468 B CN111064468 B CN 111064468B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Abstract
A calibration method and a calibration system are provided, the calibration method is suitable for a successive approximation type analog-digital converter, and the successive approximation type analog-digital converter comprises a capacitor array. The calibration method comprises the following procedures: inputting an input signal to an analog-to-digital converter, wherein the analog-to-digital converter generates an output signal according to the input signal, and the output signal comprises a plurality of specific digital codes; calculating an average code density of each of a plurality of digital code groups in the plurality of specific digital codes, wherein each digital code group comprises one or more specific digital codes in the plurality of specific digital codes; comparing the average code density of a first target group in the plurality of digital code groups with a first reference code density to generate a first comparison result; and calibrating the capacitance value of a first capacitor unit to be calibrated of the capacitor array according to the first comparison result. The calibration method can be used for calibrating the successive approximation type analog-digital converter in real time.
Description
Technical Field
The present disclosure relates to a calibration method, and more particularly, to a calibration method for calibrating an output error of a successive approximation analog-to-digital converter.
Background
A successive approximation analog-to-digital converter (SAR ADC) has the characteristics of low power consumption and small size, and is therefore widely applied to present electronic products. Successive approximation analog-to-digital converters sample and successively approximate input signals by using a capacitor array, wherein the capacitance value of each capacitor of the capacitor array needs to be accurately arranged according to the power of 2 raised. For example, the capacitance values of the capacitor array of a 4-bit successive approximation analog-to-digital converter are 8C, 4C, 2C and 1C in this order. If the capacitance of the capacitor array of the successive approximation analog-to-digital converter has an error due to the manufacturing process factor, the capacitance will inevitably lead to an erroneous output result.
Disclosure of Invention
Therefore, it is an objective of the present invention to provide a calibration method and a calibration system for calibrating an output error of a successive approximation analog-to-digital converter in real time.
The present disclosure provides a calibration method. The calibration method is suitable for a successive approximation type analog-digital converter, and the successive approximation type analog-digital converter comprises a capacitor array. The calibration method comprises the following procedures: inputting an input signal to an analog-to-digital converter, wherein the analog-to-digital converter generates an output signal according to the input signal, and the output signal comprises a plurality of digital codes; calculating an average code density of each of a plurality of digital code groups in the plurality of specific digital codes, wherein each digital code group comprises one or more specific digital codes in the plurality of specific digital codes; comparing the average code density of a first target group in the plurality of digital code groups with a first reference code density to generate a first comparison result; and calibrating the capacitance value of a first capacitor unit to be calibrated of the capacitor array according to the first comparison result.
In some embodiments, calculating the average code density of each of the plurality of digital code groups in the plurality of specific digital codes comprises the following steps: calculating the occurrence times of a first digital code group in the specific digital codes in the output signal to obtain a first accumulated time; calculating a first average code density of the first digital code group corresponding to the output signal according to the first accumulated times; calculating the occurrence times of a second digital code group in the plurality of digital codes in the output signal to obtain a second accumulated time; and calculating a second average code density of the second digital code group corresponding to the output signal according to the second accumulated times.
In some embodiments, the capacitance of the first capacitor to be calibrated is decreased when the average code density of the first target group is greater than the first reference code density, and the capacitance of the first capacitor to be calibrated is increased when the average code density of the first target group is less than the first reference code density.
In some embodiments, the calibration method further comprises the following steps: the average code density of a second target group in the plurality of digital code groups is compared with a second reference code density to generate a second comparison result. The process of calibrating the capacitance value of the first to-be-calibrated capacitor unit of the capacitor array according to the first comparison result comprises the following steps: when the capacitance value of the first capacitor unit to be calibrated is calibrated, the capacitance value of a second capacitor unit to be calibrated of the capacitor array is calibrated according to the second comparison result, wherein when the average code density of the second target group is greater than the second reference code density, the capacitance value of the second capacitor unit to be calibrated is reduced, and when the average code density of the second target group is less than the second reference code density, the capacitance value of the second capacitor unit to be calibrated is increased.
In some embodiments, the first to-be-calibrated capacitor unit includes a main capacitor, a first sub-capacitor and a second sub-capacitor, the first sub-capacitor is coupled to the main capacitor in parallel, and the process of calibrating the capacitance value of the first to-be-calibrated capacitor unit of the capacitor array according to the first comparison result further includes: disconnecting the parallel connection between the first sub-capacitor and the main capacitor when the average code density of the first target group is greater than the reference code density; when the average code density of the first target group is smaller than the reference code density, the second sub-capacitor is coupled to the main capacitor in parallel.
In some embodiments, the specific digital codes are distributed within a range of values, and comparing the average code density of the first target group of the specific digital codes with the reference code density comprises: when the first target group is selected, selecting other digital code groups adjacent to the first target group from the plurality of digital code groups according to the position of the first target group in the numerical range; average the code density of other digital code groups to obtain the reference code density.
In some embodiments, the process of calibrating the capacitance value of the first to-be-calibrated capacitor unit of the capacitor array according to the first comparison result further includes: dividing the numerical range into equal parts according to the power of raising power of 2 to obtain a plurality of binary equal division points; judging a first equally dividing point of a plurality of binary equally dividing points which are most similar to the position of the first target group in the numerical range; and selecting one of the M capacitor units as a first capacitor unit to be calibrated according to the power of 2 corresponding to the first equivalence point.
The present disclosure provides a calibration system. The calibration system comprises a continuous approximation analog-to-digital converter, a code density calculation module, a code density detection module and a capacitance calibration module. The successive approximation type analog-digital converter comprises a capacitor array used for generating an output signal according to an input signal, wherein the output signal comprises a plurality of specific digital codes. The code density calculation module is used for receiving the output signal and calculating the average code density of each of a plurality of digital code groups in a plurality of specific digital codes, wherein each digital code group comprises one or more specific digital codes in the plurality of specific digital codes. The code density detection module is used for comparing the average code density of a first target group in a plurality of digital code groups with a first reference code density and outputting a first comparison result. The capacitance calibration module is coupled to the capacitor array and used for calibrating a capacitance value of a first to-be-calibrated capacitor unit of the capacitor array according to the first comparison result.
In some embodiments, the code density calculation module performs the following operations to calculate the average code density of each of the plurality of digital code groups: calculating the occurrence times of a first digital code group in the plurality of digital codes in the output signal to obtain a first accumulated time; calculating a first average code density of the first digital code group corresponding to the output signal according to the first accumulated times; calculating the occurrence times of a second digital code group in the plurality of digital codes in the output signal to obtain a second accumulated time; and calculating a second average code density of the second digital code group corresponding to the output signal according to the second accumulated times.
In some embodiments, the capacitance calibration module decreases the capacitance of the first to-be-calibrated capacitor unit when the average code density of the first target group is greater than the first reference code density, and increases the capacitance of the first to-be-calibrated capacitor unit when the average code density of the first target group is less than the first reference code density.
In some embodiments, the code density detection module is configured to compare an average code density of a second target group of the plurality of digital code groups with a second reference code density and output a second comparison result, wherein when the capacitance calibration module calibrates the capacitance of the first to-be-calibrated capacitor unit according to the first comparison result, the capacitance calibration module calibrates the capacitance of a second to-be-calibrated capacitor unit of the capacitor array according to the second comparison result, when the average code density of the second target group is greater than the second reference code density, the capacitance calibration module decreases the capacitance of the second to-be-calibrated capacitor unit, and when the average code density of the second target group is less than the second reference code density, the capacitance calibration module increases the capacitance of the second to-be-calibrated capacitor unit.
In some embodiments, the first capacitor unit to be calibrated includes a main capacitor, a first sub-capacitor and a second sub-capacitor. The first sub-capacitor is coupled to the main capacitor in parallel, when the average code density of the first target group is greater than the reference code density, the capacitor calibration module disconnects the parallel connection between the first sub-capacitor and the main capacitor, and when the average code density of the first target group is less than the reference code density, the capacitor calibration module couples the second sub-capacitor to the main capacitor in parallel.
In some embodiments, the plurality of digital codes are distributed in a value range, when the first target group is selected, the code density detection module selects other digital code groups adjacent to the first target group from the plurality of digital code groups according to the position of the first target group in the value range, and the code density detection module averages the average code densities of the other digital code groups to obtain the reference code density.
In some embodiments, the capacitor array includes M capacitor cells, where M is a positive integer. The capacitance calibration module stores a plurality of binary equally-divided points, the numerical range of which is obtained by sequentially equally dividing according to the power of 2, judges a first equally-divided point of the plurality of binary equally-divided points which is closest to the first target group in position in the numerical range, and selects one of the M capacitance units as a capacitance unit to be calibrated according to the power of 2 corresponding to the first equally-divided point.
The calibration method and the calibration system can be used for calibrating the successive approximation type analog-digital converter in real time.
Drawings
These and other objects, features, advantages and embodiments of the disclosure will become more apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings:
FIG. 1 is a simplified functional block diagram of a calibration system according to an embodiment of the present disclosure;
FIGS. 2 (a) -2 (b) are simplified flow charts of a calibration method according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of output signals according to an embodiment of the present disclosure;
FIGS. 4 (a) -4 (b) are mean code density distribution histograms according to an embodiment of the present disclosure;
fig. 5 is a simplified schematic diagram of the capacitor unit in fig. 1 according to an embodiment of the disclosure.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.
FIG. 1 is a simplified functional block diagram of a calibration system 100 according to an embodiment of the present disclosure. The calibration system 100 includes a successive approximation analog-to-digital converter 110, a code density calculation module 120, a code density detection module 130, and a capacitance calibration module 140. The code density calculation module 120 and the capacitance calibration module 140 are coupled to the successive approximation analog-to-digital converter 110, and the code density detection module 130 is coupled between the code density calculation module 120 and the capacitance calibration module 140. For simplicity and ease of illustration, other elements and connections in the calibration system 100 are not shown in fig. 1.
The successive approximation adc 110 includes a capacitor array 112, a comparator 114 and a successive approximation logic 116, wherein the capacitor array 112 is coupled to the capacitor calibration module 140. The capacitor array 112 includes M capacitor units 118-1-118-M, each of the capacitor units 118-1-118-M has a different capacitance, and M is a positive integer. Each of the capacitor units 118-1-118-M may be selectively coupled to an input signal Vin, a reference voltage Vref, or a ground.
In other words, successive approximation adc 110 is an M-bit adc. By the cooperation of the capacitor array 112 and the comparator 114, the input signal Vin can be sampled and continuously approximated. The successive approximation logic 116 outputs an output signal Vout corresponding to the magnitude of the input signal Vin according to the successive approximation result.
The indices 1 to M in the element numbers and device numbers used in the present specification and drawings are only for convenience of referring to individual elements and signals, and are not intended to limit the number of the aforementioned elements and signals to a specific number. In the present specification and drawings, if an element number and a device number are used without specifying an index of the element number and the device number, the element number and the device number are referred to as any unspecified element or device in the element group and the device group. For example, element number 118-1 refers to the object being capacitive unit 118-1, and element number 118 refers to the object being any capacitive unit 118 not specifically identified among capacitive units 118-1-118-M.
It is worth mentioning that the output signal Vout comprises a plurality of digital codes (digital codes). For example, in some embodiments where successive approximation ADC 110 is a 4-bit ADC, output signal Vout may comprise up to 2 4 Digital codes (e.g., digital codes 0000 to 1111). Therefore, in the case where the successive approximation analog-to-digital converter 110 is M bits, the output signal Vout may include values 0 to (2) corresponding to decimal digits at most M 2 of-1) M A binary digital code.
The code density calculating module 120 is configured to receive the output signal Vout and calculate a code density (code density) of a plurality of specific digital codes of the output signal Vout. The code density detection module 130 is configured to select one or more digital codes from a plurality of specific digital codes as a target group, compare the average code density of the target group with a reference code density, and output the comparison result to the capacitance calibration module 140.
If there is a deviation between the average code density of the target group and the reference code density, and the deviation exceeds a predetermined deviation, it represents that the capacitance values of the plurality of capacitor units 118 in the capacitor array 112 are different from the design expected values, or that some elements in the successive approximation analog-to-digital converter 110 have characteristic variations due to various factors during operation. At this time, the capacitance calibration module 140 may select the corresponding capacitor unit 118 of the capacitor array 112 for calibration according to the selected target group and the corresponding offset value.
Fig. 2 (a) -2 (b) are simplified flow charts of a calibration method 200 according to an embodiment of the present disclosure. The calibration system 100 can be used to perform the calibration method 200 to calibrate the successive approximation adc 110, and the operation of the calibration system 100 will be further described with reference to fig. 1 and fig. 2 (a) -2 (b). In the flowcharts shown in fig. 2 (a) -2 (b), the flow in the column to which a specific device belongs represents the flow performed by the specific device. For example, the flow marked in the "successive approximation adc" field represents the flow performed by the successive approximation adc 110; the process marked in the column of code density detection module represents the process performed by the code density detection module 130.
In process S202, successive approximation analog-to-digital converter 110 receives input signal Vin with capacitor array 112. Then, in the process 204, the successive approximation adc 110 performs successive approximation on the input signal Vin by using the capacitor array 112 and the comparator 114, generates an output signal Vout by using the successive approximation logic 116 according to the successive approximation result, and transmits the output signal Vout to the code density calculating module 120.
In the present embodiment, the input signal Vin is a voltage or current signal conforming to the Full Scale Range (FSR) of the successive approximation adc 110. For example, the input signal Vin may be a ramp (ramp) signal or a sine wave (sine wave) signal.
In the process S206, the code density calculating module 120 accumulates the total number of occurrences of each of the plurality of digital code groups in the plurality of specific digital codes in the output signal Vout for a predetermined time period according to the received output signal Vout.
For example, in the case where the successive approximation adc 110 is a 4-bit adc and the input signal Vin is a ramp signal, the output signal Vout is as shown in fig. 3, and the specific digital codes of the output signal Vout are the digital codes 0001 to 1100. The code density calculation module 120 can calculate the total number of occurrences (e.g., 16) of a first group of digital codes (e.g., the digital codes 0001 to 0100) in the specific digital codes in a predetermined time period to obtain a first cumulative number. Then, the code density calculation module 120 may calculate the total number of occurrences (e.g., 15) of the second group of digital codes (e.g., the digital codes 0101-1000) in the plurality of specific digital codes within the same predetermined time period to obtain a second cumulative number. Furthermore, the code density calculation module 120 may calculate the total number of occurrences (e.g., 16) of a third group of digital codes (e.g., the digital codes 1001-1100) in the plurality of specific digital codes within the same predetermined time period to obtain a third cumulative number, and so on. Each digital code group may include one or more digital codes.
In the process S208, the code density calculating module 120 calculates the average code density of each digital code group according to the total occurrence number of each digital code group. For example, the average code density of the first digital code group is 4, and the average code density of the second digital code group is 3.75.
If the input signal Vin is a ramp signal, the average code density calculated by the code density calculating module 120 is in a flat distribution as shown in fig. 4 (a). If the input signal Vin is a sine wave signal, the average code density calculated by the code density calculating module 120 shows bathtub (bathtub) distribution as shown in fig. 4 (b).
In the process S210, the code density detection module 130 selects one of the plurality of digital code groups as the target group (e.g., selects one of the first digital code group, the second digital code group, and the third digital code group). In addition, the code density detection module 130 calculates the reference code density and the predetermined offset value according to other digital code groups (e.g., according to the remaining two of the first digital code group, the second digital code group, and the third digital code group).
Specifically, the digital codes of the successive approximation analog-to-digital converter 110 are distributed within a range of values. For example, as shown in fig. 3, in some embodiments where the successive approximation adc 110 is a 4-bit adc, the digital codes are distributed in the range of 0000 to 1111. Therefore, in the case of M-bit ADC 110, the digital codes are distributed over the values 0 to (2) corresponding to decimal digits M -1) in a binary range of values. The code density detection module 130 calculates the reference code density and the predetermined offset value according to the position of the target group in the value range.
In the embodiment where the input signal Vin is a ramp signal, when the target group (e.g., the second digital code group 0101 to 1000) is selected, the code density detection module 130 selects other digital code groups (e.g., the first digital code group 0001 to 0100 and the third digital code group 1001 to 1100) adjacent to the target group according to the position of the target group in the value range. Then, the code density detection module 130 averages the average code densities of the selected other digital code groups again to calculate the reference code density. Then, the code density detection module 130 divides the obtained reference code density by 2 to calculate a predetermined offset value.
In the embodiment where the input signal Vin is a sine wave signal, the reference code density is calculated in a similar manner to the embodiment where the input signal Vin is a ramp signal, except that the code density detection module 130 determines the offset value according to the position of the target group in the value range. If the target group is located in the middle of the range (e.g., the range 0000 to 1111, the range 0101 to 1011), the code density detection module 130 divides the obtained reference code density by two to obtain the predetermined offset value. On the other hand, if the target group is located at the edge of the range (e.g., the range 0000 to 1111, the range 0001 to 0010, or the range 1100 to 1111), the code density detection module 130 divides the obtained reference code density by two thirds to obtain a larger predetermined deviation value, so as to respond to the situation that the code density on both sides of the bathtub distribution is changed to a larger degree.
In the process S212, the code density detection module 130 compares the average code density of the target group with the reference code density. If the absolute value of the deviation between the average code density of the target group and the reference code density is greater than the predetermined deviation, the code density detection module 130 determines that the code density of the target group is abnormal. If the absolute value of the deviation between the average code density of the target group and the reference code density is not greater than the predetermined deviation, the code density detection module 130 determines that the code density of the target group is normal.
The operations of the aforementioned steps S210-S212 will be further described with reference to several embodiments. Referring to fig. 3, in one embodiment, the specific digital codes include digital codes 0000 through 1100, wherein the target group includes digital codes 0101 through 1000, assuming that the average code density of the target group is 3.75. Moreover, the code density detection module 130 may calculate the reference code density and the predetermined offset value by using two digital code groups (e.g., including the digital codes 0001 to 0100 and 1001 to 1100, respectively) adjacent to the target group. The calculation results of the reference code density and the preset deviation value are shown in the following table one:
table one: reference code density and preset offset value corresponding to digital codes 0001 to 0100 and 1001 to 1100
Since the absolute value (i.e., 0.125) of the deviation between the average code density (i.e., 3.75) and the reference code density (i.e., 3.875) of the target group is not greater than the predetermined deviation (i.e., 1.9375), the code density detection module 130 determines that the code density of the target group is normal.
Referring again to fig. 3, in another embodiment, the specific digital codes include digital codes 0000-1100, wherein the target group includes only digital codes 0110 and the average code density of the target group is 6. Moreover, the code density detection module 130 may calculate the reference code density and the predetermined bias value by using two digital code groups (e.g., 0100 to 0101 and 0111 to 1000 respectively) adjacent to the target group. The calculation results of the reference code density and the preset deviation value are shown in the following table two:
table two: reference code density and preset deviation value corresponding to digital codes 0100, 0101, 0111 and 1000
Since the absolute value of the deviation (i.e., 2.75) between the average code density (i.e., 6) and the reference code density (i.e., 3.25) of the target group is greater than the predetermined deviation (i.e., 1.625), the code density detection module 130 determines that the code density of the target group 0110 is abnormal.
In yet another embodiment, the specific digital codes include the digital codes 0000-1100, wherein the target group includes only the digital codes 1010, so the average code density of the target group is 4. Moreover, the code density detection module 130 may calculate the reference code density and the predetermined offset value by using two digital code groups (e.g., comprising the digital codes 1100 to 1011 and 1001 to 1000, respectively) adjacent to the target group. The calculation results of the reference code density and the preset deviation value are shown in the following table three:
a third table: reference code density and preset deviation value corresponding to digital codes 1100, 1011, 1001 and 1000
Since the absolute value of the deviation (i.e., 0.25) between the average code density (i.e., 4) and the reference code density (i.e., 3.75) of the target group is not greater than the predetermined deviation (i.e., 1.875), the code density detection module 130 determines that the code density of the target group 1010 is normal.
In the process S214, the code density detection module 130 outputs the adjustment information including the comparison result to the capacitance calibration module 140. Next, the capacitance calibration module 140 executes the process S216 to determine whether the capacitance of the capacitor array 112 needs to be adjusted according to the adjustment information received from the code density detection module 130.
When the capacitance calibration module 140 receives the adjustment information indicating that the code density is normal, the capacitance calibration module 140 will not adjust the capacitance of the capacitor array 112. At this time, the calibration system 100 will again execute the process S202 to perform real-time calibration during the operation of the successive approximation adc 110.
In some embodiments, the calibration system 100 may also end the calibration method 200 when the code densities of the plurality of digital codes are all normal.
On the other hand, when the capacitance calibration module 140 receives the adjustment information indicating the code density abnormality, the capacitance calibration module 140 executes the process S218 in fig. 2 (b) to select one of the capacitance units 118 in the capacitance array 112 as the capacitance unit to be calibrated according to the position of the target group in the value range for performing the capacitance calibration. The operation of the capacitance calibration module 140 for selecting the capacitance unit to be calibrated will be further described below.
In some embodiments, the capacitance calibration module 140 stores a range of values that are divided equally in order according to the power of 2 to obtain a plurality of binary equal division points. For example, in the embodiment where the successive approximation adc 110 is a 4-bit adc, and the digital code is distributed in the range 0000 to 1111, the capacitance calibration module 140 stores the range 0000 to 1111, which is divided into 1 bisector, 3 bisectors, 7 bisectors, and 15 sixteen bisectors according to the first power of 2 to the fourth power of 2.
Therefore, in the case that the successive approximation adc 110 is an M-bit adc, the capacitance calibration module 140 stores a plurality of binary equally dividing points obtained by equally dividing the range of values according to the first power of 2 to the M power of 2.
Referring to FIG. 1, among the M capacitor units 118 in the capacitor array 112, the capacitor unit 118-1 has the largest capacitance value, the capacitor unit 118-2 has the next largest capacitance value, the capacitor unit 118-M has the smallest capacitance value, and so on. The capacitance calibration module 140 determines a binary equally dividing point closest to the position of the target group in the numerical range from the plurality of binary equally dividing points, and sets the corresponding capacitance unit 118 as a capacitance unit to be calibrated according to the closest binary equally dividing point.
For example, in the embodiment where the successive approximation adc 110 is a 4-bit adc, if the target group is 1000, the positions of the target group in the range 0000 to 1111 are closest to the bisector point. Therefore, the capacitance calibration module 140 sets the capacitance unit 118-1 as the capacitance unit to be calibrated.
For another example, also in the embodiment where the successive approximation adc 110 is a 4-bit adc, if the target group is 1100, the positions of the target group in the range 0000 to 1111 are closest to the quartering point. Therefore, the capacitance calibration module 140 sets the capacitance unit 118-2 as the capacitance unit to be calibrated.
That is, if the position of the target group in the value range is closest to any 2X power bisector, the capacitance calibration module 140 sets the capacitance unit 118-X as the capacitance unit to be calibrated, where X is a positive integer and X is less than or equal to M.
Next, the capacitance calibration module 140 executes the process S220 to determine the calibration direction of the capacitance value of the capacitor unit to be calibrated. When the capacitance calibration module 140 determines that the code density of the target group is greater than the reference code density according to the received comparison result, the capacitance calibration module 140 determines that the capacitance of the to-be-calibrated capacitor unit needs to be decreased. When the capacitance calibration module 140 determines that the code density of the target group is smaller than the reference code density according to the received comparison result, the capacitance calibration module 140 determines that the capacitance of the to-be-calibrated capacitor unit needs to be increased.
In the process S222, the capacitance calibration module 140 sends a calibration command to the successive approximation analog-to-digital converter 110, wherein the calibration command includes a calibration direction of the capacitance value of the capacitor unit to be calibrated. In the process S224, the successive approximation adc 110 calibrates the capacitance of the capacitor unit to be calibrated according to the received calibration command.
The manner of calibrating the capacitance value of the capacitor unit to be calibrated in the process S224 will be further described with reference to fig. 5. As shown in fig. 5, taking the capacitor unit 118-1 as an example, the capacitor unit 118-1 includes a main capacitor CM, a first sub-capacitor C1, a second sub-capacitor C2, a first single-pole double-throw switch SW1 and a second single-pole double-throw switch SW2. The main capacitor CM is coupled between the first node N1 and the second node N2. A first end of the first sub-capacitor C1 is coupled to the first node N1, and a second end of the first sub-capacitor C1 is coupled to the second node N2 through the first single-pole double-throw switch SW 1. A first end of the second sub-capacitor C2 is coupled to the first node N1, and a second end of the second sub-capacitor C2 is coupled to the ground end through a second single-pole double-throw switch SW2.
In other words, the main capacitor CM is coupled to the first sub-capacitor C1 in parallel, but the main capacitor CM is not coupled to the second sub-capacitor C2 in parallel.
When the capacitor unit 118-1 is selected as the capacitor unit to be calibrated, if the code density of the target group is smaller than the reference code density, the successive approximation analog-to-digital converter 110 receives a calibration command for increasing the capacitance of the capacitor unit 118-1 in the process S224. At this time, the successive approximation adc 110 switches the second end of the second sub-capacitor C2 from the ground to the second node N2 through the second single-pole double-throw switch SW2.
That is, when the code density of the target group is less than the reference code density, the successive approximation analog-to-digital converter 110 couples the second sub-capacitor C2 in parallel with the main capacitor CM to increase the capacitance of the capacitor unit 118-1.
On the other hand, if the code density of the target group is greater than the reference code density, the successive approximation analog-to-digital converter 110 receives the calibration command to decrease the capacitance of the capacitor 118-1 in the process S224. At this time, the successive approximation adc 110 switches the second end of the first sub-capacitor C1 from the second node N2 to the ground through the first single-pole double-throw switch SW 1.
That is, when the code density of the target group is greater than the reference code density, the successive approximation analog-to-digital converter 110 disconnects the parallel connection between the first sub-capacitor C1 and the main capacitor CM to reduce the capacitance of the capacitor unit 118-1.
In some embodiments, the capacitor unit 118-1 includes a plurality of first sub-capacitors C1, a plurality of second sub-capacitors C2, a plurality of first single-pole double-throw switches SW1 and/or a plurality of second single-pole double-throw switches SW2. Each of the first sub-capacitors C1 is correspondingly coupled to the main capacitor CM in parallel through a first single-pole double-throw switch SW1, and none of the second sub-capacitors C2 is coupled to the main capacitor CM in parallel. The calibration system 100 can disconnect one of the first sub-capacitors C1 from the main capacitor CM or couple one of the second sub-capacitors C2 to the main capacitor CM according to the aforementioned rule each time the calibration method 200 is executed. Thus, the calibration accuracy of the calibration method 200 can be further improved.
The components and connection manners of the other capacitor units 118 of the capacitor array 112, and the applicable capacitance calibration method, are similar to those of the capacitor unit 118-1, and are not repeated herein for brevity.
Then, after the process S224 ends, the calibration system 100 can execute the process S202 again to perform real-time calibration on the successive approximation adc 110.
In one embodiment, the calibration system 100 ends the calibration method 200 after performing the process S224.
In another embodiment, the calibration system 100 performs the processes S210-S220 several times. That is, the calibration system 100 selects a plurality of target groups from the digital code groups, and compares the average code density of each of the plurality of target groups with the corresponding reference code density to generate a plurality of comparison results. Next, the calibration system 100 executes the process S222 to output a calibration command according to the comparison results. In this way, the calibration system 100 can calibrate the capacitance values of the to-be-calibrated capacitor units corresponding to the target groups at one time.
For example, the calibration system 100 may select a first group of targets and a second group of targets from a group of digital codes. Then, the average code density of the first target group is compared with the first reference code density to generate a first comparison result, and the average code density of the second target group is compared with the second reference code density to generate a second comparison result. The calibration system 100 outputs a calibration command according to the first comparison result and the second comparison result to calibrate the first to-be-calibrated capacitor unit corresponding to the first target group and the second to-be-calibrated capacitor unit corresponding to the second target group at one time. In other words, when the capacitance calibration module 140 calibrates the capacitance value of the first to-be-calibrated capacitor unit according to the first comparison result, the capacitance calibration module 140 calibrates the capacitance value of the second to-be-calibrated capacitor unit together according to the second comparison result.
As can be seen from the above, the calibration system 100 can execute the calibration method 200 in parallel during the operation of the successive approximation adc 110. Thus, real-time calibration of the successive approximation analog-to-digital converter 110 can be achieved to overcome output errors of the successive approximation analog-to-digital converter 110 caused by various factors during the manufacturing process or operation.
Certain terms are used throughout the description and following claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the various elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect means of connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.
As used herein, the term "and/or" is inclusive of any combination of one or more of the listed items. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.
The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
Claims (14)
1. A calibration method for a successive approximation analog-to-digital converter (SAR ADC) including a capacitor array, the calibration method comprising:
inputting an input signal to the successive approximation type analog-digital converter, wherein the successive approximation type analog-digital converter generates an output signal according to the input signal, the output signal comprises a plurality of specific digital codes, and the input signal is a voltage signal or a current signal which accords with the full scale range of the successive approximation type analog-digital converter;
calculating an average code density of each of a plurality of digital code groups in the plurality of specific digital codes, wherein each digital code group comprises one or more specific digital codes in the plurality of specific digital codes;
comparing the average code density of a first target group in the plurality of digital code groups with a first reference code density to generate a first comparison result; and
and calibrating the capacitance value of a first capacitor unit to be calibrated of the capacitor array according to the first comparison result.
2. The calibration method according to claim 1, wherein the step of calculating the average code density of each of the plurality of digital code groups in the plurality of specific digital codes comprises:
calculating the occurrence times of a first digital code group in the specific digital codes in the output signal to obtain a first accumulated time;
calculating a first average code density of the first digital code group corresponding to the output signal according to the first accumulated times;
calculating the occurrence times of a second digital code group in the plurality of digital codes in the output signal to obtain a second accumulated time; and
and calculating a second average code density of the second digital code group corresponding to the output signal according to the second accumulated times.
3. The calibration method according to claim 1, wherein the capacitance of the first capacitor to be calibrated is decreased when the average code density of the first target group is greater than the first reference code density, and the capacitance of the first capacitor to be calibrated is increased when the average code density of the first target group is less than the first reference code density.
4. The calibration method of claim 3, further comprising:
comparing the average code density of a second target group in the plurality of digital code groups with a second reference code density to generate a second comparison result;
wherein, the process of calibrating the capacitance value of the first to-be-calibrated capacitor unit of the capacitor array according to the first comparison result comprises:
when calibrating the capacitance value of the first to-be-calibrated capacitor unit, calibrating the capacitance value of a second to-be-calibrated capacitor unit of the capacitor array according to the second comparison result,
when the average code density of the second target group is smaller than the second reference code density, the capacitance of the second capacitor unit to be calibrated is increased.
5. The calibration method according to claim 3, wherein the first capacitor unit to be calibrated comprises a main capacitor, a first sub-capacitor and a second sub-capacitor, the first sub-capacitor is coupled in parallel to the main capacitor, and the process of calibrating the capacitance value of the first capacitor unit to be calibrated of the capacitor array according to the first comparison result further comprises:
disconnecting the parallel connection between the first sub-capacitor and the main capacitor when the average code density of the first target group is greater than the first reference code density; and
when the average code density of the first target group is smaller than the first reference code density, the second sub-capacitor is coupled in parallel to the main capacitor.
6. The calibration method of claim 1, wherein the specific digital codes are distributed within a range of values, and comparing the average code density of the first target group of the specific digital codes with the first reference code density comprises:
when the first target group is selected, selecting other digital code groups adjacent to the first target group from the plurality of digital code groups according to the position of the first target group in the value range;
averaging the average code densities of the other digital code groups to obtain the first reference code density.
7. The method according to claim 6, wherein the capacitor array comprises M capacitor units, and M is a positive integer, the process of calibrating the capacitance value of the first to-be-calibrated capacitor unit of the capacitor array according to the first comparison result further comprises:
dividing the numerical range into equal parts according to the power of raising power of 2 to obtain a plurality of binary equal division points;
judging a first equally dividing point of the plurality of equally dividing points of the binary bit which is most similar to the position of the first target group in the numerical range;
and selecting one of the M capacitor units as the first capacitor unit to be calibrated according to the power of 2 corresponding to the first equivalence point.
8. A calibration system, comprising:
a successive approximation analog-to-digital converter, comprising a capacitor array for generating an output signal according to an input signal, wherein the output signal comprises a plurality of specific digital codes, and the input signal is a voltage signal or a current signal conforming to the full scale range of the successive approximation analog-to-digital converter;
a code density calculation module for receiving the output signal and calculating an average code density of each of a plurality of digital code groups of the plurality of specific digital codes, wherein each digital code group comprises one or more specific digital codes of the plurality of specific digital codes;
a code density detection module for comparing the average code density of a first target group in the plurality of digital code groups with a first reference code density and outputting a first comparison result; and
and the capacitance calibration module is coupled to the capacitor array and used for calibrating the capacitance value of a first capacitor unit to be calibrated of the capacitor array according to the first comparison result.
9. The calibration system of claim 8, wherein the code density calculation module performs the following operations to calculate an average code density for each of the plurality of digital code groups:
calculating the occurrence times of a first digital code group in the specific digital codes in the output signal to obtain a first accumulated time;
calculating a first average code density of the first digital code group corresponding to the output signal according to the first accumulated times;
calculating the occurrence times of a second digital code group in the specific digital codes in the output signal to obtain a second accumulated time; and
and calculating a second average code density of the second digital code group corresponding to the output signal according to the second accumulated times.
10. The calibration system according to claim 8, wherein the capacitance calibration module decreases the capacitance of the first capacitor to be calibrated when the code density of the first target group is greater than the first reference code density, and increases the capacitance of the first capacitor to be calibrated when the code density of the first target group is less than the first reference code density.
11. The calibration system of claim 10, wherein the code density detection module is configured to compare the average code density of a second target group of the plurality of digital code groups with a second reference code density and output a second comparison result,
wherein, when the capacitance calibration module calibrates the capacitance value of the first to-be-calibrated capacitor unit according to the first comparison result, the capacitance calibration module calibrates the capacitance value of a second to-be-calibrated capacitor unit of the capacitor array according to the second comparison result,
when the average code density of the second target group is smaller than the second reference code density, the capacitance calibration module increases the capacitance of the second capacitor unit to be calibrated.
12. Calibration system according to claim 10, characterized in that the first capacitor unit to be calibrated comprises:
a main capacitor;
a first sub-capacitor, wherein the first sub-capacitor is coupled in parallel with the main capacitor; and
a second sub-capacitor;
wherein the capacitance calibration module disconnects the parallel connection between the first sub-capacitor and the main capacitor when the average code density of the first target group is greater than the first reference code density,
when the average code density of the first target group is smaller than the first reference code density, the capacitance calibration module couples the second sub-capacitor in parallel with the main capacitor.
13. The system of claim 8, wherein the specific digital codes are distributed within a range of values, when the first target group is selected, the code density detection module selects other digital code groups of the plurality of digital code groups adjacent to the first target group according to the position of the first target group within the range of values, and the code density detection module averages the average code densities of the other digital code groups to obtain the first reference code density.
14. The calibration system of claim 13, wherein the capacitor array comprises:
m capacitor units, wherein M is a positive integer;
the capacitance calibration module is used for judging a first equivalence point of the plurality of binary equivalence points which are closest to the first target group in the position of the numerical range according to the ascending power of 2, and selecting one of the M capacitance units as the capacitance unit to be calibrated according to the power of 2 corresponding to the first equivalence point.
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| US11962318B2 (en) | 2021-01-12 | 2024-04-16 | Texas Instruments Incorporated | Calibration scheme for a non-linear ADC |
| US11316525B1 (en) * | 2021-01-26 | 2022-04-26 | Texas Instruments Incorporated | Lookup-table-based analog-to-digital converter |
| US11881867B2 (en) | 2021-02-01 | 2024-01-23 | Texas Instruments Incorporated | Calibration scheme for filling lookup table in an ADC |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427368A (en) * | 2011-11-30 | 2012-04-25 | 香港应用科技研究院有限公司 | High-speed successive approximation register analog-digital converter |
| TW201310918A (en) * | 2011-08-18 | 2013-03-01 | Himax Tech Ltd | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof |
| CN105610446A (en) * | 2014-11-10 | 2016-05-25 | 瑞昱半导体股份有限公司 | Successive approximation analog-to-digital converter and conversion method |
| KR20160084685A (en) * | 2015-01-06 | 2016-07-14 | 울산과학기술원 | Sar-adc apparatus using cds and sampling method thereof |
| EP3059868A1 (en) * | 2015-02-19 | 2016-08-24 | Stichting IMEC Nederland | Circuit and method for comparator offset error detection and correction in an adc |
| CN106253901A (en) * | 2015-06-11 | 2016-12-21 | 矽创电子股份有限公司 | Analog-digital commutator and relevant calibration steps and calibration module |
| US9559716B1 (en) * | 2015-08-28 | 2017-01-31 | Renesas Electronics Corporation | AD converter, AD convert apparatus, and AD convert method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8111178B2 (en) * | 2009-11-26 | 2012-02-07 | Mediatek Inc. | Calibration method and related calibration apparatus for capacitor array |
| WO2015049720A1 (en) * | 2013-10-01 | 2015-04-09 | 富士通株式会社 | A/d converter and a/d converter calibrating method |
-
2018
- 2018-10-17 CN CN201811206734.XA patent/CN111064468B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201310918A (en) * | 2011-08-18 | 2013-03-01 | Himax Tech Ltd | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof |
| CN102427368A (en) * | 2011-11-30 | 2012-04-25 | 香港应用科技研究院有限公司 | High-speed successive approximation register analog-digital converter |
| CN105610446A (en) * | 2014-11-10 | 2016-05-25 | 瑞昱半导体股份有限公司 | Successive approximation analog-to-digital converter and conversion method |
| KR20160084685A (en) * | 2015-01-06 | 2016-07-14 | 울산과학기술원 | Sar-adc apparatus using cds and sampling method thereof |
| EP3059868A1 (en) * | 2015-02-19 | 2016-08-24 | Stichting IMEC Nederland | Circuit and method for comparator offset error detection and correction in an adc |
| CN106253901A (en) * | 2015-06-11 | 2016-12-21 | 矽创电子股份有限公司 | Analog-digital commutator and relevant calibration steps and calibration module |
| US9559716B1 (en) * | 2015-08-28 | 2017-01-31 | Renesas Electronics Corporation | AD converter, AD convert apparatus, and AD convert method |
Non-Patent Citations (1)
| Title |
|---|
| 李洪义等.（1）转换器工作.《非线性集成电路原理及应用》.第四军医大学出版社,2003,第69-73页. * |
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