JP2017211708A - Information processing system, information processing device and control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time required for transferring data to another storage device from a certain storage device of a plurality of storage devices connected to an information processing device.SOLUTION: A first control circuit has a first transmission unit that, when a first read command from a processor includes prescribed information, transmits a completion report indicative of reading completion to the processor prior to the completion of the reading, and transmits a first writing command for writing read data in a main memory to a third control circuit. Then, a second control circuit has a second transmission unit that, when a second writing command from the processor includes prescribed information, transmits a second reading command for reading data from the main memory to the third control circuit. Then, the third control circuit has a third transmission unit that, when an address of main storage to be included in the first writing command coincides with an address of main storage to be included in the second reading command, reads data stored in a first storage area, and transmits the data to the second control circuit.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a technique for transferring data between storage devices.

  When a plurality of external storage devices, shared storage devices, and the like are connected to an information processing device such as a server, data may be transferred from one storage device to another storage device. In a known transfer method, the data read from the storage device that is the data transfer source is temporarily written in the main memory of the information processing device, and after the writing to the main memory is completed, the data written in the main memory is It is read and written to the destination storage device.

  This transfer method has the advantage of relatively simple control. However, it may take a long time to finally complete the transfer. In addition, in order to secure an area on the main memory, a process of moving data originally in the main memory to another storage device may be performed, and in that case, it takes more time.

JP 2003-281084 A JP 2008-130092 A

  An object of the present invention, in one aspect, is to provide a technique for reducing the time required to transfer data from one storage device to another storage device among a plurality of storage devices connected to the information processing device. It is to be.

  An information processing apparatus according to the present invention includes a processor, a main memory, a first control circuit, a second control circuit, and a third control circuit. The first control circuit determines whether the first read instruction for reading data from the first storage device connected to the information processing device received from the processor includes predetermined information; When the first determination unit determines that the first read instruction includes predetermined information, a completion report indicating that the read is completed is transmitted to the processor before the read is completed, and from the first storage device A first transmission unit configured to transmit a first write command including the read data and predetermined information to write the read data to the main memory to the third control circuit; The second control circuit includes a second determination unit that determines whether the second write instruction for writing data to the second storage device connected to the information processing device received from the processor includes predetermined information. When the second determination unit determines that the second write command includes predetermined information, a second read command for reading data from the main memory including the predetermined information is transmitted to the third control circuit. 2 transmitters. The third control circuit stores the first write instruction in the first storage area of the third control circuit when the first write instruction received from the first control circuit includes predetermined information. A second storage processing unit for storing the second read command in the second storage area of the third control circuit; and a first storage command when the second read command received from the second control circuit includes predetermined information. When the address of the main memory included in the first write instruction stored in the storage area matches the address of the main memory included in the second read instruction stored in the second storage area, the first storage area A third transmission unit for reading the stored data and transmitting the data to the second control circuit;

  In one aspect, the time required to transfer data from one storage device to another storage device among a plurality of storage devices connected to the information processing device can be shortened.

FIG. 1 is a diagram showing an overview of a system in the present embodiment. FIG. 2 is a diagram illustrating a time chart when data is transferred via the main memory. FIG. 3 is a diagram showing a time chart when transferring data without going through the main memory. FIG. 4 is a diagram illustrating a configuration of the main device. FIG. 5A is a diagram illustrating the configuration of the MCU. FIG. 5B is a diagram illustrating the configuration of the SSM and the channel. FIG. 6 is a diagram illustrating a configuration of the packet control circuit. FIG. 7 is a diagram illustrating a configuration of the packet control circuit. FIG. 8 is a diagram showing the configuration of the bypass buffer control circuit. FIG. 9 is a diagram illustrating an example of data stored in the bypass buffer. FIG. 10 is a diagram illustrating an example of data stored in the bypass request queue. FIG. 11 is a diagram illustrating an example of a request format. FIG. 12 is a diagram for explaining the outline of the operation of the main device. FIG. 13 is a diagram illustrating a flow of an outline of processing performed in the system according to the present embodiment. FIG. 14 is a diagram showing a processing flow when data is transferred via the main memory. FIG. 15 is a diagram illustrating a processing flow of processing executed when the bypass buffer control circuit receives a write command from the SSM. FIG. 16 is a diagram illustrating a processing flow of processing executed by the second arbitration circuit of the bypass buffer control circuit. FIG. 17 is a diagram showing a processing flow of processing executed when the bypass buffer control circuit receives a read command from the SSM. FIG. 18 is a diagram showing a processing flow of processing executed when the bypass buffer control circuit receives a read command from the SSM. FIG. 19 is a diagram illustrating a processing flow of processing executed by the first arbitration circuit of the bypass buffer control circuit. FIG. 20 is a sequence diagram when the transfer method of this embodiment is used. FIG. 21 is a sequence diagram when a known transfer method is used.

  FIG. 1 shows an overview of a system in the present embodiment. The main body devices 1a and 1b are, for example, server units or server blades, and each operate independently as one computer. An I / O (Input / Output) 5a is connected to the main unit 1a, and an I / O 5b is connected to the main unit 1b. The I / Os 5a and 5b are external storage devices such as HDD (Hard Disk Drive), for example. The main devices 1a and 1b are connected to an SSU (System Storage Unit) 3 which is a shared storage device. The SSU 3 is, for example, a nonvolatile memory.

  However, the number of main devices connected to the SSU 3 may be three or more. Further, the number of I / Os connected to each main device may be two or more.

  In the present embodiment, it is considered that data is transferred from the SSU 3 to the I / O (for the sake of simplicity, it will be referred to as I / O 5a hereinafter). FIG. 2 shows a time chart when data is transferred via the main memory. In FIG. 2, SSM (System Storage Manager) is a unit that performs interface control between the SSU 3 and the main apparatus 1a, and a channel is a unit that performs interface control between the I / O 5a and the main apparatus 1a.

  When transferring data via the main memory, first, a CPU (Central Processing Unit) issues a read command for data stored in the SSU 3 to the SSM. When the SSM receives a read command for data stored in the SSU 3 from the CPU, the SSM reads the data from the SSU 3 and transfers it to the main memory. When the data transfer to the main memory is completed, the SSM issues a completion report indicating that the reading is completed to the CPU. When the CPU receives the completion report, it issues a write command to the I / O 5a to the channel. When the channel receives a write command to the I / O 5a, the channel transfers the data stored in the main memory to the I / O 5a. When the transfer to the I / O 5a is completed, the channel issues a completion report to the CPU indicating that the writing has been completed. Thus, a series of data transfer is completed.

  In this transfer method, since processing is performed serially, as described in the background section, it takes a long time to complete data transfer.

  Therefore, in the present embodiment, the transfer time is shortened by transferring data so as not to go through the main memory and to perform some processes in parallel. FIG. 3 shows a time chart when transferring data without going through the main memory. In FIG. 3, the bypass buffer is a buffer provided in an MCU (Memory Controller unit) of the main device 1a. First, the CPU issues a read command for data stored in the SSU 3 to the SSM. When the SSM receives an instruction to read data stored in the SSU 3 from the CPU, the SSM issues a completion report indicating that the reading has been completed to the CPU. Then, the SSM starts reading data from the SSU 3 and transferring it to the bypass buffer. In parallel with this, when the CPU receives the completion report, it issues a write command to the I / O 5a to the channel. When the channel receives a write command to the I / O 5a, the channel transfers the data stored in the bypass buffer to the I / O 5a. When the transfer to the I / O 5a is completed, the channel issues a completion report to the CPU indicating that the writing has been completed. Thus, a series of data transfer is completed.

  Below, the specific content of this Embodiment is demonstrated.

  FIG. 4 shows the configuration of the main device 1a. The main device 1 a includes a CPU 11, a main memory 12, an MCU 10, an SSM 13, and a channel 14. The SSM 13 is connected to the SSU 3, and the channel 14 is connected to the I / O 5a.

  FIG. 5A shows the configuration of the MCU 10. The MCU 10 includes packet control circuits 150a to 150f that execute packet transfer and the like, and a bypass buffer control circuit 100. The numbers in parentheses correspond to the numbers of the operations of the main device 1a described below.

  The packet control circuit 150a is connected to the CPU 11, the packet control circuit 150c, and the packet control circuit 150e. The packet control circuit 150b is connected to the CPU 11, the packet control circuit 150d, and the packet control circuit 150f. The packet control circuit 150c is connected to the SSM 13, the packet control circuit 150a, and the bypass buffer control circuit 100. The packet control circuit 150d is connected to the SSM 13, the packet control circuit 150b, and the bypass buffer control circuit 100. The packet control circuit 150e is connected to the channel 14, the packet control circuit 150a, and the bypass buffer control circuit 100. The packet control circuit 150f is connected to the channel 14, the packet control circuit 150b, and the bypass buffer control circuit 100. The bypass buffer control circuit 100 is connected to the main memory 12 and the packet control circuits 150c to 150f.

  FIG. 5B shows the configuration of the SSM 13 and the channel 14. The SSM 13 includes a packet control circuit 13p that executes packet transfer and the like, a data transfer circuit 13t that executes data writing to the SSU 3, reading data from the SSU 3, and the like, and a memory 13m used for the data transfer circuit 13t. Have The packet control circuit 13p has a bypass control circuit 130. The channel 14 includes a packet control circuit 14p that executes packet transfer and the like, a program execution circuit 14e that executes a program for performing a characteristic operation of the channel 14, and data writing to the I / O 5a and I / O 5a. A data transfer circuit 14t for reading data from the memory 14m and a memory 14m used for the data transfer circuit 14t. The packet control circuit 14p has a bypass control circuit 140. The numbers in parentheses correspond to the numbers of the operations of the main device 1a described below.

  The data transfer circuit 13t is connected to the SSU 3, the memory 13m, and the packet control circuit 13p. The memory 13m is connected to the data transfer circuit 13t. The packet control circuit 13p is connected to the MCU 10 and the data transfer circuit 13t. The data transfer circuit 14t is connected to the I / O 5a, the memory 14m, and the program execution circuit 14e. The memory 14m is connected to the data transfer circuit 14t. The program execution circuit 14e is connected to the data transfer circuit 14t and the packet control circuit 14p. The packet control circuit 14p is connected to the MCU 10 and the program execution circuit 14e.

  FIG. 6 shows the configuration of the packet control circuit 13p. The packet control circuit 13p includes a bypass control circuit 130, an input packet analysis unit 131, a write control circuit 132, a completion report control circuit 133, and an output packet generation unit 134. The bypass control circuit 130 includes a bypass mode check unit 1301 and a first-out flag 1302. The numbers in parentheses correspond to the numbers of the operations of the main device 1a described below.

  The input packet analysis unit 131 is connected to the bypass mode check unit 1301. The write control circuit 132 is connected to the advance flag 1302 and the output packet generator 134. The completion report control circuit 133 is connected to the output packet generator 134 and the advance flag 1302. The output packet generator 134 is connected to the completion report control circuit 133 and the write control circuit 132. The bypass mode check unit 1301 is connected to the input packet analysis unit 131 and the advance flag 1302. The advance flag 1302 is connected to the bypass mode check unit 1301, the completion report control circuit 133, and the write control circuit 132.

  FIG. 7 shows the configuration of the packet control circuit 14p. The packet control circuit 14p includes a bypass control circuit 140, an input packet analysis unit 141, a read control circuit 142, a completion report control circuit 143, and an output packet generation unit 144. The bypass control circuit 140 includes a bypass mode check unit 1401 and a bypass execution flag 1402. The numbers in parentheses correspond to the numbers of the operations of the main device 1a described below.

  The input packet analysis unit 141 is connected to the bypass mode check unit 1401. The read control circuit 142 is connected to the bypass execution flag 1402 and the output packet generation unit 144. The completion report control circuit 143 is connected to the output packet generation unit 144. The output packet generation unit 144 is connected to the completion report control circuit 143 and the read control circuit 142. The bypass mode check unit 1401 is connected to the input packet analysis unit 141 and the bypass execution flag 1402. The bypass execution flag 1402 is connected to the bypass mode check unit 1401 and the read control circuit 142.

  FIG. 8 shows a configuration of the bypass buffer control circuit 100. The bypass buffer control circuit 100 includes a bypass buffer 101, a bypass mode check circuit 102, a bypass mode check circuit 103, a data check circuit 104, a first switching unit 105, a second switching unit 106, and a bypass request queue control. The circuit 107 includes a bypass request queue 108, a bypass request port 109, an address comparison circuit 110, a first arbitration circuit 111, a second arbitration circuit 112, and a completion report control circuit 113. The numbers in parentheses correspond to the numbers of the operations of the main device 1a described below.

  The bypass buffer 101 is connected to the first switching unit 105, the completion report control circuit 113, the address comparison circuit 110, and the arbitration port A. The bypass mode check circuit 102 is connected to the data check circuit 104 and the first switching unit 105. The bypass mode check circuit 103 is connected to the second switching unit 106. The data check circuit 104 is connected to the bypass mode check circuit 102 and the first switching unit 105. The first switching unit 105 is connected to the data check circuit 104, the bypass buffer 101, and the completion report control circuit 113. The second switching unit 106 is connected to the bypass mode check circuit 103 and the bypass request queue 108. The bypass request queue control circuit 107 is connected to the address comparison circuit 110 and the bypass request queue 108. The bypass request queue 108 is connected to the second switching unit 106, the bypass request queue control circuit 107, and the bypass request port 109. The bypass request port 109 is connected to the bypass request queue 108, the address comparison circuit 110, and the arbitration port A. The address comparison circuit 110 is connected to the bypass request queue control circuit 107, the bypass request port 109, the bypass buffer 101, and the arbitration port A. The first arbitration circuit 111 is connected to the arbitration ports A and B. The second arbitration circuit 112 is connected to the arbitration ports C and D. The completion report control circuit 113 is connected to the first switching unit 105 and the arbitration port C. The arbitration ports A to D are storage devices such as registers.

  FIG. 9 shows an example of data stored in the bypass buffer 101. In the example of FIG. 9, data, an address on the main memory where the data is stored (hereinafter referred to as an MS (Main Storage) address), and the value of the valid flag are stored. If the valid flag is set to valid (for example, the value is “1”), the data has not yet been output to the arbitration port A. If the valid flag is set to invalid (for example, the value is “0”), the data has already been output to the arbitration port A.

  FIG. 10 shows an example of data stored in the bypass request queue 108. In the example of FIG. 10, a request is stored. FIG. 11 shows an example of a request format. In the example of FIG. 11, the request includes an operation code that defines the type of access, an MS address, information indicating a bypass mode, and data. When the operation code is “0001”, the request corresponds to a read command issued from the SSU 3 to the SSM 13 from the CPU 11. When the operation code is “1001”, the request corresponds to a read completion report from the SSU 3 issued from the SSM 13 to the CPU 11. When the operation code is “0010”, the request corresponds to a write instruction for the I / O 5 a issued from the CPU 11 to the channel 14. When the operation code is “1010”, the request corresponds to a write completion report for the I / O 5 a issued from the channel 14 to the CPU 11. When the operation code is “0100”, the request corresponds to a read instruction from the main memory 12 issued from the SSM 13 or the channel 14 to the main memory 12. When the operation code is “1100”, the request corresponds to a read response from the main memory 12 (hereinafter referred to as a read response) issued from the main memory 12 to the SSM 13 or the channel 14. When the operation code is “0101”, the request corresponds to a write instruction to the main memory 12 issued from the SSM 13 or the channel 14 to the main memory 12. When the operation code is “1101”, the request corresponds to a write completion report to the main memory 12 issued from the main memory 12 to the SSM 13 or the channel 14. Even if the command is a write command to the main memory 12 and a read command from the main memory 12, if the bypass mode is set to be effective, writing to the main memory 12 and reading from the main memory 12 are not performed. I will not.

  The outline of the operation of the main device 1a in the present embodiment will be described with reference to FIG.

  The CPU 11 issues a data read command from the SSU 3 to the SSM 13 with the bypass mode enabled (that is, with the bypass mode value set to 1) ((i) in FIG. 12).

  The SSM 13 detects a read command in which the bypass mode is effective, and issues a read completion report from the SSU 3 to the CPU 11 first without waiting for the data of the SSU 3 to be read and written to the main memory 12 ( (Ii) in FIG.

  The SSM 13 reads data from the SSU 3 in accordance with the data read command from the SSU 3 ((iii) in FIG. 12), and issues a write command for writing the read data to the main memory 12 with the bypass mode enabled (FIG. 12). (Iv) in 12). The bypass buffer control circuit 100 of the MCU 10 receives a write command in which the bypass mode is valid from the SSM 13, and if there is no error, the MS flag and the data included in the write command are set to valid flags to enable the bypass buffer. 101.

  On the other hand, when the CPU 11 receives a read completion report from the SSU 3 from the SSM 13, the CPU 11 issues a write command for the I / O 5a to the channel 14 with the bypass mode enabled ((v) in FIG. 12).

  The channel 14 receives a write command in which the bypass mode is valid from the CPU 11. The channel 14 issues a read command from the main memory 12 to the MCU 10 with the bypass mode enabled in order to read data and write it to the I / O 5a ((vi) in FIG. 12).

  The bypass buffer control circuit 100 of the MCU 10 receives a read command in which the bypass mode is valid from the channel 14. The bypass buffer control circuit 100 reads data from the bypass buffer 101 in accordance with the received read command, and issues a read response including the read data to the channel 14 ((vii) in FIG. 12).

  When the channel 14 receives a read response from the MCU 10, the channel 14 writes data included in the received read response to the I / O 5a. Then, the channel 14 issues a write completion report for the I / O 5a to the CPU 11 ((viii) in FIG. 12).

  The above is the outline of the operation of the main device 1a.

  More specifically, the main device 1a operates as follows. The numbers in parentheses correspond to the numbers shown in FIGS. 5A to 8.

  First, the CPU 11 issues a read command from the SSU 3 to the SSM 13 via the MCU 10 while enabling the bypass mode (1).

  The bypass mode check unit 1301 of the SSM 13 determines whether the bypass mode of the read command received via the input packet analysis unit 131 is valid (2). When the bypass mode is valid, the SSM 13 sets the advance flag 1302 to be valid (for example, “1”) in order to advance the read completion report from the SSU 3 (3). When the advance flag 1302 is set to be valid, the SSM 13 activates the completion report control circuit 133. The completion report control circuit 133 generates a read completion report from the SSU 3, and the output packet generation unit 134 issues the generated completion report to the CPU 11 (4).

  The CPU 11 receives a read completion report from the SSU 3. Then, the CPU 11 issues a write command for the I / O 5a to the channel 14 via the MCU 10 while enabling the bypass mode (5).

  The input packet analysis unit 131 of the SSM 13 issues a read command from the SSU 3 to the SSU 3 (6). The SSM 13 receives the data read from the SSU 3 (7). If the advance flag 1302 is valid, the write control circuit 132 of the SSM 13 issues a data write command read from the SSU 3 to the MCU 10 with the bypass mode enabled (8). Processes (6) to (8) are repeated until data is written without omission.

  The bypass mode check circuit 102 in the bypass buffer control circuit 100 of the MCU 10 confirms the bypass mode set in the write command received from the SSM 13 (9).

  When the bypass mode is “valid”, the bypass buffer control circuit 100 executes the following processing. Specifically, the data check circuit 104 checks whether the data of the write command is normal, and when an error has occurred, discards the write command and resends the write command to the SSM 13. A request is transmitted (10-1). The first switching unit 105 stores the set including the MS address and the data to be written in the bypass buffer 101 with the validity flag validated (10-2). When the bypass buffer 101 is empty, the completion report control circuit 113 sets a completion report for writing to the main memory 12 in the arbitration port C (10-3). When there is no empty space in the bypass buffer 101 due to the writing of (10-2), the completion report control circuit 113 suspends issuing the completion report until the empty space is generated.

  On the other hand, when the bypass mode is not “valid”, the bypass buffer control circuit 100 executes the following processing. Specifically, the bypass buffer control circuit 100 executes writing to the main memory 12 according to the write command (11-1). Then, the bypass buffer control circuit 100 sets a completion report of writing to the main memory 12 in the arbitration port D (11-2).

  The second arbitration circuit 112 performs selection so that only one of the arbitration port C and the arbitration port D does not continue to be selected, and issues a completion report set for the selected arbitration port to the SSM 13 ( 12).

  When the completion report control circuit 133 receives the complete report of the write command corresponding to the read command for the transfer length designated by the CPU 11 and the advance flag 1302 is set to be valid, A completion report of the read command is not issued to the CPU 11, the advance flag 1302 is set to be invalid, and the process is terminated (13).

  On the other hand, the bypass mode check unit 1401 in the bypass control circuit 140 of the channel 14 determines whether the bypass mode of the write command received through the input packet analysis unit 141 is valid (14). When the bypass mode is valid, the bypass mode check unit 1401 sets the bypass execution flag 1402 to be valid (15). The read control circuit 142 issues a read command from the main memory 12 to the MCU 10 via the output packet generator 144 with the bypass mode enabled (16). The channel 14 repeats the process of (16) to acquire data for writing for the specified transfer length from the CPU 11, and when the read command is issued, the read control circuit 142 invalidates the bypass execution flag 1402 (17).

  The bypass mode check circuit 103 in the bypass buffer control circuit 100 of the MCU 10 confirms the bypass mode of the read command received from the channel 14 (18).

  When the bypass mode is “valid”, the bypass buffer control circuit 100 executes the following processing. Specifically, the second switching unit 106 stores the received read command at the end of the bypass request queue 108 (19-1). The bypass request queue control circuit 107 stores the read instruction at the head of the bypass request queue 108 in the bypass request port 109 when the bypass request port 109 is empty, and shifts the bypass request queue 108 (19-2). If the arbitration port A is not empty, the bypass buffer control circuit 100 waits until the arbitration port A becomes empty (19-3). When the arbitration port A is empty, the address comparison circuit 110 sets a condition that satisfies the condition that the MS address is the same as the MS address of the read instruction stored in the bypass request port 109 and the valid flag is set to valid. It is determined whether it exists in the bypass buffer 101 (19-4). If there is a set that satisfies the condition, the address comparison circuit 110 reads data from the set, stores it in the arbitration port A, and sets the valid flag to invalid. Further, the address comparison circuit 110 reads information indicating the return destination channel of the read command from the bypass request port 109, stores it in the arbitration port A, and empties the bypass request port 109 (19-5). If there is no set that satisfies the condition, the bypass request queue control circuit 107 extracts the read instruction stored in the bypass request port 109 and stores it at the tail of the bypass request queue 108 to empty the bypass request port 109. (19-6). When the read command remains in the bypass request port 109, the bypass buffer control circuit 100 repeats the processes from (19-1) to (19-6). When data is stored in the arbitration port A, (21) described below is also executed.

  On the other hand, when the bypass mode is not “valid”, the bypass buffer control circuit 100 executes the following processing. Specifically, the bypass buffer control circuit 100 reads data from the main memory 12 according to a read command from the main memory 12 (20-1), and stores the read data in the arbitration port B (20-2).

  The first arbitration circuit 111 in the bypass buffer control circuit 100 performs selection so that only one of the arbitration port A and the arbitration port B is not continuously selected, and the data stored in the selected arbitration port is transmitted to the channel 14. (21).

  The input packet analysis unit 141 of the channel 14 receives data from the MCU 10 (22), and writes the received data to the I / O 5a (23). The completion report control circuit 143 receives a write completion report from the I / O 5a (24), and issues a write completion report for the I / O 5a to the CPU 11 via the output packet generator 144 (25).

  This is the end of the description of the outline of the operation of the main device 1a.

  Next, the operation of the main unit 1a will be described using the flowcharts of FIGS.

  First, an outline of processing performed in the system according to the present embodiment will be described with reference to FIG. The CPU 11 issues a read command from the SSU 3 to the SSM 13 (FIG. 13: step S1). In response to this, the SSM 13 issues a read instruction completion report to the CPU 11 (step S3).

  And the process of step S9 thru | or S17 and the process of step S5 and S7 are performed in parallel. First, the processing of steps S5 and S7 will be described.

  The SSM 13 starts transferring the data read from the SSU 3 from the SSU 3 to the bypass buffer 101 via the SSM 13 (step S5).

  The SSM 13 determines whether the data transfer from the SSU 3 to the bypass buffer 101 has been completed (step S7). If the data transfer has not been completed (step S7: No route), the process returns to step S7. When the data transfer is completed (step S7: Yes route), the process ends.

  On the other hand, the CPU 11 issues a write command for the I / O 5a to the channel 14 (step S9). The channel 14 issues a read command from the main memory 12 to the bypass buffer control circuit 100 of the MCU 10.

  The bypass buffer control circuit 100 determines whether there is an MS address in the bypass buffer 101 that matches the MS address included in the read command (step S11). If there is no MS address in the bypass buffer 101 that matches the MS address included in the read command (step S11: No route), the process returns to step S11.

  On the other hand, when the MS address that matches the MS address included in the read command is present in the bypass buffer 101 (step S11: Yes route), the channel 14 sends the I / O 5a from the bypass buffer 101 via the channel 14 to the I / O 5a. The transfer of data read from the SSU 3 is started (step S13).

  The channel 14 determines whether the data transfer from the bypass buffer 101 to the I / O 5a is completed (step S15). If the data transfer has not been completed (step S15: No route), the process returns to step S15. When the data transfer is completed (step S15: Yes route), the channel 14 issues a completion report of the write command for the I / O 5a to the CPU 11 (step S17). Then, the process ends.

  As described above, when data reading and data writing are performed in parallel, the time required for data transfer can be shortened. Further, since it can be realized by modifying the main device, the existing instruction flow executed by the CPU 11 can be maintained. Furthermore, since it is not necessary to save the data stored in the main memory 12 to another location, other accesses to the main memory 12 are not delayed.

  For comparison, the processing for transferring data via the main memory described with reference to FIG. 2 will be described with reference to FIG.

  First, the CPU 11 issues a read command from the SSU 3 to the SSM 13 (FIG. 14: step S21).

  The SSM 13 starts transferring the data stored in the SSU 3 to the main memory 12 (step S23). The SSM 13 determines whether the data transfer has been completed (step S25). When the data transfer is not completed (step S25: No route), the process returns to step S25.

  On the other hand, when the data transfer is completed (step S25: Yes route), the SSM 13 issues a read instruction completion report to the CPU 11 (step S27).

  Receiving the completion report of the read command, the CPU 11 issues a write command for writing data read from the SSU 3 and stored in the main memory 12 to the I / O 5a to the channel 14 (step S29).

  The channel 14 starts to transfer the data stored in the main memory 12 to the I / O 5a (step S30). The channel 14 determines whether the data transfer has been completed (step S31). If the data transfer has not been completed (step S31: No route), the processing returns to step S31.

  On the other hand, when the data transfer is completed (step S31: Yes route), the channel 14 issues a write command completion report to the CPU 11 (step S33). Then, the process ends.

  In the case of the above processing, since writing cannot be started until the data reading is completed, the time until the transfer is completed tends to be long. Further, since the data is transferred to the main memory 12, the transfer distance is longer than in the case of the present embodiment.

  Next, the operation of the main unit 1a will be described in more detail with reference to FIGS.

  First, processing executed when the bypass buffer control circuit 100 receives a write command from the SSM 13 will be described with reference to FIG.

  The bypass mode check circuit 102 of the bypass buffer control circuit 100 detects a write command from the SSM 13 (FIG. 15: step S41) and determines whether the bypass mode is valid (step S43). Then, the bypass mode check circuit 102 outputs information indicating the determination result to the data check circuit 104.

  When the bypass mode is not valid (step S43: No route), the data check circuit 104 sets the first switching unit 105 that the bypass mode is not valid. Then, the 1st switching part 105 outputs a write command to the main memory 12, and the writing with respect to the main memory 12 is performed by this (step S45). The bypass buffer control circuit 100 receives a completion report for writing to the main memory 12 (step S47), and stores the received completion report in the arbitration port D (step S49). Then, the process ends.

  On the other hand, when the bypass mode is valid (step S43: Yes route), the data check circuit 104 determines whether the data included in the write command is normal (step S51).

  If the data is not normal (step S51: No route), the data check circuit 104 transmits a write command retransmission request to the SSM 13 (step S53). Then, the process ends.

  On the other hand, when the data is normal (step S51: Yes route), the data check circuit 104 sets the first switching unit 105 that the bypass mode is valid. Then, the first switching unit 105 outputs a write command to the bypass buffer 101. Then, the bypass buffer control circuit 100 stores the set including the MS address and data included in the write command in the bypass buffer 101 with the validity flag being validated (step S55).

  The completion report control circuit 113 determines whether the bypass buffer 101 has a free space (step S57). If there is no space (step S57: No route), the process returns to step S57. On the other hand, when there is a vacancy (step S57: Yes route), the completion report control circuit 113 generates a completion report of writing to the main memory 12 (step S59). Then, the completion report control circuit 113 sets the generated completion report in the arbitration port C (step S61). Then, the process ends.

  Next, processing executed by the second arbitration circuit 112 of the bypass buffer control circuit 100 will be described with reference to FIG.

  First, the second arbitration circuit 112 determines whether data is stored in the arbitration port C (FIG. 16: step S71).

  When data is not stored in the arbitration port C (step S71: No route), the second arbitration circuit 112 determines whether data is stored in the arbitration port D (step S73). If no data is stored in the arbitration port D (step S73: No route), the process ends. On the other hand, when data is stored in the arbitration port D (step S73: Yes route), the process proceeds to step S79.

  When data is stored in the arbitration port C (step S71: Yes route), the second arbitration circuit 112 determines whether data is stored in the arbitration port D (step S75). When data is not stored in the arbitration port D (step S75: No route), the process proceeds to step S81. On the other hand, when data is stored in the arbitration port D (step S75: Yes route), the second arbitration circuit 112 determines whether the arbitration port C has been selected immediately before (step S77).

  When the arbitration port C is selected immediately before (step S77: Yes route), the second arbitration circuit 112 selects the arbitration port D (step S79). Then, the second arbitration circuit 112 outputs the data stored in the arbitration port D. Then, the process ends.

  On the other hand, when the arbitration port C has not been selected immediately before (step S77: No route), the second arbitration circuit 112 selects the arbitration port C (step S81). Then, the second arbitration circuit 112 outputs the data stored in the arbitration port C. Then, the process ends.

  Next, processing executed when the bypass buffer control circuit 100 receives a read command from the channel 14 will be described with reference to FIGS. 17 and 18.

  First, the bypass mode check circuit 103 detects a read command from the channel 14 (FIG. 17: step S91) and determines whether the bypass mode is valid (step S93).

  When the bypass mode is not valid (step S93: No route), the bypass mode check circuit 103 sets the second switching unit 106 that the bypass mode is not valid. Then, the 2nd switching part 106 outputs a read command to the main memory 12, and the read from the main memory 12 is performed by this (step S95). The bypass buffer control circuit 100 receives the data read from the main memory 12 (step S97), and stores the received data in the arbitration port B (step S99). Then, the processing shifts to the description of FIG.

  On the other hand, when the bypass mode is valid (step S93: Yes route), the bypass mode check circuit 103 sets the second switching unit 106 that the bypass mode is valid. Then, the second switching unit 106 outputs the read command to the bypass request queue 108, and the bypass buffer control circuit 100 stores the read command at the end of the bypass request queue 108 (step S101).

  The bypass request queue control circuit 107 determines whether the bypass request port 109 is empty (step S103). If the bypass request port 109 is not empty (step S103: No route), the process returns to step S103.

  On the other hand, when the bypass request port 109 is empty (step S103: Yes route), the bypass request queue control circuit 107 stores the read instruction at the head of the bypass request queue 108 in the bypass request port 109 (step S105).

  The bypass buffer control circuit 100 determines whether the arbitration port A is empty (step S107). If the arbitration port A is not empty (step S107: No route), the process returns to step S107. On the other hand, when the arbitration port A is empty (step S107: Yes route), the process proceeds to step S109 in FIG.

  Shifting to the description of FIG. 18, the address comparison circuit 110 determines whether the MS address included in the read instruction stored in the bypass request port 109 exists in the bypass buffer 101 (FIG. 18: step S109).

  When the MS address included in the read instruction stored in the bypass request port 109 does not exist in the bypass buffer 101 (step S111: No route), the address comparison circuit 110 is included in the read instruction stored in the bypass request port 109. The bypass request queue control circuit 107 is notified that the MS address does not exist in the bypass buffer 101. In response to this, the bypass request queue control circuit 107 takes out the read instruction stored in the bypass request port 109 and stores it at the end of the bypass request queue 108 (step S113). Then, the process proceeds to step S119.

  On the other hand, when the MS address included in the read instruction stored in the bypass request port 109 exists in the bypass buffer 101 (step S111: Yes route), the address comparison circuit 110 bypasses the data corresponding to the detected MS address and the bypass. Information indicating the return destination channel stored in the request port 109 is stored in the arbitration port A (step S115).

  The address comparison circuit 110 resets the validity flag of the data corresponding to the detected MS address (for example, sets it to invalid) (step S117), and empties the bypass request port 109 for the bypass request queue control circuit 107. Make a notification. In response to this, the bypass request queue control circuit 107 empties the bypass request port 109 (step S119).

  The bypass request queue control circuit 107 determines whether a request remains in the bypass request queue 108 (step S121). When the request remains (step S121: Yes route), the process returns to step S103 to process the next request. On the other hand, when no request remains in the bypass request queue 108 (step S121: No route), the process ends.

  Next, processing executed by the first arbitration circuit 111 of the bypass buffer control circuit 100 will be described with reference to FIG.

  First, the first arbitration circuit 111 determines whether data is stored in the arbitration port A (FIG. 19: step S131).

  When data is not stored in the arbitration port A (step S131: No route), the first arbitration circuit 111 determines whether data is stored in the arbitration port B (step S133). If no data is stored in the arbitration port B (step S133: No route), the process ends. On the other hand, when data is stored in the arbitration port B (step S133: Yes route), the process proceeds to step S139.

  When data is stored in the arbitration port A (step S131: Yes route), the first arbitration circuit 111 determines whether data is stored in the arbitration port B (step S135). When data is not stored in the arbitration port B (step S135: No route), the process proceeds to step S141. On the other hand, when data is stored in the arbitration port B (step S135: Yes route), the first arbitration circuit 111 determines whether the arbitration port A has been selected immediately before (step S137).

  When the arbitration port A is selected immediately before (step S137: Yes route), the first arbitration circuit 111 selects the arbitration port B (step S139). Then, the first arbitration circuit 111 outputs the data stored in the arbitration port B. Then, the process ends.

  On the other hand, when the arbitration port A has not been selected immediately before (step S137: No route), the first arbitration circuit 111 selects the arbitration port A (step S141). Then, the first arbitration circuit 111 outputs the data stored in the arbitration port A. Then, the process ends.

  The reduction of the data transfer time will be described with reference to FIGS. FIG. 20 is a sequence diagram when the transfer method of the present embodiment is used, and FIG. 21 is a sequence diagram when a known transfer method is used. 20 and 21, the vertical axis represents time (unit is period). “MEM” represents main memory, and “CH” represents channel. The circle graphic represents the start of the instruction sequence, the triangle graphic represents the data to be transferred, the dashed line represents the sequence for the read command, and the solid line represents the sequence for the write command. The numbers in parentheses in FIG. 20 correspond to the numbers shown in FIGS. 5A to 8.

  As shown in FIG. 20, the CPU 11 first issues a read command from the SSU 3 to the SSM 13 (1). The SSM 13 issues a read instruction completion report from the SSU 3 to the CPU 11 (4) and issues a read instruction from the SSU 3 to the SSU 3 (6). The SSM 13 receives the data read from the SSU 3 (7). Then, the SSM 13 issues a data write command read from the SSU 3 to the MCU 10 with the bypass mode enabled (8). The MCU 10 issues a write completion report to the SSM 13 (12). Finally, the sequence for the read instruction is completed in 5 cycles.

  On the other hand, the sequence for the write command starts when the CPU 11 receives a completion report (that is, when two cycles are completed). First, the CPU 11 issues a write command for the I / O 5a to the channel 14 with the bypass mode enabled (5). The channel 14 issues a read command from the main memory 12 to the MCU 10 with the bypass mode enabled (16). The MCU 10 transmits the data stored in the bypass buffer 101 to the channel 14 (21). The channel 14 writes the data received from the MCU 10 to the I / O 5a (23). The channel 14 receives a write completion report from the I / O 5a (24), and issues a write completion report for the I / O 5a to the CPU 11 (25).

  On the other hand, when not using the method of this Embodiment, it is as follows. That is, as shown in FIG. 21, first, the CPU 11 issues a read command from the SSU 3 to the SSM 13 (a). The SSM 13 issues a read command from the SSU 3 to the SSU 3 (b). The SSM 13 receives the data read from the SSU 3 (c) and issues a write command for writing the received data to the main memory 12 to the MCU 10 (d). The MCU 10 writes data to the main memory 12 according to the write command (e). When the MCU 10 confirms that data has been written to the main memory 12 (f), it issues a write completion report to the SSM 13 (g). The SSM 13 issues a read completion report of the SSU 3 to the CPU 11 (h). Thus, the sequence for the read instruction is completed in 8 cycles.

  When the sequence for the read command is completed, the CPU 11 issues a write command for the I / O 5a to the channel 14 (i). The channel 14 issues a read command from the main memory 12 to the MCU 10 to obtain the data read from the SSU 3 (j). The MCU 10 reads data from the main memory 12 (k), and transmits the read data to the channel 14 (l). The channel 14 writes the received data to the I / O 5a (m), and receives a write completion report from the I / O 5a (n). The channel 14 issues a write completion report to the CPU 11 (o). Thus, the sequence for the write instruction is completed in 16 cycles. Therefore, if the method of this embodiment is used, the time until transfer is completed can be reduced to about ½.

  Although one embodiment of the present invention has been described above, the present invention is not limited to this. For example, the configuration of the main body device 1a described above may not match the actual hardware module configuration.

  In addition, the data holding configuration described above is an example, and the above configuration is not necessarily required. Further, in the processing flow, the processing order can be changed if the processing result does not change. Further, it may be executed in parallel.

  Further, the storage device that stores the transfer source data may not be shared. In that case, the number of main body devices may be one.

  Further, even when data is transferred from the I / O 5a or I / O 5b to the SSU 3, it can be dealt with by applying this embodiment.

  The embodiment of the present invention described above is summarized as follows.

  The information processing apparatus according to the first aspect of the present embodiment includes (A) a processor, (B) a main memory, (C) a first control circuit, (D) a second control circuit, and (E). And a third control circuit. The first control circuit (c1) determines whether the first read instruction received from the processor for reading data from the first storage device connected to the information processing device includes predetermined information. And (c2) when the first determination unit determines that the first read instruction includes predetermined information, a completion report indicating that the reading is completed is transmitted to the processor before the reading is completed. And a first transmitter that transmits a first write command for writing the read data to the main memory, including data read from the first storage device and predetermined information, to the third control circuit. The second control circuit determines (d1) whether the second write command received from the processor for writing data to the second storage device connected to the information processing device includes predetermined information. And (d2) if the second determination unit determines that the second write command includes predetermined information, a third read command for reading data including the predetermined information from the main memory is And a second transmitter for transmitting to the control circuit. The third control circuit stores (e1) the first write command in the first storage area of the third control circuit when the first write command received from the first control circuit includes predetermined information. And (e2) a second storage that stores the second read instruction in the second storage area of the third control circuit when the second read instruction received from the second control circuit includes predetermined information. A processing unit; (e3) an address of the main memory included in the first write instruction stored in the first storage area; and an address of the main memory included in the second read instruction stored in the second storage area. If they coincide with each other, a third transmission unit is provided for reading data stored in the first storage area and transmitting the data to the second control circuit.

  In this way, since reading and writing can be performed in parallel, the time required to transfer data from the first storage device to the second storage device can be shortened. In addition, the existing instruction flow executed by the processor can be maintained.

  The second control circuit may further include (d3) a writing unit that receives data from the third control circuit and writes the received data to the second storage device. Thereby, data transfer can be completed.

  The first storage processing unit stores (e11) data included in the received first write instruction in the main memory when the first write instruction received from the first control circuit does not include predetermined information. The second storage processing unit reads (e21) data from the main memory according to the second read command when the second read command received from the second control circuit does not include predetermined information, and the third transmission unit ( e31) The data read from the main memory may be transmitted to the second control circuit. A normal transfer method using the main memory can also be supported.

  Further, the third transmission unit (e32), when both the data stored in the first storage area and the data read from the main memory exist, which is transmitted next based on which was transmitted last time. You may decide to do it. It is possible to suppress transmission of only one of them.

  The information processing system according to the second aspect of the present embodiment includes (F) an information processing device, (G) a first storage device connected to the information processing device, and (H) connected to the information processing device. And a second storage device. The information processing apparatus includes (f1) a processor, (f2) main memory, (f3) first control circuit, (f4) second control circuit, and (f5) third control circuit. The first control circuit includes (f31) a first determination unit that determines whether the first read instruction received from the processor for reading data from the first storage device includes predetermined information; When the first determination unit determines that one read instruction includes predetermined information, a completion report indicating that the read is completed is transmitted to the processor before the read is completed, and the read data and And a first transmitter that transmits a first write command for writing the read data to the main memory including predetermined information to the third control circuit. The second control circuit includes (f41) a second determination unit that determines whether the second write instruction received from the processor for writing data to the second storage device includes predetermined information; and (f42). When the second determination unit determines that the second write command includes predetermined information, a second read command for reading data from the main memory including the predetermined information is transmitted to the third control circuit. And a transmission unit. The third control circuit stores (f51) the first write command in the first storage area of the third control circuit when the first write command received from the first control circuit includes predetermined information. And (f52) a second storage that stores the second read command in the second storage area of the third control circuit when the second read command received from the second control circuit includes predetermined information. A processing unit; (f53) an address of the main memory included in the first write instruction stored in the first storage area; and an address of the main memory included in the second read instruction stored in the second storage area. And a third transmission unit that transmits data to the second control circuit when they match.

  In the control circuit of the information processing device according to the third aspect of the present embodiment, (I) a read command received from the processor for reading data from the first storage device connected to the information processing device is predetermined. And (J) if the determination unit determines that the read instruction includes predetermined information, a completion report indicating that the read is completed is sent to the processor before the read is completed. A transmission unit for transmitting to the network.

  The control circuit according to the fourth aspect of the present embodiment includes (K) a write command when the write command for writing data to the main memory further includes predetermined information when the write command includes data. And a second storage for storing the read instruction in the second storage area of the control circuit when the read instruction for reading data from the main memory includes predetermined information. When the processing unit and (L) the address of the main memory included in the write instruction stored in the first storage area match the address of the main memory included in the read instruction stored in the second storage area, A transmission unit that reads data stored in the first storage area and transmits the data;

  A program for causing the processor to perform the processing according to the above method can be created, and the program can be a computer-readable storage medium such as a flexible disk, a CD-ROM, a magneto-optical disk, a semiconductor memory, a hard disk, or the like. It is stored in a storage device. The intermediate processing result is temporarily stored in a storage device such as a main memory.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Appendix 1)
A processor;
Main memory,
A first control circuit;
A second control circuit;
A third control circuit;
An information processing apparatus having
The first control circuit includes:
A first determination unit that determines whether or not a first read command received from the processor for reading data from a first storage device connected to the information processing device includes predetermined information;
When the first determination unit determines that the first read instruction includes the predetermined information, a completion report indicating that the read is completed is transmitted to the processor before the read is completed, and the A first transmission unit configured to transmit a first write command including the data read from the first storage device and the predetermined information to write the read data to the main memory to the third control circuit; Have
The second control circuit includes:
A second determination unit that determines whether a second write command for writing the data to the second storage device connected to the information processing device received from the processor includes the predetermined information;
When the second determination unit determines that the second write instruction includes the predetermined information, a second read instruction for reading the data including the predetermined information from the main memory is the third A second transmitter for transmitting to the control circuit;
Have
The third control circuit includes:
A first storage processing unit that stores the first write command in a first storage area of the third control circuit when the first write command received from the first control circuit includes the predetermined information; ,
A second storage processing unit for storing the second read command in a second storage area of the third control circuit when the second read command received from the second control circuit includes the predetermined information;
The address of the main memory included in the first write instruction stored in the first storage area matches the address of the main memory included in the second read instruction stored in the second storage area A third transmitter for reading the data stored in the first storage area and transmitting the data to the second control circuit;
An information processing apparatus.

(Appendix 2)
The second control circuit includes:
The information processing apparatus according to claim 1, further comprising: a writing unit that receives the data from the third control circuit and writes the received data to the second storage device.

(Appendix 3)
The first storage processing unit
When the first write command received from the first control circuit does not include the predetermined information, the data included in the received first write command is stored in the main memory;
The second storage processing unit
When the second read command received from the second control circuit does not include the predetermined information, the data is read from the main memory according to the second read command,
The third transmitter is
Transmitting the data read from the main memory to the second control circuit;
The information processing apparatus according to attachment 1 or 2.

(Appendix 4)
The third transmitter is
If both the data stored in the first storage area and the data read from the main memory exist, determine which to transmit next based on which was transmitted last time;
The information processing apparatus according to attachment 3.

(Appendix 5)
An information processing device;
A first storage device connected to the information processing device;
A second storage device connected to the information processing device;
An information processing system having
The information processing apparatus includes:
A processor;
Main memory,
A first control circuit;
A second control circuit;
A third control circuit;
Have
The first control circuit includes:
A first determination unit that determines whether a first read instruction received from the processor for reading data from the first storage device includes predetermined information;
When the first determination unit determines that the first read instruction includes the predetermined information, a completion report indicating that the read is completed is transmitted to the processor before the read is completed, and the read A first transmission unit configured to transmit a first write command for writing the read data to the main memory including the issued data and the predetermined information to the third control circuit; ,
The second control circuit includes:
A second determination unit that determines whether a second write command received from the processor for writing the data to the second storage device includes the predetermined information;
When the second determination unit determines that the second write instruction includes the predetermined information, a second read instruction for reading the data including the predetermined information from the main memory is the third A second transmitter for transmitting to the control circuit;
Have
The third control circuit includes:
A first storage processing unit that stores the first write command in a first storage area of the third control circuit when the first write command received from the first control circuit includes the predetermined information; ,
A second storage processing unit for storing the second read command in a second storage area of the third control circuit when the second read command received from the second control circuit includes the predetermined information;
The address of the main memory included in the first write instruction stored in the first storage area matches the address of the main memory included in the second read instruction stored in the second storage area A third transmitter for transmitting the data to the second control circuit;
An information processing system having

(Appendix 6)
The control circuit of the information processing apparatus having a processor and a control circuit,
A determination unit that determines whether a read command received from the processor for reading data from a first storage device connected to the information processing device includes predetermined information;
When the determination unit determines that the read instruction includes the predetermined information, a transmission unit that transmits a completion report indicating that the read is complete to the processor before the read is completed;
A control circuit.

(Appendix 7)
The control circuit of the information processing apparatus having a processor, a main memory, and a control circuit,
A first storage processing unit for storing the write instruction in a first storage area of the control circuit, when the write instruction for writing the data to the main memory further includes predetermined information; ,
A second storage processing unit that stores the read command in a second storage area of the control circuit when a read command for reading the data from the main memory includes the predetermined information;
When the address of the main memory included in the write instruction stored in the first storage area matches the address of the main memory included in the read instruction stored in the second storage area, A transmitter that reads the data stored in the first storage area and transmits the data;
A control circuit.

1a, 1b Main unit 3 SSU
5a, 5b I / O 10 MCU
11 CPU 12 Main memory 13 SSM 14 Channel 13p Packet control circuit 13t Data transfer circuit 13m Memory 130 Bypass control circuit 1301 Bypass mode check unit 1302 Advance flag 131 Input packet analysis unit 132 Write control circuit 133 Completion report control circuit 134 Output packet generation 14p packet control circuit 14t data transfer circuit 14m memory 14e program execution circuit 140 bypass control circuit 1401 bypass mode check unit 1402 bypass execution flag 141 input packet analysis unit 142 read control circuit 143 completion report control circuit 144 output packet generation unit 100 bypass buffer Control circuit 101 Bypass buffer 102, 103 Bypass mode check circuit 104 Data check circuit 105 First Replacement unit 106 Second switching unit 107 Bypass request queue control circuit 108 Bypass request queue 109 Bypass request port 110 Address comparison circuit 111 First arbitration circuit 112 Second arbitration circuit 113 Completion report control circuits 150a, 150b, 150c, 150d, 150e, 150f packet control circuit

Claims (6)

A processor;
Main memory,
A first control circuit;
A second control circuit;
A third control circuit;
An information processing apparatus having
The first control circuit includes:
A first determination unit that determines whether or not a first read command received from the processor for reading data from a first storage device connected to the information processing device includes predetermined information;
When the first determination unit determines that the first read instruction includes the predetermined information, a completion report indicating that the read is completed is transmitted to the processor before the read is completed, and the A first transmission unit configured to transmit a first write command including the data read from the first storage device and the predetermined information to write the read data to the main memory to the third control circuit; Have
The second control circuit includes:
A second determination unit that determines whether a second write command for writing the data to the second storage device connected to the information processing device received from the processor includes the predetermined information;
When the second determination unit determines that the second write instruction includes the predetermined information, a second read instruction for reading the data including the predetermined information from the main memory is the third A second transmitter for transmitting to the control circuit;
Have
The third control circuit includes:
A first storage processing unit that stores the first write command in a first storage area of the third control circuit when the first write command received from the first control circuit includes the predetermined information; ,
A second storage processing unit for storing the second read command in a second storage area of the third control circuit when the second read command received from the second control circuit includes the predetermined information;
The address of the main memory included in the first write instruction stored in the first storage area matches the address of the main memory included in the second read instruction stored in the second storage area A third transmitter for reading the data stored in the first storage area and transmitting the data to the second control circuit;
An information processing apparatus. The second control circuit includes:
The information processing apparatus according to claim 1, further comprising: a writing unit that receives the data from the third control circuit and writes the received data to the second storage device. The first storage processing unit
When the first write command received from the first control circuit does not include the predetermined information, the data included in the received first write command is stored in the main memory;
The second storage processing unit
When the second read command received from the second control circuit does not include the predetermined information, the data is read from the main memory according to the second read command,
The third transmitter is
Transmitting the data read from the main memory to the second control circuit;
The information processing apparatus according to claim 1 or 2. The third transmitter is
If both the data stored in the first storage area and the data read from the main memory exist, determine which to transmit next based on which was transmitted last time;
The information processing apparatus according to claim 3. The control circuit of the information processing apparatus having a processor and a control circuit,
A determination unit that determines whether a read command received from the processor for reading data from a first storage device connected to the information processing device includes predetermined information;
When the determination unit determines that the read instruction includes the predetermined information, a transmission unit that transmits a completion report indicating that the read is complete to the processor before the read is completed;
A control circuit. The control circuit of the information processing apparatus having a processor, a main memory, and a control circuit,
A first storage processing unit for storing the write instruction in a first storage area of the control circuit, when the write instruction for writing the data to the main memory further includes predetermined information; ,
A second storage processing unit that stores the read command in a second storage area of the control circuit when a read command for reading the data from the main memory includes the predetermined information;
When the address of the main memory included in the write instruction stored in the first storage area matches the address of the main memory included in the read instruction stored in the second storage area, A transmitter that reads the data stored in the first storage area and transmits the data;
A control circuit.

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