JP2005182485A - Serial transmission controller, computer system, and serial transmission control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the versatility of inter-device wiring by enabling to freely establish a logical lane number and to suppress a decrease in performance when a failure is caused in a plurality of lanes. <P>SOLUTION: The link control circuit 13 of a serial transmission controller 1D manages the training (initialization) of a link and the state of each lane. A lane control circuit 11 decides its defined logical lane number based on the state (the presence or absence of the failure) of each lane from the link control circuit 13 and the receiving logical lane number of a serial transmission controller 2E at a connection destination, and automatically re-assigns the logical lane number for the usable lane only in encountering the failure. A crossbar circuit 10 receives the defined logical lane number generated from the lane control circuit 11 to convert the defined logical lane number into any physical lane number. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a serial transmission control device, a computer system, and a serial transmission control method, and more particularly to a serial transmission control device, a computer system, and a serial transmission control method that can freely set logical lane numbers.

  A conventional serial transmission control device, particularly PCI Express, will be described with reference to the drawings.

  FIG. 5 is a block diagram illustrating a configuration example of a x4 PCI Express.

PCI Express is a communication standard between apparatuses, and supports x1, x2, x4, x8, x12, x16, and x32 (links in which a number of lanes are bundled). (Example: In the case of x16, a link that bundles 16 lanes)
Referring to FIG. 5, a serial transmission control device 1A (physical layer) on the upstream side and a serial transmission control device 2B (physical layer) on the downstream side are connected by a PCI Express of x4. Here, for example, in the personal computer, the upstream side is a part close to the main processor on which the operating system operates, and the downstream side is a part close to the peripheral device.

  As a method of assigning logical lane numbers to physical lane numbers of PCI Express, a method of assigning logical lane numbers in the order of physical lane numbers (logical lane numbers 0, 1, 2, 3 are assigned to physical lane numbers 0, 1, 2, 3). 5) and the method of inverting the logical lane number (assigning logical lane numbers 3, 2, 1, 0 to physical lane numbers 0, 1, 2, 3; right of FIG. 5). .

  The method of reversing the logical lane number is used as a workaround in the case of a lane failure or when the logical lane number of the connected device is reversed. Assignment control is performed by the link control circuit 3C.

  When a lane failure occurs, the link control circuit 3C performs link retraining and link reconfiguration. FIG. 5 shows a case where a failure has occurred in physical lane number 1. A method of using as x1 (physical lane number 0, logical lane number 0) without changing the logical lane number, and inverting the logical lane number to x2 (logical lane numbers 1, 0 in physical lane numbers 2, 3) In the example of FIG. 5, x2 with the logical lane number inverted is selected from the viewpoint of performance.

  In addition, there is a technique for controlling the correspondence between a logical port and a physical port using a virtual port identification address (for example, Patent Document 1).

Special table 2003-504961

  Conventionally, the physical lane number and logical lane number of each lane are fixedly assigned. Therefore, if a failure occurs in a lane (logical lane number 0) that is essential for link configuration according to the PCI Express specification, There was a problem that links could not be used even though there were usable lanes. As a workaround, the function to invert the logical lane number (eg, when the logical lane number 0, 1, 2, 3 is assigned to the physical lane number 0, 1, 2, 3 in the 4-lane configuration link, the inversion function is (If used, the logical lane number will be 3, 2, 1, 0). However, it has the same problem, and even if the first failure can be saved, the link cannot be used due to the second failure. There was a possibility. If a failure occurs in a lane (logical lane number 0) that is indispensable for configuring a link, the link becomes unusable.

  As described above, there are only two types of PCI Express logical lane number assignment methods, normal and inverted. When a failure occurs in two lanes, the youngest number and the oldest physical lane number that can be logical lane number 0, Even if other usable lanes remain, the link becomes unusable.

  Furthermore, since the physical lane number and the logical lane number of the lane are fixedly assigned, the pins of each device are also fixed, and the wiring between the devices is limited.

  In addition, the technique described in Patent Document 1 does not disclose an efficient function for reassigning logical lane numbers at the time of failure.

  An object of the present invention is to increase the degree of freedom of inter-device wiring by making it possible to freely set logical lane numbers, and to suppress performance degradation when a failure occurs in a plurality of lanes.

  The first serial transmission control device according to the present invention logically stores all the valid lanes except for the invalid lane indicated by the lane valid flag and the invalid lane indicated by the lane valid flag. And a control circuit assigned to the lane.

  The second serial transmission control device of the present invention includes a lane valid flag for storing a bit indicating validity / invalidity of each physical lane, a value of the lane valid flag, a function of a connection destination device, and the connection destination. And a control circuit that allocates all the valid lanes except the invalid physical lane indicated by the lane valid flag to the logical lane based on whether it is upstream or downstream of itself.

  The third serial transmission control device of the present invention includes a lane valid flag for storing a bit indicating validity / invalidity of each physical lane, and “logical lane number = number of valid flags (number of target physical lane number or less) −1. And a control circuit that allocates all the valid lanes except the invalid physical lane indicated by the lane valid flag to the logical lane based on the algorithm of "."

  The fourth serial transmission control device of the present invention includes a lane valid flag for storing a bit indicating validity / invalidity of each physical lane, a value of the lane valid flag, a function of a connection destination device, and the connection destination. Only the invalid physical lane indicated by the lane valid flag based on whether it is upstream or downstream from itself and based on the algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1” And a control circuit that allocates all effective lanes except for to logical lanes.

  The fifth serial transmission control device according to the present invention is a reception device corresponding to a physical lane that stores a lane validity flag for storing a bit indicating validity / invalidity of each physical lane and a logical lane number for reception from a connected device. Logical lane number register and a logical lane number register for transmission corresponding to a physical lane that stores a logical lane number for transmission based on an algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1” And stores the value of the logical lane number register for reception or the value of the logical lane number register for transmission based on the function of the connection destination device and whether the connection destination is upstream or downstream of itself. And a definite logical lane number register corresponding to the physical lane.

  A sixth serial transmission control device of the present invention receives a reception logical lane number from a connection destination device, and transmits a transmission logical lane number to the connection destination device, and the validity of each physical lane. A lane valid flag for storing a bit indicating invalidity, a reception logical lane number register corresponding to a physical lane for storing a reception logical lane number from the transmission logical lane number, and “logical lane number = number of valid flags” Based on the algorithm of (number of target physical lane number or less) -1 ", the transmission logical lane number register corresponding to the physical lane for storing the transmission logical lane number, the function of the connection destination device, and the connection destination Based on whether it is upstream or downstream from itself, either the value of the reception logical lane number register or the value of the transmission logical lane number register is determined. A lane control circuit including a defined logical lane number register corresponding to the physical lane stored as a signal, and a crossbar circuit that performs data transfer based on the determined logical lane number from the lane control circuit. .

  The computer system of the present invention is characterized in that it includes one or more of the first, second, third, fourth, fifth, and sixth serial transmission control devices.

  According to the first serial transmission control method of the present invention, the serial transmission control device stores all valid lanes except for the invalid physical lane indicated by the lane valid in which the bit indicating the validity / invalidity of each physical lane is stored. Including the step of assigning to.

  In the second serial transmission control method of the present invention, the serial transmission control device has a value of a lane valid flag for storing a bit indicating validity / invalidity of each physical lane, a function of a connection destination device, and the connection destination The method includes a step of allocating all valid lanes excluding only invalid physical lanes indicated by the lane valid flag to logical lanes based on whether they are upstream or downstream.

  In the third serial transmission control method of the present invention, the serial transmission control device stores a lane valid flag for storing a bit indicating validity / invalidity of each physical lane, “logical lane number = number of valid flags (subject physical lane number or less). The method includes a step of allocating all valid lanes excluding only invalid physical lanes indicated by the lane valid flag to logical lanes based on an algorithm of “number of -1)”.

  According to a fourth serial transmission control method of the present invention, a serial transmission control device stores a lane validity flag for storing a bit indicating validity / invalidity of each physical lane, a value of the lane validity flag, a function of a connection destination device, and Based on whether the connection destination is upstream or downstream from itself and indicated by the lane valid flag based on an algorithm of “logical lane number = number of valid flags (number of target physical lane numbers) −1”. Assigning all valid lanes except logical physical lanes to logical lanes.

  According to a fifth serial transmission control method of the present invention, the serial transmission control device stores a bit indicating validity / invalidity of each physical lane in a lane validity flag and is connected to a reception logical lane number register corresponding to the physical lane. The step of storing the logical lane number for reception from the previous device, and the algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1” in the transmission logical lane number register corresponding to the physical lane−1 Storing the logical lane number for transmission based on the above, in the fixed logical lane number register corresponding to the physical lane, based on the function of the connection destination device, and whether the connection destination is upstream or downstream from itself, Storing either the value of the reception logical lane number register or the value of the transmission logical lane number register. To.

  According to a sixth serial transmission control method of the present invention, the link control circuit receives a reception logical lane number from a connection destination device, and transmits the transmission logical lane number to the connection destination device. The circuit stores the bits indicating the validity / invalidity of each physical lane in the lane validity flag, and the lane control circuit receives the logical lane number for reception from the connected device in the logical lane number register for reception corresponding to the physical lane. And the lane control circuit uses the transmission logical lane number register corresponding to the physical lane for transmission based on an algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1”. The step of storing the logical lane number and the lane control circuit store the function of the connected device in the determined logical lane number register corresponding to the physical lane. And storing either the value of the logical lane number register for reception or the value of the logical lane number register for transmission based on whether the connection destination is upstream or downstream of itself, a crossbar circuit, and the lane control circuit And transferring data based on the determined logical lane number from

  The first effect of the present invention is that it is possible to suppress a decrease in performance when a failure occurs in a plurality of lanes.

  This is because the logical lane number can be freely assigned to the physical lane number.

  The second effect is that wiring between devices can be performed freely, and it is also a workaround when a wiring mistake occurs.

  This is also because the logical lane number can be freely assigned to the physical lane number.

  Next, a first best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the first best mode for carrying out the present invention.

  Referring to FIG. 1, an upstream serial transmission control device 1D and a downstream serial transmission control device 2E are connected by a serial link. The serial transmission control device 1D includes a crossbar circuit 10, a lane control circuit 11, and a link control circuit 13. The serial transmission control device 2E includes a link control circuit 13.

  The crossbar circuit 10 uses each logical lane number determined by the lane control circuit 11 to associate the logical lane number with the physical lane number and transfers data. The link control circuit 13 performs serial link training (initialization) and status monitoring, and reports the connection destination logical lane number and the status of each lane (whether there is a failure) to the lane control circuit 11.

  The lane control circuit 11 uses the information received from the link control circuit 13 and considers whether or not the connection destination is a conventional device. When the devices having the functions of the present invention are connected, the lane control circuit 11 11 determines the logical lane number for the physical lane number in consideration of the upstream side and the downstream side.

  Here, with the conventional device, there are only two types of logical lane number assignment methods, normal and inverted, and there is a failure in two lanes of the physical lane number of the youngest number and the oldest number that can be logical lane number 0. When this happens, the link becomes unavailable even if other usable lanes remain.

  If a failure is reported from the link control circuit 13, the lane control circuit 11 refers to each bit (described later) of the built-in lane valid flag 20 and reassigns the lane number using only valid lanes. To do.

  Next, the detailed configuration of the lane control circuit 11 will be described with reference to the drawings.

  FIG. 2 is a block diagram showing a detailed configuration of the lane control circuit 11 of FIG.

  Referring to FIG. 2, the lane control circuit 11 of the serial transmission control device 1D determines the lane valid flag 20 and the logical lane number register 21 for reception and the logical lane number register 22 for reception corresponding to the physical lane, respectively. A selection circuit 24 that selects one of the output of the logical lane number register 23, the output of the transmission logical lane number register 21, and the output of the reception logical lane number register 22, the output of the transmission logical lane number register 21, and the determined logical lane And a selection circuit 25 that houses either of the outputs of the number register 23. Further, a control circuit (not shown) exists, and executes control including transfer of values of the lane valid flag 20, the transmission logical lane number register 21, and the reception logical lane number register 22.

  The lane valid flag 20 indicates whether or not each physical lane can be used, and a logical lane number is generated only for the usable lane and stored in the transmission logical lane number register 21. As a method of generating a logical lane number, there is a method of calculating from the effective number of physical lanes that are younger than the own physical lane number. For example, when assigning a logical lane number to physical lane number 2, if the valid flag for physical lane 0 is valid for lane 0 and the valid flag for physical lane 1 is invalid, the logical lane for physical lane 2 As the number, “1” is assigned, and when both physical lanes 0 and 1 are valid, “2” is assigned as a logical number, and when both are invalid, “0” is assigned as a logical number.

  The lane valid flags 20 are all “1” (Bit 0-3 = “1111”) when the power is turned on (initial), and when a lane failure is detected during link training or data communication. Bit of the faulty lane is turned off ("1" to "0"). In the transmission logical lane number register 21, the logical lane number assigned using the lane valid flag 20 is constantly updated and stored. That is, when the value of the lane valid flag 20 is updated, the value of the transmission logical lane number register 21 is also updated at the same time. A lane failure is detected by the link control circuit 13, and when it is detected, retraining of the link is started, and the logical lane number is reset using the updated value.

  Allocation of logical lane numbers to the transmission logical lane number register 21 is performed in order from the smallest physical lane number, and the logical numbers are in order of 0, 1, 2, 3,. Is not assigned to invalid lanes.

  Logically, <logical lane number (physical lane number) = number of valid flags (number of target physical lane number or less) -1>.

  For example, (1) when the lane valid flag 20 is Bit0-3 = 1111, the transmission logical lane number register 21 stores the following values.

  <Physical lane 0 → logical lane number = 1 (bit 0) −1 = 0>, <physical lane 1 → logical lane number = 2 (bit 0: bit 1) −1 = 1>, <physical lane 2 → logical lane number = 3 (Bit0: Bit1: Bit2) -1 = 2>, <physical lane 3 → logical lane number = 4 (Bit0: Bit1: Bit2: Bit3) -1 = 3>.

  Further, (2) when the lane valid flag 20 is Bit0-3 = 1101 (Bit2: a failure occurs in the lane 2 and is off), the transmission logical lane number register 21 stores the following values.

  <Physical lane 0 → logical lane number = 1 (bit 0) −1 = 0>, <physical lane 1 → logical lane number = 2 (bit 0: bit 1) −1 = 1>, <physical lane 2 → logical lane number = (No assignment because Bit2 = 0)>, <Physical Lane 3 → Logical Lane Number = 3 (Bit0: Bit1: Bit3) -1 = 2>.

  FIG. 3 is an explanatory diagram of an example of logical lane number reallocation.

  Referring to FIG. 3, a failure occurs in the connection between the physical lane 0 of the serial transmission control device 1D and the physical lane 2 of the serial transmission control device 2E, and the logical lane number is reassigned.

  The reception logical lane number register 22 stores the logical lane number received from the connected serial transmission control device 2E. The transmission logical lane number register 21 stores the logical lane number to the connection destination serial transmission control device 2E, and the reception logical lane number register 22 stores the logical lane number received from the connection destination serial transmission control device 2E. Store.

  In determining the fixed logical lane number stored in the fixed logical lane number register 23, it is considered whether or not the serial transmission control device 2E to be connected is a conventional serial transmission control device. When serial transmission control devices having the same function are connected to each other, it is determined whether they are upstream or downstream, and the logical lane number selected as a result is stored in the confirmed logical lane number register 23. The confirmed logical lane number in the confirmed logical lane number register 23 is transmitted to the connected serial transmission control device 2E via the crossbar circuit 10 and the link control circuit 13.

  The configuration of the embodiment has been described in detail above, but the link control circuit 13 and the crossbar circuit 10 in FIG. 1 are well known to those skilled in the art, and the detailed configuration is omitted.

Next, the operation of the best mode for carrying out the present invention will be described with reference to the drawings.

  FIG. 4 is a flowchart showing the operation of the best mode for carrying out the present invention.

  Referring to FIG. 4, in order for the serial transmission control device 1D (serial transmission control device 2E) to communicate with the connected serial transmission control device 2E (serial transmission control device 1D), first, the link control circuit 13 Link training is performed (step S1 in FIG. 4).

  Each of the serial transmission control device 1D and the serial transmission control device 2E previously incorporates function information indicating whether or not the device itself is a conventional device (information indicating whether the device does not have the function of the present invention). . In addition, the serial transmission control device 1D and the serial transmission control device 2E incorporate in advance position identification information (for example, serial numbers) for determining upstream and downstream.

  In training, function information and position identification information of a connection destination are acquired.

  Next, the serial transmission control device 1D (serial transmission control device 2E) transmits the value of the transmission logical lane number register 21 of the lane control circuit 11 via the link control circuit 13, and the serial transmission control device of the connection destination The logical lane number sent from 2E (serial transmission control device 1D) is received and stored in the reception logical lane number register 22 of the lane control circuit 11 via the link control circuit 13 (step S2).

  Next, the serial transmission control device 1D (serial transmission control device 2E) is connected to the serial transmission control device 2E (serial transmission control device 1D) as a connection destination. If there is a failure in two lanes, the youngest number and the oldest number of physical lane numbers that can be logical lane number 0, there are only two types of inversion, and the link cannot be used even if other usable lanes remain. It is checked whether it is a device that becomes (step S3). Since a fixed reception logical lane number is sent from the connected serial transmission control device 2E (serial transmission control device 1D), the received logical lane number is set as the confirmed logical lane number (step S5).

  If the connection destination serial transmission control device 2E (serial transmission control device 1D) is not a conventional device (step S3 / No), the serial transmission control device 1D (serial transmission control device 2E) is located at the connection destination. It is checked whether it is upstream from the serial transmission control device 2E (serial transmission control device 1D) (step S4 in FIG. 4).

  When the serial transmission control device 1D (serial transmission control device 2E) is located upstream of the serial transmission control device 2E (serial transmission control device 1D) to which it is connected (step S4 / Yes), the upstream side receives it. If the logical lane number is a confirmed logical lane number (step S6 in FIG. 4), and its own position is on the downstream side of the connection destination serial transmission control device 2E (serial transmission control device 1D) (step S4 / No), The transmission logical lane number (step S7 in FIG. 4) is set as the confirmed logical lane number.

  When a lane failure occurs (step S8), the bit corresponding to the lane in which the failure of the lane valid flag 20 in the lane control circuit 11 occurs is turned off (step S9), and the confirmed logical lane number is re-established only in the usable lane. Allocation is performed (step S10), and link retraining is performed.

  The determination of the confirmed logical lane number in the upstream serial transmission control device 1D is performed in the following order in detail.

  (1) The value in the transmission logical lane number register 21 is transmitted to the downstream serial transmission control device 2E. (2) The logical lane number received from the serial transmission control device 2E is stored in the reception logical lane number register 22. (3) Store the value of the reception logical lane number register 22 in the fixed logical lane number register 23.

The determination of the confirmed logical lane number in the downstream serial transmission control device 2E is performed in the following order in detail.
(1) The logical lane number received from the upstream serial transmission control device 1D is stored in the reception logical lane number register 22. (2) The value of the transmission logical lane number register 21 is transmitted to the serial transmission control device 1D. (3) Store the value of the transmission logical lane number register 21 in the fixed logical lane number register 23.

  Next, a second best mode for carrying out the present invention will be described in detail with reference to the drawings.

  Next, a second best mode for carrying out the present invention is a method including the steps of FIG.

  The serial transmission control device 1D of the present invention can be applied to various computer systems.

It is a block diagram which shows the structure of the 1st best form for implementing this invention. It is a block diagram which shows the detailed structure of the lane control circuit 11 of FIG. It is explanatory drawing which shows one example of reallocation of a logical lane number. It is a flowchart which shows operation | movement of the best form for implementing this invention. It is a block diagram which shows the structural example of PCI Express.

Explanation of symbols

1A Serial transmission control device 1D Serial transmission control device 2B Serial transmission control device 2E Serial transmission control device 3C Link control circuit 10 Crossbar circuit 11 Lane control circuit 13 Link control circuit 20 Lane valid flag 21 Transmission logical lane number register 22 Reception logical Lane number register 23 Deterministic logic lane number register 24 Selection circuit 25 Selection circuit

Claims (13)

A lane valid flag that stores a bit indicating validity / invalidity of each physical lane, and a control circuit that allocates all valid lanes except the invalid physical lane indicated by the lane valid flag to logical lanes. Serial transmission control device. Based on a lane valid flag that stores a bit indicating validity / invalidity of each physical lane, a value of the lane validity flag, a function of a connection destination device, and whether the connection destination is upstream or downstream of itself, the lane And a control circuit for allocating all valid lanes excluding only invalid physical lanes indicated by valid flags to logical lanes. A lane valid flag for storing a bit indicating validity / invalidity of each physical lane, and the lane valid flag based on an algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1”. And a control circuit for allocating all valid lanes except logical invalid lanes to logical lanes. Based on a lane valid flag that stores a bit indicating validity / invalidity of each physical lane, a value of the lane valid flag, a function of a connection destination device, and whether the connection destination is upstream or downstream of itself, and Control that allocates all valid lanes to logical lanes except for invalid physical lanes indicated by the lane valid flag based on the algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1”. A serial transmission control device comprising a circuit. A lane valid flag that stores a bit indicating validity / invalidity of each physical lane, a reception logical lane number register corresponding to a physical lane that stores a reception logical lane number from a connected device, and “logical lane number = valid” The number of flags (number of target physical lane numbers or less) -1 "based on the algorithm for transmission, the logical lane number register for transmission corresponding to the physical lane, the function of the connection destination device, Based on whether the connection destination is upstream or downstream of itself, the logical lane number register for reception and the fixed logical lane number register for the physical lane for storing either the value of the logical lane number register for transmission are included. A serial transmission control device. A link control circuit that receives a reception logical lane number from a connection destination device and transmits a transmission logical lane number to the connection destination device;
A lane valid flag for storing a bit indicating validity / invalidity of each physical lane, a reception logical lane number register corresponding to a physical lane for storing a reception logical lane number from the transmission logical lane number, and a “logical lane number” = Number of valid flags (number of target physical lane numbers or less) -1 "based on the algorithm of the transmission logical lane number register for storing the logical lane number for transmission, the function of the connection destination device, and Based on whether the connection destination is upstream or downstream from itself, either the value of the reception logical lane number register or the value of the transmission logical lane number register is stored as a fixed logical lane number. A lane control circuit comprising a logical lane number register;
A crossbar circuit that performs data transfer based on the determined logical lane number from the lane control circuit;
A serial transmission control device comprising: A computer system comprising one or more serial transmission control devices according to claim 1, 2, 3, 4, 5, or 6. The serial transmission control device includes a step of assigning all valid lanes except logical physical lanes indicated by lane valid to store bits indicating validity / invalidity of each physical lane to logical lanes. Control method. Based on the value of the lane valid flag in which the serial transmission control device stores a bit indicating validity / invalidity of each physical lane, the function of the connection destination device, and whether the connection destination is upstream or downstream of itself A serial transmission control method comprising a step of allocating all valid lanes excluding only invalid physical lanes indicated by a valid flag to logical lanes. The serial transmission control device is based on an algorithm of a lane valid flag for storing a bit indicating validity / invalidity of each physical lane, “logical lane number = number of valid flags (number of target physical lane numbers) −1”. A serial transmission control method comprising a step of allocating all valid lanes excluding only invalid physical lanes indicated by a lane valid flag to logical lanes. The serial transmission control device stores a lane valid flag for storing a bit indicating validity / invalidity of each physical lane, the value of the lane valid flag, the function of the connection destination device, and whether the connection destination is upstream or downstream of itself. And all valid lanes excluding only invalid physical lanes indicated by the lane valid flag based on the algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1”. A serial transmission control method comprising the steps of: assigning to a logical lane. Serial transmission control device
Storing a bit indicating validity / invalidity of each physical lane in a lane validity flag;
Storing the logical lane number for reception from the connected device in the logical lane number register for reception corresponding to the physical lane;
Storing a transmission logical lane number in a transmission logical lane number register corresponding to a physical lane based on an algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1”;
In the determined logical lane number register corresponding to the physical lane, the value of the reception logical lane number register, the transmission logical lane number, based on the function of the connection destination device and whether the connection destination is upstream or downstream from itself Storing either of the register values;
A serial transmission control method comprising: A link control circuit receiving a reception logical lane number from a connection destination device and transmitting a transmission logical lane number to the connection destination device;
A step in which the lane control circuit stores a bit indicating validity / invalidity of each physical lane in a lane validity flag;
A step in which the lane control circuit stores the reception logical lane number from the connection destination device in the reception logical lane number register corresponding to the physical lane;
The lane control circuit stores the transmission logical lane number in the transmission logical lane number register corresponding to the physical lane based on the algorithm of “logical lane number = number of valid flags (number of target physical lane number or less) −1”. Steps,
The lane control circuit determines the value of the reception logical lane number register based on the function of the connection destination device in the fixed logical lane number register corresponding to the physical lane, and whether the connection destination is upstream or downstream from itself. Storing one of the values of the logical lane number register for transmission; and
Crossbar circuit performing data transfer based on the determined logical lane number from the lane control circuit;
A serial transmission control method comprising:

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