JP2017208411A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hinder occurrence of chipping and cracking when a semiconductor wafer is diced.SOLUTION: A plurality of chip areas are arranged on a semiconductor wafer and in a grid pattern according to a relation that ensures a dicing width between adjacent chip areas, and a dicing area is obtained so as to extend straight between adjacent chip areas and reaching an outer periphery of the semiconductor. An alignment mark is formed in an area that belongs neither the chip nor the dicing area in the semiconductor wafer. Processing is performed for the plurality of chip areas by using the alignment mark as a reference for positioning. After the processing, the dicing area is diced into a plurality of chips. By preventing dicing of the alignment mark, occurrence of chipping and cracking can be hindered.SELECTED DRAWING: Figure 3

Description

  The present specification discloses a method for manufacturing a semiconductor device.

  In the manufacturing process of the semiconductor device, the process for the semiconductor wafer is executed in a plurality of times. An alignment mark is formed on a part of the semiconductor wafer in order to prevent a positional shift between the processes. In some cases, a plurality of chips are manufactured from one semiconductor wafer. In this case, a plurality of chip areas are arranged in a grid pattern in accordance with the relationship of securing a dicing width between adjacent chip areas. After the processing on the semiconductor wafer is completed, a dicing area that extends linearly between adjacent chip areas and reaches the outer periphery of the semiconductor wafer is diced. As a result, it is divided into a plurality of chips. Depending on the position where the alignment mark is formed, the number of chips that can be manufactured from one semiconductor wafer decreases. In Patent Document 1, an alignment mark is formed in a dicing region. When the alignment mark is formed in the dicing region, it is possible to prevent the number of chips that can be manufactured from one semiconductor wafer from being reduced by the alignment mark.

JP-A-5-152433

  With the technique disclosed in Patent Document 1, chipping and cracks are likely to occur when dicing a semiconductor wafer, and the manufacturing yield of semiconductor devices is not good. The present specification discloses a technique capable of preventing a reduction in the number of chips that can be manufactured from one semiconductor wafer and suppressing the occurrence of chipping and cracks during dicing.

  The alignment mark is changed to a mark using a step extending along the mark outline by changing the height of the wafer surface outside the mark and the height of the wafer surface inside the mark, or the wafer surface material and mark outside the mark Marking is performed using a material boundary line extending along the mark outline by changing the material of the inner wafer surface. It has been found that if the alignment mark is formed in the dicing area, the step or the material boundary line is cut, and this is likely to cause chipping and cracks. For example, when a step is cut, a stress concentration portion is generated, which may cause chipping or cracking. When the material boundary line is cut, the semiconductor wafer may be damaged by cutting pieces of different materials, which may cause chipping or cracks.

  Therefore, a manufacturing method has been created in which the alignment mark is not diced and the number of chips that can be manufactured from one semiconductor wafer is not reduced by the alignment mark.

  According to the method for manufacturing a semiconductor device disclosed in this specification, a plurality of chip regions are arranged in a grid pattern in accordance with a relationship of securing a dicing width between adjacent chip regions in a region where a semiconductor wafer can be processed. A step of arranging, a step of securing a dicing region extending linearly between adjacent chip regions and reaching the outer periphery of the semiconductor wafer, and a region not belonging to either the chip region or the dicing region in the semiconductor wafer The method includes a step of forming an alignment mark, a processing step of executing processing for a plurality of chip regions using the alignment mark as a positioning reference, and a step of dicing the dicing region after the processing is executed.

An effective area exists in a semiconductor device manufacturing apparatus, and the entire semiconductor wafer cannot always be processed or inspected. In this specification, an area that can be processed and inspected for manufacturing a semiconductor device is referred to as an area where a semiconductor wafer can be processed (hereinafter referred to as an area that can be processed). The entire area of the semiconductor wafer may be a processable area, but only a part of the semiconductor wafer may be a processable area. In the latter case, an area that is not a processable area exists in the semiconductor wafer. .
In the case of manufacturing a plurality of semiconductor devices, a plurality of chip regions are arranged in the processable region. A plurality of chip areas are arranged in a grid pattern so that the chips can be divided into a plurality of chips by dicing along a straight line. Further, a dicing width is secured between adjacent chip regions. The chip area has a size and cannot always be arranged in the processable area without a gap. There may be a region in the processable region that is neither a chip region nor a dicing region.
In the technique described in this specification, alignment marks are formed in a region that does not belong to either the chip region or the dicing region in the semiconductor wafer. In a semiconductor wafer, an area that does not belong to either a chip area or a dicing area is an area that is outside the processable area and is not a dicing area, and an area that is within the processable area but is not a chip area or a dicing area. Say.

  In the manufacturing method described above, no alignment mark is formed in the dicing region. No chipping or cracks are generated by cutting the alignment mark. In addition, since the alignment mark is formed in the area where the chip cannot be manufactured, the alignment mark does not reduce the number of chips that can be manufactured from one semiconductor wafer.

A stage where a plurality of chip regions 62 and dicing regions 66 are arranged in the semiconductor wafer 50 is schematically shown. The enlarged view of the II section of FIG. The stage in which the alignment mark 70 is formed in the semiconductor wafer 50 is shown. IV-IV sectional view taken on the line of FIG. A step of reading the alignment mark 70 and forming a semiconductor element in the chip region 62 is shown. A stage in which an electrode and an insulating film are formed on a semiconductor wafer is shown. The step of cutting the semiconductor wafer 50 along the dicing region 66 is shown.

  An embodiment of a method for manufacturing a semiconductor device will be described with reference to FIGS. The semiconductor device manufactured by the manufacturing method according to the present embodiment is a kind of power semiconductor device, and is used in a power supply circuit that supplies current to a load such as a motor. In the following, only the process that is a feature of the present embodiment will be described. Therefore, an actual manufacturing method of a semiconductor device may include one or a plurality of steps that are not included in the following description as needed.

  In this embodiment, the entire area of the semiconductor wafer 50 is a processable area. Therefore, a plurality of chip regions 62 are arranged in a grid pattern in the semiconductor wafer 50 in a state where the semiconductor wafer 50 is viewed in plan. However, a dicing width D is secured between the adjacent chip regions 62. Each chip region 62 has the same shape and the same size, and has a rectangular shape. Since the plurality of rectangular chip regions 62 are arranged in a grid pattern, the dicing regions 66 secured between the adjacent chip regions 62 are aligned in a straight line. For example, the dicing areas 66a and 66b are aligned on a straight line, and the dicing areas 66c and 66d are aligned on a straight line.

  Since a plurality of rectangular chip regions 62 are arranged in a grid pattern in the semiconductor wafer 50 whose outer periphery is a circle, there is an area 54 in which the chip regions 62 cannot be disposed at positions along the outer periphery of the semiconductor wafer 50. Will remain. The plurality of chip regions 62 are arranged in a grid pattern in a polygon 52 indicated by a thick line in FIG. Even in the semiconductor wafer 50, the area outside the polygon 52 is an area in which the chip area 62 cannot be arranged (hereinafter referred to as an unplaceable area 54).

  The dicing areas 66 secured between the adjacent chip areas 62 are aligned in a straight line, and when extended as they are, reach the outer periphery of the semiconductor wafer 50. A region secured between the adjacent chip regions 62 and a region extending from the region which passes through the non-placeable region 54 and reaches the outer periphery of the semiconductor wafer 50 are referred to as a dicing region 66. Each of the areas in the non-placeable area 54 and divided into a plurality of parts by the dicing area 66 is referred to as a non-dicing area 64 that cannot be placed (meaning an area where the chip area 62 cannot be placed and is not diced). ).

  An alignment mark 70 (see FIG. 3) is provided later in some of the non-dicing regions 64 that cannot be arranged. Even if the alignment mark 70 is provided in the non-dicing region 64 that cannot be arranged, the number of chip regions 62 that can be arranged in the semiconductor wafer 50 does not decrease. In addition, since the alignment mark 70 is not formed in the dicing region 66, the alignment mark 70 does not cause a chipping or a crack.

  Next, a step of forming alignment mark 70 is performed. In this step, as shown in FIGS. 3 and 4, one or more alignment marks 70 are formed on the surface 64 a of the non-dicing region 64 that cannot be arranged. The alignment mark 70 may have various shapes, patterns, or colors depending on the purpose. The method for forming the alignment mark 70 is not particularly limited. The material constituting the alignment mark 70 is also not particularly limited, and for example, Al, polysilicon, an oxide film, or the like is used. Further, the alignment mark 70 may be formed by forming a step on the surface of the semiconductor wafer 50. An alignment mark 70 may also be formed on the back surface 64b of the non-dicing region 64 that cannot be arranged, if necessary.

  Next, a process for processing the semiconductor wafer 50 is performed. In this step, a semiconductor element structure is formed in the chip region 62 of the semiconductor wafer 50 using the alignment mark 70 as shown in FIG. For example, an ion implantation process for introducing a conductive impurity into a part of the chip region 62, an annealing process for activating the conductive impurity in the semiconductor wafer 50, and a process for forming the insulating film 12 on the surface of the semiconductor wafer 50 Etc. are implemented. In this step, various processes are performed while one or more alignment marks 70 are detected by the optical device 90. For example, in the ion implantation process, a plurality of alignment marks 70 are detected, and alignment of the exposure mask is performed based on those positions. Note that the arrow group B shown in FIG. 5 schematically shows various processes performed on the chip region 62, and does not mean a specific process. After various processes are repeatedly performed on the chip region 62 of the semiconductor wafer 50, as shown in FIG. 6, the front electrode 14, the back electrode 16, and the like are formed.

  Subsequently, a step of dicing the semiconductor wafer 50 is performed. As shown in FIG. 7, the dicing area 66 of the semiconductor wafer 50 is cut by a dicing blade 80, and the semiconductor wafer 50 is divided into a plurality of chips. Since the semiconductor device 10 is manufactured in each chip, a plurality of semiconductor devices 10 are manufactured simultaneously from one semiconductor wafer 50.

  In the manufacturing method of the semiconductor device 10 according to the present embodiment, the alignment mark 70 is formed in the non-placeable region 54 where the chip region 62 cannot be placed and not the dicing region 66, that is, the non-placeable non-dicing region 64. When the semiconductor wafer 50 is diced in order to form the alignment mark 70 in the non-dicing region 64 that cannot be arranged, the alignment mark 70 is not cut. Therefore, chipping and cracks resulting from cutting the alignment mark 70 can be prevented. Since the alignment mark 70 is formed in the non-dicable region 64 that cannot be arranged, the number of chip regions 62 that can be arranged in one semiconductor wafer 50 does not decrease. For this reason, the manufacturing yield of the semiconductor device 10 can be improved. Further, it is not necessary to remove the alignment mark 70. The possibility that the semiconductor wafer 50 is contaminated by the step of removing the alignment mark 70 can be avoided.

  In the present embodiment, the case where the entire area of the semiconductor wafer 50 is a processable area is illustrated, but when a part of the semiconductor wafer is a processable area, a plurality of chip areas 62 are arranged in the processable area. The polygon 52 is obtained by arranging in a grid, and a non-dicing region 64 that cannot be arranged is secured outside, and the alignment mark 70 may be formed in the non-dicing region 64 that cannot be arranged.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor device 12: Insulating film 14: Front electrode 16: Back electrode 50: Semiconductor wafer 52: Polygon 54: Non-placeable area 62: Chip area 64: Non-dicing non-dicing area 66: Dicing area 70: Alignment mark

Claims (1)

A step of arranging a plurality of chip regions in a grid pattern according to the relationship of securing a dicing width between adjacent chip regions in a region where processing for a semiconductor wafer is possible,
Securing a dicing area extending linearly between the adjacent chip areas and reaching the outer periphery of the semiconductor wafer;
Forming an alignment mark in a region not belonging to either the chip region or the dicing region in the semiconductor wafer;
A processing step of executing processing for the plurality of chip regions using the alignment mark as a positioning reference;
A method for manufacturing a semiconductor device, comprising: a step of dicing the dicing region after the processing step.

Images