JP2017183714A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2017183714A5 JP2017183714A5 JP2017046029A JP2017046029A JP2017183714A5 JP 2017183714 A5 JP2017183714 A5 JP 2017183714A5 JP 2017046029 A JP2017046029 A JP 2017046029A JP 2017046029 A JP2017046029 A JP 2017046029A JP 2017183714 A5 JP2017183714 A5 JP 2017183714A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- bridge circuit
- circuit layer
- circuit
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000969 carrier Substances 0.000 claims 14
- 238000004519 manufacturing process Methods 0.000 claims 9
- 230000001808 coupling Effects 0.000 claims 3
- 238000010168 coupling process Methods 0.000 claims 3
- 238000005859 coupling reaction Methods 0.000 claims 3
- 238000007689 inspection Methods 0.000 claims 2
- 229910000679 solder Inorganic materials 0.000 claims 2
- 239000011521 glass Substances 0.000 claims 1
- 230000002787 reinforcement Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Claims (18)
前記ブリッジ回路層が内蔵され、前記ブリッジ回路よりも密度が低い低密度回路を具備した低密度回路層を含み、
前記ブリッジ回路層の一面または他面には接続パッドが形成され、前記接続パッドはビアまたはソルダーバンプを通じて前記低密度回路と電気的に連結される、印刷回路基板。 A bridge circuit layer having a high-density bridge circuit for electrically connecting a plurality of dies; and a low-density circuit including the bridge circuit layer and having a lower density than the bridge circuit. Including a low density circuit layer provided;
A printed circuit board, wherein connection pads are formed on one surface or the other surface of the bridge circuit layer, and the connection pads are electrically connected to the low density circuit through vias or solder bumps.
前記外層回路に前記複数のダイが結合される、請求項１〜請求項４のいずれか一項に記載の印刷回路基板。 An outer layer circuit formed on one surface of the bridge circuit layer to connect the plurality of dies and the bridge circuit;
The printed circuit board according to claim 1, wherein the plurality of dies are coupled to the outer layer circuit.
前記ブリッジ回路層に仮接合される第２キャリアを接合し、前記第１キャリアを分離する段階；および
低密度回路を具備した低密度回路層に前記ブリッジ回路層を結合し埋め立てる段階を含む、印刷回路基板製造方法。 Forming a bridge circuit layer having a high-density bridge circuit on a low-roughness first carrier;
Printing, comprising: bonding a second carrier temporarily bonded to the bridge circuit layer and separating the first carrier; and coupling and bridging the bridge circuit layer to a low density circuit layer having a low density circuit. Circuit board manufacturing method.
前記低密度回路を具備した低密度回路層を形成する段階；
前記低密度回路層に前記ブリッジ回路層を結合させて電気的に連結する段階；
前記第２キャリアを分離させる段階；および
前記ブリッジ回路層を埋め立てる段階を含む、請求項８または請求項９に記載の印刷回路基板製造方法。 The step of combining and reclaiming the bridge circuit layer comprises:
Forming a low density circuit layer comprising the low density circuit;
Coupling and electrically connecting the bridge circuit layer to the low density circuit layer;
The method for manufacturing a printed circuit board according to claim 8, comprising: separating the second carrier; and refilling the bridge circuit layer.
第３キャリアに前記ブリッジ回路層を装着させる段階；
前記第２キャリアを分離させる段階；
前記第３キャリアに前記ブリッジ回路層を埋め立てる前記低密度回路層をビルドアップ（ｂｕｉｌｄ−ｕｐ）する段階；および
前記第３キャリアを分離する段階を含む、請求項８〜請求項１２のいずれか一項に記載の印刷回路基板製造方法。 The step of combining and reclaiming the bridge circuit layer comprises:
Attaching the bridge circuit layer to a third carrier;
Separating the second carrier;
13. The method according to claim 8, further comprising: building-up the low-density circuit layer that buryes the bridge circuit layer in the third carrier; and separating the third carrier. The printed circuit board manufacturing method according to Item.
前記ブリッジ回路層と低密度回路層をビアで連結する段階を含む、請求項１３に記載の印刷回路基板製造方法。 The build-up step includes
The method of manufacturing a printed circuit board according to claim 13, comprising connecting the bridge circuit layer and the low density circuit layer with vias.
前記低密度回路層を具備した低密度回路層を形成する段階；Forming a low density circuit layer comprising the low density circuit layer;
前記低密度回路層に前記ブリッジ回路層を結合させて電気的に連結する段階；およびCoupling and electrically connecting the bridge circuit layer to the low density circuit layer; and
前記第２キャリアが結合された前記ブリッジ回路層を埋め立てる段階を含む、請求項８に記載の印刷回路基板製造方法。The printed circuit board manufacturing method according to claim 8, comprising filling the bridge circuit layer to which the second carrier is bonded.
第３キャリアに前記ブリッジ回路層を装着させる段階；Attaching the bridge circuit layer to a third carrier;
前記第３キャリアに、前記第２キャリアが結合された前記ブリッジ回路層を埋め立てる前記低密度回路層をビルドアップ（ｂｕｉｌｄ−ｕｐ）する段階；およびBuilding-up the low-density circuit layer filling the bridge circuit layer to which the second carrier is coupled to the third carrier; and
前記第３キャリアを分離する段階を含む、請求項８に記載の印刷回路基板製造方法。The method of manufacturing a printed circuit board according to claim 8, comprising separating the third carrier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0037600 | 2016-03-29 | ||
| KR1020160037600A KR101966328B1 (en) | 2016-03-29 | 2016-03-29 | Printed circuit board and manufacturing for the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019003328A Division JP6787550B2 (en) | 2016-03-29 | 2019-01-11 | Printed circuit board |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017183714A JP2017183714A (en) | 2017-10-05 |
| JP2017183714A5 true JP2017183714A5 (en) | 2018-08-30 |
| JP6489660B2 JP6489660B2 (en) | 2019-03-27 |
Family
ID=60007673
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017046029A Active JP6489660B2 (en) | 2016-03-29 | 2017-03-10 | Printed circuit board manufacturing method |
| JP2019003328A Active JP6787550B2 (en) | 2016-03-29 | 2019-01-11 | Printed circuit board |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019003328A Active JP6787550B2 (en) | 2016-03-29 | 2019-01-11 | Printed circuit board |
Country Status (2)
| Country | Link |
|---|---|
| JP (2) | JP6489660B2 (en) |
| KR (1) | KR101966328B1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10867954B2 (en) | 2017-11-15 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect chips |
| KR102101712B1 (en) * | 2018-03-21 | 2020-04-21 | (주)심텍 | Printed Circuit Board with Bridge Substrate |
| KR102648090B1 (en) * | 2019-05-17 | 2024-03-18 | 삼성전자주식회사 | Wiring substrate and semiconductor package comprising the same |
| JP2021093516A (en) | 2019-12-11 | 2021-06-17 | インテル・コーポレーション | Composite bridge die-to-die interconnection for integrated circuit package |
| KR20220015573A (en) | 2020-07-31 | 2022-02-08 | 삼성전기주식회사 | Printed circuit board and manufacturing method for the same |
| KR20220065550A (en) | 2020-11-13 | 2022-05-20 | 삼성전기주식회사 | Connection structure embedded substrate |
| CN113035827B (en) * | 2021-02-25 | 2022-07-05 | 日月光半导体制造股份有限公司 | Semiconductor package device and method of manufacturing the same |
| KR20230075176A (en) | 2021-11-22 | 2023-05-31 | 삼성전기주식회사 | Printed circuit board |
| KR20240045007A (en) * | 2022-09-29 | 2024-04-05 | 엘지이노텍 주식회사 | Semiconductor package |
| KR20240044946A (en) * | 2022-09-29 | 2024-04-05 | 엘지이노텍 주식회사 | Semiconductor package |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4581768B2 (en) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | Manufacturing method of semiconductor device |
| US8064224B2 (en) * | 2008-03-31 | 2011-11-22 | Intel Corporation | Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same |
| US8227904B2 (en) * | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| JP5282005B2 (en) * | 2009-10-16 | 2013-09-04 | 富士通株式会社 | Multi-chip module |
| US8754514B2 (en) | 2011-08-10 | 2014-06-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip wafer level package |
| US9059179B2 (en) * | 2011-12-28 | 2015-06-16 | Broadcom Corporation | Semiconductor package with a bridge interposer |
| JP2013214578A (en) * | 2012-03-30 | 2013-10-17 | Ibiden Co Ltd | Wiring board and method for manufacturing the same |
| JP2014049578A (en) * | 2012-08-30 | 2014-03-17 | Ibiden Co Ltd | Wiring board and manufacturing method of wiring board |
| US8872349B2 (en) * | 2012-09-11 | 2014-10-28 | Intel Corporation | Bridge interconnect with air gap in package assembly |
| US9236366B2 (en) * | 2012-12-20 | 2016-01-12 | Intel Corporation | High density organic bridge device and method |
| US8901748B2 (en) * | 2013-03-14 | 2014-12-02 | Intel Corporation | Direct external interconnect for embedded interconnect bridge package |
| US9642259B2 (en) * | 2013-10-30 | 2017-05-02 | Qualcomm Incorporated | Embedded bridge structure in a substrate |
| WO2015130264A1 (en) * | 2014-02-26 | 2015-09-03 | Intel Corporation | Embedded multi-device bridge with through-bridge conductive via signal connection |
| US9542522B2 (en) * | 2014-09-19 | 2017-01-10 | Intel Corporation | Interconnect routing configurations and associated techniques |
| US9806044B2 (en) * | 2016-02-05 | 2017-10-31 | Dyi-chung Hu | Bonding film for signal communication between central chip and peripheral chips and fabricating method thereof |
-
2016
- 2016-03-29 KR KR1020160037600A patent/KR101966328B1/en active IP Right Grant
-
2017
- 2017-03-10 JP JP2017046029A patent/JP6489660B2/en active Active
-
2019
- 2019-01-11 JP JP2019003328A patent/JP6787550B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2017183714A5 (en) | ||
| KR101642338B1 (en) | Interconnect system, microelectronic die and interconnecting method | |
| JP6489660B2 (en) | Printed circuit board manufacturing method | |
| KR100997199B1 (en) | Manufacturing method of printed circuit board having electro component | |
| TWI379624B (en) | Printed circuit board and method of producing the same | |
| JP6806316B2 (en) | Printed circuit board, manufacturing method of printed circuit board and semiconductor package including this | |
| KR101516072B1 (en) | Semiconductor Package and Method of Manufacturing The Same | |
| JP4990826B2 (en) | Multilayer printed circuit board manufacturing method | |
| US20120176751A1 (en) | Electronic component module and manufacturing method therefor | |
| TW201618247A (en) | Package structure and manufacturing method thereof | |
| JP2011071533A (en) | Method of manufacturing multilayer printed circuit board | |
| JP2011133456A (en) | Multilayered ceramic substrate and probe substrate formed by using columnar conductor, and method for manufacturing the substrate | |
| TW201501600A (en) | Printed circuit board and method for manufacturing same | |
| JP2016162835A (en) | Multilayer wiring board | |
| TW201344862A (en) | Ball grid array package substrate with through holes and method of forming same | |
| JP2005311371A (en) | Semiconductor chip package | |
| JP6378616B2 (en) | Printed wiring board with built-in electronic components | |
| WO2018113746A1 (en) | Discrete device packaging method and discrete device | |
| JP2011187912A (en) | Electro device-embedded printed circuit board and manufacturing method thereof | |
| TW201606964A (en) | Chip package substrate, chip packaging structure and manufacturing method of same | |
| TWI530240B (en) | Printed circuit board and method for manufacturing same | |
| CN100591193C (en) | Wiring substrate, wiring material, copper-clad laminate, and method of manufacturing the wiring substrate | |
| JP2013030808A (en) | Temporary substrate for wiring board manufacturing and manufacturing method of the same | |
| KR102473408B1 (en) | Printed circuit board and manufacturing for the same | |
| KR100689018B1 (en) | Printed circuit board with embedded coaxial cable and manufacturing method thereof |