JP2017174980A - Abnormality detection circuit and operation method therefor, semiconductor device and operation method therefor, and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an abnormality detection circuit that monitors a voltage variation at the time of supplying a power source to quickly detect a sign of abnormality such as deterioration or a failure of a power source element and the like.SOLUTION: An abnormality detection circuit 40 comprises: a timer 30 that starts incrementing a count value CNT when a voltage VNinput from the outside starts rising and executes the increment until the count value CNT reaches a predetermined count setting value CNT_MAX; and a comparator 20 that compares the voltage VNwith a predetermined threshold voltage Vth, sets counter output C1 to a first level when the voltage is equal to or higher than the threshold voltage, and sets the counter output C1 to a second level when the voltage is lower than the threshold voltage. The timer 30, when the count value CNT reaches the predetermined count setting value CNT_MAX, refers to the counter output C1 output from the comparator 20; and, when the counter output C1 is not the first level, determines that abnormality has occurred to execute countermeasure processing for the abnormal time.SELECTED DRAWING: Figure 3

Description

  The present embodiment relates to an abnormality detection circuit and an operation method thereof, a semiconductor device and an operation method thereof, and a communication system.

  Standards for safety functions (for example, fail-safe functions, abnormality detection functions, safety stop functions, etc.) for all parts mounted on automobiles are being reviewed. In particular, many in-vehicle devices are electrically / electronically controlled, and not only high performance and high functionality but also safety are important needs.

  An international standard ISO 26262 that systematically summarizes development methods and management methods for safe in-vehicle devices has been formulated (for example, see Non-Patent Document 1).

"ISO 26262-1: 2011", [online], 2011-11-15, International Organization for Standardization, [Search February 17, 2016], Internet <URL: https://www.iso.org/obp / ui / # iso: std: iso: 26262: -1: ed-1: v1: en>

  For example, in order to avoid in advance a serious accident that may occur in a communication system due to deterioration or failure of a power supply element that supplies a pull-up voltage, it is required to quickly detect deterioration or failure of the power supply element.

  The present embodiment monitors a voltage change at the time of power supply, and can quickly detect an abnormality such as deterioration or failure of a power supply element, an abnormality detection circuit and an operation method thereof, a semiconductor device and an operation method thereof, And a communication system.

  According to one aspect of the present embodiment, a timer that starts counting up when a voltage input from the outside starts increasing, and executes count-up until the count value reaches a predetermined count setting value; The externally input voltage is compared with a predetermined threshold voltage. If the voltage is equal to or higher than the threshold voltage, the counter output is set to the first level. If the voltage is lower than the threshold voltage, A comparator for setting the counter output to a second level, and the timer refers to the counter output output from the comparator when the count value reaches the predetermined count set value, and the counter An abnormality detection circuit is provided that determines that an abnormality has occurred when the output is not at the first level and executes a response process at the time of abnormality.

  According to another aspect of the present embodiment, abnormality detection is performed to monitor whether or not an abnormality has occurred based on the slope and required time when the externally input voltage rises from a low level to a desired voltage value. There is provided a semiconductor device that includes a circuit and executes a response process when an abnormality occurs when the voltage does not rise to the desired voltage with a normal slope and a normal required time.

  According to another aspect of the present embodiment, a communication system for connecting a plurality of devices to each other via a bus so that the voltage pulled up to the bus rises from a low level to a desired voltage value. When an abnormality detection circuit for monitoring whether or not an abnormality has occurred based on the inclination and the required time when the voltage is not increased to the desired voltage at a normal inclination and a normal required time, There is provided a communication system including a semiconductor device that executes a response process when an abnormality occurs.

  According to another aspect of the present embodiment, when the externally input voltage starts to rise, the timer starts counting up the count value, and counts up until the count value reaches a predetermined count setting value. A step of executing, the comparator compares the voltage inputted from the outside with a predetermined threshold voltage, and if the voltage is equal to or higher than the threshold voltage, the counter output is set to a first level; If the voltage is less than the threshold voltage, setting the counter output to a second level; and when the count value reaches the predetermined count set value, the timer outputs the counter output from the comparator And an operation method of an abnormality detection circuit comprising the step of executing a response process when an abnormality occurs when the counter output is not at the first level It is provided.

  According to another aspect of the present embodiment, the step of monitoring whether or not an abnormality has occurred based on the slope and required time when the externally input voltage rises from the Low level to a desired voltage value; And a step of performing a response process when an abnormality occurs when the voltage does not rise to the desired voltage with a normal slope and a normal required time, and monitoring whether or not the abnormality has occurred When the voltage input from the outside starts to rise, a timer starts counting up the count value, and executes a count-up until the count value reaches a predetermined count setting value; and a comparator The externally input voltage is compared with a predetermined threshold voltage. If the voltage is equal to or higher than the threshold voltage, the counter output is set to the first level, and the voltage is Is less than a threshold voltage, the counter output is set to a second level, and when the count value reaches the predetermined count set value, the timer outputs the counter output output from the comparator. A method of operating a semiconductor device is provided that includes a step of executing a response process when an abnormality occurs when the counter output is not at the first level.

  According to the present embodiment, an abnormality detection circuit capable of monitoring voltage changes during power supply and quickly detecting signs of abnormality such as deterioration or failure of a switching power supply element, an operation method thereof, a semiconductor device, and the An operation method and a communication system can be provided.

The typical block diagram which illustrates the I2C communication system which serially connects a some block. Schematic which shows an example of the voltage value when abnormality generate | occur | produces in the switching power supply element of the I2C communication system illustrated in FIG. The typical block diagram which shows an example of the semiconductor device which concerns on embodiment applied to the I2C system. (A) Waveform example of drive N in normal operation in semiconductor device according to embodiment, (b) Waveform example of node N ₁ . (A) Waveform example of drive N at the time of abnormal operation in the semiconductor device according to the embodiment, (b) Waveform example of node N ₁ . (A) waveform example of the drive N of the normal operation of the semiconductor device according to the embodiment, (b) a waveform example of a node N _1, (c) example of the timing of the timer. (A) waveform example of the drive N of the abnormal operation of the semiconductor device according to the embodiment, (b) a waveform example of a node N _1, (c) example of the timing of the timer. The typical block diagram which shows an example of the semiconductor device which concerns on embodiment applied to the CAN system. The typical block diagram which shows another example of the I2C system to which the semiconductor device which concerns on embodiment is applied. 1 is a schematic configuration diagram illustrating an example of a monitoring LSI in which semiconductor devices according to an embodiment are integrated. FIG. 3 is a schematic configuration diagram illustrating one application example of a monitoring LSI in which a semiconductor device according to an embodiment is integrated. FIG. 10 is a schematic configuration diagram illustrating another application example of the monitoring LSI in which the semiconductor device according to the embodiment is integrated. 1 is a schematic configuration diagram showing a bus configuration example of a CAN system to which a monitoring LSI according to an embodiment is applied. The schematic diagram which illustrates the relationship between the CAN packet error correction signal of the CAN system to which the LSI for monitoring which concerns on embodiment is applied, and a serial interface. 7 is a flowchart illustrating an example of a processing operation of the semiconductor device according to the embodiment.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and in this embodiment, the material, shape, structure, arrangement, etc. of the component parts are described below. It is not something specific. This embodiment can be modified in various ways within the scope of the claims.

[Embodiment]
(Configuration example of semiconductor device applied to I2C system)
FIG. 1 schematically illustrates a communication system using an I2C interface. In this communication system, a plurality of blocks (block A (81) and block B (82)) are serially connected so as to be communicable via an I2C (Inter-Integrated Circuit) bus.

  The I2C interface is a synchronous serial communication interface used when communication is performed between ICs (for example, between block A (81) and block B (82)) in a microcomputer system or the like. The signal line in the I2C interface is composed of two signal lines (not shown in FIG. 1) of a clock line (SCL: serial clock) and a data line (SDA: serial data). For example, the signal line is pulled by a pull-up resistor RP. This is an up-and-down bidirectional signal line. Here, the block A (81) is, for example, a master device, and the block B (82) is, for example, a slave device.

  The data line is pulled up to a certain voltage. The pull-up voltage is supplied from the switching power supply element 10 or the like. However, when the switching power supply element 10 is deteriorated, failed, destroyed, or the like, the microcomputer system program may malfunction (for example, runaway).

  If signs of abnormality such as deterioration or failure of the switching power supply element 10 can be detected promptly, a serious accident or the like may be prevented in advance.

  FIG. 2 schematically shows an example of the voltage value Vcc when an abnormality occurs in the switching power supply element 10.

  When the switching power supply element 10 or the like deteriorates or has a minor failure, the voltage (stage SP1) that has been stably supplied during normal operation (within the specification range) starts to gradually drop (stage SP2) and is left as it is. Then, it drops significantly to the extent that it leads to a serious failure such as destruction (step SP3), and as a result, a serious accident may be caused. If an abnormality can be detected and an alert or the like can be output before reaching the stage SP3, that is, in the stage SP2 at which it starts to descend, there is a possibility that a serious accident or the like can be prevented.

  FIG. 3 schematically shows an example of the semiconductor device 100 according to the embodiment applied to the I2C system.

The semiconductor device 100, the I2C data bus which is pulled up by pull-up resistor RP, port (Port) is connected via the A, node N ₁ of the voltage VN ₁ from Low level desired voltage Vcc (threshold voltage Vth) An abnormality detection circuit 40 is provided for monitoring whether or not an abnormality has occurred in the switching power supply element 10 based on the gradient (Vth / (t2-t1)) and the required time (t2-t1).

The abnormality detection circuit 40 starts counting up the count value CNT when the voltage VN ₁ of the node N ₁ input from the outside via the port A starts to rise, and the count value CNT reaches a predetermined count setting value CNT_MAX. a timer a (30) to perform the counting up to a voltage VN ₁ of the node N ₁ which is input via the port a from the outside, compared with a predetermined threshold voltage Vth, the voltage VN ₁ ≧ node N ₁ if the threshold voltage Vth, the counter output C1 first level is set to (High level ( "1")), if the node N ₁ of the voltage VN ₁ <threshold voltage Vth, the counter output C1 second And a comparator A (20) set to a level (Low level (“0”)). When the count value CNT reaches a predetermined count set value CNT_MAX, the timer A (30) refers to the counter output C1 output from the comparator A (20), and copes with an abnormality when the counter output C1 is not at a high level. Execute the process.

The predetermined count set value CNT_MAX is set based on a standard time required for the voltage VN ₁ to reach the desired voltage Vcc (threshold voltage Vth) during normal operation (within the specification range).

  The predetermined threshold voltage Vth is set to a value sufficient to determine whether or not an abnormality has occurred in the switching power supply element 10. If the value of the threshold voltage Vth is set to a large value, the detection accuracy of occurrence of abnormality increases, but the time required for detection of occurrence of abnormality increases. If the threshold voltage Vth is set to a small value, the detection accuracy of abnormality is lowered, but the time required to detect abnormality is reduced.

  Further, the semiconductor device 100 may include an nMOS transistor M1 that supplies a timer start signal S instructing start of timer processing (counting up) to the timer A (30).

Further, the abnormality detection circuit 40 may include a buffer 35 that temporarily stores the voltage VN ₁ or the like input from the port A.

  Port A is a bidirectional (input / output) terminal. For example, an I2C data line (SDA) is connected.

The voltage VN ₁ of the node N ₁ takes two values, that is, a GND level (Low level “0”) and a power supply voltage Vcc by a drive N in the semiconductor device 100. If drive N is High level of the nMOS transistor M1 ( "1"), the node voltage VN ₁ of N ₁ is Low level ( "0"), and if the drive N is Low level ( "0"), the node The voltage VN _{1 of} N ₁ becomes High level (“1”). The high level of the voltage VN _{1 at} the node N ₁ is maintained by the switching power supply element 10.

Figure 4 schematically illustrates the relationship between the normal operation of the drive N (FIG. 4 (a)) and the node N ₁ of the voltage VN ₁ (FIG. 4 (b)) in the semiconductor device 100. Time t1 drive N transitions from High level to Low level, i.e., at time t1 the voltage VN ₁ of node N ₁ is changed from the Low level to the High level, the voltage level of node N ₁ goes gently rises.

Figure 5 is a semiconductor device malfunction during drive N at 100 (FIG. 5 (a)) and a node the relationship between the voltage VN ₁ of N ₁ (FIG. 5 (b)) schematically illustrates.

Here, it is assumed that the switching power supply element 10 starts to deteriorate and the current I supplied by the switching power supply element 10 starts to decrease. Then, from time t1, the node N time required for raising the voltage VN ₁ of ₁ from the Low level to the desired voltage Vcc (broken line in FIG. 5 (b)) is, the time required for the normal operation (FIG. 5 (b ) Begins to become longer than the solid line). This is because the time required for the switching power supply element 10 to be charged with the current I via the pull-up resistor RP takes longer than the normal operation due to the deterioration of the pull-up resistor RP.

The semiconductor device 100 according to the embodiment measures a time required for the voltage VN _{1 at} the node N ₁ to reach a desired voltage Vcc (threshold voltage Vth), and when the time becomes longer than a predetermined time. Then, it is determined that an abnormality (for example, a sign of deterioration) has occurred in the switching power supply element 10, and an alert or the like is output to prevent a serious accident or the like.

6, the semiconductor normal in the apparatus 100 during operation of the drive N (FIG. 6 (a)) and the node N ₁ of the voltage VN ₁ and (FIG. 6 (b)) Timer A (30) and (FIG. 6 (c)) The relationship is schematically illustrated.

  When the drive N changes from the High level to the Low level, the timer start signal S is supplied to the timer A (30), and the timer A (30) starts to count up the count value CNT. The timer A (30) stops counting up when the count value CNT reaches a predetermined count set value CNT_MAX.

Comparator A (20) compares the voltage VN ₁ of node N ₁ and a predetermined threshold voltage Vth, if the voltage VN ₁ ≧ the threshold voltage Vth of the node N _1, the counter output C1 High level ( "1" set), if the voltage VN ₁ <the threshold voltage Vth of the node N _1, sets the counter output C1 to Low level ( "0").

As illustrated in FIG. 6, during normal operation, the counter output C1 changes from the Low level to the High level before the count value CNT reaches the predetermined count setting value CNT_MAX (time t2). Accordingly, in the range time during normal operation required for the voltage VN ₁ of node N ₁ reaches the threshold voltage Vth, it is determined that an abnormality in the switching power supply device 10 (e.g., signs of deterioration) does not occur, the timer A (30) does not output an alert or the like.

7, the voltage VN ₁ (FIG. 7 (b)) and a timer A (30) of the semiconductor device malfunction during drive N at 100 (FIG. 7 (a)) and the node N ₁ according to the embodiment (FIG. 7 The relationship with (c)) is schematically illustrated.

As illustrated in FIG. 7, during an abnormal operation, even when the count value CNT reaches a predetermined count setting value CNT_MAX, the counter output C1 remains at the low level (the counter output C1 changes from the low level to the high level). It is turned (time t2) after the count value CNT reaches a predetermined count set value CNT_MAX). Therefore, it is determined that the time required for the voltage VN _{1 at} the node N ₁ to reach the threshold voltage Vth is longer than that during normal operation, and that the switching power supply element 10 is abnormal (for example, a sign of deterioration). 30) outputs an alert or the like.

  As described above, according to the semiconductor device 100 according to the embodiment applied to the I2C system, by monitoring the voltage change at the time of power supply, the switching power supply element 10 and the like can show signs of abnormality such as deterioration or failure. It can be detected quickly.

(Configuration example of semiconductor device applied to CAN system)
In addition to the I2C system, the semiconductor device 100 according to the embodiment includes LVDS (Low Voltage Differential Signaling), DisplayPort (display port), HDMI (registered trademark) (High-Definition Multimedia Interface), CAN ( It can also be applied to a controller area network.

  FIG. 8 schematically shows an example of the semiconductor device 100 according to the embodiment applied to the CAN system.

  In semiconductor device 100 according to the embodiment, when it is determined that a specific bit of a specific data frame is at a high level, the time required for the specific bit to reach a desired voltage is set to timer A (30 ) Measure.

  The semiconductor device 100 including the abnormality detection circuit 40 is connected to the CAN devices SG1 (61) and SG2 (62), and the CAN signal is changed from the low level to the high level or from the high level to the low level with a normal inclination and a normal required time. Monitor for changes. When an abnormality is detected, the semiconductor device 100 outputs an IRQ (Interrupt ReQuest) signal to the CPU 200 to notify the abnormality detection.

  During normal operation, the CPU 200 outputs enable signals EN1 and EN2 for enabling the functions of the CAN devices SG1 (61) and SG2 (62) to the CAN devices SG1 (61) and SG2 (62), respectively. On the other hand, the CPU 200 that has received the IRQ signal from the semiconductor device 100 generates a disable signal that disables the functions of the CAN devices SG1 (61) and SG2 (62) in response to the IRQ signal. To CAN devices SG1 (61) and SG2 (62), respectively.

  As described above, according to the semiconductor device 100 according to the embodiment applied to the CAN system, by monitoring the voltage change of the CAN signal, it is possible to quickly detect an abnormality such as deterioration or failure of the CAN device or the like. be able to.

(Another configuration example of the I2C system to which the semiconductor device is applied)
FIG. 9 schematically shows another configuration example of the I2C system to which the semiconductor device 100 according to the embodiment is applied.

  In the I2C system illustrated in FIG. 9, the I2C master block 310 and the I2C slave block 320 are communicably connected via two signal lines, a clock line (SCL) and a data line (SDA). The clock line (SCL) and the data line (SDA) are bidirectional signal lines that are pulled up by the pull-up resistors R1 and R2, respectively.

  The I2C master device (master 1) 300 is an I2C master device incorporating the I2C master block 310 and the semiconductor device 100 according to the embodiment. The semiconductor device 100 includes at least the abnormality detection circuit 40 according to the embodiment.

  The semiconductor device 100 including the abnormality detection circuit 40 is connected to the clock line (SCL) and the data line (SDA) via the terminals SDA1 and SCL1, and the voltage of the clock line (SCL) and the data line (SDA) is normal. In addition, it is monitored whether the voltage rises from the Low level to a desired voltage Vcc (threshold voltage Vth) in a normal required time. When the abnormality is detected, the semiconductor device 100 outputs an IRQ signal to the CPU 200 to notify the abnormality detection.

  During normal operation, the CPU 200 outputs enable signals SCL1 and SDA1 that enable the functions of the I2C master block 310 and the I2C slave block 320 to the 2C master block 310 and the I2C slave block 320, respectively.

  On the other hand, the CPU 200 that has received the IRQ signal from the semiconductor device 100 sends the disable signals SCL1 and SDA1 that disable the functions of the 2C master block 310 and the I2C slave block 320 in response to the IRQ signal, respectively. And output to the I2C slave block 320. However, in such a situation where an abnormality has occurred, it may not be preferable to transmit the enable signals SCL1 and SDA1 using a normal I2C signal line (bus). Therefore, the CPU 200 uses the emergency I2C signal line (bus) to stop the function of only the I2C master block 310 in the I2C master device (master 1) 300. Output to the emergency terminals SDA2 and SCL2 of the I2C master device (master 1) 300 using the bus.

  The semiconductor device 100 that receives the disable signals SCL2 and SDA2 from the CPU 200 via the emergency terminals SDA2 and SCL2 stops the function of the I2C master block 310 in the I2C master device (master 1) 300.

  As described above, according to another configuration example of the I2C system to which the semiconductor device 100 is applied, it is possible to quickly detect signs of abnormality such as deterioration and failure, and to safely stop the I2C master block 310 and the like. be able to.

(Monitoring LSI)
FIG. 10 schematically shows an example of the monitoring LSI 70 in which the semiconductor device 100 according to the embodiment is integrated. The monitoring LSI 70 includes a semiconductor device 100 (not shown) provided with an abnormality detection circuit 40 (not shown) and a monitoring register 71, and is connected to the CPU 200 via an I2C signal line I2C1. When the monitoring LSI 70 detects an abnormality, the monitoring LSI 70 outputs an IRQ signal to the CPU 200 or another device to notify the abnormality detection.

  FIG. 11 schematically shows one application example of the monitoring LSI 70, and the I2C master device 300 includes the I2C master block 310 and the monitoring LSI 70.

  In the example illustrated in FIG. 11, the I2C master block 310 and the monitoring LSI 70 are integrated. However, the I2C slave block 320 and the monitoring LSI 70 may be integrated.

  FIG. 12 schematically shows still another example of the monitoring LSI, and the monitoring LSI 70 is provided independently of the I2C master block 310 and the I2C slave block 320.

  FIG. 13 schematically shows a bus configuration example of a CAN system to which the monitoring LSI 70 (semiconductor device 100) is applied. FIG. 14 schematically illustrates the relationship between the CAN packet error correction signal 401 and the serial interface 402 in the CAN system to which the semiconductor device according to the embodiment is applied.

(Processing operation example of semiconductor device)
FIG. 15 schematically shows a processing operation example of the semiconductor device 100 (abnormality detection circuit 40) according to the embodiment.

  In step S101, when the drive N changes from high level to low level, the timer start signal S is supplied to the timer A (30), and in step S102, the timer A (30) starts to count up the count value CNT.

  Next, in step S103, the timer A (30) determines whether or not the count value CNT has reached a predetermined count set value CNT_MAX. As a result of the determination in step S103, if the count value CNT has reached the predetermined count set value CNT_MAX, the process proceeds to step S108. Conversely, if the count value CNT has not reached the predetermined count set value CNT_MAX, the process proceeds to step S104. move on.

In step S104, the comparator A (20) compares the voltage VN ₁ of node N ₁ and a predetermined threshold voltage Vth. As a result of the judgment in the step S104, if the voltage VN ₁ ≧ the threshold voltage Vth of the node N _1, the comparator A (20), in step S106, sets the counter output C1 to the High level ( "1"). Conversely, if the voltage VN ₁ of the node N ₁ <the threshold voltage Vth, the comparator A (20) sets the counter output C1 to the low level (“0”) in step S105.

  Next, in step S107, the timer A (30) counts up the count value CNT.

  The series of processes of steps S103 to S107 described above are repeated until the count value CNT reaches a predetermined count set value CNT_MAX.

  If the count value CNT has reached the predetermined count set value CNT_MAX as a result of the determination in step S103, then in step S108, the semiconductor device 100 determines whether or not the counter output C1 is at a high level.

As a result of the judgment in the step S108, if the counter output C1 is High level, within a predetermined time, the voltage VN ₁ of node N ₁ is an abnormality in the switching power supply device 10 for reaching the desired voltage Vcc (threshold voltage Vth) ( For example, it is determined that there is no sign of deterioration), and the series of processing ends.

Step S108 a result of the judgment in the counter output C1 is not High level (i.e., the counter output C1 is at Low level), even after the elapse of a predetermined time, the voltage VN ₁ of node N ₁ is the desired voltage Vcc ( Since the threshold voltage Vth has not been reached, it is determined that an abnormality (for example, a sign of deterioration) has occurred in the switching power supply element 10, and in step S109, the semiconductor device 100 executes an abnormality handling process. As a response process at the time of abnormality in step S109, as described above, an alert (for example, warning message, warning sound, etc.) is output, an IRQ signal is output to the CPU 200, and power supply is stopped. It is assumed that the supply will be reduced.

  As described above, according to the present embodiment, an abnormality detection circuit that can monitor voltage changes during power supply and quickly detect signs of abnormality such as deterioration or failure of a switching power supply element and the operation thereof A method, a semiconductor device, an operation method thereof, and a communication system can be provided.

[Other embodiments]
While the embodiments have been described as described above, the discussion and drawings that form part of this disclosure are illustrative and should not be construed as limiting. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the embodiment, a power supply device (switching power supply element 10) that supplies power to a vehicle-mounted electronic device has been described as an example. Not limited to this, power can be supplied to electronic devices used for various purposes.

  In the embodiments, the example in which the semiconductor device 100 is applied to a communication system such as I2C, LVDS, DisplayPort, HDMI (registered trademark), or CAN has been described. The present invention is not limited to this, and can be applied to various communication systems such as SIO (Serial Input / Output) and UART (Universal Asynchronous Receiver Transmitter).

  As described above, various embodiments that are not described herein are included.

  This embodiment can be applied to electronic devices in various fields such as automobiles, airplanes, ships, railways, rockets, medical equipment, industrial machines, robots, and the like.

DESCRIPTION OF SYMBOLS 10 ... Switching power supply element 40 ... Abnormality detection circuit 30 ... Timer A
20 ... Comparator A
61 ... CAN device SG1
62 ... CAN device SG2
70: Monitoring LSI
71 ... Monitoring register 81 ... Block A
82 ... Block B
100 ... Semiconductor device 200 ... CPU
300 ... I2C master device (master 1)
310 ... I2C master block 320 ... I2C slave block 401 ... CAN packet error correction signal 402 ... serial interface C1 ... counter output CNT ... count value CNT_MAX ... count set value EN1, EN2 ... enable terminals EN1, EN2, SCL1, SDA1 ... enable signal I ... Current I2C1 ... I2C signal line L-ch, R-ch ... Data signal M1 ... nMOS transistor N ... Drive (Drive)
N _1, nodes RP, R ₁ , R 2, pull-up resistors S, timer start signals SCL 2, SDA 2, disable signals SCL, clock lines SDA, data lines SDA 1, SCL 1, terminals SDA 2, SCL 2, emergency terminals SP 1, SP 2, SP3 stage t1, t2 time Vcc power supply voltage (desired voltage)
VN ₁ ... voltage Vth ... threshold voltage

Claims (21)

A timer that starts counting up the count value when the voltage input from the outside starts rising, and executes the count-up until the count value reaches a predetermined count setting value;
The externally input voltage is compared with a predetermined threshold voltage. If the voltage is equal to or higher than the threshold voltage, the counter output is set to the first level. If the voltage is lower than the threshold voltage, A comparator for setting the counter output to a second level,
When the count value reaches the predetermined count setting value, the timer refers to the counter output output from the comparator, and determines that an abnormality has occurred when the counter output is not at the first level. An abnormality detection circuit characterized by executing an emergency response process.   The abnormality detection circuit according to claim 1, wherein the voltage input from the outside is a voltage supplied by a switching power supply element.   3. The abnormality detection circuit according to claim 1, wherein the abnormality handling process includes at least one of an alert output process and an interrupt request signal output process. An abnormality detection circuit for monitoring whether or not an abnormality has occurred, based on the slope and required time when the voltage input from the outside rises from the Low level to a desired voltage value,
A semiconductor device characterized in that when the voltage does not rise to the desired voltage with a normal slope and a normal required time, processing for handling an abnormality is executed. The abnormality detection circuit is
A timer that starts counting up a count value when the voltage input from the outside starts increasing, and counts up until the count value reaches a predetermined count setting value;
The externally input voltage is compared with a predetermined threshold voltage. If the voltage is equal to or higher than the threshold voltage, the counter output is set to the first level. If the voltage is lower than the threshold voltage, A comparator for setting the counter output to a second level,
When the count value reaches the predetermined count setting value, the timer refers to the counter output output from the comparator, and determines that an abnormality has occurred when the counter output is not at the first level. The semiconductor device according to claim 4.   6. The semiconductor device according to claim 5, further comprising a transistor that supplies a timer start signal instructing start of the count-up to the timer.   The semiconductor device according to claim 4, wherein the voltage input from the outside is a voltage supplied by a switching power supply element.   8. The semiconductor device according to claim 4, wherein the process for handling an abnormality includes at least one of an alert output process and an interrupt request signal output process. 9. A communication system for connecting a plurality of devices via a bus so that they can communicate with each other.
An abnormality detection circuit for monitoring whether or not an abnormality has occurred based on a slope and a required time when the voltage pulled up to the bus rises from a low level to a desired voltage value, and the voltage is normal A communication system comprising: a semiconductor device that executes a response process when an abnormality occurs when the voltage does not rise to the desired voltage in a slant and normal time. The abnormality detection circuit is
A timer that starts counting up a count value when the pulled up voltage starts increasing, and counts up until the count value reaches a predetermined count setting value;
The pulled-up voltage is compared with a predetermined threshold voltage, and if the voltage is greater than or equal to the threshold voltage, the counter output is set to the first level, and if the voltage is less than the threshold voltage, A comparator for setting the counter output to a second level,
The timer refers to the counter output output from the comparator when the count value reaches the predetermined count set value, and performs the processing for the abnormality when the counter output is not the first level. The communication system according to claim 9, wherein the communication system is executed.   The communication system according to claim 10, further comprising a transistor that supplies a timer start signal instructing start of the count-up to the timer.   The communication system according to claim 9, wherein the pulled-up voltage is a voltage supplied by a switching power supply element.   The communication system according to claim 9, wherein the process for handling an abnormality includes at least one of an alert output process and an interrupt request signal output process. A CPU that transmits an enable signal for enabling the functions of the plurality of devices to the plurality of devices;
The semiconductor device transmits an interrupt request signal to the CPU as a process for handling the abnormality,
14. The CPU according to claim 9, wherein the CPU that has received the interrupt request signal transmits a disable signal that disables the functions of the plurality of devices to the plurality of devices. Communication system.   The CPU that receives the interrupt request signal transmits a disable signal that disables the functions of the plurality of devices to the plurality of devices using an emergency bus. The communication system described.   The communication system according to claim 9, wherein the bus is an I2C bus or a CAN bus.   The communication system according to claim 9, wherein the semiconductor device is integrated with one of the plurality of devices.   The communication system according to claim 9, wherein the semiconductor device is integrated as a monitoring LSI.   The communication system according to claim 18, wherein the monitoring LSI includes a monitoring register. When the voltage input from the outside starts increasing, the timer starts counting up the count value, and executes the count up until the count value reaches a predetermined count setting value;
The comparator compares the voltage input from the outside with a predetermined threshold voltage, and if the voltage is equal to or higher than the threshold voltage, the counter output is set to the first level, and the voltage is less than the threshold voltage. If so, setting the counter output to a second level;
When the count value reaches the predetermined count setting value, the timer refers to the counter output output from the comparator, and executes a response process when the counter output is not the first level. And a step of operating the abnormality detection circuit. Monitoring whether or not an abnormality has occurred based on the slope and required time when the externally input voltage rises from a low level to a desired voltage value;
When the voltage does not rise to the desired voltage with a normal slope and a normal required time, a step of performing a response process at the time of abnormality is included.
Monitoring whether the abnormality has occurred,
When the voltage input from the outside starts to rise, a timer starts counting up the count value, and executes the count up until the count value reaches a predetermined count setting value;
The comparator compares the voltage input from the outside with a predetermined threshold voltage, and if the voltage is equal to or higher than the threshold voltage, the counter output is set to the first level, and the voltage is less than the threshold voltage. If so, setting the counter output to a second level;
When the count value reaches the predetermined count setting value, the timer refers to the counter output output from the comparator, and executes a response process when the counter output is not the first level. And a step of operating the semiconductor device.

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