JP2017152944A - Image processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid reduction of an image reading speed while preventing line image data from being varied by spectrum spreading even when processing a line image signal by using a modulation clock that is modulated by the spectrum spreading.SOLUTION: A clock selection section 831 alternately selects one of a first modulation clock Ck1 and a second modulation clock Ck2 synchronously to a cycle of a drive signal Sd controlling an image sensor 13. The first modulation clock Ck1 is a clock that is modulated by spectrum spreading. For the second modulation clock Ck2, a phase of modulation of the spectrum spreading is deviated from the first modulation clock Ck1 by 180° at a time point in which the drive signal Sd is generated. A line image signal is processed while defining a selection modulation clock Ck3 that is selected, as a reference.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an image processing apparatus including an image sensor.

  An image processing apparatus having an image reading function such as a scanner, a copier, or a facsimile apparatus includes an image sensor such as a charge coupled device (CCD) or a contact image sensor (CIS). The image sensor reads a line image along the main scanning direction in synchronization with an input drive signal and outputs an analog line image signal. The image sensor may be referred to as a linear image sensor or a line sensor.

  In the image processing apparatus, unnecessary radiation (EMI) caused by a timing signal such as a high-speed clock associated with the image sensor becomes a problem. As a measure against EMI, a spread spectrum clock generator (SSCG) is used. The SSCG generates a modulation clock obtained by modulating a reference clock having a fixed period by spread spectrum. By adopting the SSCG, the peak level of the EMI per unit time is reduced.

  In general, the higher the spread rate of the spectrum spread, the more the peak level of the EMI per unit time is reduced.

  However, if a signal processing unit such as an analog front end (AFE) processes the analog line image signal at a timing based on the modulation clock, the image data varies in synchronization with the modulation period.

  When a line period, which is an output period of the drive signal to the image sensor, is not synchronized with a modulation period of the spread spectrum, it is difficult to suppress variation included in each line image signal. As a result, a striped pattern is formed in the output image.

  In the image processing apparatus, it is known that the line period is set to an integral multiple of the modulation period (see, for example, Patent Document 1). Accordingly, the modulation clock is synchronized every time the line image signal for one line is processed. In this case, by using the line image data for one line when the image sensor reads a uniform light amount in advance, correction for suppressing variation included in each line image signal is performed.

JP 2002-281252 A

  By the way, when the line period is set to an integral multiple of the modulation period, the read time may be delayed for each line in order to adjust the output timing of the drive signal to the image sensor. As a result, the image reading speed may be reduced.

  An object of the present invention is to reduce the image reading speed while suppressing variations in the line image data due to the spectrum spread even when the line image signal is processed using a modulation clock modulated by the spectrum spread. An object of the present invention is to provide an image processing apparatus that can be avoided.

  An image processing apparatus according to an aspect of the present invention includes a drive signal generation unit, an image sensor, a scanning mechanism, a first modulation clock generation unit, a second modulation clock generation unit, a clock selection unit, and an analog front. An end and an image processing unit. The drive signal generation unit generates a drive signal for controlling timing for reading a line image along the main scanning direction from the document. The image sensor is a sensor that reads the line image from the document and outputs an analog line image signal in synchronization with the drive signal. The scanning mechanism is a mechanism that moves the reading position of the line image on the document at a constant speed in a sub-scanning direction orthogonal to the main scanning direction. The first modulation clock generator generates a first modulation clock by modulating a reference clock having a constant period by spread spectrum. The second modulation clock generation unit generates a second modulation clock by delaying the first modulation clock. The second modulation clock is a clock whose phase of the spread spectrum modulation is shifted by 180 ° with respect to the first modulation clock when the drive signal is generated. The clock selection unit alternately selects one of the first modulation clock and the second modulation clock in synchronization with the cycle of the drive signal and outputs the selected modulation clock. The analog front end converts the line image signal into digital line image data at a timing based on the selected modulation clock. The image processing unit processes the line image data at a timing based on the selected modulation clock. The image processing unit includes a pre-processing unit and a post-processing unit. The pre-processing unit synthesizes the line image data for two consecutive lines and generates combined line image data for one line. The post-processing unit processes the combined line image data as image data for one line in the read image.

  According to the present invention, even when a line image signal is processed using a modulation clock modulated by spread spectrum, the image reading speed is reduced while suppressing variations in the line image data due to the spread spectrum. An image processing apparatus that can be avoided can be provided.

FIG. 1 is a configuration diagram of an image processing apparatus according to the embodiment. FIG. 2 is a block diagram of a data processing unit of the image processing apparatus according to the embodiment. FIG. 3 is a block diagram of a clock generation unit of the image processing apparatus according to the embodiment. FIG. 4 is a time chart of the period of the modulation clock and the drive signal during image reading of the image processing apparatus according to the embodiment. FIG. 5 is a flowchart illustrating an example of a procedure of image reading processing in the image processing apparatus according to the embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the following embodiment is an example which actualized this invention, Comprising: It does not have the character which limits the technical scope of this invention.

  First, the configuration of the image processing apparatus 10 according to the embodiment will be described with reference to FIG.

  The image processing apparatus 10 includes an image reading apparatus 1 and an image forming apparatus 2. Further, the image processing apparatus 10 also includes a data processing unit 8 and an operation display unit 80 that are common to the image reading apparatus 1 and the image forming apparatus 2. The data processing unit 8 controls each device in the image reading apparatus 1 and the image forming apparatus 2 and performs other data processing.

  For example, the image processing apparatus 10 is a copying machine, a printer or a facsimile machine having a copying machine function, or a multifunction machine having a plurality of image processing functions including an image reading function.

[Image reading apparatus 1]
The image reading apparatus 1 includes a document scanning unit 11 and a document table cover 12. The document table cover 12 is supported so as to be rotatable with respect to the document scanning unit 11. The document scanning unit 11 includes a transparent first contact glass 16 and a second contact glass 160, and the document table cover 12 covers the upper surfaces of the first contact glass 16 and the second contact glass 160.

  The first contact glass 16 is a document table on which a document 90 as an image reading object is placed. In general, the first contact glass 16 is called platen glass or the like.

  The document scanning unit 11 further includes an image sensor 13 and an optical system moving mechanism 110. The document scanning unit 11 in this embodiment also includes a light guide unit 111 including a mirror and a lens.

  The image sensor 13 is a linear image sensor that reads a one-dimensional line image along the main scanning direction D1 from the document 90 and outputs an analog line image signal Ia0. The image sensor 13 in this embodiment is a CCD image sensor.

  The image sensor 13 reads the line image and outputs the line image signal Ia0 in synchronization with the input drive signal Sd (see FIG. 2). The drive signal Sd is a signal that controls the timing for reading the line image from the document 90 along the main scanning direction D1. In the following description, the output cycle of the drive signal Sd is referred to as a line cycle Td.

  In the following description, one direction along the original 90 and a direction perpendicular thereto are referred to as a main scanning direction D1 and a sub-scanning direction D2, respectively. The line image is a one-dimensional image along the main scanning direction D1.

  The light emitting unit 14 is a light source such as an LED array that irradiates the original 90 with light. The light emitting unit 14 is formed to extend in the main scanning direction D1, and illuminates a region along the main scanning direction D1 in the document 90.

  The light guide unit 111 guides the reflected light from the document 90 to the image sensor 13 and condenses it on the light receiving unit of the image sensor 13. The light guide 111 includes a first light guide 112 supported by the optical system moving mechanism 110 and other second light guides 113.

  The optical system moving mechanism 110 is a mechanism that moves the light emitting unit 14 and the first light guide unit 112 at a constant speed along the sub-scanning direction D2 at a position close to the first contact glass 16. As the light emitting unit 14 and the first light guide unit 112 move along the sub-scanning direction D2, the reading position of the line image on the document 90 moves at a constant speed in the sub-scanning direction D2.

  The image sensor 13 sequentially reads the line images at different positions on the document 90 in the sub-scanning direction D2. The optical system moving mechanism 110 is an example of a scanning mechanism.

  An ADF 120 is incorporated in the document table cover 12. The ADF 120 includes a document supply tray 121, a document delivery mechanism 122, a document transport mechanism 123, and a document discharge tray 124.

  The document delivery mechanism 122 sends the documents 90 set on the document supply tray 121 one by one to the document transport path R0. The document transport mechanism 123 transports the document 90 sent from the document delivery mechanism 122 along the document transport path R0 and further discharges it to the document discharge tray 124.

  The document transport path R0 is formed along a predetermined path that passes through the fixed reading position P0 along the transparent second contact glass 160. For example, the second contact glass 160 is a part of the first contact glass 16. The document transport mechanism 123 transports the document 90 at a constant speed at least when the document 90 passes the fixed reading position P0.

  The optical system moving mechanism 110 can hold the first light guide 112 at a position facing the fixed reading position P0. The ADF 120 operates in a state where the document table cover 12 is closed and the image sensor 13 faces the fixed reading position P0.

  When the ADF 120 operates, the first light guide unit 112 is held at a position facing the fixed reading position P0. In this state, the light emitting unit 14 irradiates light toward the fixed reading position P0. Further, the image sensor 13 sequentially detects the amount of reflected light from a portion of one line passing through the fixed reading position P0 on the document 90, and sequentially outputs a line image signal Ia0 representing the line image.

  When the ADF 120 conveys the original 90 at a constant speed, the reading position of the line image on the original 90 moves at a constant speed in the sub-scanning direction D2. The ADF 120 is also an example of the scanning mechanism.

  The second contact glass 160 and the color reference portion 17 are arranged to face each other on both sides of the fixed reading position P0 of the document transport path R0. The surface facing the fixed reading position P0 in the color reference unit 17 is a surface of a uniform reference color having a high light reflectance. Generally, the reference color is white. It is also conceivable that the reference color is a light yellowish color.

  The operation display unit 80 is, for example, an operation input unit including a touch panel and operation buttons, and is also a display unit including a liquid crystal display panel and a notification lamp.

  The data processing unit 8 controls various electric devices included in the image reading apparatus 1 and the image forming apparatus 2 based on input data input through the operation display unit 80 and detection results of various sensors.

  Furthermore, the data processing unit 8 also executes various signal processing on the line image signal Ia0 output from the image sensor 13. The data processing unit 8 includes an AFE 86 that performs predetermined signal processing on the line image signal Ia0 output from the image sensor 13.

  The AFE 86 converts the line image signal Ia0 into digital line image data Id0 (see FIG. 2). More specifically, the AFE 86 performs offset adjustment on the line image signal Ia0, and further amplifies the signal on which the offset adjustment has been performed. Further, the AFE 86 generates line image data Id0 by digitally converting the amplified signal.

[Image forming apparatus 2]
The image forming apparatus 2 includes a device that forms an image on the sheet material 9 according to the image data output from the image reading apparatus 1. The sheet material 9 is a sheet-like image forming medium such as paper, coated paper, postcard, envelope, and OHP sheet.

  The image forming apparatus 2 includes a sheet supply unit 30, a sheet conveying unit 3, an image forming unit 4, an optical scanning unit 5, a fixing unit 6, and the like. An image forming apparatus 2 shown in FIG. 1 is an electrophotographic image forming apparatus. It is also conceivable that the image forming apparatus 2 is an image forming apparatus of another method such as an ink jet method.

  The sheet supply unit 30 is a portion on which a plurality of sheet materials 9 are stacked. The sheet conveying unit 3 includes a sheet feeding mechanism 31 and a sheet conveying mechanism 32.

  The sheet delivery mechanism 31 sends the sheet material 9 from the sheet supply unit 30 toward the sheet conveyance path 300. The sheet transport mechanism 32 transports the sheet material 9 along the sheet transport path 300. As a result, the sheet material 9 passes through the image forming unit 4 and the fixing unit 6 and then is discharged onto the sheet discharge tray 101 from the discharge port of the sheet conveyance path 300.

  The image forming unit 4 includes a drum-shaped photoconductor 41, a charging device 42, a developing device 43, a transfer device 45, a cleaning device 47, and the like. The photoreceptor 41 is an example of an image carrier that carries a developer image.

  The photoconductor 41 rotates, and the charging device 42 charges the surface of the photoconductor 41 uniformly. Further, an electrostatic latent image is written on the surface of the photoreceptor 41 charged by the optical scanning unit 5 scanning the laser beam. Further, the developing device 43 supplies the developer to the photoconductor 41 to develop the electrostatic latent image into the image of the developer.

  Further, the transfer device 45 transfers the developer image on the surface of the photoconductor 41 to the sheet material 9 moving between the photoconductor 41 and the transfer device 45. Further, the cleaning device 47 removes the developer remaining on the surface of the photoreceptor 41.

  The fixing unit 6 sends the sheet material 9 on which an image is formed between the heating roller 61 and the pressure roller 62 including the heater to the subsequent process. As a result, the fixing unit 6 heats the developer on the sheet material 9 to fix the image on the sheet material 9.

  As will be described later, the image processing apparatus 10 includes an SSCG 842 as a measure against the EMI. The SSCG 842 generates a first modulation clock Ck1 obtained by modulating the reference clock Ck0 having a fixed period by spread spectrum (see FIG. 2). By adopting SSCG842, the peak level of the EMI per unit time is reduced.

  In general, the higher the spread rate of the spectrum spread, the more the peak level of the EMI per unit time is reduced.

  The line image signal Ia0 output from the image sensor 13 is converted into digital line image data Id0 by an AFE 86 described later (see FIG. 2). Further, the image processing unit 87 performs various data processing on the line image data Id0.

  When the analog line image signal Ia0 and the line image data Id0 are processed at the timing based on the clock modulated by the spread spectrum, the line image data Id0 varies in synchronization with the modulation period.

  When the line period Td is not synchronized with the spread spectrum modulation period Ts, it is difficult to suppress variations included in each of the line image data Id0. As a result, a striped pattern is formed in the output image.

  By the way, when the line period Td is set to an integral multiple of the modulation period Ts, the read time may be delayed for each line in order to adjust the output timing of the drive signal Sd to the image sensor 13. As a result, the image reading speed may be reduced.

  On the other hand, according to the image processing apparatus 10, even when the line image signal Ia0 is processed using the clock modulated by the spectrum spread, the line resulting from the spectrum spread is avoided while avoiding a decrease in the image reading speed. Variations in the image data Id0 can be suppressed.

[Data processing unit 8]
Next, the data processing unit 8 of the image processing apparatus 10 will be described with reference to FIGS.

  As shown in FIG. 2, the data processing unit 8 includes an MPU (Micro Processor Unit) 81, a data storage unit 82, a clock generation unit 83, an AFE 86, an image processing unit 87, an image storage unit 88, and the like.

  As shown in FIG. 3, the clock generation unit 83 includes a first modulation clock generation unit 84, a second modulation clock generation unit 85, a selector 831, a timing signal generation unit 832, and the like. The first modulation clock generator 84 includes an oscillator 841, an SSCG 842, a first PLL circuit 843, and the like.

  The second modulation clock generator 85 includes a first delay circuit 851, a second delay circuit 852, a second PLL circuit 853, and the like.

  The portions other than the oscillator 841 and the SSCG 842 in the clock generation unit 83, the AFE 86, and the image processing unit 87 are configured by, for example, a DSP (Digital Signal Processor) or an ASIC (Application Specific Integrated Circuit).

  The MPU 81 is a processor that executes various arithmetic processes. The data storage unit 82 is a nonvolatile information storage medium in which a program for causing the MPU 81 to execute various processes and other information are stored in advance. The data storage unit 82 is also an information storage medium in which various information can be read and written by the MPU 81.

  The MPU 81 comprehensively controls the image processing apparatus 10 by executing various programs stored in advance in the data storage unit 82.

  The oscillator 841 is an element that generates a reference clock Ck0 having a constant period. The SSCG 842 generates a first modulation clock Ck1 obtained by modulating a reference clock Ck0 having a fixed period by spread spectrum. In this embodiment, the spread spectrum modulation period Ts is constant.

  The first modulation clock Ck1 is stabilized by the first PLL circuit 843 and output to the selector 831. As described above, the first modulation clock generation unit 84 is a circuit that generates the first modulation clock Ck1 by modulating the reference clock Ck0 having a constant period by the spectrum spreading.

  The second modulation clock generation unit 85 is a circuit that generates the second modulation clock Ck2 by delaying the first modulation clock Ck1. The second modulation clock Ck2 is a clock whose phase of the spread spectrum modulation is shifted by 180 ° with respect to the first modulation clock Ck1 when the drive signal Sd is generated.

  In the second modulation clock generation unit 85, the first delay circuit 851 is a circuit that outputs a clock obtained by delaying the input clock by a time that is half the modulation period of the spread spectrum. On the other hand, the second delay circuit 852 is a circuit that outputs a clock obtained by delaying the input clock by the time of the line period Td. The line cycle Td is output from the timing signal generator 832.

  Then, the first delay circuit 851 and the second delay circuit 852 generate the second modulation clock Ck2 by acting in series with the first modulation clock Ck1. Accordingly, the second modulation clock Ck2 can be generated with a relatively simple circuit configuration.

  The first delay circuit 851 and the second delay circuit 852 are examples of the first delay unit and the second delay unit, respectively.

  In the example shown in FIG. 3, the first delay circuit 851 delays the time by half the modulation period Ts of the first modulation clock Ck1. In this case, the output clock of the first delay circuit 851 is a clock whose phase of the spectrum spread modulation is opposite to that of the first modulation clock Ck1. Hereinafter, this clock is referred to as an antiphase modulation clock Ck11.

  Further, the second delay circuit 852 delays the antiphase modulation clock Ck11 by the time of the line period Td. As a result, the second modulation clock Ck2 output from the second delay circuit 852 becomes a clock whose phase of the spread spectrum modulation is shifted by 180 ° with respect to the first modulation clock Ck1 when the drive signal Sd is generated.

  The second modulation clock Ck2 output from the second delay circuit 852 is stabilized by the second PLL circuit 853 and output to the selector 831.

  FIG. 4 is a time chart of the periods Tck1, Tck11, Tck2, and Tck3 of each modulation clock and the drive signal Sd during image reading by the image processing apparatus 10.

  In FIG. 4, the first modulation clock cycle Tck1 is the cycle of the first modulation clock Ck1 that varies due to the spread spectrum modulation. The anti-phase modulation clock cycle Tck11 is the cycle of the anti-phase modulation clock Ck11 that varies due to the spread spectrum modulation.

  The second modulation clock cycle Tck2 is a cycle of the second modulation clock Ck2 that varies due to the spread spectrum modulation. The selective modulation clock cycle Tck3 is a cycle of a selective modulation clock Ck3 described later.

  Due to the action of the first delay circuit 851, the phase of change of the anti-phase modulation clock cycle Tck11 is delayed by half the time of the modulation cycle Ts of the first modulation clock Ck1 with respect to the phase of change of the first modulation clock cycle Tck1. Yes.

  Further, by adopting the second delay circuit 852, the phase of change of the second modulation clock cycle Tck2 is delayed by the time of the line cycle Td with respect to the phase of change of the anti-phase modulation clock cycle Tck11.

  Therefore, as apparent from FIG. 4, when the active drive signal Sd is generated, the phase of the change in the second modulation clock cycle Tck2 is substantially the phase of the change in the first modulation clock cycle Tck1 one line before. Is shifted by 180 °. The phase of change of the first modulation clock cycle Tck1 and the phase of change of the second modulation clock cycle Tck2 are the phases of the spread spectrum modulation. In the present embodiment, the active and inactive states of the drive signal Sd are High and Low states, respectively. Note that the active and inactive states of the drive signal Sd may be opposite to the above.

  The selector 831 is a circuit that alternately selects one of the first modulation clock Ck1 and the second modulation clock Ck2 and outputs the selected modulation clock. In the following description, the clock output from the selector 831 is referred to as a selective modulation clock Ck3.

  The selector 831 alternately selects one of the first modulation clock Ck1 and the second modulation clock Ck2 every time a preset target number of clock pulses is generated in the selected modulation clock Ck3. As will be described later, every time the target number of clock pulses is generated in the selected modulation clock Ck3, an active drive signal Sd is output to the image sensor 13.

  Therefore, the selector 831 alternately selects one of the first modulation clock Ck1 and the second modulation clock Ck2 in synchronization with the cycle of the drive signal Sd, and outputs the selected modulation clock Ck3. The selector 831 is an example of a clock selection unit.

  As shown in FIG. 4, the phase of change of the selected modulation clock cycle Tck3 is shifted by 180 ° every time the active drive signal Sd is generated. In other words, the phase of the selected modulation clock cycle Tck3 is shifted by 180 ° between the odd line and the even line.

  The timing signal generator 832 is a circuit that generates various timing signals based on the selected modulation clock Ck3. The timing signal generator 832 generates the timing signal by frequency multiplication processing, frequency division processing, and count processing for the selected modulation clock Ck3.

  The timing signal generation unit 832 includes a pixel clock output circuit 8320, a sample hold signal generation circuit 8321, a drive signal generation circuit 8322, and the like.

  The pixel clock output circuit 8320 is a circuit that outputs the pixel clock Ckp. The pixel clock Ckp is a signal that defines the timing of capturing each image value of the line image data Id0 by the image processing unit 87. The pixel clock Ckp is also a signal that defines the image reading timing in units of pixels by the image sensor 13. For example, it is conceivable that the pixel clock Ckp is the selective modulation clock Ck3 itself.

  The sample hold signal generation circuit 8321 is a circuit that generates the sample hold signal Sh. The sample hold signal Sh is a signal that defines the timing at which the analog line image signal Ia0 is digitally converted into data of each pixel in the AFE 86. The pixel clock Ckp and the sample hold signal Sh are synchronized with each other.

  The drive signal generation circuit 8322 is a circuit that generates the drive signal Sd output to the image sensor 13. The drive signal generation circuit 8322 generates the drive signal Sd with reference to the selected modulation clock Ck3. The drive signal generation circuit 8322 is an example of a drive signal generation unit.

  The drive signal generation circuit 8322 outputs an active (High) drive signal Sd each time the target number of clock pulses set in advance in the selected modulation clock Ck3 is generated. The output cycle of the drive signal Sd generated in this way is the line cycle Td.

  In the present embodiment, the drive signal generation circuit 8322 generates a drive signal Sd that is generated at a cycle in which the resolution of the line image signal Ia0 in the sub-scanning direction D2 is twice the resolution of the image sensor 13 in the main scanning direction D1. .

  For example, assume that the resolution of the image sensor 13 in the main scanning direction D1 is 600 dpi. In this case, the line period Td is set so that the line image signal Ia0 having a resolution of 1200 dpi is obtained in the sub-scanning direction D2. Then, the target number of clock pulses corresponding to the line period Td is preset.

  The image sensor 13 reads an image in units of pixels every time the pixel clock Ckp is input, and outputs a line image signal Ia0 for one line every time the drive signal Sd changes from inactive (Low) to active (High). Output.

  The AFE 86 is a circuit that processes the line image signal Ia0 in synchronization with a timing signal based on the selected modulation clock Ck3. The AFE 86 includes a sample hold unit 861, an amplification unit 862, an analog / digital converter 863, and the like.

  The sample hold unit 861 samples the line image signal Ia0 in synchronization with the sample hold signal Sh and outputs a sampling signal. The level of the sampling signal is maintained until a new sampling signal is obtained. The sample hold signal Sh is an example of a timing signal based on the selected modulation clock Ck3.

  The amplifying unit 862 is a programmable gain amplifier that amplifies the sampling signal. The amplifying unit 862 amplifies the sampling signal with a gain according to an input not shown gain control signal. For example, it is conceivable that the gain control signal is supplied from the MPU 81.

  The analog / digital converter 863 converts the amplified sampling signal into digital data. A data string for one line output from the analog / digital converter 863 is line image data Id0. As described above, the AFE 86 converts the line image signal Ia0 into the digital line image data Id0 at a timing synchronized with the sample hold signal Sh generated based on the selected modulation clock Ck3. The timing synchronized with the sample hold signal Sh is an example of timing based on the selected modulation clock Ck3.

  The image processing unit 87 processes the line image data Id0 at a timing synchronized with the pixel clock Ckp. The pixel clock Ckp is an example of a timing signal based on the selected modulation clock Ck3.

  The image processing unit 87 includes a synthesis unit 871, a correction unit 872, and a post-correction processing unit 874. Further, the image processing unit 87 includes a black reference data recording unit 875, a white reference data recording unit 876, a correction data storage unit 873, and the like.

  The synthesizing unit 871 executes a synthesizing process every time line image data Id0 for two continuous lines is obtained. The synthesizing process is a process for synthesizing line image data Id0 for two continuous lines to generate synthesized line image data Id01 for one line. The synthesizing unit 871 is an example of a preprocessing unit.

  For example, in the combining process, the combining unit 871 may calculate the addition value of the corresponding pixel values in the line image data Id0 for two consecutive lines as each pixel value of the combined line image data Id01. In the synthesis process, it is not unimaginable that the average value of the corresponding pixel values in the line image data Id0 for two consecutive lines is calculated as each pixel value of the synthesized line image data Id01.

  The correction unit 872 performs shading correction on the combined line image data Id01. Further, the correction unit 872 performs known correction processing such as conversion processing from light amount equivalent data to density equivalent data and gamma correction processing on the combined line image data Id01. The correction unit 872 is an example of a shading correction unit.

  The correction data storage unit 873 stores correction data Dc0 used for the shading correction. The post-correction processing unit 874 performs other image processing on the combined line image data Id01 after the correction such as the shading correction.

  That is, the correction unit 872 and the post-correction processing unit 874 process the combined line image data Id01 as image data for one line in the read image. The read image is an image read from the document 90 by the image sensor 13.

  The image storage unit 88 stores the combined line image data Id01 after the image processing is performed. The image storage unit 88 is a so-called frame memory. The MPU 81 can acquire the pixel value included in the line image data Id0 output from the AFE 86 via the image processing unit 87 and the image storage unit 88.

  The black reference data recording unit 875 and the white reference data recording unit 876 execute processing for recording the combined line image data Id01 obtained under a predetermined condition in the correction data storage unit 873 as the correction data Dc0.

[Image reading processing]
Next, an example of the procedure of the image reading process in the image reading apparatus 1 of the image processing apparatus 10 will be described with reference to the flowchart shown in FIG. In the following description, S1, S2,... Represent identification codes of respective steps executed by the data processing unit 8 in the image reading process.

  The MPU 81 of the data processing unit 8 starts the image reading process when detecting that a predetermined start operation has been performed on the operation display unit 80.

<Process S1>
First, the MPU 81 controls the optical system moving mechanism 110 to position the first light guide unit 112 and the light emitting unit 14 at the home position. The home position is a position where the first light guide 112 faces the fixed reading position P 0, that is, a position where the first light guide 112 faces the color reference portion 17.

<Process S2>
Next, the clock generation unit 83 starts outputting timing signals such as the pixel clock Ckp, the sample hold signal Sh, and the drive signal Sd. The output periods of the pixel clock Ckp and the sample hold signal Sh output in step S2 are the same as those output periods during image reading.

<Process S3>
When the output of the drive signal Sd is started, the black reference data recording unit 875 of the image processing unit 87 executes black reference data recording processing.

  The black reference data recording process is a process of storing the composite line image data Id01 obtained in the dark state in the correction data storage unit 873 as the black reference data. The dark state is a state where the reading direction of the line image is not illuminated. The combined line image data Id01 is data obtained by combining two line image data Id0 obtained continuously.

<Step S4>
Next, the MPU 81 lights the light emitting unit 14. When the light emitting unit 14 is turned on, the reading direction of the line image is illuminated.

<Step S5>
When the light emitting unit 14 is turned on, the white reference data recording unit 876 of the image processing unit 87 executes white reference data recording processing.

  The white reference data recording process is a process of storing the composite line image data Id01 obtained in the bright state in the correction data storage unit 873 as the black reference data. The bright state is a state in which the color reference unit 17 arranged in the reading direction of the line image is illuminated.

  The post-processing unit that the correction unit 872, the post-correction processing unit 874, the black reference data recording unit 875, and the white reference data recording unit 876 process the combined line image data Id01 as image data for one line in the read image. It is an example.

<Step S6>
Next, the data processing unit 8 executes reading processing of the original image for one page. In the document image reading process, the correction unit 872 of the image processing unit 87 executes the shading correction using the correction data Dc0 every time the combined line image data Id01 is obtained. The correction data Dc0 used here is the black reference data and the white reference data recorded in the correction data storage unit 873 by the processes of steps S3 to S5.

<Step S7>
When the document image reading process for one page is completed, the MPU 81 determines whether the image reading of the document 90 on the last page is completed. When the image reading of the document 90 of the last page is completed, the MPU 81 ends the image reading process.

  If the image reading of the last-page document 90 has not been completed, the data processing unit 8 repeats the process of step S6 until the image reading of the last-page document 90 is completed.

  According to the present embodiment, the change phase of the selected modulation clock cycle Tck3 is reversed every time an active (High) drive signal Sd is generated (see FIG. 4). Therefore, the component of the variation caused by the spectrum spread is also opposite in phase between the two line image data Id0 obtained continuously.

  Therefore, when the line image data Id0 for two lines obtained continuously is synthesized, the component of variation caused by the spectrum spread is canceled in the synthesized line image data Id01. Further, it is not necessary to set a waiting time for adjusting the output timing of the drive signal Sd in order to obtain line image data Id0 that alternately includes variations in opposite phases.

  From the above, according to the present embodiment, even when the line image signal Ia0 is processed using the clock modulated by the spectrum spread, it is caused by the spectrum spread while avoiding a decrease in the image reading speed. Variations in the line image data Id0 can be suppressed.

  Similarly, with respect to the correction data Dc0 used for the shading correction, the variation in the line image data Id0 due to the spread spectrum is suppressed.

  In the present embodiment, the line period Td is set so that the resolution of the line image signal Ia0 in the sub-scanning direction D2 is twice the resolution in the main scanning direction D1. Thereby, it is possible to make the resolutions in the main scanning direction D1 and the sub-scanning direction D2 uniform while avoiding a decrease in the image reading speed.

[Application example]
In the image processing apparatus 10 shown above, the image sensor 13 may be a CIS (Contact Image Sensor). The CIS is modularized as a CIS module together with the light emitting unit 14 and the lens.

  When the image sensor 13 is the CIS, the optical system moving mechanism 110 is a mechanism that moves the CIS module along the first contact glass 16 and the second contact glass 160.

  The image processing apparatus according to the present invention can be freely combined with the above-described embodiments and application examples, or can be appropriately modified within the scope of the invention described in each claim. Alternatively, it may be configured by omitting a part.

1: Image reading device 2: Image forming device 3: Sheet conveying unit 4: Image forming unit 5: Optical scanning unit 6: Fixing unit 8: Data processing unit 9: Sheet material 10: Image processing device 11: Document scanning unit 12: Document table cover 13: Image sensor 14: Light emitting unit 16: First contact glass 17: Color reference unit 30: Sheet supply unit 31: Sheet feeding mechanism 32: Sheet transport mechanism 41: Photoconductor 42: Charging device 43: Developing device 45 : Transfer device 47: Cleaning device 61: Heating roller 62: Pressure roller 80: Operation display unit 81: MPU
82: data storage unit 83: clock generation unit 84: first modulation clock generation unit 85: second modulation clock generation unit 87: image processing unit 88: image storage unit 90: document 101: sheet discharge tray 110: optical system moving mechanism (Scanning mechanism)
111: Light guide 112: First light guide 113: Second light guide 120: ADF (scanning mechanism)
121: Document supply tray 122: Document delivery mechanism 123: Document conveyance mechanism 124: Document discharge tray 160: Second contact glass 300: Sheet conveyance path 831: Selector (clock selection unit)
832: Timing signal generator 841: Oscillator 843: First PLL circuit 851: First delay circuit (first delay unit)
852: second delay circuit (second delay unit)
853: Second PLL circuit 861: Sample hold unit 862: Amplifying unit 863: Digital converter 871: Synthesizer (pre-processing unit)
872: Correction unit (shading correction unit, post-processing unit)
873: Correction data storage unit 874: Post-correction processing unit (post-processing unit)
875: black reference data recording unit 876: white reference data recording unit 8320: pixel clock output circuit 8321: sample hold signal generation circuit 8322: drive signal generation circuit (drive signal generation unit)
Ck0: reference clock Ck1: first modulation clock Ck11: antiphase modulation clock Ck2: second modulation clock Ck3: selection modulation clock Ckp: pixel clock D1: main scanning direction D2: sub-scanning direction Dc0: correction data Ia0: line image signal Id0: Line image data Id01: Composite line image data P0: Fixed reading position R0: Document transport path Sd: Drive signal Sh: Sample hold signal Tck1: First modulation clock cycle Tck11: Antiphase modulation clock cycle Tck2: Second modulation clock Period Tck3: Selected modulation clock period Td: Line period Ts: Modulation period

Claims (3)

A drive signal generation unit that generates a drive signal for controlling the timing of reading a line image along the main scanning direction from the document;
An image sensor that reads the line image from the document and outputs an analog line image signal in synchronization with the drive signal;
A scanning mechanism for moving the reading position of the line image on the document at a constant speed in a sub-scanning direction orthogonal to the main scanning direction;
A first modulation clock generator for generating a first modulation clock by modulating a reference clock having a fixed period by spread spectrum;
Second modulation clock generation for delaying the first modulation clock to generate a second modulation clock whose phase of modulation of the spread spectrum is shifted by 180 ° with respect to the first modulation clock at the time when the drive signal is generated And
A clock selection unit that alternately selects one of the first modulation clock and the second modulation clock in synchronization with a cycle of the drive signal and outputs a selected modulation clock;
An analog front end for converting the line image signal into digital line image data at a timing based on the selected modulation clock;
An image processing unit that processes the line image data at a timing based on the selected modulation clock;
The image processing unit
A pre-processing unit that generates a combined line image data for one line by combining the line image data for two consecutive lines, and
And a post-processing unit that processes the combined line image data as image data for one line in the read image.   The drive signal generation unit generates the drive signal generated at a period in which the resolution of the line image signal in the sub-scanning direction is twice the resolution of the image sensor in the main scanning direction. The image processing apparatus described. The post-processing unit of the image processing unit is
A black reference data recording unit for storing the combined line image data obtained in a state where the reading direction of the line image is not illuminated as black reference data in a correction data storage unit;
A white reference data recording unit that stores the combined line image data obtained in a state where the color reference unit arranged in the reading direction of the line image is illuminated as white reference data in the correction data storage unit;
The image processing apparatus according to claim 1, further comprising: a shading correction unit that performs a shading correction of the combined line image data using the black reference data and the white reference data.

Images