JP6150618B2 - Image processing apparatus and data transfer method - Google Patents

Description

  The present invention relates to an image processing apparatus and a data transfer method for transferring image data by serial communication.

  In image processing apparatuses such as scanners, facsimile apparatuses, copiers, and multifunction machines, image data may be transferred inside the apparatus by serial communication. For example, image data is transferred from an image reading unit that reads image data to an image processing unit that performs image processing on the image data by serial communication. At this time, in serial communication, a transfer clock, image data, and a synchronization signal are transferred from the image reading unit to the image processing unit. The synchronization signal is, for example, a horizontal synchronization signal indicating the line switching timing in the image data and a vertical synchronization signal indicating the page switching timing in the image data.

  In this type of image processing apparatus, the image reading unit and the image processing unit may be provided with a PLL (Phase Locked Loop) circuit that generates a transfer clock by multiplying the frequency of the reference clock. Specifically, in the image reading unit, the image data and the synchronization signal are converted from parallel data to serial data in accordance with the transfer clock after frequency multiplication by the PLL circuit. On the other hand, in the image processing unit, the image data and the synchronization signal are converted from serial data to parallel data in accordance with the transfer clock after frequency multiplication by the PLL circuit. Thereby, the frequency of the reference clock transferred between the image reading unit and the image processing unit can be reduced.

  By the way, when the locked state of the PLL circuit on the image processing unit side is released due to the influence of noise on the communication path during the execution of serial communication, the transfer clock output from the PLL circuit becomes indefinite. In this case, the image data converted from the serial data to the parallel data and the synchronization signal are disturbed according to the transfer clock, and the image obtained as a processing result of the image processing unit may be disturbed. On the other hand, a technique is known in which when the locked state of the PLL circuit is released, the transfer is stopped, the reading position is returned by a predetermined line, and the image reading is resumed (see, for example, Patent Document 1).

JP 2011-111981 A

  However, for example, a configuration in which the image data reading operation in the image reading unit cannot be interrupted and restarted, and the transfer of image data by serial communication cannot be interrupted and restarted.

  An object of the present invention is to provide an image processing apparatus and data capable of suppressing image disturbance without interrupting serial communication when the locked state of a multiplier such as a PLL circuit is released during execution of serial communication. It is to provide a transfer method.

  An image processing apparatus according to the present invention includes a receiving unit, a first multiplying unit, a first converting unit, a processing unit, and a signal fixing unit. The receiving means receives a first clock, image data, and a synchronization signal by serial communication. The first multiplication means multiplies the frequency of the first clock and outputs a second clock. The first conversion unit converts the image data and the synchronization signal from serial data to parallel data in accordance with the second clock output from the first multiplication unit. The processing means executes a preset process based on the converted image data and the synchronization signal input from the first conversion means. The signal fixing means is input to the processing means until the first multiplying means shifts to the locked state when the locked state of the first multiplying means is released during execution of the serial communication. The synchronization signal is fixed to a predetermined value.

  A data transfer method according to the present invention is a data transfer method in an image processing apparatus including a receiving means, a first multiplying means, a first converting means, and a processing means, and includes a determination step and a signal fixing step. The receiving means receives a first clock, image data, and a synchronization signal by serial communication. The first multiplication means multiplies the frequency of the first clock and outputs a second clock. The first conversion unit converts the image data and the synchronization signal from serial data to parallel data in accordance with the second clock output from the first multiplication unit. The processing means executes a preset process based on the converted image data and the synchronization signal input from the first conversion means. In the determination step, it is determined whether or not the first multiplication means is in a locked state during execution of the serial communication. In the signal fixing step, when it is determined that the locked state of the first multiplication unit is released, the synchronization signal input to the processing unit is changed until the first multiplication unit shifts to the locked state. The value is fixed to a predetermined value.

  According to the present invention, when the locked state of the multiplication unit such as the PLL circuit is released during execution of serial communication, it is possible to suppress image distortion without interrupting serial communication.

1 is a schematic diagram illustrating a configuration of a multifunction machine according to an embodiment of the present invention. 1 is a block diagram showing a hardware configuration of a multifunction machine according to an embodiment of the present invention. 6 is a timing chart illustrating an example of data transfer processing executed by the multifunction peripheral according to the embodiment of the present invention. 6 is a timing chart showing another example of data transfer processing executed by the multifunction peripheral according to the embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the accompanying drawings for understanding of the present invention. In addition, the following embodiment is an example which actualized this invention, Comprising: The thing of the character which limits the technical scope of this invention is not.

[Schematic configuration of MFP 10]
First, a schematic configuration of a multifunction machine 10 according to an embodiment of the present invention will be described with reference to FIG. The multifunction machine 10 is an example of an image processing apparatus according to the present invention. The present invention can also be applied to an image processing apparatus that involves transferring image data, such as a printer, a facsimile machine, a copier, a personal computer, a tablet terminal, a smartphone, and a mobile phone.

  The multifunction machine 10 is an image forming apparatus including an ADF 1, an image reading unit 2, an image forming unit 3, a paper feeding unit 4, a control unit 5, and an operation display unit 6. The operation display unit 6 inputs a variety of information to the display unit such as a liquid crystal display that displays various types of information according to control instructions from the control unit 5 and the control unit 5 according to user operations. An input unit such as a touch panel is provided.

  The ADF 1 is an automatic document conveying device including a document setting unit 11, a plurality of conveyance rollers 12, a document pressing unit 13, and a paper discharge unit 14. In the ADF 1, each of the transport rollers 12 is driven by a motor (not shown) so that the document placed on the document setting unit 11 passes through the image data reading position by the image reading unit 2. It is conveyed to the paper discharge unit 14. As a result, the image reading unit 2 can read image data from a document conveyed by the ADF 1.

  The image reading unit 2 includes a document table 21, a reading unit 22, mirrors 23 and 24, an optical lens 25, and a CCD (Charge Coupled Device) 26. The image reading unit 2 reads image data from a document set on the document table 21 or the ADF 1. The document table 21 is a document placement unit provided on the upper surface of the image reading unit 2. The reading unit 22 includes an LED light source 221 and a mirror 222, and is movable in a sub-scanning direction (left and right direction in FIG. 1) by a motor (not shown). The LED light source 221 includes a large number of white LEDs arranged along the main scanning direction (the depth direction in FIG. 1). The mirror 222 reflects the light emitted from the LED light source 221 and reflected by the surface of the document at the reading position on the document table 21 toward the mirror 23. The light reflected by the mirror 222 is guided to the optical lens 25 by the mirrors 23 and 24. The optical lens 25 collects incident light and makes it incident on the CCD 26. The CCD 26 includes a photoelectric conversion element that inputs an electrical signal corresponding to the amount of light incident from the optical lens 25 to the control unit 5 as image data of the document.

  The image forming unit 3 performs an image forming process (printing process) based on image data read by the image reading unit 2 or image data input from an information processing apparatus such as an external personal computer. The image forming unit. Specifically, the image forming unit 3 includes a photosensitive drum 31, a charging device 32, an exposure device (LSU) 33, a developing device 34, a transfer roller 35, a cleaning device 36, a fixing roller 37, a pressure roller 38, and a discharge roller. A paper tray 39 is provided. In the image forming unit 3, an image is formed on the paper supplied from the paper feeding cassette 4 that can be attached to and detached from the paper feeding unit 4 according to the following procedure, and the paper after the image formation is discharged to the paper discharge tray 39. Is done.

  First, the photosensitive drum 31 is uniformly charged to a predetermined potential by the charging device 32. Next, the exposure device 33 irradiates the surface of the photosensitive drum 31 with light based on image data. As a result, an electrostatic latent image corresponding to the image data is formed on the surface of the photosensitive drum 31. The electrostatic latent image on the photosensitive drum 31 is developed (visualized) as a toner image by the developing device 34. The developing device 34 is supplied with toner (developer) from a toner container 34 </ b> A that can be attached to and detached from the image forming unit 3. Subsequently, the toner image formed on the photosensitive drum 31 is transferred onto a sheet by the transfer roller 35. Thereafter, the toner image transferred to the sheet is heated and fixed by the fixing roller 37 when the sheet passes between the fixing roller 37 and the pressure roller 38. The toner remaining on the surface of the photosensitive drum 31 is removed by the cleaning device 36.

  Next, a schematic configuration of the control unit 5 will be described with reference to FIG. The control unit 5 includes a CPU 51, ROM 52, RAM 53, SDRAM 54, communication I / F 55, HDD 56, scan processing unit 57, and image processing unit 58.

  The CPU 51 is a processor that executes various arithmetic processes. The ROM 52 is a non-volatile storage unit in which information such as a control program for causing the CPU 51 to execute various processes is stored in advance. The CPU 51 performs overall control of the multifunction machine 10 by executing various processes according to various control programs stored in advance in the ROM 52. The RAM 53 is a volatile storage unit, and is used as a temporary storage memory (working area) for various processes executed by the CPU 51.

  The SDRAM 54 is a volatile storage unit such as a DDR-SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) that stores image data read by the image reading unit 2. Note that reading / writing of data to / from the SDRAM 54 is controlled by a DMAC (Direct Memory Access Controller) (not shown) or the like. The communication I / F 55 is a communication interface that connects the multifunction machine 10 to a communication network such as the Internet or a LAN and executes data communication through the communication network. The HDD 56 is a hard disk in which image data read by the image reading unit 2 or image data received from an information processing apparatus such as an external personal computer is stored.

  The scan processing unit 57 is an ASIC including a clock generation unit 571, an AFE circuit 572, and a transmission circuit 573. The image processing unit 58 is an ASIC including a receiving circuit 581, an image processing circuit 584, and a mask processing unit 585. The transmission circuit 573 of the scan processing unit 57 and the reception circuit 581 of the image processing unit 58 are connected by a communication cable 50. The scan processing unit 57 and the image processing unit 58 execute data transfer processing for transferring image data read by the CCD 26 by serial communication via the communication cable 50. As a transfer method of the serial communication, for example, an FPLink method that transfers data using an LVDS (small amplitude operation signal) technique can be considered.

  The clock generation unit 571 is an example of a clock generation unit that includes a crystal oscillator or the like and generates a first clock having a preset frequency as a reference clock. The first clock generated by the clock generation unit 571 is input to the CCD 26, the AFE circuit 572, the transmission circuit 573, and the like.

  The scan processing unit 57 generates a synchronization signal including a horizontal synchronization signal indicating the switching timing of the image data line and a vertical synchronization signal indicating the switching timing of the page of the image data, based on the first clock. Input to the CCD 26. As a result, the CCD 26 reads image data from the document in accordance with the first clock, the horizontal synchronization signal, and the vertical synchronization signal. The synchronization signal including the horizontal synchronization signal and the vertical synchronization signal is input to the P / S conversion unit 575 together with the image data read by the CCD 26 and transferred to the image processing unit 58. Note that the synchronization signal transferred from the scan processing unit 57 to the image processing unit 58 may include, for example, an MRE signal indicating an effective range in one line.

  The AFE circuit 572 is an analog front-end circuit that executes various kinds of processing such as noise removal processing, analog-digital conversion processing, amplification processing, CMYK conversion processing, and correction processing on the image data input from the CCD 26. . The correction process includes, for example, a shading correction process and a gamma correction process. The image data processed by the AFE circuit 572 is input to the transmission circuit 573.

  The transmission circuit 573 is an example of a transmission unit including a PLL (Phase Locked Loop) circuit 574 and a P / S conversion unit 575. The transmission circuit 573 transmits the first clock, the image data, and the synchronization signal to the image processing unit 58 by serial communication to the reception circuit 581.

  The PLL circuit 574 is a phase synchronization circuit that outputs a third clock obtained by multiplying the frequency of the first clock generated by the clock generation unit 571 as a transfer clock, and is an example of a second multiplying unit. The third clock generated by the PLL circuit 574 is output to the P / S converter 575. The frequency of the third clock is an integer multiple of the first clock. Specifically, in the present embodiment, the PLL circuit 574 outputs the third clock that is seven times the frequency of the first clock. Of course, the multiplication factor in the PLL circuit 574 is not limited to seven, and may be any arbitrary integer that is the same as the multiplication factor of a PLL circuit 582 (described later) provided in the image processing unit 58.

  For example, the PLL circuit 574 includes a frequency dividing circuit, a phase comparison circuit, a voltage controlled oscillator, and the like. The frequency dividing circuit divides the third clock output from the voltage controlled oscillator as an output result of the PLL circuit 574 by a predetermined frequency dividing ratio. The frequency division ratio is the same value as the multiplication factor by the PLL circuit 574. That is, when the multiplication factor of the PLL circuit 574 is 7, the frequency dividing ratio of the frequency dividing circuit is 7, and the frequency of the third clock output from the frequency dividing circuit is the voltage controlled oscillator. 1/7 of the third clock output from the first clock. The phase comparison circuit outputs a voltage corresponding to the phase difference of the third clock output from each of the frequency divider circuit and the voltage controlled oscillator. The voltage controlled oscillator outputs the third clock having a frequency corresponding to the voltage output from the phase comparison circuit. In the PLL circuit 574 configured as described above, the third clock having a frequency seven times that of the first clock is output from the voltage controlled oscillator, and the first clock and the third clock are synchronized with each other. This state is called the locked state of the PLL circuit 574.

  The P / S conversion unit 575 converts the image data and the synchronization signal transmitted to the image processing unit 58 from parallel data to serial data according to the third clock output from the PLL circuit 574. Circuit. The P / S conversion unit 575 is an example of a second conversion unit. Specifically, the P / S converter 575 converts the parallel data into the serial data using a shift register that shifts the image data bit by bit in accordance with the third clock. As a result, 7-bit data is included in one clock in the first clock whose frequency is 1/7 of the third clock.

  On the other hand, the receiving circuit 581 is an example of receiving means including a PLL circuit 582 and an S / P converter 583. The receiving circuit 581 of the image processing unit 58 receives the first clock, the image data, and the synchronization signal transmitted from the scan processing unit 57 by serial communication.

  The PLL circuit 582 is configured in the same manner as the PLL circuit 574, and is a phase synchronization circuit that outputs a second clock obtained by multiplying the frequency of the first clock input from the transmission circuit 573 as a transfer clock. It is an example of a 1-times multiplication means. Then, the second clock generated by the PLL circuit 582 is output to the S / P converter 583. Specifically, in the present embodiment, the PLL circuit 582 outputs the second clock obtained by multiplying the frequency of the first clock by 7 times, similarly to the PLL circuit 574. Of course, the multiplication factor in the PLL circuit 582 is not limited to seven, and may be any integer as long as it is the same as the multiplication factor of the PLL circuit 574.

  Here, the PLL circuit 582 has a lock detection function for detecting whether or not the PLL circuit 582 is in a locked state. The PLL circuit 582 inputs a lock signal indicating whether or not the PLL circuit 582 is in a locked state to the mask processing unit 585. For example, in the lock signal, “L” indicates a locked state and “H” indicates an unlocked state. The PLL circuit 582 determines whether or not the PLL circuit 582 is in a locked state according to the phase difference determined by the phase comparison circuit. Further, the method for determining whether or not the PLL circuit 582 is in a locked state is not limited to this, and the PLL circuit 582 is provided on condition that a predetermined number of the second clocks are output during a predetermined period. It is conceivable that the lock state is detected.

  The S / P converter 583 converts the image data and the synchronization signal received from the scan processor 57 from serial data to parallel data according to the second clock output from the PLL circuit 583. Circuit. The S / P converter 583 is an example of a first converter. Specifically, the S / P converter 583 converts the serial data into the parallel data using a shift register that shifts the image data bit by bit in accordance with the second clock. As a result, 7-bit data included in one clock in the first clock is restored as parallel data. Therefore, the control unit 5 can use the first clock having a frequency lower than that of the third clock as the transfer clock transferred from the scan processing unit 57 to the image processing unit 58. Then, the image data and the synchronization signal converted into the parallel data by the S / P converter 583 are output to the image processing circuit 584.

  The image processing circuit 584 is a processing means for executing various preset image processing such as rotation processing, halftone processing, and size cut processing on the image data based on the image data and the synchronization signal. It is an example. When the MFP 10 executes a scanning process, the image data after the image processing by the image processing unit 584 is output to and stored in the storage unit such as the HDD 56. Further, when a copy process is executed in the multifunction device 10, the image data after the image processing by the image processing unit 58 is output to the image forming unit 3, and the image forming unit 3 outputs the image data. An image forming process is executed based on the synchronization signal. Further, in the MFP 10, when the FAX transmission process is executed, the image data after the image processing by the image processing unit 58 is output to the communication I / F 55 and a communication network such as the Internet or a telephone line. To the external device via

  The mask processing unit 585 is configured so that the PLL circuit 582 is locked based on the lock signal input from the PLL circuit 582 during execution of serial communication between the scan processing unit 57 and the image processing unit 58. A determination step of determining whether or not there is is executed. When the mask processing unit 585 determines that the locked state of the PLL circuit 582 is released during the execution of the serial communication, the synchronization signal input from the S / P conversion unit 583 to the image processing circuit 584. A mask process for fixing the value to a preset value is executed.

  For example, the mask processing unit 585 fixes the value of the synchronization signal so that the image processing circuit 584 does not execute a process (line feed or page break) corresponding to the input of the synchronization signal. Specifically, when the horizontal synchronization signal and the vertical synchronization signal are “L” and a low active signal indicating an enabled state, the mask processing unit 585 sets the horizontal synchronization signal and the vertical synchronization signal to “H”. ”.

  Thereafter, when the mask processing unit 585 determines that the PLL circuit 582 has returned to the locked state based on the lock signal, the mask processing unit 585 outputs the synchronization signal input from the S / P conversion unit 583 to the image processing circuit 584. Unpin. Thus, the image processing circuit 584 executes image processing based on the image data and the synchronization signal.

  That is, when the PLL circuit 582 is unlocked during execution of the serial communication, the mask processing unit 585 causes the image processing circuit 584 to wait until the PLL circuit 582 shifts to the locked state. The value of the input synchronization signal is fixed. Thereby, in the multi-function device 10, the serial communication is not interrupted when the locked state of the PLL circuit 582 is released, and various types of images based on the image data after the image processing of the image processing unit 58 and the synchronization signal are performed. Disturbances in the image obtained as a processing result are suppressed.

[Data transfer processing]
Hereinafter, an example of a data transfer process (data transfer method) executed by the control unit 5 in the multifunction machine 10 will be described with reference to FIG. In the multi-function device 10, after both the PLL circuit 575 and the PLL circuit 582 are locked, data transfer processing for transferring image data read by the CCD 26 is performed by the scan processing unit 57 and the image processing unit. It is executed between the units 58.

  Here, “CLK” shown in FIG. 3 is the first clock input to the PLL circuit 582, and “LCK” shown in FIG. 3 is the lock signal. “HSYNC1” and “VSYNC1” shown in FIG. 3 are the horizontal synchronization signal and the vertical synchronization signal input to the S / P converter 583. Further, “HSYNC2” and “VSYNC2” shown in FIG. 3 are the horizontal synchronization signal and the vertical synchronization signal input to the image processing circuit 584. Here, the case where the vertical synchronization signal VSYNC1 and the vertical synchronization signal VSYNC2 are continuous signals of “H” or “L” will be described as an example, but the horizontal synchronization signal HSYNC1 and the horizontal synchronization signal are described. It may be a pulse signal similar to HSYNC2.

  As shown in FIG. 3, during execution of the serial communication, for example, when noise is mixed into the first clock CLK on the communication path 50, the lock state of the PLL circuit 582 is released and the lock signal LCK is “ H ”may occur (time t1). In this case, the mask processing unit 585 fixes the horizontal synchronization signal HSYNC2 and the vertical synchronization signal VSYNC2 input from the S / P conversion unit 583 to the image processing circuit 584 to preset values. Here, both the horizontal synchronization signal HSYNC2 and the vertical synchronization signal VSYNC2 are fixed to "H".

  Thereby, in the image processing circuit 584, even if the horizontal synchronization signal HSYNC1 is disturbed (shaded area in FIG. 3), the horizontal synchronization signal HSYNC2 does not become “L”. Unnecessary line breaks in are blocked. In the image processing circuit 584, even if the vertical synchronization signal VSYNC1 is disturbed (shaded area in FIG. 3), the vertical synchronization signal VSYNC2 does not become “L”. Unnecessary page breaks are prevented.

  Thereafter, when the PLL circuit 582 is again stably shifted to the locked state and the lock signal LCK becomes “L” (time point t2), the mask processing unit 585 inputs the horizontal input to the image processing circuit 584. The fixing of the synchronization signal HSYNC2 and the vertical synchronization signal VSYNC2 is released. That is, the mask processing unit 585 performs the horizontal synchronization signal HSYNC2 during a period T1 from when the lock signal LCK becomes “H” to when the lock signal LCK becomes “L” during execution of the serial communication. And the value of the vertical synchronization signal VSYNC2 is fixed. Here, the mask processing unit 585 is an example of a signal fixing unit, and the step executed by the mask processing unit 585 is an example of a signal fixing step. The signal fixing step may be executed by a processor such as the CPU 51 in accordance with a control program stored in the ROM 52. In this case, the processor is an example of the signal fixing means.

  Therefore, according to the multifunction machine 10, when the locked state of the PLL circuit 582 is released during execution of serial communication, the image data output from the image processing unit 58 without interrupting the serial communication. Image disturbance can be suppressed. Specifically, in the multi-function device 10, since both the horizontal synchronization signal and the vertical synchronization signal are fixed by the mask processing unit 585, line breaks and page breaks in the image data are prevented, and the image data in the image data is prevented. Disturbance is limited to within one line.

  In this embodiment, the case where image data is transferred between the scan processing unit 57 and the image processing unit 58 has been described as an example. However, the present invention is not limited to this. For example, the same configuration can be applied to the case where image data is transferred from the image processing unit 58 to the image forming unit 3 in the multi-function peripheral 10. A transmission circuit 573 is provided, and the image forming unit 3 is provided with the reception circuit 581 and the mask processing unit 585. The image forming unit 3 executes image forming processing for forming an image based on the converted image data and the synchronization signal input from the S / P conversion unit 583 of the receiving circuit 581. An engine control unit or the like is an example of a processing unit. As a result, in the image forming unit 3, when the PLL circuit 582 is released from the locked state, the mask processing unit 585 fixes the synchronization signal, and the image formed based on the image data and the synchronization signal is disturbed. Is suppressed.

[Other Embodiments]
By the way, there is a possibility that a time lag may occur between the time when noise is mixed in the synchronization signal and the time when the unlocked state of the PLL circuit 582 is detected. Therefore, the image processing unit 58 delays the image data and the synchronization signal input from the S / P conversion unit 583 to the image processing circuit 584 by a preset delay time (a delay means). An example) is conceivable as another embodiment. In this case, the mask processing unit 585 switches between fixing and releasing the synchronization signal input from the delay circuit 586 to the image processing circuit 584 depending on whether or not the PLL circuit 582 is in a locked state.

  FIG. 4 is a diagram illustrating an example of a data transfer process executed by the image processing unit 58 including the delay circuit 586. As shown in FIG. 4, when the delay circuit 586 is provided, the horizontal synchronization signal HSYNC2 and the vertical synchronization signal VSYNC2 are preset with respect to the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1. Delayed by the delay time T2. Here, the delay time T2 is the same as the time T3 known as a time lag from the time t1 when noise is mixed in the first clock CLK to the time t11 when the release of the locked state is detected by the PLL circuit 582, or It is longer than time T3.

  In this case, the mask processing unit 585 performs the horizontal synchronization signal HSYNC2 and the period of time T4 from the time t11 when the lock signal LCK becomes “H” to the time t12 when the lock signal becomes “L”. The vertical synchronization signal VSYNC2 is fixed to “H”. The time point t12 is a time point delayed by the delay time T2 from the time point t2.

  According to the multi-function device 10 configured as described above, the horizontal synchronization signal HSYNC1 is generated during the time T3 from when noise is mixed into the synchronization signal until the release of the locked state is detected by the PLL circuit 582. Even when the vertical synchronization signal VSYNC1 is disturbed, the image distortion is suppressed.

1: ADF
2: Image reading unit 3: Image forming unit 4: Paper feeding unit 5: Control unit 51: CPU
52: ROM
53: RAM
54: SDRAM
55: Communication I / F
56: HDD
57: Scan processing unit 571: Clock generation unit 572: AFE circuit 573: Transmission circuit 574: PLL circuit 575: P / S conversion unit 58: Image processing unit 581: Reception circuit 582: PLL circuit 583: S / P conversion unit 584 : Image processing circuit 585: Mask processing unit 586: Delay circuit 6: Operation display unit 10: Multifunction machine

Claims (6)

Receiving means for receiving the first clock, the image data, and the synchronization signal by serial communication;
First multiplying means for multiplying the frequency of the first clock and outputting a second clock;
First conversion means for converting the image data and the synchronization signal from serial data to parallel data in accordance with the second clock output from the first multiplication means;
Processing means for executing processing set in advance based on the converted image data and the synchronization signal input from the first conversion means;
When the locked state of the first multiplying unit is released during execution of the serial communication, the synchronization signal input to the processing unit is determined in advance until the first multiplying unit shifts to the locked state. Signal fixing means for fixing to a given value;
Delay means for delaying the output of the image data and the synchronization signal input from the first conversion means to the processing means by a preset delay time;
With
The first multiplication means includes a frequency dividing circuit, a phase comparison circuit, and a voltage controlled oscillator, and the frequency dividing circuit divides the second clock output from the voltage controlled oscillator by a preset frequency dividing ratio. by frequency, the phase comparator circuit determines the phase difference between the second clock and the first clock output the frequency dividing circuit or, et al., the voltage controlled oscillator, according to a determination result of the phase comparison circuit Output the second clock of the selected frequency,
The first multiplying unit determines whether or not the first multiplying unit is in a locked state according to a phase difference determined in the phase comparison circuit of the first multiplying unit ,
The delay time is not less than a known time as a time lag from the time when noise is mixed into the first clock to the time when release of the locked state is detected by the first multiplying unit.
Image processing device.   The image processing apparatus according to claim 1, wherein the synchronization signal includes a first synchronization signal indicating a line switching timing in the image data, and a second synchronization signal indicating a page switching timing in the image data. Clock generating means for generating the first clock;
Second multiplying means for multiplying the frequency of the first clock generated by the clock generating means and outputting a third clock;
Second conversion means for converting the image data and the synchronization signal from parallel data to serial data in accordance with the third clock output from the second multiplication means;
Transmission means for transmitting the first clock output from the clock generation means and the image data and the synchronization signal output from the second conversion means by serial communication;
The image processing apparatus according to claim 1 or 2 comprising a. An image reading unit for reading image data from the document;
The image processing apparatus according to any one of claims 1 to 3, wherein said processing means for executing predetermined image processing on the image data. The image processing apparatus according to any one of claims 1-4 wherein at least one of the first multiplying means and said second multiplier means is a PLL circuit. A receiving means for receiving the first clock, the image data, and the synchronization signal by serial communication, a first multiplying means for multiplying the frequency of the first clock and outputting a second clock, and the first multiplying means. Based on the first conversion means for converting the image data and the synchronization signal from serial data to parallel data according to the second clock, and based on the converted image data and the synchronization signal input from the first conversion means. An image comprising: processing means for executing set processing; and delay means for delaying the output of the image data and the synchronization signal input from the first conversion means to the processing means by a preset delay time. A data transfer method in a processing device, comprising:
A determination step of determining whether or not the first multiplication means is locked during execution of the serial communication;
When it is determined that the locked state of the first multiplying unit is released, the synchronization signal input to the processing unit is set to a predetermined value until the first multiplying unit shifts to the locked state. A signal fixing step to be fixed;
A data transfer method including:
The first multiplication means includes a frequency dividing circuit, a phase comparison circuit, and a voltage controlled oscillator, and the frequency dividing circuit divides the second clock output from the voltage controlled oscillator by a preset frequency dividing ratio. by frequency, the phase comparator circuit determines the phase difference between the second clock and the first clock output the frequency dividing circuit or, et al., the voltage controlled oscillator, according to a determination result of the phase comparison circuit Output the second clock of the selected frequency,
The first multiplying unit determines whether or not the first multiplying unit is in a locked state according to a phase difference determined in the phase comparison circuit of the first multiplying unit ,
The delay time is not less than a known time as a time lag from the time when noise is mixed into the first clock to the time when release of the locked state is detected by the first multiplying unit.
Data transfer method.

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