JP2017152653A - Method of manufacturing semiconductor light-emitting element and method of manufacturing wafer for semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a light-emitting element having a semiconductor layer with high crystal quality by a simple method.SOLUTION: A method of manufacturing a wafer for a semiconductor light-emitting element comprises: a step (a) of preparing a growth substrate; a step (b) of forming a semiconductor layer on an upper layer of the growth substrate; a step (c) of irradiating the semiconductor layer with excitation light; a step (d) of receiving fluorescence radiated from the semiconductor layer during execution of the step (c); and a step (e) of performing quality determination of the semiconductor layer on the basis of the light output of the fluorescence received in the step (d).SELECTED DRAWING: Figure 3H

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting element and a method for manufacturing a wafer for a semiconductor light emitting element.

  In recent years, light-emitting elements using nitride semiconductors have been developed. This light-emitting element includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed so as to be sandwiched between the n-type semiconductor layer and the p-type semiconductor layer. By providing a potential difference between the n-type semiconductor layer and the p-type semiconductor layer, a current flows between them, and electrons and holes are recombined in the active layer to emit light. Various researches and developments are in progress to effectively use the light generated in the active layer.

  FIG. 7 schematically shows a cross-sectional view of a nitride semiconductor light emitting device disclosed in Patent Document 1. As shown in FIG. The light emitting element 90 includes a conductive layer 92, a reflective film 93, an insulating layer 94, a reflective electrode 95, a semiconductor layer 99, and an n-side electrode 100 on a substrate 91. The semiconductor layer 99 is configured by sequentially stacking a p-type semiconductor layer 96, an active layer 97, and an n-type semiconductor layer 98 from the substrate 91 side.

  A reflective film 93 made of a metal material is formed below the insulating layer 94. However, the reflective film 93 does not have ohmic properties and does not function as an electrode. On the other hand, the reflective electrode 95 is made of a metal material and functions as an electrode (p-side electrode) by realizing ohmic contact between the p-type semiconductor layers 96.

  The reflective electrode 95 reflects light emitted in the direction toward the substrate 91 (downward in the drawing) out of the light generated in the active layer 97 and extracts the light to the n-side semiconductor layer 98 side (upward in the drawing). It also serves the purpose of increasing the take-out efficiency. The reflective film 93 is also formed for the same purpose, and reflects light that travels downward through a portion where the reflective electrode 95 is not formed, and changes the traveling direction to the n-side semiconductor layer 98 side. The take-out efficiency is increased.

Japanese Patent No. 4207781

  When a light emitting element is formed of a nitride semiconductor such as the light emitting element 90 shown in FIG. 7, a substrate made of a material different from the semiconductor layer is generally used as a growth substrate for growing the semiconductor layer. Is done. Patent Document 1 also describes that a semiconductor layer made of a material different from sapphire is grown on the upper surface of a sapphire substrate.

  However, when a semiconductor layer is grown on such a heterogeneous substrate, lattice mismatch between the substrate and the semiconductor inevitably occurs. Such lattice mismatch may cause cracks or regions having different compositions at specific locations in the semiconductor layer. Such a phenomenon causes a decrease in light output.

  In recent years, a method for growing a semiconductor layer with improved crystal quality has been developed so as not to produce a semiconductor layer with low crystal quality as described above. However, in order to grow a semiconductor layer with extremely improved crystal quality, there are practical problems such as a complicated manufacturing process and a significant increase in the unit manufacturing cost of the device.

  By the way, conventionally, a method of performing an appearance inspection using an optical microscope is known in order to exclude a low-quality wafer from the production line in advance. In this method, the surface of the semiconductor layer is irradiated with white light, and the presence or absence of cracks is visually inspected based on the illuminance of the reflected light using a phenomenon in which the degree of reflection of white light varies depending on the presence or absence of cracks. However, according to the earnest study of the present inventor, it has been found that white light is scattered on the surface of the semiconductor layer and it is sometimes difficult to visually recognize cracks.

  FIG. 8 is a photograph of the light emitting element including the semiconductor layer having cracks when irradiated with white light, but no cracks can be confirmed from the photograph. When the inspection is performed by such a method, there is a possibility that only a low light output can be realized or an element having a low life characteristic is distributed in the market due to the presence of a crack or the like in the element determined as a non-defective product.

  In view of the above problems, an object of the present invention is to manufacture a light-emitting element having a semiconductor layer with high crystal quality by a simple method.

A first aspect of the present invention is a method for producing a semiconductor light emitting device wafer,
A step (a) of preparing a growth substrate;
Forming a semiconductor layer on the growth substrate (b);
Irradiating the semiconductor layer with excitation light (c);
Receiving the fluorescence emitted from the semiconductor layer during the execution of the step (c) (d);
And (e) performing a quality determination of the semiconductor layer based on the light output of the fluorescence received in the step (d).

  As a result of intensive research conducted by the present inventors, when the semiconductor layer having a defective part such as a crystal defect or a crack is irradiated with excitation light, fluorescence light is emitted between the part where the defective part exists and the part where the defective part does not exist. It was confirmed that the output was different. Therefore, according to the above method, the presence or absence of a defective portion can be confirmed by the output of the received fluorescence.

  FIG. 1 is a photograph of the fluorescence emitted by irradiating the device of FIG. 8 with excitation light. According to FIG. 1, the region 2 having a light intensity lower than that of the surrounding area appears blackish as an oblique line. Such a region is not confirmed in the photograph of FIG. From the photograph in FIG. 1, it is considered that since the defective portion exists in the semiconductor layer in this region 2, the intensity of fluorescence is weaker than in other regions.

  In particular, when ultraviolet light is used as excitation light, it is not difficult to visually recognize the light reflected from the surface of the semiconductor layer as in the case of irradiating white light. That is, the determination accuracy of the defective portion can be further enhanced by using excitation light as light in a wavelength band not in the visible range and fluorescence as light in a wavelength band in the visible range.

  The step (e) may be a step of determining that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity received from the specific portion of the semiconductor layer is a predetermined threshold value or less. .

  When cracks exist in the semiconductor layer or when a plurality of different levels exist, the intensity of fluorescence generated when the excitation light is irradiated is weakened. Therefore, it can be determined that there is a defective portion when only fluorescence below a predetermined threshold is received.

The step (d) is a step of selecting and receiving light of a predetermined wavelength band from the fluorescence.
The step (e) determines that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity of the predetermined wavelength band received from the specific portion of the semiconductor layer is equal to or less than a predetermined threshold value. It does n’t matter what you do.

  When a region having a different composition exists in the semiconductor layer, the region has a band gap energy different from that of the surrounding region. For this reason, the wavelength of fluorescence generated when the region is irradiated with excitation light is different from the wavelength of fluorescence generated when the region indicating the original composition of the semiconductor layer is irradiated with excitation light. Therefore, when selectively receiving light in the wavelength band indicated by the fluorescence that would be generated when the region showing the original composition of the semiconductor layer is irradiated with excitation light, the intensity of the received light is below the threshold value. In some cases, it can be determined that a defective portion exists in the area.

  The step (b) may be a step of forming the semiconductor layer made of a nitride semiconductor. At this time, the semiconductor layer may include a nitride semiconductor containing Al, and the excitation light may be ultraviolet light.

  When growing a nitride semiconductor containing Al, especially when abnormal irregularities are formed on the surface of the semiconductor layer, the crystal arrangement is disturbed and the composition of the semiconductor layer differs from the desired value. And it is easy to form a defective part. In such a case, according to the above method, it is possible to determine in advance whether or not there is a defective portion, so that it is possible to provide a high-quality wafer to the market.

A second aspect of the present invention is a method for manufacturing a semiconductor light emitting device,
A step (a) of preparing a growth substrate;
Forming an n-type or p-type first semiconductor layer, an active layer, and a semiconductor layer including a second semiconductor layer having a conductivity type different from that of the first semiconductor layer on the growth substrate;
Irradiating the semiconductor layer with excitation light (c);
Receiving the fluorescence emitted from the semiconductor layer during the execution of the step (c) (d);
A step (e) of determining the quality of the semiconductor layer based on the light output of the fluorescence received in the step (d);
A step (f) of forming a second electrode on the second semiconductor layer after the step (b);
A step (g) of attaching a substrate different from the growth substrate to the upper layer of the second electrode;
After the step (g), the step (h) of peeling the growth substrate and exposing the first semiconductor layer;
And (i) forming a first electrode on the upper surface of the first semiconductor layer.

  According to the above method, the quality of the semiconductor layer is determined based on the fluorescence light output. For this reason, it is possible to supply a high-quality light-emitting element to the market by taking measures such as sending only elements determined to be non-defective products to a subsequent process. Further, according to the above method, it is only necessary to irradiate the semiconductor layer with the excitation light and receive the fluorescence emitted from the semiconductor layer, and the quality determination can be performed by a simple method. Therefore, a high-quality light-emitting element can be provided to the market without increasing manufacturing costs.

  The step (e) may determine that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity received from the specific portion of the semiconductor layer is a predetermined threshold value or less.

The step (d) is a step of selecting and receiving light of a predetermined wavelength band from the fluorescence.
The step (e) determines that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity of the predetermined wavelength band received from the specific portion of the semiconductor layer is equal to or less than a predetermined threshold value. It does not matter even if it is a process to do.

  The step (c), the step (d), and the step (e) may be performed after the step (h) and before the step (i). After the step (h) and before the step (i), since the semiconductor layer is completely exposed, the entire surface of the semiconductor layer can be irradiated with excitation light, and the accuracy of good / bad determination is improved. Can be made.

After the step (i), a step (j) of dividing the wafer into chips,
A step (k) of performing a mounting process on each chip,
The step (c), the step (d), and the step (e) are performed before the step (k),
The step (k) may be performed only on the chips that are determined to be non-defective in the step (e).

  The step (b) may be a step of forming the semiconductor layer made of a nitride semiconductor.

The semiconductor layer has a nitride semiconductor containing Al,
The step (c) may be a step of irradiating with ultraviolet light.

  According to the present invention, an inexpensive and high-brightness semiconductor light emitting device is realized.

It is the photograph which irradiated the excitation light with respect to the light emitting element containing the semiconductor layer which has a crack, and observed the emitted fluorescence. It is a top view which shows typically the structure of one Embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically the structure of one Embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. The energy band figure of a semiconductor layer in case a defective part exists in a one part area | region is shown typically. The energy band figure of a semiconductor layer in case a defective part exists in a one part area | region is shown typically. The energy band figure of a semiconductor layer in case a defective part exists in a one part area | region is shown typically. It is the photograph which irradiated the excitation light with respect to the light emitting element containing the semiconductor layer which shows a normal composition, and observed the emitted fluorescence. It is the photograph which irradiated the excitation light with respect to the light emitting element containing the semiconductor layer in which a composition abnormal part exists in a one part area | region, and observed the emitted fluorescence. It is sectional drawing which shows typically the structure of another embodiment of a semiconductor light-emitting device. It is a top view which shows typically the structure of another embodiment of a semiconductor light-emitting device. It is sectional drawing which shows the structure of the conventional semiconductor light-emitting device typically. It is a photograph when white light is irradiated with respect to the light emitting element containing the semiconductor layer which has a crack.

  A method for manufacturing a semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device wafer of the present invention will be described with reference to the drawings. In each drawing, the dimensional ratio of the drawings does not necessarily match the actual dimensional ratio. The manufacturing conditions and film thickness dimensions described below are merely examples, and are not limited to these numerical values.

In the following, the description “AlGaN” is synonymous with the description Al _m Ga _1-m N (0 <m <1), and the description of the composition ratio of Al and Ga is simply omitted. And it is not the meaning limited to the case where the composition ratio of Al and Ga is 1: 1. The same applies to descriptions such as “InGaN”.

[Construction]
2A to 2B are drawings schematically showing a configuration of an embodiment of a semiconductor light emitting device. FIG. 2A corresponds to a plan view when viewed from the light extraction direction. FIG. 2B corresponds to a cross-sectional view taken along line X1-X1 in FIG. 2A. Hereinafter, the light extraction surface is defined as an XY plane, and a direction orthogonal to the XY plane is defined as a Z direction.

  FIG. 2A corresponds to the photograph of FIG. 1 described above.

  As shown in FIG. 2B, the semiconductor light emitting element 1 includes a substrate 3, a semiconductor layer 5 formed on the upper layer of the substrate 3, a first electrode 15, and a second electrode 13. Hereinafter, the semiconductor light emitting element 1 may be simply abbreviated as “light emitting element 1” as appropriate.

(Substrate 3)
The substrate 3 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.

(Semiconductor layer 5)
In this embodiment, the semiconductor layer 5 is formed by sequentially stacking a p-type semiconductor layer 11, an active layer 9, and an n-type semiconductor layer 7 from the side close to the substrate 3. In the present embodiment, the n-type semiconductor layer 7 corresponds to a “first semiconductor layer”, and the p-type semiconductor layer 11 corresponds to a “second semiconductor layer”.

  The p-type semiconductor layer 11 is composed of a nitride semiconductor layer doped with a p-type impurity such as Mg, Be, Zn, or C, for example. As the nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN, or the like can be used.

The active layer 9 is composed of a semiconductor layer in which, for example, a light emitting layer composed of InGaN and a barrier layer composed of n-type AlGaN are periodically repeated. These layers may be undoped or p-type or n-type doped. The active layer 9 only needs to be configured by laminating layers made of at least two kinds of materials having different energy band gaps. The constituent material of the active layer 9 is appropriately selected according to the wavelength of light to be generated. In the light emitting device 1 of the present embodiment, the main light emission wavelength in the active layer 9 can be ultraviolet light of 410 nm or less. For example, when the main emission wavelength is 365 nm, the active layer 9 is configured by repeatedly laminating In _0.05 Ga _0.95 N and Al _0.09 Ga _0.91 N.

The n-type semiconductor layer 7 is composed of a nitride semiconductor layer doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te. As this nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN or the like can be used. Note that the n-type impurity concentration of the n-type semiconductor layer 7 is set to, for example, about 2 to 5 × 10 ¹⁹ / cm ³ . The n-type impurity concentration of the n-type semiconductor layer 7 is preferably 1 × 10 ¹⁸ / cm ³ or more, and more preferably 1 × 10 ¹⁹ / cm ³ or more.

  The n-type semiconductor layer 7 may be made of a material having a composition different from that of the p-type semiconductor layer 11.

(First electrode 15)
The first electrode 15 is formed in contact with the surface of the semiconductor layer 5 that is far from the substrate 3. More specifically, the first electrode 15 is formed in contact with the surface of the n-type semiconductor layer 7.

  In the present embodiment, the first electrode 15 constitutes an n-side electrode. The first electrode 15 is made of, for example, a Ni / Al / Ni / Ti / Au multilayer structure, Cr / Au, Ti / Pt / Au, Ti / Pt / Cr / Au / Cr / Pt / Au, or the like. be able to.

  As shown in FIG. 2A, the first electrode 15 has a frame shape when viewed in the Z direction (direction orthogonal to the surface of the substrate 3). More specifically, the outer edge portion of the first electrode 15 has a frame shape along the outer edge portion of the semiconductor layer 5. The light emitting element 1 shown in FIG. 2A has two first extending in the Y direction at two positions inside the outer edge portion of the first electrode 15 having a frame shape and spaced from the outer edge portion in the X direction. An electrode 15 is provided. However, the number of the first electrodes 15 to be extended inside the region indicating the frame shape is not limited to two, and may be one or three or more. Further, the shape of the first electrode 15 is not limited to the frame shape. The shape of the first electrode 15 shown in FIG. 2A is merely an example, and can be arbitrarily changed according to the design.

  The first electrode 15 is configured to include a current supply unit 15a to which the current supply line 14 is connected in some places. The current supply unit 15 a has a wider area than other areas of the first electrode 15. The current supply line 14 is made of, for example, Au or Cu. The end of the current supply line 14 opposite to the end connected to the current supply unit 15a is connected to, for example, a power supply pattern of a package substrate.

(Second electrode 13)
The second electrode 13 is formed in contact with the p-type semiconductor layer 11, and an ohmic contact is formed with the p-type semiconductor layer 11. In the present embodiment, the second electrode 13 constitutes a p-side electrode.

  When a voltage is applied between the first electrode 15 and the second electrode 13, a current flows through the active layer 9, and the active layer 9 emits light.

  The second electrode 13 is preferably made of a conductive material exhibiting a high reflectance (for example, 80% or more, more preferably 90% or more) with respect to light emitted from the active layer 9. More specifically, the second electrode 13 is made of a material containing, for example, Ag, Al, or Rh. As described above, the light emitting element 1 shown in FIG. 2A is assumed to extract light emitted from the active layer 9 to the n-type semiconductor layer 7 side. Since the second electrode 13 is made of a material exhibiting a high reflectance, the light emitted from the active layer 9 toward the substrate 3 is reflected toward the n-type semiconductor layer 7. Is increased.

(Conductive layer 20)
The conductive layer 20 is formed on the upper layer of the substrate 3. In the present embodiment, the conductive layer 20 has a multilayer structure of a protective layer 23, a bonding layer 21, a bonding layer 19, and a protective layer 17.

  The bonding layer 19 and the bonding layer 21 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the bonding layer 19 and the bonding layer 21 make the bonding layer 21 formed on the substrate 3 and the bonding layer 19 formed on another substrate (a growth substrate 25 described later) face each other. Later, they were formed by bonding them together. The bonding layer 19 and the bonding layer 21 may be integrated as a single layer.

  The protective layer 17 has a multilayer structure such as Ni / Ti / Pt, TiW / Pt, etc., and the material constituting the bonding layer (19, 21) diffuses to the second electrode 13 side, and the second electrode 13 is provided for the purpose of suppressing a decrease in reflectance. However, whether or not the light emitting element 1 includes the protective layer 17 is arbitrary.

  The protective layer 23 is made of the same material as that of the protective layer 17, for example, and is provided for the purpose of suppressing the material constituting the bonding layers (19, 21) from diffusing to the substrate 3 side. However, whether or not the light emitting element 1 includes the protective layer 23 is arbitrary.

(Current blocking layer 24)
The light emitting element 1 of the present embodiment includes a current blocking layer 24 that is formed to be in contact with the second electrode 13 at a position facing the first electrode 15 in the Z direction. Current blocking layer 24 is constituted for example _{SiO 2, SiN, Zr 2 O} 3, AlN, etc. Al ₂ O _3. The current blocking layer 24 plays a role of spreading the current flowing through the active layer 9 in a direction parallel to the XY plane. However, whether or not the light emitting element 1 includes the current blocking layer 24 is arbitrary.

[Production method]
Next, a method for manufacturing the light emitting element 1 will be described with reference to the drawings.

(Step S1)
First, as shown in FIG. 3A, a growth substrate 25 is prepared. As an example of the growth substrate 25, a sapphire substrate having a C-plane can be used.

  As a preparation step, the growth substrate 25 is cleaned. As a more specific example of this cleaning, a growth substrate 25 is disposed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen gas at a predetermined flow rate is placed in the processing furnace. The temperature in the furnace is raised to, for example, 1150 ° C. while flowing.

  Step S1 corresponds to step (a).

(Step S2)
As shown in FIG. 3B, an underlayer 27, an n-type semiconductor layer 7, an active layer 9, and a p-type semiconductor layer 11 are formed in this order on the growth substrate 25. This step S2 is performed by the following procedure, for example.

  First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas with a flow rate of 5 slm respectively as carrier gas into the processing furnace, trimethylgallium (TMG) with a flow rate of 50 μmol / min and ammonia with a flow rate of 250,000 μmol / min are used as the raw material gas in the processing furnace. For 68 seconds. Thereby, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the growth substrate 25.

  Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while supplying nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are used as the processing furnace. In for 30 minutes. Thereby, a buffer layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer. The base layer 27 is formed by these buffer layers.

  Next, the n-type semiconductor layer 7 is formed on the base layer 27. A specific method for forming the n-type semiconductor layer 7 is, for example, as follows.

Subsequently, the furnace pressure of the MOCVD apparatus is set to 30 kPa in a state where the furnace temperature is 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, trimethylaluminum (TMA) having a flow rate of 6 μmol / min, Ammonia with a flow rate of 250,000 μmol / min and tetraethylsilane with a flow rate of 0.013 μmol / min are supplied into the treatment furnace for 60 minutes. Thereby, for example, an n-type semiconductor layer 7 having a composition of Al _0.06 Ga _0.94 N, a thickness of 2 μm, and an n-type impurity concentration of 3 × 10 ¹⁹ / cm ³ is formed on the base layer 27. When the n-type semiconductor layer 7 is made of GaN or AlGaN, the Al composition ratio is preferably 0% to 15%, more preferably 2% to 11%, and more preferably 5% or more. Even more preferably, it is 9% or less.

  After this, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, thereby having a protective layer made of n-type GaN having a thickness of about 5 nm on the n-type AlGaN layer. An n-type semiconductor layer 7 may be realized.

  In the above description, the case where Si is used as the n-type impurity contained in the n-type semiconductor layer 7 has been described. However, Ge, S, Se, Sn, Te, or the like can be used as the n-type impurity in addition to Si. .

  Next, an active layer 9 is formed on the n-type semiconductor layer 7. A specific method for forming the active layer 9 is, for example, as follows.

  First, the furnace pressure of the MOCVD apparatus is 100 kPa, and the furnace temperature is 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, an active layer 9 in which a light-emitting layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm are stacked for 15 periods is formed into an n-type semiconductor layer. 7 is formed on the upper layer.

  When the wavelength of light emitted from the active layer 9 is 410 nm or less, the In composition ratio of InGaN constituting the light emitting layer is preferably 10% or less. In this case, the Al composition ratio of GaN or AlGaN constituting the barrier layer is preferably 0% to 15%, more preferably 2% to 13%, and more preferably 5% to 10%. Is even more preferred.

  Next, the p-type semiconductor layer 11 is formed on the active layer 9. A specific method for forming the p-type semiconductor layer 11 is, for example, as follows.

Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace. To do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadiene with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (Cp ₂ Mg) is fed into the processing furnace for 60 seconds. Thus, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the active layer 9. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. A p-type semiconductor layer 11 is formed by these hole supply layers. The p-type impurity concentration of these hole supply layers is set to about 2 to 5 / cm ³ , for example.

After this step, the supply of TMA is stopped, the flow rate of CP ₂ Mg is changed to 0.2 μmol / min, and the source gas is supplied for 20 seconds, so that the thickness is about 5 nm and the p-type impurity concentration is increased. However, a p-type semiconductor layer 11 having a p-type GaN layer of about 1 × 10 ²⁰ / cm ³ may be realized.

  In the above description, the case where Mg is used as the p-type impurity contained in the p-type semiconductor layer 11 has been described. However, Be, Zn, C, or the like can be used in addition to Mg as the p-type impurity.

  Step S2 corresponds to step (b).

(Step S3)
An activation process is performed on the wafer obtained in step S2. As a specific example, an activation process is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) apparatus.

(Step S4)
As illustrated in FIG. 3C, the current blocking layer 24 is formed on the p-type semiconductor layer 11. The current blocking layer 24 is formed, for example, by depositing SiO ₂ , SiN, Zr ₂ O ₃ , AlN, Al ₂ O ₃ or the like by a sputtering method or the like. In this step S4, the current blocking layer 24 is formed at a position facing the Z direction with respect to the region where the first electrode 15 is to be formed in the subsequent step S13.

(Step S5)
As shown in FIG. 3C, the second electrode 13 is formed on the upper surface of a predetermined region of the p-type semiconductor layer 11. Here, the second electrode 13 is also formed on the upper surface of the current blocking layer 24, but the shape of the second electrode 13 is arbitrarily selected. For example, the second electrode 13 is formed by depositing Ni / Ag with a sputtering apparatus and performing contact annealing in a dry air atmosphere using an RTA apparatus. Here, as an example, an alloy of Ni and Ag is used as the material of the second electrode 13, but an alloy of Al, Rh, Ag, Pd, and Cu can also be used. As described above, as the material of the second electrode 13, it is preferable to use a material having a high reflectance with respect to the light emitted from the active layer 9.

  This step S5 corresponds to the step (f).

(Step S6)
Next, as illustrated in FIG. 3C, the protective layer 17 is formed on the upper surface of the second electrode 13, and the bonding layer 19 is formed on the upper surface of the protective layer 17.

  The protective layer 17 is formed, for example, by depositing Ni with a thickness of 80 nm, Ti with a thickness of 100 nm, and Pt with a thickness of 200 nm using an electron beam evaporation apparatus (EB apparatus). In addition to Ti / Ti / Pt, TiW / Pt or the like can be used as the material for the protective layer 17.

  Thereafter, Ti having a film thickness of 10 nm is vapor-deposited on the upper surface of the protective layer 17, and Au—Sn solder composed of Au 80% Sn 20% is vapor-deposited with a film thickness of 3 μm, thereby forming the bonding layer 19. As the bonding layer 19, in addition to Au—Sn solder, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like can be used.

(Step S7)
As shown in FIG. 3D, a protective layer 23 and a bonding layer 21 are formed on the upper surface of the substrate 3 prepared separately from the growth substrate 25. As the substrate 3, as described above, a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si can be used. The protective layer 23 can be formed in the same manner as the protective layer 17, and the bonding layer 21 can be formed in the same manner as the bonding layer 19. Whether or not the protective layer 23 is provided is arbitrary.

(Step S8)
As shown in FIG. 3E, the growth substrate 25 and the substrate 3 are bonded together by bonding the bonding layer 19 formed on the upper layer of the growth substrate 25 and the bonding layer 21 formed on the upper layer of the substrate 3. As a specific example, the bonding process is performed at a temperature of 280 ° C. and a pressure of 0.2 MPa.

  By this process, the bonding layer 19 and the bonding layer 21 are melted and bonded to form a structure in which the substrate 3 and the growth substrate 25 are bonded to the front and back surfaces. That is, the bonding layer 19 and the bonding layer 21 may be integrated after this step. And since the protective layer 23 and the protective layer 17 are formed in the stage before execution of this step S8, the spreading | diffusion of the constituent material of a joining layer (19, 21) is suppressed.

  This step S8 corresponds to the step (g).

(Step S9)
As shown in FIG. 3F, the growth substrate 25 is peeled off. More specifically, the laser beam is irradiated from the growth substrate 25 side. Here, the laser beam to be irradiated is light having a wavelength that transmits the constituent material of the growth substrate 25 (sapphire in this embodiment) and is absorbed by the constituent material of the base layer 27 (GaN in this embodiment). . As a result, the laser light is absorbed by the underlayer 27, so that the interface between the growth substrate 25 and the underlayer 27 is heated to decompose GaN, and the growth substrate 25 is peeled off.

(Step S10)
After removing the metal Ga remaining on the wafer using hydrochloric acid or the like, GaN (underlying layer 27) is removed by dry etching using an ICP device to expose the n-type semiconductor layer 7 (see FIG. 3G). .

  Steps S9 and S10 correspond to step (h).

(Step S11)
The excitation light 55 having a predetermined wavelength is irradiated from the light source unit 51 to the semiconductor layer 5. Then, the light receiving unit 52 receives the fluorescence 56 emitted from the semiconductor layer 5, and outputs information on the received intensity to the calculation unit 53. The computing unit 53 compares the intensity of the fluorescence 56 with a predetermined threshold value for each location in the semiconductor layer 5, for example. When the intensity received by the light receiving unit 52 is equal to or less than the threshold value, the calculation unit 53 determines that a defective portion exists in the region in the semiconductor layer 5 that indicates the intensity.

  The light source unit 51 can use an arbitrary light source. As an example, a light emitting diode element, a laser element, a solid-state laser, a discharge lamp, or the like can be used. As the light source unit 51, it is possible to use the light emitting element 1 that has been determined to be non-defective.

  The light receiving unit 52 may use a light receiving element that can generate an electrical signal according to the amount of received light, such as a phototransistor, a photodiode, or an image sensor.

  The calculation unit 53 can be realized by a calculation device such as a CPU or a microcomputer.

  4A to 4C schematically show energy band diagrams of the semiconductor layer 5 in the case where a defective portion exists in a partial region A2.

  FIG. 4A schematically shows an energy band diagram when a crack is generated in the region A2. When the region A1 is irradiated with excitation light, electrons are excited and fluorescence L1 is emitted. On the other hand, since the semiconductor layer 5 does not exist in the region A2, the excited electrons do not exist and no fluorescence is generated. Therefore, in the case of the configuration as shown in FIG. 4A, it is determined that there is a defective portion in the region A2 where the intensity of the fluorescence received by the light receiving unit 52 is equal to or less than the threshold value.

  FIG. 4B schematically shows an energy band diagram in the case where a level different from the level formed by the semiconductor layer 5 exists in the region A2. When a crystal defect exists in the semiconductor layer 5, an electron capture level is formed. Under such a configuration, when the region A2 is irradiated with excitation light, the free electrons existing in the conduction band are sequentially trapped in the electron capture level, thereby being converted into heat and causing no fluorescence. There is a case. Further, when trapped in the electron capture level, fluorescence L2 may be emitted.

  Also in the case of FIG. 4B, the intensity of the fluorescence L2 emitted from the region A2 is lower than the fluorescence L1 emitted in the region A1. Therefore, in the case of the configuration shown in FIG. 4B, it is determined that there is a defective portion in the region A2 where the intensity of the fluorescence received by the light receiving unit 52 is equal to or less than the threshold value.

  FIG. 4C schematically shows an energy band diagram in the case where the semiconductor layer 5 having a composition different from that of the region A1 is formed in the region A2. In particular, in the case of growing a nitride semiconductor layer containing Al, when abnormal irregularities are formed on the surface of the semiconductor layer, the crystal arrangement is disturbed, and an abnormal composition portion in which the composition in the semiconductor layer 5 has changed from a predetermined value is generated. It may be randomly formed. At this time, regions having different Al compositions are formed in the semiconductor layer 5.

  At this time, as shown in FIG. 4C, the region A2 having a different composition from the surrounding has a different energy band gap compared to the region A1. Therefore, the wavelength of the fluorescence L2 emitted from the region A2 is different from that of the fluorescence L1 emitted from the region A1. In this case, the light receiving unit 52 is previously provided with a wavelength selection element (filter) that selectively receives light in a wavelength band including the wavelength of the fluorescence L1 that would be emitted when the semiconductor layer 5 exhibits a desired composition. It doesn't matter as what you have. When configured in this manner, as in the case of FIGS. 4A and 4B, it is determined that there is a defective portion in the region A2 in which the intensity of the fluorescence received by the light receiving unit 52 is equal to or less than the threshold value.

  FIG. 5A is a photograph when the light emitting element including the semiconductor layer 5 having no composition abnormality portion is irradiated with excitation light, and FIG. 5B illustrates the light emitting element including the semiconductor layer 5 having the composition abnormality portion. It is a photograph when irradiated with excitation light. According to the photograph shown in FIG. 5B, a part 2a having different brightness is confirmed at a specific part. This suggests that the portion 2a emits fluorescence having a wavelength different from that of other portions.

  This step S11 corresponds to steps (c), (d), and (e). In addition, although the wavelength of the excitation light emitted from the light source part 51 is selected suitably, it can be set as the ultraviolet region of 320 nm-380 nm, for example. The calculation unit 53 may be configured to be able to store the location of the semiconductor layer 5 that is determined to have a defective portion.

(Step S12)
As shown in FIG. 3I, adjacent elements are separated from each other. Specifically, the semiconductor layer 5 is etched with respect to the boundary region with the adjacent element using an ICP apparatus until the upper surface of the current blocking layer 24 formed in the element isolation region is exposed. At this time, the current blocking layer 24 functions as an etching stopper layer. In FIG. 3I, the side surface of the semiconductor layer 5 is illustrated as being inclined with respect to the vertical direction, but this is only an example and is not intended to be limited to such a shape.

(Step S13)
As shown in FIG. 3J, the first electrode 15 is formed on a part of the upper surface of the n-type semiconductor layer 7. For example, a conductive material made of, for example, Ni / Al / Ni / Ti / Au is deposited by an electron beam deposition apparatus, for example, with a film thickness of about 3 μm.

  As described above with reference to FIG. 2A, the outer edge of the first electrode 15 formed through this step S13 has a frame shape. In the present embodiment, in particular, the first electrode 15 is disposed at a position facing the current blocking layer 24 in the Z direction (direction perpendicular to the surface of the substrate 3).

  This step S13 corresponds to step (i).

(Step S14)
Divide the wafer into chips. As a specific example, each element is separated by, for example, a laser dicing apparatus. This step S14 corresponds to the step (j).

(Step S15)
A mounting process is performed for each element divided into chips. Specifically, the back surface of the substrate 3 is bonded to the package with, for example, Ag paste, and the current supply line 14 is connected to the current supply unit 15a. For example, wire bonding is performed by connecting a current supply line 14 made of Au to a current supply unit 15a having a diameter of 100 μm with a load of 50 g. Thereby, the light emitting element 1 is formed.

  In step S15, for the chip corresponding to the area determined to have a defective portion in step S11, this step S15 is not performed, and only the chip determined to have no defective portion is processed in this step S15. It does not matter if you do.

  Step S15 corresponds to step (k).

[Action]
By manufacturing the semiconductor light emitting element 1 by the above method, the light emitting element determined to have a defective portion is not sent to the subsequent process, and only the light emitting element determined to have no defective portion is processed later. Can be sent to the process. In particular, as in step S11, since it is possible to make a good / bad determination only by confirming the intensity of the fluorescent light received by irradiating the excitation light, the determination process can be performed in batches for each wafer. In addition, unlike white light, since ultraviolet light is irradiated as excitation light, the problem that the determination accuracy is reduced due to scattered light hardly occurs. Therefore, it is possible to make a good / defective determination with high accuracy without complicating the manufacturing process.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> In the above-described embodiment, the case where step S11 is executed between step S10 and step S12 has been described. However, step S11 can be executed at various timings.

  For example, step S11 may be executed after step S3. In this case, the quality of the wafer shown in FIG. 3B can be determined. Therefore, when distributing wafers as shown in FIG. 3B, only good products can be distributed.

  Moreover, after performing the element isolation process which concerns on step S12, or after performing the formation process of the 1st electrode 15 which concerns on step S13, you may perform the determination process of step S11. That is, step S11 may be executed at an arbitrary timing after step S3 and before step S14.

  <2> In each of the embodiments described above, the semiconductor light emitting element 1 has been described as having a structure as shown in FIGS. 2A to 2B. However, the structure of the semiconductor light emitting element 1 is not limited to the above. 6A and 6B are drawings schematically showing another structure of the semiconductor light emitting device 1. 6A corresponds to a plan view, and FIG. 6B corresponds to a cross-sectional view.

  When manufacturing this structure, after performing steps S1 to S3, step S11 is performed to determine whether the semiconductor layer 5 is good or bad. Thereafter, the following steps are performed.

(Step S21)
In the region determined as non-defective, the p-type semiconductor layer 11 and the active layer 9 formed in a part of the region are etched until the upper surface of the n-type semiconductor layer 7 is exposed.

(Step S22)
The second electrode 13 is formed on the upper surface of the predetermined region of the p-type semiconductor layer 11, and the first electrode 15 is formed on the upper surface of the predetermined region of the exposed n-type semiconductor layer 7. In this structure, the second electrode 13 may be made of the same material as the first electrode 15. Thereafter, necessary mounting processing is performed.

  <3> In the embodiment described above, the side close to the substrate 3 among the layers constituting the semiconductor layer 5 has been described as the p-type semiconductor layer 11, and the side far from the substrate 3 has been described as the n-type semiconductor layer 7. The conductivity type may be reversed.

  <4> As described above, whether or not the light-emitting element 1 illustrated in FIG. 2B includes the current blocking layer 24 is arbitrary.

  In the case where the current blocking layer 24 is provided, the current blocking layer 24 made of an insulating layer is formed in the element isolation region, while the current blocking layer made of a metal material is disposed at a position facing the first electrode 15 in the Z direction. 24 may be configured. The current blocking layer 24 may be made of, for example, the same material as the second electrode 13 and a Schottky contact may be formed with the p-type semiconductor layer 11. Even in this case, since the contact resistance between the current blocking layer 24 and the p-type semiconductor layer 11 is higher than the contact resistance between the second electrode 13 and the p-type semiconductor layer 11, the current flowing in the active layer 9 is reduced to the substrate 3. The effect of spreading in a direction parallel to the surface of the is exhibited.

1: Semiconductor light emitting element 2: Region where fluorescence intensity is lower than surroundings 3: Substrate 5: Semiconductor layer 7: n-type semiconductor layer 9: active layer 11: p-type semiconductor layer 13: second electrode 14: current supply line 15: First electrode 15a: current supply unit 17: protective layer 19: bonding layer 20: conductive layer 21: bonding layer 23: protective layer 24: current blocking layer 25: growth substrate 27: base layer 51: light source unit 52: light receiving unit 53 : Calculation unit 55: Excitation light 56: Fluorescence 90: Conventional semiconductor light emitting device 91: Substrate 92: Conductive layer 93: Reflective film 94: Insulating layer 95: Reflective electrode 96: P-type semiconductor layer 97: Active layer 98: n-type Semiconductor layer 99: Semiconductor layer 100: n-side electrode

Claims (12)

A method for manufacturing a semiconductor light emitting device wafer, comprising:
A step (a) of preparing a growth substrate;
Forming a semiconductor layer on the growth substrate (b);
Irradiating the semiconductor layer with excitation light (c);
Receiving the fluorescence emitted from the semiconductor layer during the execution of the step (c) (d);
And (e) performing a quality determination of the semiconductor layer based on the light output of the fluorescence received in the step (d).   The step (e) is a step of determining that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity received from the specific portion of the semiconductor layer is a predetermined threshold value or less. The manufacturing method of the wafer for semiconductor light-emitting devices of Claim 1. The step (d) is a step of selecting and receiving light of a predetermined wavelength band from the fluorescence.
The step (e) determines that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity of the predetermined wavelength band received from the specific portion of the semiconductor layer is equal to or less than a predetermined threshold value. The method of manufacturing a wafer for a semiconductor light-emitting element according to claim 1, wherein   The method of manufacturing a wafer for a semiconductor light emitting element according to claim 1, wherein the step (b) is a step of forming the semiconductor layer made of a nitride semiconductor. The semiconductor layer has a nitride semiconductor containing Al,
The method for manufacturing a wafer for a semiconductor light emitting element according to claim 4, wherein the excitation light is ultraviolet light. A method for manufacturing a semiconductor light emitting device, comprising:
A step (a) of preparing a growth substrate;
Forming an n-type or p-type first semiconductor layer, an active layer, and a semiconductor layer including a second semiconductor layer having a conductivity type different from that of the first semiconductor layer on the growth substrate;
Irradiating the semiconductor layer with excitation light (c);
Receiving the fluorescence emitted from the semiconductor layer during the execution of the step (c) (d);
A step (e) of determining the quality of the semiconductor layer based on the light output of the fluorescence received in the step (d);
A step (f) of forming a second electrode on the second semiconductor layer after the step (b);
A step (g) of attaching a substrate different from the growth substrate to the upper layer of the second electrode;
After the step (g), the step (h) of peeling the growth substrate and exposing the first semiconductor layer;
And (i) forming a first electrode on the upper surface of the first semiconductor layer.   The step (e) is a step of determining that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity received from the specific portion of the semiconductor layer is a predetermined threshold value or less. A method for manufacturing a semiconductor light emitting device according to claim 6. The step (d) is a step of selecting and receiving light of a predetermined wavelength band from the fluorescence.
The step (e) determines that the specific portion of the semiconductor layer has a defective portion when the fluorescence intensity of the predetermined wavelength band received from the specific portion of the semiconductor layer is equal to or less than a predetermined threshold value. The method of manufacturing a semiconductor light emitting element according to claim 6, wherein   9. The step (c), the step (d), and the step (e) are performed after the step (h) and before the step (i). The manufacturing method of the semiconductor light-emitting device of any one of these. After the step (i), a step (j) of dividing the wafer into chips,
A step (k) of performing a mounting process on each chip,
The step (c), the step (d), and the step (e) are performed before the step (k),
9. The method of manufacturing a semiconductor light emitting element according to claim 6, wherein the step (k) is performed only on the chip determined to be a non-defective product in the step (e). .   The method of manufacturing a semiconductor light-emitting element according to claim 6, wherein the step (b) is a step of forming the semiconductor layer made of a nitride semiconductor. The semiconductor layer has a nitride semiconductor containing Al,
The method of manufacturing a semiconductor light emitting element according to claim 11, wherein the step (c) is a step of irradiating with ultraviolet light.

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