JP2017147685A - Filter time constant change circuit and d/a conversion circuit - Google Patents

Filter time constant change circuit and d/a conversion circuit Download PDF

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JP2017147685A
JP2017147685A JP2016029963A JP2016029963A JP2017147685A JP 2017147685 A JP2017147685 A JP 2017147685A JP 2016029963 A JP2016029963 A JP 2016029963A JP 2016029963 A JP2016029963 A JP 2016029963A JP 2017147685 A JP2017147685 A JP 2017147685A
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filter
time constant
input signal
change
output
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JP6626362B2 (en
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康弘 小木曽
Yasuhiro Ogiso
康弘 小木曽
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Azbil Corp
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Azbil Corp
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Priority to CN201710081756.7A priority patent/CN107104656B/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/0009—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0626—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by filtering
    • H03M1/0631—Smoothing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2210/00—Indexing scheme relating to details of tunable filters
    • H03H2210/04—Filter calibration method
    • H03H2210/043—Filter calibration method by measuring time constant

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress ripple of an output of a filter in a configuration of changing a time constant of a filter according to a change in an input signal.SOLUTION: A filter time constant change circuit (4) includes: change amount calculation parts (40, 41) for calculating a change amount h(t,T)=f(t)-f(t-T) per predetermined time T obtained from a value f(t) of an input signal at a present time and a value f(t-T) of an input signal at T hour before a present time; a comparison part (42) for outputting a control signal controlling a time constant of a filter (2) on the basis of a comparison result between the change amount h(t,T) and a predetermined threshold value.SELECTED DRAWING: Figure 10

Description

本発明は、入力信号の変化に応じてフィルタの時定数を変更するフィルタ時定数変更回路、およびフィルタ時定数変更回路を用いるＤ／Ａ変換回路に関するものである。   The present invention relates to a filter time constant changing circuit for changing a filter time constant in accordance with a change in an input signal, and a D / A conversion circuit using the filter time constant changing circuit.

Ｄ／Ａ変換回路の出力においては、一般にパルスの波形をローパスフィルタにより平滑化して出力する方式が採られる。このときフィルタの時定数の大小により、応答速度とリップルがトレードオフの関係になる。実際にフィルタの時定数を決める際は、例えば許容出来るリップルの値の中で出来るだけ早い応答速度にするなどして決める。一方で、Ｄ／Ａ変換回路の出力の大きな変化をステップ的に行なうとき、この応答速度の制限による追従の遅さが問題になるケースがある。   In the output of the D / A conversion circuit, a method is generally adopted in which the pulse waveform is smoothed and output by a low-pass filter. At this time, the response speed and the ripple have a trade-off relationship depending on the magnitude of the time constant of the filter. When the time constant of the filter is actually determined, for example, it is determined by setting the response speed as fast as possible within the allowable ripple value. On the other hand, when a large change in the output of the D / A conversion circuit is made in a stepwise manner, there is a case where the tracking delay due to the limitation of the response speed becomes a problem.

このような問題の解決策として、Ｄ／Ａ変換回路の出力の大きくかつ急な変化があったときに、フィルタの時定数を小さくすることで、リップルの制限を達成しつつ応答を早める技術が提案されている（特許文献１参照）。図１４は特許文献１に開示されたＤ／Ａ変換回路の構成を示すブロック図である。図１４のＤ／Ａ変換回路は、ＡＳＩＣ（Application Specific Integrated Circuit）３００を使って、応答性を向上させるようにしたものである。ＰＷＭ信号をつくるデジタルデータが変化したときは、抵抗３０２とコンデンサ３０３とからなる時定数が小さいアナログフィルタに切り替えて、応答性を良くする。デジタルデータに変化がないときは、抵抗３０１とコンデンサ３０３とからなる時定数が大きいアナログフィルタに切り替えて、出力リップルを抑制する。   As a solution to such a problem, there is a technique for speeding up the response while achieving ripple limitation by reducing the time constant of the filter when the output of the D / A converter circuit is large and suddenly changed. It has been proposed (see Patent Document 1). FIG. 14 is a block diagram showing a configuration of the D / A conversion circuit disclosed in Patent Document 1. In FIG. The D / A conversion circuit of FIG. 14 uses an ASIC (Application Specific Integrated Circuit) 300 to improve responsiveness. When the digital data for generating the PWM signal changes, the response is improved by switching to an analog filter composed of a resistor 302 and a capacitor 303 with a small time constant. When there is no change in the digital data, the output ripple is suppressed by switching to an analog filter comprising a resistor 301 and a capacitor 303 with a large time constant.

Ｄ／Ａ変換回路からフィルタに入力される入力信号の変化の大きさに応じてフィルタの時定数を変化させる場合、常識的な発想として、例えば図１５のような構成が考えられる。図１５の例では、変化量演算部１００が入力信号ｆ（ｔ）の変化量Δｆ（ｔ）／Δｔを演算し、この変化量Δｆ（ｔ）／Δｔに応じて時定数変更部１０１がフィルタ１０２の時定数を変更する。図１６の例では、入力信号ｆ（ｔ）に変化が生じたときにフィルタ１０２の時定数を変更する。一方、図１７の例では、変化量Δｆ（ｔ）／Δｔが閾値ＴＨを超えたときにフィルタ１０２の時定数を変更する。   When changing the time constant of the filter according to the magnitude of the change of the input signal input to the filter from the D / A conversion circuit, for example, a configuration as shown in FIG. In the example of FIG. 15, the change amount calculation unit 100 calculates the change amount Δf (t) / Δt of the input signal f (t), and the time constant changing unit 101 performs filtering according to the change amount Δf (t) / Δt. The time constant of 102 is changed. In the example of FIG. 16, when the input signal f (t) changes, the time constant of the filter 102 is changed. On the other hand, in the example of FIG. 17, the time constant of the filter 102 is changed when the change amount Δf (t) / Δt exceeds the threshold value TH.

一般的に変化量演算部１００で行われる処理は微分に相当し、フィルタ１０２の時定数変更のための制御信号（図１６、図１７のフィルタ時定数変更フラグ）が生じるのは、入力信号ｆ（ｔ）が傾きを持つ間に限られる。したがって、入力信号ｆ（ｔ）が傾きを持つ時間幅が非常に短い場合は、時定数変更のための制御信号が生じる時間幅も短くなる。フィルタ１０２の時定数変更を行なう適切な時間幅は、フィルタ１０２の持つ時定数及びフィルタ１０２の目的に依存するため、時定数変更のための制御信号が生じる時間幅が短くなると、フィルタ１０２の時定数変更が目的とする機能を充分に発揮出来ない可能性がある。   In general, the process performed by the change amount calculation unit 100 corresponds to differentiation, and the control signal for changing the time constant of the filter 102 (filter time constant change flag in FIGS. 16 and 17) is generated by the input signal f. Only when (t) has a slope. Therefore, when the time width in which the input signal f (t) has a slope is very short, the time width in which the control signal for changing the time constant is also shortened. The appropriate time width for changing the time constant of the filter 102 depends on the time constant of the filter 102 and the purpose of the filter 102. Therefore, when the time width in which the control signal for changing the time constant is reduced, the time of the filter 102 There is a possibility that the target function cannot be fully achieved by changing the constant.

例えば、ある一定以上の入力信号ｆ（ｔ）の急峻な変化に対応するため、入力信号ｆ（ｔ）の変化に合わせてフィルタ１０２の時定数を一時的に小さくする場合を考える。このとき、時定数を変更する時間幅は、変更後のフィルタ１０２の時定数により、充分に入力信号ｆ（ｔ）に追従出来る分だけの長さが必要になるが、入力信号ｆ（ｔ）の変化の間だけ（微分値が閾値ＴＨを超える間だけ）、フィルタ１０２の時定数を小さくしても、フィルタ１０２の出力は図１８のようになり、フィルタ１０２の機能を充分に発揮することが出来ない。図１８の例では、ｇ（ｔ）がフィルタ１０２の実際の出力を表し、ｇ’（ｔ）は理想の出力を表している。図１８によると、フィルタ１０２の出力ｇ（ｔ）が入力信号ｆ（ｔ）の変化に追従出来ていないことが分かる。   For example, a case is considered in which the time constant of the filter 102 is temporarily reduced in accordance with the change of the input signal f (t) in order to cope with a sudden change of the input signal f (t) above a certain level. At this time, the time width for changing the time constant needs to be long enough to follow the input signal f (t) depending on the time constant of the filter 102 after the change, but the input signal f (t) Even when the time constant of the filter 102 is reduced only during the change of (the differential value exceeds the threshold value TH), the output of the filter 102 is as shown in FIG. 18, and the function of the filter 102 is fully exhibited. I can't. In the example of FIG. 18, g (t) represents the actual output of the filter 102, and g '(t) represents the ideal output. As can be seen from FIG. 18, the output g (t) of the filter 102 cannot follow the change in the input signal f (t).

このような図１５の構成の問題点に対し、タイマを使って、変化量演算部１００の出力（入力信号ｆ（ｔ）の微分値）をトリガにして、変化量演算部１００の出力が閾値を超えた場合にフィルタ１０２の時定数変更を一定時間保持する仕組みにすることで、フィルタ１０２の機能を充分に発揮出来るようにすることが容易に考えられる。図１９の例では、変化量演算部１００と時定数変更部１０１との間にタイマ１０３を設けることにより、入力信号ｆ（ｔ）への追従に必要な時間幅の信号をタイマ１０３で作ることで、図２０に示すように、入力信号ｆ（ｔ）への追従に必要な時定数変更の時間幅を与えるようにしている。   To solve the problem of the configuration of FIG. 15, the output of the change amount calculation unit 100 is triggered by the output of the change amount calculation unit 100 (the differential value of the input signal f (t)) using a timer. It can be easily considered that the function of the filter 102 can be sufficiently exhibited by setting the mechanism for holding the change of the time constant of the filter 102 for a certain period of time when the value of the filter 102 is exceeded. In the example of FIG. 19, by providing the timer 103 between the change amount calculation unit 100 and the time constant changing unit 101, the timer 103 generates a signal having a time width necessary for following the input signal f (t). Thus, as shown in FIG. 20, a time width for changing the time constant necessary for following the input signal f (t) is given.

しかし、図１９に示した構成では、変化量演算部１００の出力（入力信号ｆ（ｔ）の微分値）をフィルタ１０２の時定数変更のトリガにすることで、本来意図しない場面での誤動作の恐れが大きくなってしまうという問題がある。例えば、図２１に示すような瞬間的な入力信号ｆ（ｔ）の変化に対して一定時間、フィルタ１０２の時定数変更を行なってしまうと、意図しない領域でフィルタ１０２の出力ｇ（ｔ）にリップルを生じさせてしまうという問題がある。   However, in the configuration shown in FIG. 19, by using the output of the change amount calculation unit 100 (differential value of the input signal f (t)) as a trigger for changing the time constant of the filter 102, malfunction in a scene that is not originally intended. There is a problem of increasing fear. For example, if the time constant of the filter 102 is changed for a certain time with respect to the instantaneous change of the input signal f (t) as shown in FIG. 21, the output g (t) of the filter 102 is output in an unintended region. There is a problem of causing ripples.

特開２００３−１０１４１３号公報JP 2003-101413 A

以上のように、入力信号の変化に応じてフィルタの時定数を変更する構成では、フィルタの出力を入力信号の変化に充分に追従させようとすると、フィルタの出力に大きなリップルが生じてしまうという問題点があった。
なお、以上の問題はＤ／Ａ変換回路の出力を入力とするフィルタに限らず、例えばアナログ信号をフィルタ処理してＡ／Ｄ変換回路に入力するフィルタ等においても同様に発生する。 As described above, in the configuration in which the time constant of the filter is changed according to the change in the input signal, if the filter output is made to sufficiently follow the change in the input signal, a large ripple is generated in the filter output. There was a problem.
The above problem is not limited to a filter that uses the output of the D / A conversion circuit as an input, but also occurs in a filter that filters an analog signal and inputs the analog signal to the A / D conversion circuit, for example.

本発明は、上記課題を解決するためになされたもので、入力信号の変化に応じてフィルタの時定数を変更する構成において、フィルタの出力のリップルを低減することができるフィルタ時定数変更回路を提供することを目的とする。   The present invention has been made in order to solve the above-described problems. A filter time constant changing circuit capable of reducing the output ripple of a filter in a configuration in which the time constant of the filter is changed in accordance with a change in an input signal. The purpose is to provide.

本発明は、入力信号をフィルタリングするためのフィルタの時定数を決定するフィルタ時定数変更回路において、現時点の前記入力信号の値ｆ（ｔ）と現時点からＴ時間前の入力信号の値ｆ（ｔ−Ｔ）とから得られる所定時間Ｔあたりの変化量ｈ（ｔ，Ｔ）＝ｆ（ｔ）−ｆ（ｔ−Ｔ）を演算する変化量演算部と、前記変化量ｈ（ｔ，Ｔ）と所定の閾値との比較結果に基づいて前記フィルタの時定数を制御する制御信号を出力する比較部とを備えることを特徴とするものである。
また、本発明のフィルタ時定数変更回路の１構成例において、前記比較部は、前記変化量ｈ（ｔ，Ｔ）が前記閾値以下の場合に前記フィルタの時定数を第１のフィルタ時定数τ１とする制御信号を出力し、前記変化量ｈ（ｔ，Ｔ）が前記閾値を超える場合に前記フィルタの時定数を前記第１のフィルタ時定数τ１よりも小さい第２のフィルタ時定数τ２に変更する制御信号を出力することを特徴とするものである。
また、本発明のフィルタ時定数変更回路の１構成例において、前記所定時間Ｔは、前記入力信号の変化開始時点から、前記第２のフィルタ時定数τ２において、その変化の最終値に対して前記フィルタの出力信号の値が所定の割合に到達するまでの時間であることを特徴とするものである。 The present invention relates to a filter time constant changing circuit that determines a time constant of a filter for filtering an input signal, and a value f (t) of the current input signal and a value f (t) of an input signal T time before the current time. -T) and a change amount calculation unit for calculating a change amount h (t, T) = f (t) -f (t-T) per predetermined time T obtained from the above-mentioned change amount h (t, T) And a comparator that outputs a control signal for controlling the time constant of the filter based on a comparison result between the filter and a predetermined threshold value.
Further, in one configuration example of the filter time constant changing circuit of the present invention, the comparison unit sets the filter time constant to the first filter time constant τ1 when the change amount h (t, T) is equal to or less than the threshold value. When the change amount h (t, T) exceeds the threshold value, the filter time constant is changed to a second filter time constant τ2 that is smaller than the first filter time constant τ1. The control signal to output is output.
Further, in one configuration example of the filter time constant changing circuit according to the present invention, the predetermined time T is from the start of change of the input signal to the final value of the change in the second filter time constant τ2. It is a time until the value of the output signal of the filter reaches a predetermined ratio.

また、本発明のＤ／Ａ変換回路は、デジタル入力信号をアナログ信号に変換するＤ／Ａ変換部と、このＤ／Ａ変換部の出力信号を平滑化するフィルタと、前記デジタル入力信号を入力とし、前記フィルタの時定数を制御する制御信号を出力する、請求項１乃至３のいずれか１項に記載のフィルタ時定数変更回路とを備えることを特徴とするものである。   The D / A conversion circuit according to the present invention includes a D / A converter that converts a digital input signal into an analog signal, a filter that smoothes the output signal of the D / A converter, and the digital input signal. And a filter time constant changing circuit according to any one of claims 1 to 3, which outputs a control signal for controlling a time constant of the filter.

本発明によれば、変化量演算部と比較部とを設けることにより、フィルタの出力を入力信号の変化に追従させつつ、フィルタの出力のリップルを低減することが出来る。また、本発明では、フィルタの出力のリップル低減を、従来のようなタイマを使用せずに実現することが出来るので、回路の実装を容易にすることができる。   According to the present invention, by providing the change amount calculation unit and the comparison unit, it is possible to reduce the ripple of the output of the filter while making the output of the filter follow the change of the input signal. Further, in the present invention, the ripple of the output of the filter can be reduced without using a conventional timer, so that the circuit can be easily mounted.

本発明に係る変化量演算の原理を説明する波形図である。It is a wave form diagram explaining the principle of variation | change_quantity calculation which concerns on this invention. 本発明に係る変化量演算の原理を説明する波形図である。It is a wave form diagram explaining the principle of variation | change_quantity calculation which concerns on this invention. 本発明においてフィルタの時定数を変更する動作を説明する波形図である。It is a wave form diagram explaining the operation | movement which changes the time constant of a filter in this invention. 本発明に係る変化量演算の別の例を示す波形図である。It is a wave form diagram which shows another example of the variation calculation which concerns on this invention. 本発明に係る変化量演算の別の例を示す波形図である。It is a wave form diagram which shows another example of the variation calculation which concerns on this invention. 本発明においてフィルタの時定数を変更する動作を説明する波形図である。It is a wave form diagram explaining the operation | movement which changes the time constant of a filter in this invention. 本発明に係る変化量演算の別の例を示す波形図である。It is a wave form diagram which shows another example of the variation calculation which concerns on this invention. 本発明に係る変化量演算の別の例を示す波形図である。It is a wave form diagram which shows another example of the variation calculation which concerns on this invention. 本発明においてフィルタの時定数を変更する動作を説明する波形図である。It is a wave form diagram explaining the operation | movement which changes the time constant of a filter in this invention. 本発明の実施の形態に係るＤ／Ａ変換回路の構成を示すブロック図である。1 is a block diagram showing a configuration of a D / A conversion circuit according to an embodiment of the present invention. 本発明の実施の形態における所定時間の設定の仕方を説明する図である。It is a figure explaining how to set the predetermined time in the embodiment of the present invention. 本発明の実施の形態に係るＤ／Ａ変換回路の応答の例を示す波形図である。It is a wave form diagram which shows the example of the response of the D / A converter circuit which concerns on embodiment of this invention. 本発明の実施の形態に係るＤ／Ａ変換回路の応答の実測結果を示す波形図である。It is a wave form diagram which shows the actual measurement result of the response of the D / A converter circuit which concerns on embodiment of this invention. 従来のＤ／Ａ変換回路の構成を示すブロック図である。It is a block diagram which shows the structure of the conventional D / A conversion circuit. フィルタの時定数を変化させる構成を示すブロック図である。It is a block diagram which shows the structure which changes the time constant of a filter. 図１５の構成においてフィルタの時定数を変更する動作を説明する波形図である。It is a wave form diagram explaining the operation | movement which changes the time constant of a filter in the structure of FIG. 図１５の構成においてフィルタの時定数を変更する別の動作を説明する波形図である。It is a wave form diagram explaining another operation | movement which changes the time constant of a filter in the structure of FIG. 図１５の構成の問題点を説明する波形図である。It is a wave form diagram explaining the problem of the structure of FIG. フィルタの時定数を変化させる別の構成を示すブロック図である。It is a block diagram which shows another structure which changes the time constant of a filter. 図１９の構成においてフィルタの時定数を変更する動作を説明する波形図である。It is a wave form diagram explaining the operation | movement which changes the time constant of a filter in the structure of FIG. 図１９の構成の問題点を説明する波形図である。FIG. 20 is a waveform diagram illustrating a problem of the configuration of FIG. 19.

［発明の原理］
図１（Ａ）〜図１（Ｃ）、図２（Ａ）〜図２（Ｃ）は、本発明に係る変化量演算の原理を説明する波形図である。本発明では、入力信号の変化量（微分値）を演算する従来の構成を、フィルタの目的とする時定数変化に対応させた時間幅Ｔあたりの変化量を演算する構成に置き換えることで、フィルタの時定数変更の効果を適切に反映させる。具体的には、変化量を演算しようとする現時点の入力信号の値ｆ（ｔ）と、現時点からＴ時間前の入力信号の値ｆ（ｔ−Ｔ）とから得られる所定時間Ｔあたりの変化量ｈ（ｔ，Ｔ）＝ｆ（ｔ）−ｆ（ｔ−Ｔ）を演算し、この演算結果に基づいてフィルタの時定数を決定する。図１（Ａ）〜図１（Ｃ）、図２（Ａ）〜図２（Ｃ）の例では、時間と共に変化する入力信号に応じて変化量ｈ（ｔ，Ｔ）が逐次演算される様子が示されている。 [Principle of the Invention]
1 (A) to 1 (C) and FIGS. 2 (A) to 2 (C) are waveform diagrams for explaining the principle of variation calculation according to the present invention. In the present invention, the conventional configuration for calculating the amount of change (differential value) of the input signal is replaced with a configuration for calculating the amount of change per time width T corresponding to the target time constant change of the filter. The effect of changing the time constant is appropriately reflected. Specifically, the change per predetermined time T obtained from the current input signal value f (t) for which the change amount is to be calculated and the input signal value f (t−T) T hours before the current time. The quantity h (t, T) = f (t) −f (t−T) is calculated, and the time constant of the filter is determined based on the calculation result. In the examples of FIGS. 1A to 1C and FIGS. 2A to 2C, the change amount h (t, T) is sequentially calculated according to the input signal that changes with time. It is shown.

以上のようにして演算した変化量ｈ（ｔ，Ｔ）が所定の閾値ＴＨを超えたときにフィルタの時定数を小さい方に変更する（フィルタ時定数変更フラグを“１”にする）構成を採用すると、フィルタの出力ｇ（ｔ）は図３に示すような挙動になる。図３におけるｇ’（ｔ）は理想の出力を表している。   A configuration in which the time constant of the filter is changed to a smaller one (the filter time constant change flag is set to “1”) when the change amount h (t, T) calculated as described above exceeds a predetermined threshold value TH. When employed, the output g (t) of the filter behaves as shown in FIG. In FIG. 3, g ′ (t) represents an ideal output.

図２０の場合と比べると明らかなように、本発明の方がフィルタの出力ｇ（ｔ）がより早く入力信号ｆ（ｔ）に追いついている。
また、本発明では、変化量ｈ（ｔ，Ｔ）が、入力信号ｆ（ｔ）の変化の大きさの総量を情報として含む形になっているため、図２１で説明したようなリップルの問題は発生しない。図２１に示したような瞬間的な入力信号ｆ（ｔ）の変化に対する本発明の変化量演算の結果を図４（Ａ）〜図４（Ｄ）、図５に示す。 As is clear from the case of FIG. 20, the output g (t) of the filter catches up with the input signal f (t) earlier in the present invention.
Further, in the present invention, the amount of change h (t, T) includes the total amount of change in the input signal f (t) as information, so that the ripple problem as described with reference to FIG. Does not occur. FIG. 4A to FIG. 4D and FIG. 5 show the results of the change amount calculation according to the present invention for the instantaneous input signal f (t) change as shown in FIG.

図４（Ａ）〜図４（Ｄ）、図５の演算結果が閾値ＴＨを超えたときにフィルタの時定数を小さい方に変更する構成を採用すると、フィルタの出力ｇ（ｔ）は図６に示すような挙動になる。本発明では、入力信号の二点間の差（ｆ（ｔ）−ｆ（ｔ−Ｔ）のとり得る最大値に応じて閾値ＴＨを定めるため、閾値ＴＨを下回るノイズによる誤動作は起こらない。   When the configuration in which the time constant of the filter is changed to a smaller one when the calculation results of FIGS. 4A to 4D and FIG. 5 exceed the threshold value TH, the output g (t) of the filter is as shown in FIG. The behavior is as shown in. In the present invention, the threshold value TH is determined in accordance with the maximum value that can be taken by the difference (f (t) −f (t−T) between two points of the input signal, so that malfunction due to noise below the threshold value TH does not occur.

また、本発明では、非常に鋭く大きな値のノイズが入力信号ｆ（ｔ）に混入した場合でも、そのノイズのピークの時間幅×２以内の時間幅でフィルタの時定数を変更する動作となるので、図１９のタイマを用いた場合に比べてフィルタ出力への影響は小さくなることが期待出来る。このようなノイズ入力に対する本発明の変化量演算の結果を図７（Ａ）〜図７（Ｃ）、図８（Ａ）、図８（Ｂ）に示す。   Further, in the present invention, even when a very sharp and large noise is mixed in the input signal f (t), the time constant of the filter is changed within the time width of the peak time of the noise × 2 or less. Therefore, the influence on the filter output can be expected to be smaller than in the case of using the timer of FIG. 7A to 7C, FIG. 8A, and FIG. 8B show the results of the change amount calculation of the present invention for such noise input.

図７（Ａ）〜図７（Ｃ）、図８（Ａ）、図８（Ｂ）の演算結果が閾値ＴＨを超えたときにフィルタの時定数を小さい方に変更する構成を採用すると、フィルタの出力ｇ（ｔ）は図９に示すような挙動になる。
以上のように、本発明では、従来技術で生じる、意図しない領域でフィルタの出力ｇ（ｔ）にリップルを生じさせてしまうという問題を解決することが出来る。 When the configuration in which the time constant of the filter is changed to a smaller one when the calculation results in FIGS. 7A to 7C, FIG. 8A, and FIG. Output g (t) behaves as shown in FIG.
As described above, according to the present invention, it is possible to solve the problem that a ripple occurs in the output g (t) of the filter in an unintended region, which occurs in the prior art.

[実施の形態]
以下、本発明の実施の形態について図面を参照して説明する。図１０は本発明の実施の形態に係るＤ／Ａ変換回路の構成を示すブロック図である。本実施の形態のＤ／Ａ変換回路は、１６ｂｉｔのデジタル入力信号ｆ（ｔ）をアナログ信号に変換するＤ／Ａ変換部１と、Ｄ／Ａ変換部１の出力信号を平滑化するローパスフィルタ２と、ローパスフィルタ２の出力端子に接続されるバッファ回路３と、入力信号ｆ（ｔ）の変化量に基づいてローパスフィルタ２の時定数を決定するフィルタ時定数変更回路４とから構成される。 [Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 10 is a block diagram showing a configuration of the D / A conversion circuit according to the embodiment of the present invention. The D / A converter circuit according to the present embodiment includes a D / A converter 1 that converts a 16-bit digital input signal f (t) into an analog signal, and a low-pass filter that smoothes the output signal of the D / A converter 1. 2, a buffer circuit 3 connected to the output terminal of the low-pass filter 2, and a filter time constant changing circuit 4 that determines the time constant of the low-pass filter 2 based on the amount of change in the input signal f (t). .

Ｄ／Ａ変換部１としては、ΔΣ変調器、ＰＷＭ（Pulse Width Modulation）変調器、ラダー抵抗型のＤ／Ａ変換器など様々な構成を適用することができ、本発明はＤ／Ａ変換の方式に限定されるものではない。   As the D / A converter 1, various configurations such as a ΔΣ modulator, a PWM (Pulse Width Modulation) modulator, a ladder resistance type D / A converter, and the like can be applied. It is not limited to the method.

ローパスフィルタ２は、Ｄ／Ａ変換部１の出力端子とバッファ回路３の入力端子との間に直列に設けられた抵抗Ｒ１，Ｒ２と、フィルタ時定数変更回路４からの制御信号に応じて抵抗Ｒ１を短絡するスイッチＳＷ１と、バッファ回路３の入力端子と接地との間に設けられたコンデンサＣ１とから構成される。   The low-pass filter 2 includes resistors R1 and R2 provided in series between the output terminal of the D / A converter 1 and the input terminal of the buffer circuit 3, and a resistor according to a control signal from the filter time constant changing circuit 4. The switch SW1 for short-circuiting R1 and a capacitor C1 provided between the input terminal of the buffer circuit 3 and the ground.

フィルタ時定数変更回路４は、遅延部４０と、減算部４１と、比較部４２（コンパレータ）とから構成される。遅延部４０と減算部４１とは、変化量演算部を構成している。
遅延部４０は、デジタル入力信号ｆ（ｔ）を所定時間Ｔだけ遅延させる。遅延部４０としては、複数段縦続接続されたフリップフロップを用いることができる。
減算部４１は、デジタル入力信号ｆ（ｔ）から遅延部４０のデジタル出力信号を減算する。こうして、時間Ｔあたりの入力信号の変化量であるｈ（ｔ，Ｔ）＝ｆ（ｔ）−ｆ（ｔ−Ｔ）を演算することができる。 The filter time constant changing circuit 4 includes a delay unit 40, a subtraction unit 41, and a comparison unit 42 (comparator). The delay unit 40 and the subtraction unit 41 constitute a change amount calculation unit.
The delay unit 40 delays the digital input signal f (t) by a predetermined time T. As the delay unit 40, flip-flops connected in cascade at a plurality of stages can be used.
The subtractor 41 subtracts the digital output signal of the delay unit 40 from the digital input signal f (t). In this way, it is possible to calculate h (t, T) = f (t) −f (t−T), which is the amount of change in the input signal per time T.

比較部４２は、減算部４１のデジタル出力信号と所定の閾値ＴＨとを比較する。比較部４２は、減算部４１のデジタル出力信号の値が閾値ＴＨを超えたとき、ローパスフィルタ２のスイッチＳＷ１を制御するための制御信号（フィルタ時定数変更フラグ）を“１”（Ｈｉｇｈ）にし、減算部４１のデジタル出力信号の値が閾値ＴＨ以下のとき、制御信号を“０”（Ｌｏｗ）にする。閾値ＴＨは、入力信号の二点間の差（ｆ（ｔ）−ｆ（ｔ−Ｔ）のとり得る最大値と、除去したいノイズの大きさとを考慮して予め設定しておけばよい。   The comparison unit 42 compares the digital output signal of the subtraction unit 41 with a predetermined threshold value TH. The comparison unit 42 sets the control signal (filter time constant change flag) for controlling the switch SW1 of the low-pass filter 2 to “1” (High) when the value of the digital output signal of the subtraction unit 41 exceeds the threshold value TH. The control signal is set to “0” (Low) when the value of the digital output signal of the subtractor 41 is equal to or less than the threshold value TH. The threshold value TH may be set in advance in consideration of the maximum value that the difference (f (t) −f (t−T) between two points of the input signal can take and the magnitude of the noise to be removed.

ローパスフィルタ２は、時定数を変えることができるアクティブフィルタとなっている。比較部４２から出力される制御信号が“１”になると、スイッチＳＷ１はオン状態となる。これにより、抵抗Ｒ１が短絡されるので、ローパスフィルタ２の時定数が小さくなる。比較部４２から出力される制御信号が“０”になると、スイッチＳＷ１はオフ状態となる。これにより、抵抗Ｒ１とＲ２とが直列に接続されるので、ローパスフィルタ２の時定数が大きくなる。   The low-pass filter 2 is an active filter that can change the time constant. When the control signal output from the comparison unit 42 is “1”, the switch SW1 is turned on. Thereby, since the resistor R1 is short-circuited, the time constant of the low-pass filter 2 is reduced. When the control signal output from the comparison unit 42 becomes “0”, the switch SW1 is turned off. Thereby, since the resistors R1 and R2 are connected in series, the time constant of the low-pass filter 2 is increased.

遅延部４０の遅延時間となる所定時間Ｔは、図１１に示すように入力信号ｆ（ｔ）の変化開始時点から、その変化の最終値（１００％）に対してＤ／Ａ変換回路の出力信号ｇ（ｔ）の値が所定の割合Ａ（例えば６３．２％あるいは９０％）に到達するまでの時間をＴとして予め設定しておけばよい。割合Ａは、Ｄ／Ａ変換回路の所望の性能に応じて設定すればよい。   The predetermined time T, which is the delay time of the delay unit 40, is output from the D / A conversion circuit with respect to the final value (100%) of the change from the change start time of the input signal f (t) as shown in FIG. The time until the value of the signal g (t) reaches a predetermined ratio A (for example, 63.2% or 90%) may be set in advance as T. The ratio A may be set according to the desired performance of the D / A conversion circuit.

本実施の形態では、ローパスフィルタ２の時定数によりＤ／Ａ変換回路の出力信号ｇ（ｔ）が入力信号ｆ（ｔ）に追従する速度と出力信号ｇ（ｔ）のリップルのレベルが決まり、この速度とリップルのレベルはトレードオフの関係にある。本実施の形態では、ローパスフィルタ２は例えばτ１＝１０ｍｓｅｃの時定数を基本としているが、一方で１ｍｓｅｃでの高速応答が必要になる場合もある。しかし、ローパスフィルタ２の時定数をτ２＝１ｍｓｅｃにすると、出力信号ｇ（ｔ）のリップルが大きくなってしまう。そこで、Ｔ＝１ｍｓｅｃ、Ａ＝６３．２％として、入力信号ｆ（ｔ）の急峻な変化に追従可能な高速応答モードを用意した。   In the present embodiment, the speed at which the output signal g (t) of the D / A converter circuit follows the input signal f (t) and the ripple level of the output signal g (t) are determined by the time constant of the low-pass filter 2. This speed and the level of ripple are in a trade-off relationship. In the present embodiment, the low-pass filter 2 is based on a time constant of τ1 = 10 msec, for example, but on the other hand, a high-speed response at 1 msec may be required. However, when the time constant of the low-pass filter 2 is set to τ2 = 1 msec, the ripple of the output signal g (t) becomes large. Therefore, a high-speed response mode capable of following a steep change in the input signal f (t) was prepared with T = 1 msec and A = 63.2%.

本実施の形態によると、図１２に示すように入力信号ｆ（ｔ）が変化したときに、変化量ｈ（ｔ，Ｔ）が閾値ＴＨを超えたｔ１時点で、ローパスフィルタ２の時定数が例えばτ１＝１０ｍｓｅｃからτ２＝１ｍｓｅｃ（スイッチＳＷ１オン）に変更され、出力信号ｇ（ｔ）が入力信号ｆ（ｔ）に対して割合Ａ＝６３．２％まで到達したｔ２時点で、ローパスフィルタ２の時定数がτ２＝１ｍｓｅｃからτ１＝１０ｍｓｅｃ（スイッチＳＷ１オフ）に変更されるという動作になる。   According to the present embodiment, when the input signal f (t) changes as shown in FIG. 12, the time constant of the low-pass filter 2 is changed at time t1 when the change amount h (t, T) exceeds the threshold value TH. For example, when the output signal g (t) is changed from τ1 = 10 msec to τ2 = 1 msec (switch SW1 ON) and the output signal g (t) reaches the ratio A = 63.2% with respect to the input signal f (t), the low-pass filter 2 Is changed from τ2 = 1 msec to τ1 = 10 msec (switch SW1 off).

図１３は本実施の形態のＤ／Ａ変換回路の応答の実測結果を示す波形図である。図１３の１３０はローパスフィルタ２の時定数を１ｍｓｅｃに固定したときのＤ／Ａ変換回路の出力信号ｇ（ｔ）を示し、１３１はローパスフィルタ２の時定数を１０ｍｓｅｃに固定したときのＤ／Ａ変換回路の出力信号ｇ（ｔ）を示し、１３２は本実施の形態のＤ／Ａ変換回路の出力信号ｇ（ｔ）を示している。   FIG. 13 is a waveform diagram showing an actual measurement result of the response of the D / A conversion circuit of the present embodiment. 13 shows an output signal g (t) of the D / A conversion circuit when the time constant of the low-pass filter 2 is fixed at 1 msec, and 131 shows the D / A when the time constant of the low-pass filter 2 is fixed at 10 msec. The output signal g (t) of the A conversion circuit is shown, and 132 shows the output signal g (t) of the D / A conversion circuit of the present embodiment.

図１３から明らかなように、ローパスフィルタ２の時定数を小さくすると出力信号ｇ（ｔ）にリップルが大きく出てしまう。そこで、入力信号ｆ（ｔ）の変化に追従している間だけローパスフィルタ２の時定数を小さくしたいが、入力信号ｆ（ｔ）の変化の瞬間だけ時定数を小さくしても不十分になる。そこで、本実施の形態では、入力信号ｆ（ｔ）の変化量ｈ（ｔ，Ｔ）を演算し、変化量ｈ（ｔ，Ｔ）が閾値ＴＨを超えている間だけローパスフィルタ２の時定数を小さくすることにより、充分な時定数変更の時間を実現した。   As is apparent from FIG. 13, when the time constant of the low-pass filter 2 is reduced, a large ripple appears in the output signal g (t). Therefore, it is desired to reduce the time constant of the low-pass filter 2 only while following the change of the input signal f (t), but it is not sufficient to reduce the time constant only at the moment of change of the input signal f (t). . Therefore, in this embodiment, the amount of change h (t, T) of the input signal f (t) is calculated, and the time constant of the low-pass filter 2 is only while the amount of change h (t, T) exceeds the threshold value TH. A sufficient time constant change time has been realized by reducing.

本実施の形態では、出力のリップル低減を、図１９に示したようなタイマを使用せずに実現することが出来るので、集積回路へのＤ／Ａ変換回路の実装を容易にすることができる。   In the present embodiment, output ripple can be reduced without using a timer as shown in FIG. 19, so that the D / A conversion circuit can be easily mounted on the integrated circuit. .

なお、本実施の形態では、ローパスフィルタ２の例として１次のフィルタを例に挙げて説明しているが、これに限るものではなく、例えば１次のフィルタを複数段縦続接続した高次のフィルタ等の他のフィルタに本発明を適用してもよい。   In the present embodiment, the first-order filter is described as an example of the low-pass filter 2. However, the present invention is not limited to this. For example, a high-order filter in which a plurality of primary filters are cascade-connected. The present invention may be applied to other filters such as a filter.

また、本実施の形態では、Ｄ／Ａ変換回路に適用する例で説明しているが、本発明のフィルタ時定数変更回路４をＡ／Ｄ変換回路の入力部に適用してもよい。この場合は、アナログ入力信号ｆ（ｔ）をローパスフィルタ２に入力し、ローパスフィルタ２の出力信号をＡ／Ｄ変換回路に入力すればよい。フィルタ時定数変更回路４は、アナログ回路で構成される。遅延部４０の例としては、例えばＣＣＤ（Charge-Coupled Device）がある。   In the present embodiment, the example applied to the D / A conversion circuit is described. However, the filter time constant changing circuit 4 of the present invention may be applied to the input unit of the A / D conversion circuit. In this case, the analog input signal f (t) may be input to the low pass filter 2 and the output signal of the low pass filter 2 may be input to the A / D conversion circuit. The filter time constant changing circuit 4 is composed of an analog circuit. An example of the delay unit 40 is a CCD (Charge-Coupled Device), for example.

本発明は、入力信号に応じてフィルタの時定数を変更する技術に適用することができる。   The present invention can be applied to a technique for changing the time constant of a filter in accordance with an input signal.

１…Ｄ／Ａ変換部、２…ローパスフィルタ、３…バッファ回路、４…フィルタ時定数変更回路、４０…遅延部、４１…減算部、４２…比較部、Ｒ１，Ｒ２…抵抗、Ｃ１…コンデンサ、ＳＷ１…スイッチ。   DESCRIPTION OF SYMBOLS 1 ... D / A conversion part, 2 ... Low pass filter, 3 ... Buffer circuit, 4 ... Filter time constant change circuit, 40 ... Delay part, 41 ... Subtraction part, 42 ... Comparison part, R1, R2 ... Resistance, C1 ... Capacitor , SW1 ... switch.

Claims (4)

入力信号をフィルタリングするためのフィルタの時定数を決定するフィルタ時定数変更回路において、
現時点の前記入力信号の値ｆ（ｔ）と現時点からＴ時間前の入力信号の値ｆ（ｔ−Ｔ）とから得られる所定時間Ｔあたりの変化量ｈ（ｔ，Ｔ）＝ｆ（ｔ）−ｆ（ｔ−Ｔ）を演算する変化量演算部と、
前記変化量ｈ（ｔ，Ｔ）と所定の閾値との比較結果に基づいて前記フィルタの時定数を制御する制御信号を出力する比較部とを備えることを特徴とするフィルタ時定数変更回路。 In the filter time constant changing circuit for determining the filter time constant for filtering the input signal,
A change amount h (t, T) per predetermined time T obtained from the current value f (t) of the input signal and the value f (t−T) of the input signal T time before the current time = f (t) A change amount calculation unit for calculating −f (t−T);
A filter time constant changing circuit comprising: a comparison unit that outputs a control signal for controlling a time constant of the filter based on a comparison result between the change amount h (t, T) and a predetermined threshold value. 請求項１記載のフィルタ時定数変更回路において、
前記比較部は、前記変化量ｈ（ｔ，Ｔ）が前記閾値以下の場合に前記フィルタの時定数を第１のフィルタ時定数τ１とする制御信号を出力し、前記変化量ｈ（ｔ，Ｔ）が前記閾値を超える場合に前記フィルタの時定数を前記第１のフィルタ時定数τ１よりも小さい第２のフィルタ時定数τ２に変更する制御信号を出力することを特徴とするフィルタ時定数変更回路。 The filter time constant changing circuit according to claim 1,
The comparison unit outputs a control signal that sets the time constant of the filter as a first filter time constant τ1 when the change amount h (t, T) is equal to or less than the threshold value, and the change amount h (t, T ) Exceeds the threshold value, a control signal for changing the filter time constant to a second filter time constant τ2 smaller than the first filter time constant τ1 is output. . 請求項２記載のフィルタ時定数変更回路において、
前記所定時間Ｔは、前記入力信号の変化開始時点から、前記第２のフィルタ時定数τ２において、その変化の最終値に対して前記フィルタの出力信号の値が所定の割合に到達するまでの時間であることを特徴とするフィルタ時定数変更回路。 The filter time constant changing circuit according to claim 2,
The predetermined time T is the time from when the input signal starts to change until the value of the output signal of the filter reaches a predetermined ratio with respect to the final value of the change in the second filter time constant τ2. A filter time constant changing circuit characterized by the above. デジタル入力信号をアナログ信号に変換するＤ／Ａ変換部と、
このＤ／Ａ変換部の出力信号を平滑化するフィルタと、
前記デジタル入力信号を入力とし、前記フィルタの時定数を制御する制御信号を出力する、請求項１乃至３のいずれか１項に記載のフィルタ時定数変更回路とを備えることを特徴とするＤ／Ａ変換回路。 A D / A converter for converting a digital input signal into an analog signal;
A filter for smoothing the output signal of the D / A converter;
4. A filter time constant changing circuit according to claim 1, comprising: the digital input signal as an input, and a control signal for controlling a time constant of the filter being output. 5. A conversion circuit.
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