JP2003101413A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve responsiveness when switching digital setting data, to suppress ripple after switching and to enable stable output in a D/A converter for converting digital data to a PWM pulse and converting it to an analog voltage through a low-pass filter (LPF). SOLUTION: The PWM pulse outputted from the terminal of an ASIC 15 having the PWM pulse generating circuit (composed of a counter and a comparator) of a duty ratio corresponding to the digital setting data is inputted after selecting any one of a plurality of different LPF (with R1C and R2C as a time constant) by an SW. When switching the digital setting data, the filter of the small time constant is selected and the response of analog output is accelerated. After the lapse of prescribed time, the filter of the large time constant is selected as ordinary operation and a ripple voltage generated in the output is suppressed.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to digital data.
The present invention relates to a DA converter that converts a PWM (pulse width modulation) pulse and outputs an analog voltage through a low pass filter.

[0002]

[Prior Art] Converting digital data into PWM pulse,
A DA (digital / analog) converter that outputs an analog voltage through a low-pass filter has been conventionally known. FIG. 4 shows a general example of this type of DA converter. As shown in FIG. 4, a counter 11 and a comparator 12 each having the same number of bits as the resolution of the DA converter to be realized (8 bits in this example) are provided.
The setting digital data DSET having the same number of bits (8 bits) corresponding to the analog (voltage) level to be output is applied to the two input terminals A0 to A7. Counter 11 is a master clock MC
LK is always counted, and the counter values Q0 to Q7 are output to the input terminals B0 to B7 of the comparator 12. In case of 8bit, 256 clocks is 1 cycle. The comparator 12 is
When DSET> counter value, the output pulse is set to high (hereinafter referred to as “H”) level, and when DSET ≦ counter value, it is set to low (hereinafter referred to as “L”) level. Therefore, as a result of the comparison, a pulse signal Vpwm = H having a pulse width corresponding to the setting data DSET is output. That is, as shown in FIG. 5, it has a cycle of 256 × Tmclk and outputs a pulse having a duty ratio according to DSET. The output signal Vpwm is the resistance R,
Smoothed by RC low pass filter by capacitor C, analog voltage Vd of level according to setting data DSET
ac is output.

In the examples of FIGS. 4 and 5, the relationship between the analog voltage Vdac and the set value DSET can be expressed by the following equation. Vdac = (DSET / 256) × (Vh-Vl) ＋ Vl where Vh: Vpwm = H output voltage Vl: Vpwm = L output voltage At this time, when Vpwm rises and falls H and L, , Vdac
Ripples occur. That is, Vdac change at Vpwm = H output is {Vh−Vdac (0)} × {1−exp (−Th / τ)} Vpwm = Vdac change at L output is {Vl−Vdac (1)} × {1−exp (−Th / τ)} where Vdac (0): Vdac immediately before Vpwm = H Vdac (1): Vdac τ just before Vpwm = L: time constant of RC filter In the case of T (Th + Tl), the ripple shows the maximum value when Th = Tl.

As described above, the DA converter using PWM has the merit that it is cheaper than a general analog DA converter, but since the PWM pulse signal is smoothed into an analog voltage, It has a demerit that ripple occurs in the analog voltage output. In order to reduce this demerit ripple, the time constant of the RC filter that smoothes the PWM pulse signal may be increased, but as the time constant of the RC filter is increased, the response speed of the analog output voltage becomes slower. There is a problem of becoming. Therefore, a method for reducing the ripple without changing the time constant of the RC filter has been proposed (actual Kaihei 6-132).
31 publication). Here, in order to reduce the ripple, a method of reducing the ripple by dividing the high level period and the low level period in one cycle of the PWM pulse signal into a plurality of periods is adopted. FIG. 6 shows an example of this period division. The high-level period and the low-level period in one cycle of the PWM pulse signal are divided into four states (the lower stage in the figure) from the non-divided state (the upper stage in the figure). )
To output. Dividing in this way shortens the high-level period and the low-level period, so Vdac
The change is small and the ripple is small.

[0005]

However, the method of dividing the high level period and the low level period in one cycle of the PWM pulse signal into a plurality of periods has a certain effectiveness in reducing the ripple, but is actually used. In the device, PW
The speed of the master clock that generates the M pulse signal (corresponding to the master clock MCLK in FIG. 4) is limited, and the number of high-level periods and low-level periods in one cycle divided into multiple periods is also limited. , It is difficult to get enough results. Further, this method can increase the response speed by reducing the time constant of the RC filter, but this method also has a limit, and if the response speed is still insufficient,
In particular, the response may not be sufficient when switching the digital data converted to analog. The present invention relates to a conventional DA converter having a low-pass filter that converts digital data converted into an analog voltage into a high-level and low-level pulse signal having a duty ratio corresponding to the value and inputs the pulse signal. The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide the DA converter which has good responsiveness at the time of switching a digital value converted into analog, and which can suppress ripples after switching and provide stable output. To do.

[0006]

According to a first aspect of the present invention, there is provided means for converting digital data converted into an analog voltage into pulse signals of high level and low level having a duty ratio corresponding to the value, and the pulse signal. A DA converter comprising: a plurality of different low-pass filters each of which has an input and a switch for turning on / off the input of the pulse signal to the plurality of low-pass filters for selecting an analog output voltage. .

According to a second aspect of the present invention, in the DA converter according to the first aspect, the pulse signal is a 3-state output.

According to a third aspect of the present invention, in the DA converter according to the first or second aspect, the timing for turning on / off the switch is in the middle of a high level or low level period. is there.

According to a fourth aspect of the present invention, means for converting digital data converted into an analog voltage into pulse signals of high level and low level having a duty ratio according to the value,
Means for forcibly outputting a high-level or low-level pulse signal for a period corresponding to the change of the data at the time of switching the digital data, and a low-pass filter for receiving the pulse signal from the conversion means and the forced output means The DA converter is provided with a table of period data set corresponding to the change of the digital data.

According to a fifth aspect of the present invention, in the DA converter according to the fourth aspect, there is provided selection means for making the output period of the forced output means and the time constant of the low pass filter have a predetermined relationship. It is a feature.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described based on the following embodiments shown in the accompanying drawings. Here, the response when switching the digital value converted to analog is good,
Stable output by suppressing ripple after switching D
The A converter is solved by the first and second inventions, and embodiments of the respective inventions will be shown below. FIG. 1 shows a DA converter according to an embodiment of the first invention. The DA converter of the present embodiment is different from the conventional DA converter in that it has means for converting digital data converted into an analog voltage into high-level and low-level PWM pulse signals having a duty ratio corresponding to the value. There is no change. In the example shown in FIG.
The circuit that outputs the PWM pulse signal is in the ASIC 15, and the specific configuration is the pulse signal Vpwm shown in FIG. 4 described above.
Can be configured by the same means as the circuit for generating (a circuit including the counter 11 and the comparator 12). ASIC1
The pulse signal output from the terminal 5 is configured to be input by selecting a plurality of different low-pass filters, that is, filter circuits having time constants R1C and R2C by SW. The time constant of the R1C filter circuit of the pulse signal PWM1 is set large, and the time constant of the R2C filter circuit of the pulse signal PWM2 is set small.

When operating in a state (steady state) in which the digital setting data of the PWM signal output circuit (data is changed by setting) does not change (steady state), only the pulse signal PWM1 is output from the ASIC 15 and the pulse signal PWM2 Terminal is Hi-Z
State. In this state, the time constant of the low-pass filter is large, so that the ripple voltage generated at the output can be suppressed. When the digital setting data is changed, the PWM1 pin is set to the Hi-Z state and the PWM2 pin is set to the output state. In this state, since the time constant of the low pass filter is small, the ripple voltage becomes large, but the response of the analog output voltage can be speeded up. After a predetermined time has passed from the SW operation for selecting a filter with a small time constant,
Set the PWM1 pin to the output state and return the PWM2 pin to the Hi-Z state to increase the time constant. In addition, it is desirable to set the time for the analog voltage to respond sufficiently from the time constant of PWM2 for the time to return the output state, and it is desirable to be able to freely change the set time. Make it happen. In the above method, it is possible to set the time constant of PWM1 to a large value so that the required ripple voltage can be obtained, and to set the time constant of PWM2 to a small value so that the required response speed of the analog voltage can be obtained. . With such a setting, the response speed at the time of changing the digital setting data is fast, and the analog voltage waveform has a small ripple in the steady state.

Further, since the ripple voltage is generated in the ± direction with respect to the analog output voltage and the difference between the average analog voltage and the change timing of H⇔L of the pulse signal is large, the ON / OFF switching of the SW is performed. To reduce the step of the analog voltage and reduce the difference between the average analog voltage immediately after increasing the time constant of the low-pass filter and the analog voltage according to the digital setting data, the output switching is
It is better to do it in the central part of the H and L periods. Figure 2 shows such PWM
FIG. 3 is a diagram for explaining the switching timing of the PWM2 signal output. In the example shown in the figure, switching is performed in the central portion of the H period, and the state in which the duty ratio of the pulse is changed after switching is shown. In addition, you may make it perform in the central part of L period. The PWM1 and PWM2 signals may be different signals or the same signal, and can be arbitrarily changed according to the conversion characteristics to be obtained.

Next, a DA converter according to the second embodiment of the invention will be described. FIG. 3 shows a DA converter according to an embodiment of the second invention. The DA converter of the present embodiment is also different from the conventional DA converter in that it has means for converting the digital data converted into the analog voltage into the high-level and low-level PWM pulse signals having the duty ratio according to the value. There is no change. In the example shown in FIG. 3, the circuit that outputs the PWM pulse signal is in the ASIC 15, and the specific configuration is
It can be configured by the same means as the circuit (the circuit including the counter 11 and the comparator 12) for generating the pulse signal Vpwm shown in FIG. The pulse signal PWM1 output from the terminal of the ASIC 15 is configured to be input to a low-pass filter, that is, a filter circuit having R1C as a time constant. Here, the time constant R1C of the low-pass filter that smoothes the pulse signal PWM1 is set to a large value. Since the time constant R1C of the low pass filter is set large,
The ripple voltage generated at the output is small. However, with this low-pass filter, as described above, the responsiveness becomes poor when the digital setting data converted into analog is switched.

Therefore, in this example, in the control unit for generating the pulse signal PWM1 in the ASIC 15, the operation in the steady state, that is, the digital setting data does not change during the predetermined period at the time of switching, and the duty ratio corresponding to the setting data is changed. The operation is changed from the operation in which the PWM pulse signal is output to the operation state in which one of the H and L signals is forcibly output as PWM1 to prevent deterioration of responsiveness. In other words, when changing the digital setting data and increasing the setting data,
When H is decreased, L is forcibly output for a predetermined period. By the way, the analog voltage when outputting H and L changes with an exponential function that uses the time constant as a function, and the potential difference between the analog voltage corresponding to the setting data before the change and the driving voltage of H or L,
The driving time determines the time required for the analog voltage to reach the voltage corresponding to the changed setting data. Therefore, the above-mentioned predetermined period (the period in which Hor L is forcibly output) for achieving the desired response time is the known time constant, the data before change,
It can be determined by ascertaining how many cycles of MCLK the H or L should be output from the changed data. As an example, prepare the data of the H or L output period (number of MCLK cycles) for the time constant, pre-change data, and post-change data as Table data, and refer to the Table data during operation to set the H Outputs or L.

Now, another embodiment according to the second invention will be described. As the embodiment according to the second invention, the PWM signal having one terminal as shown in FIG. 3 has been illustrated above. By the way, when the PWM signal has one terminal, the time constant is determined from the ripple voltage obtained in the steady state, and the time constant is fixed at this value. Therefore, refer to the table data used to set the forced drive time. The time constant is also fixed. In such a configuration, if MCLK is changed, Ta
Since the forced drive time obtained from the ble data is given by the number of MCLK cycles, the forced drive time is inconsistent. Therefore, separate the terminals, one terminal for the low-pass filter with the time constant set to suppress the ripple voltage generated during steady state to the desired value, and the other terminal for H or L forced drive. The terminal for which the time constant of can be set.
This structure can be implemented by the same structure as the low-pass filter having two terminals to be selected in the AD converter shown in FIG. The time constant set during H or L forced drive is determined so that the time ratio between this time constant and the new MCLK cycle after the change is constant. In this way, even if MCLK is changed, Ta used for setting the forced drive time
The ble data does not need to be changed, and it can be used universally in devices with different MCLK conditions. As described above, also in the second aspect of the invention, it is possible to provide a DA converter that has a good responsiveness even when the digital value converted to analog is switched, suppresses ripples after switching, and is capable of stable output.

[0017]

(1) Effect corresponding to the invention of claim 1 At the time of switching the digital setting data converted into the analog voltage, the PWM pulse signal input is turned on / off by the switch, so that the time constant is small. Select a low-pass filter so that the ripple is large but the response speed of the analog voltage is fast, and after a predetermined period of responding to the analog voltage according to the digital setting data, select a low-pass filter with a large time constant again to By reducing the number of states, it is possible to improve the performance when used in a device that requires both operating states. (2) Effect corresponding to the invention of claim 2 In addition to the effect of (1) above, by implementing the switch for turning on / off the input of the PWM pulse signal with the 3-state output of the pulse signal, the DA conversion is inexpensively performed. It becomes possible to provide a container. (3) Effect corresponding to the invention of claim 3 In addition to the effects of (1) and (2) above, by performing on / off by a switch of the PWM pulse signal input at a timing midway between high level and low level, Stabilize the characteristics by reducing the step of the analog voltage when switching the switch on / off and reducing the difference between the analog voltage immediately after the time constant of the RC filter was increased and the analog voltage according to the digital setting data. It will be possible.

(4) Effects corresponding to claims 4 and 5 When switching digital setting data converted into an analog voltage, a high-level or low-level pulse signal is forcibly forced for a period corresponding to the change in the data. Even if a low-pass filter with a small time constant is used to suppress the ripple in the steady state by outputting, the response speed of the analog voltage can be increased, so it was used for devices that require both operating states. It is possible to improve the performance at the time. Further, since the means for making the forced output period of the high-level or low-level pulse signal and the time constant of the low-pass filter have a predetermined relationship, the data consistency can be maintained even if the master clock is changed. , It becomes possible to give versatility.

[Brief description of drawings]

FIG. 1 shows a DA converter according to an embodiment of the first invention.

FIG. 2 is a diagram for explaining a switching timing of PWM pulse output.

FIG. 3 shows a DA converter according to an embodiment of the second invention.

FIG. 4 shows a general example of a DA converter that converts digital data into PWM pulses.

FIG. 5 shows a PWM pulse (comparator output Vpmw) having a duty ratio according to DSET.

FIG. 6 is a diagram for explaining a conventional PWM pulse division method for suppressing ripples.

[Explanation of symbols]

11 ... Counter, 12 ... Comparator, 15 ... ASIC C ... Capacitor, R, R1, R2 ... Resistor.

Claims (5)

[Claims] 1. A means for converting digital data converted into an analog voltage into pulse signals of high level and low level having a duty ratio according to the value, and a plurality of different low pass filters having the pulse signal as an input. A DA converter comprising a switch for turning on / off the input of the pulse signal to the plurality of low-pass filters in order to select an analog output voltage. 2. The DA converter according to claim 1, wherein the pulse signal is a 3-state output. 3. The DA converter according to claim 1, wherein the timing for turning on / off the switch is in the middle of a high level or low level period. 4. A means for converting digital data converted into an analog voltage into pulse signals of high level and low level having a duty ratio according to the value, and a period corresponding to the change of the data at the time of switching the digital data, Means for forcibly outputting a high-level or low-level pulse signal, a low-pass filter that receives the pulse signal from the conversion means and the forcible output means, and period data that is set in response to changes in the digital data DA converter characterized by having a table of. 5. The DA converter according to claim 4, further comprising selection means for making the output period of the forced output means and the time constant of the low-pass filter have a predetermined relationship. vessel.