JP2017146736A - Transmitting device and image forming apparatus including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitting device that reduces the size of a substrate without performing equal-length wiring and reduces an influence of a reflection wave, and an image forming apparatus including the same.SOLUTION: A transmitting device comprises: a device; a first DDR memory; a second DDR memory; a first signal line L1 that is a signal line from the device to a branch point; a second signal line L2 from the branch point to the second DDR memory; and a third signal line L3 from the branch point to the first DDR memory. The first signal line, second signal line, and third signal line have the lengths in which the relationship between a first propagation delay time A of the first signal line, a second propagation delay time B of the second signal line, and a third propagation delay time C of the third signal line satisfies any combination of combinations of specific formulas.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a transmission apparatus including a device and a plurality of DDR memories. The present invention also relates to an image forming apparatus including the transmission device.

  In a printed wiring board, a signal line may be branched into a plurality. A reflected wave may occur due to reflection at the branch destination of the signal line. Under the influence of the reflected wave (by overlapping the signal and one or more reflected waves), the waveform of the received signal may be disturbed. Therefore, Patent Document 1 below describes an example of a technique for suppressing the influence of reflection.

  Specifically, in Patent Document 1, a resistor R1 is disposed between the branch point and the first signal line, a resistor R2 is disposed between the branch point and the second signal line, and the branch point and the third signal line are arranged. A resistor R3 is arranged between the signal wires, and the relationship between the resistance element and the characteristic impedance of each signal wire is a matching condition when the signal propagates from the branch source signal wire to the branch point and each of the branched signal wires. A printed wiring board is described which satisfies both the matching condition when the signal is propagated by being reflected from the terminal and returning in the opposite direction. With this configuration, an attempt is made to keep the signal transmission waveform in a good waveform even if there is a branch point (see Patent Document 1: Abstract, Claim 1, Paragraph [0011], etc.).

JP 2001-084070 A

  On the substrate of the image forming apparatus, an integrated circuit such as a CPU and an ASIC and a RAM such as a DDR memory are mounted. For example, when a plurality of RAMs are mounted, signal lines from an integrated circuit that writes data to the RAM to the RAM may be branched, and the branched signal lines may be connected to the RAMs.

  Conventionally, in order to suppress the influence of reflection, wiring design has been made such that the signal lines from the branch point of the signal line to each RAM have the same length (equal length wiring). In the equal-length wiring, the shorter signal line among the signal lines from the branch point to each RAM is made equal to the longer signal line.

  Making the substrate small can reduce the manufacturing cost and lead to miniaturization of the image forming apparatus. Therefore, there is a problem that the substrate is desired to be smaller than before. The shorter the signal line, the easier it is to downsize the board. Therefore, it is conceivable to eliminate the isometric wiring and shorten each signal line in the substrate. However, when the equal length wiring is stopped, there is a problem that the influence of reflection becomes large.

  For example, when a reflected wave arrives at the terminal of the RAM overlapping with a change in signal potential, a large overshoot or undershoot occurs. For this reason, if the equal-length wiring is stopped, the potential of the RAM terminal may be outside the specified voltage range (appropriate input voltage range) due to the influence of the reflected wave, and may become an abnormal value.

  In the technique described in Patent Document 1, it is necessary to add a plurality of terminating resistors for reflecting wave attenuation. The addition of elements hinders the downsizing of the substrate. Therefore, the above problem cannot be solved.

  The present invention has been made in view of the above-described problems of the prior art, and reduces the influence of reflected waves while reducing the size of the substrate without performing equal-length wiring.

In order to solve the above problems, a transmission apparatus according to the present invention includes a device, a first DDR memory, a second DDR memory, a first signal line, a second signal line, and a third signal line. The first DDR memory exchanges signals with the device. The second DDR memory also exchanges signals with the device. The first signal line is a signal line from the device to a branch point. The second signal line is a signal line from the branch point to the second DDR memory. The third signal line is a signal line from the branch point to the first DDR memory. The first propagation delay time that is the propagation delay time of the first signal line is A, the second propagation delay time that is the propagation delay time of the second signal line is B, and the first propagation delay time is the propagation delay time of the third signal line. 3 Let C be the propagation delay time. Further, X is a time obtained by subtracting a predetermined margin time from the half cycle of the operation clock, and Y is a time obtained by adding the margin time to the half cycle of the operation clock. In the first signal line, the second signal line, and the third signal line, the relationship between the first propagation delay time, the second propagation delay time, and the third propagation delay time is expressed by the following three expressions: The length satisfying any one of the combinations.

  According to the present invention, each signal line is shifted so that the arrival timing of the reflected wave (the peak of the reflected wave) at the receiving terminal and the timing at which the change in the signal level at the transmitting terminal reaches the receiving terminal are shifted. The length of can be determined. Therefore, the influence of the reflected wave can be reduced without performing equal length wiring. And the board | substrate of a transmission apparatus or an image forming apparatus can be reduced in size, and manufacturing cost can be reduced.

1 is a diagram illustrating an example of a multifunction machine according to an embodiment. It is a figure which shows an example of the transmission apparatus which concerns on embodiment. It is a figure which shows an example of the dispersion | variation in the timing of the signal level change in ASIC which concerns on embodiment. It is a figure for demonstrating the setting of the length of the signal wire | line based on the 1st combination which concerns on embodiment. It is a figure for demonstrating the setting of the length of the signal wire | line based on the 2nd combination which concerns on embodiment. It is a figure for demonstrating the setting of the length of the signal wire | line based on the 3rd combination which concerns on embodiment.

  Hereinafter, an image forming apparatus including the transmission apparatus 1 according to the present invention will be described with reference to FIGS. The multifunction peripheral 100 will be described as an example of the image forming apparatus. However, each element such as the configuration and arrangement described in this embodiment does not limit the scope of the invention and is merely an illustrative example.

(Outline of image forming apparatus)
First, a multifunction peripheral 100 according to the embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of a multifunction peripheral 100 according to the embodiment.

  The multifunction device 100 includes a main control unit 2 (controller board). The main control unit 2 controls the operation of the entire apparatus and controls each unit of the multifunction peripheral 100. The main control unit 2 is provided with a CPU 21. The main control unit 2 is mounted with an ASIC 22 (corresponding to a device) that performs image processing necessary for printing, and a ROM 23 that stores a control program and data. The main control unit 2 is provided with a first DDR memory 6 and a second DDR memory 7 as RAM.

  The main control unit 2 is connected to the image reading unit 3 so as to be communicable. The image reading unit 3 reads a document and generates image data. The main control unit 2 controls the operation of the image reading unit 3. The main control unit 2 is connected to the operation panel 4 so as to be communicable. The operation panel 4 displays a setting screen, the status of the multifunction peripheral 100, and a message. In addition, the operation panel 4 accepts a user operation on a touch panel and hard keys provided on the operation panel 4. Then, the main control unit 2 recognizes the setting operation content performed on the operation panel 4. Then, the main control unit 2 controls the multifunction device 100 so as to operate according to the user's setting.

  The multifunction device 100 includes a printing unit 5. The printing unit 5 includes an engine control unit 50, a paper feeding unit 5a, a conveying unit 5b, an image forming unit 5c, and a fixing unit 5d. The engine control unit 50 actually controls printing-related processes such as paper feeding, paper conveyance, toner image formation, transfer, and fixing. The engine control unit 50 and the main control unit 2 are connected to be communicable. The main control unit 2 gives the engine control unit 50 a print instruction, the contents of the print job, and image data used for printing. Based on the received content, the engine control unit 50 controls the paper feeding unit 5a, the conveyance unit 5b, the image forming unit 5c, and the fixing unit 5d. Specifically, various types of rotating bodies related to paper feeding, conveyance, image formation, transfer, and fixing are rotated to control printing.

  The engine control unit 50 supplies sheets one by one to the sheet feeding unit 5a. The engine control unit 50 transports the supplied paper to the transport unit 5b through the image forming unit 5c and the fixing unit 5d to a discharge tray (not shown). The engine control unit 50 causes the image forming unit 5c to form a toner image to be placed on the sheet conveyed by the conveyance unit 5b. Further, the engine control unit 50 fixes the toner image transferred onto the sheet to the fixing unit 5d. The conveyance unit 5b discharges the sheet on which the toner image is fixed to the discharge tray.

  The multifunction device 100 includes a communication unit 24. The communication unit 24 is an interface for connecting to a network. Thereby, the main control part 2 can communicate via a network. The communication unit 24 receives printing data including data indicating printing contents such as image data and data indicating settings relating to printing from the computer 200. The main control unit 2 causes the printing unit 5 to perform printing based on the printing data.

(Transmission device 1)
Next, an example of the transmission apparatus 1 according to the embodiment will be described with reference to FIG. FIG. 2 is a diagram illustrating an example of the transmission apparatus 1 according to the embodiment.

  The main control unit 2 is provided with a first DDR memory 6 (DDR memory chip) and a second DDR memory 7 (DDR memory chip). The device that communicates with the first DDR memory 6 and the second DDR memory 7 is an ASIC 22. In the following description, the ASIC 22 will be described as an example of the device. The device may be the CPU 21. For example, the ASIC 22 stores the image data after image processing in the first DDR memory 6 and the second DDR memory 7.

  The first DDR memory 6 is mounted on the controller board. The memory chip of the second DDR memory 7 is included in a memory module substrate 71 (DIMM substrate) attached to a socket 72 provided on the substrate. In the multi-function device 100, the RAM can be expanded by inserting the memory module substrate 71 into an open (unused) socket 72. For example, the first DDR memory 6 and the second DDR memory 7 are 32-bit DDR3 memories.

  FIG. 2 shows an example of the wiring topology of the transmission apparatus 1 (ASIC 22, first DDR memory 6, and second DDR memory 7). The ASIC 22, the first DDR memory 6 and the second DDR memory 7 are connected by a signal line. A signal line from the ASIC 22 is branched at a branch point P and connected to the first DDR memory 6 and the second DDR memory 7. Specifically, the transmission apparatus 1 includes a first signal line L1 that is a signal line from the ASIC 22 to the branch point P, a second signal line L2 from the branch point P to the second DDR memory 7, and a first DDR from the branch point P. And a third signal line L3 to the memory 6.

  In FIG. 2, the first signal line L1, the second signal line L2, and the third signal line L3 are shown one by one for convenience. The ASIC 22 and each DDR memory exchange a plurality of types of signals such as a multi-bit DQ signal (data signal) and a DQS signal (data strobe signal). Therefore, there are actually a plurality of combinations of the first signal line L1, the second signal line L2, and the third signal line L3.

(Reflected wave)
Next, the reflected wave in the transmission apparatus 1 according to the embodiment will be described with reference to FIG. In the following description, one of the combinations of the first signal line L1, the second signal line L2, and the third signal line L3 of the transmission apparatus 1 will be described as a representative example. In the following description, the ASIC 22 is described as the signal transmission side, and the first DDR memory 6 and the second DDR memory 7 are described as the signal reception side (writing of data to the RAM).

  The propagation delay time of the first signal line L1 is the first propagation delay time A, the propagation delay time of the second signal line L2 is the second propagation delay time B, and the propagation delay time of the third signal line L3 is the third propagation delay time C. And When the potential of the terminal of the ASIC 22 is changed from the Low level to the High level, or from the High level to the Low level, the potential of the branch point P changes when the first propagation delay time A elapses from the change in the potential of the terminal of the ASIC 22. To do. The potential at the terminal of the first DDR memory 6 changes when the first propagation delay time A + the third propagation delay time C elapses. The potential of the terminal of the second DDR memory 7 changes when the first propagation delay time A + the second propagation delay time B has elapsed.

  Conventionally, when branching a signal line, wiring from the branch point P to the branch destination has been made equal in length in order to suppress the influence of reflection due to the signal. However, in order to reduce the size of the substrate, there is an increasing need to reduce the interface related to DDR and shorten the wiring. However, if the equal length wiring is broken (stopped), the influence of reflection increases.

  If the timing at which the signal level (potential) change of the transmitting terminal reaches the receiving terminal overlaps with the timing at which the reflected wave reaches the receiving terminal, overshoot and undershoot increase. Due to a large overshoot or undershoot, a voltage outside the specified range in the specification of the DDR memory may be input to the terminal of each DDR memory. Input to terminals with voltages outside the specified range may lead to failure.

  Each time reflection is repeated, the amplitude of the reflected wave decreases. For this reason, if the timing at which the reflected wave of one or two reflections reaches the receiving terminal overlaps with the timing at which the change in the level (potential) of the transmitting terminal reaches the receiving terminal, a large overshoot will occur. Shooting or undershooting may occur.

  In the wiring topology shown in FIG. 2, the path until the reflected wave of one reflection reaches the second DDR memory 7 is as follows: ASIC 22 → branch point P → first DDR memory 6 (reflection) → branch point P → second DDR memory 7. Become. The time from when the level of the terminal on the transmission side changes until the reflected wave of one-time reflection reaches the second DDR memory 7 is the first propagation delay time A (ASIC 22 to branch point P) + the third propagation delay time C. (Branch point P to first DDR memory 6) + third propagation delay time C (first DDR memory 6 to branch point P) + second propagation delay time B (branch point P + second DDR memory 7). In summary, the time from when the level of the terminal on the transmission side changes until the reflected wave of one reflection reaches the second DDR memory 7 is A + B + 2C.

  In the wiring topology shown in FIG. 2, the path until the first-type reflected wave of the second reflection reaches the second DDR memory 7 is ASIC 22 → the branch point P → the second DDR memory 7 (reflection) → the branch point P → the ASIC 22. (Reflection) → branch point P → second DDR memory 7 The time from when the level of the terminal on the transmission side changes until the first kind of reflected wave of the second reflection reaches the second DDR memory 7 is the first propagation delay time A (ASIC 22 to branch point P) + second Propagation delay time B (branch point P to second DDR memory 7) + second propagation delay time B (second DDR memory 7 to branch point P) + first propagation delay time A (branch point P to ASIC 22) + first propagation delay Time A (ASIC 22 to branch point P) → second propagation delay time B (branch point P to second DDR memory 7). In summary, the time from when the level of the terminal on the transmission side changes until the reflected wave of the first type of twice reflected reaches the second DDR memory 7 is 3A + 3B.

  In the wiring topology shown in FIG. 2, the path until the second-type reflected wave of the second reflection reaches the second DDR memory 7 is as follows: ASIC 22 → branch point P → second DDR memory 7 (reflection) → branch point P → second 1DDR memory 6 (reflection) → branch point P → second DDR memory 7 The time from when the level of the terminal on the transmission side changes until the second kind of reflected wave of the second reflection reaches the second DDR memory 7 is the first propagation delay time A (ASIC 22 to branch point P) + second Propagation delay time B (branch point P to second DDR memory 7) + second propagation delay time B (second DDR memory 7 to branch point P) + third propagation delay time C (branch point P to first DDR memory 6) + first 3 propagation delay time C (first DDR memory 6 to branch point P) → second propagation delay time B (branch point P to second DDR memory 7). In summary, the time from when the level of the terminal on the transmission side changes until the second kind of reflected wave of the second reflection reaches the second DDR memory 7 is A + 3B + 2C.

  In the transmission apparatus 1 of the present embodiment, no equal length wiring is performed. On the other hand, in order to avoid the influence of the reflected wave due to not performing the equal length wiring, the time (A + B + 2C, 3A + 3B, A + 3B + 2C) from the change in the signal level of the terminal on the transmission side until the reflected wave reaches the terminal on the reception side is set. Considering this, the lengths of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 for transmitting the DQ signal and the DQS signal are determined (details will be described later).

(Signal level change variation)
Next, the variation in the timing of the signal level change in the ASIC 22 according to the embodiment will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a variation in timing of a signal level change in the ASIC 22 according to the embodiment.

  First, in the exchange of data with the DDR memory, one bit of data is transmitted per half cycle of the operation clock per data signal line. In other words, data is transmitted and received at both the rising and falling timings of the operation clock. Thus, in the exchange of data with the DDR memory, the signal level of the data signal line changes once every half cycle depending on the case.

  Here, in DDR memory communication, the signal level does not always change at a constant value of a half cycle, but there is some variation at the time of change. As shown by a one-dot chain line in FIG. 3, the signal level may change earlier than a half cycle, or as shown by a two-dot chain line in FIG. 3, the signal level may change later than a half cycle. .

  When determining the lengths of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 so as to reduce the influence of the reflected wave, it is necessary to take into account timing variations when the signal level changes. . Specifically, in the transmission apparatus 1 of the present embodiment, it is assumed that the signal level change timing varies within a range of half cycle ± 6%. For example, when the operating frequency of the DDR memory is 400 MHz, half of 2500 ps per cycle is 1250 ps. At this time, the interval at which the signal level changes varies within the range of 1175 ps (1250 × 0.94) to 1325 ps (1250 × 1.06). And even if the interval at which the signal level changes varies, the timing at which the reflected wave reaches the receiving terminal does not overlap with the timing at which the change in the level (potential) of the transmitting terminal reaches the receiving terminal. The lengths of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 are determined.

(Setting of signal line length based on relational expression)
Next, the length of the signal line in the transmission apparatus 1 according to the embodiment will be described with reference to FIGS. FIG. 4 is a diagram for explaining the setting of the length of the signal line based on the first combination according to the embodiment. FIG. 5 is a diagram for explaining setting of the length of the signal line based on the second combination according to the embodiment. FIG. 6 is a diagram for explaining the setting of the signal line length based on the third combination according to the embodiment.

（第２の組み合わせ）

（第３の組み合わせ）

When the signal level change of the transmission side terminal (transmission side DQ terminal or DQS terminal) reaches the reception side terminal (reception side DQ terminal or DQS terminal), the reflected wave reaches the reception side terminal. The lengths of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 are determined so that the time points do not overlap. Specifically, the lengths of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 are determined so as to satisfy any one of the following three combinations. Each combination includes three equations. The first combination includes formulas (1) to (3). The second combination includes formulas (4) to (6). The third combination includes formulas (7) to (9).
(First combination)

(Second combination)

(Third combination)

  In each equation (1) to (9), A is the first propagation delay time, B is the second propagation delay time, and C is the third propagation delay time. X is a time (minimum change interval X, see FIG. 3) obtained by subtracting a predetermined margin time (6% of the half cycle) from the half cycle of the operation clock in consideration of variations in the change in signal level. Y is a time (maximum change interval Y, see FIG. 3) obtained by adding a predetermined margin time (6% of the half cycle) from the half cycle of the operation clock in consideration of the variation in the signal level.

  A + B + 2C, A + 3B + 2C, and 3A + 3B of each expression included in the combination start from the n-th time point (n is a positive integer; n = 1, 2,. ) And the time (total propagation delay time) until the reflected wave of the one-time reflection or the two-time reflection reaches the terminal on the receiving side.

A. Regarding the first combination (A + B) + X in the right term of the expressions (1) to (3) included in the first combination has a change in the signal level of the terminal on the transmission side at the minimum change interval X from the reference time point. (There is a change in the (n + 1) th signal level), and then indicates the time until the change in the (n + 1) th signal level reaches the terminal on the receiving side. In other words, the length from the reference time point to the arrival time point when the signal level change reaches the terminal on the receiving side at the earliest time point in the time zone that can be reached is shown.

  When the length of each signal line is determined based on the first combination, the change in the signal level of the (n + 1) th transmission side terminal reaches the reception side terminal (the change in the signal level reaches the reception side terminal). The reflected wave (A + B + 2C, A + 3B + 2C, 3A + 3B) generated by the change in the signal level of the (n-th) transmission-side terminal half a cycle ago reaches the reception-side terminal. Become.

  Here, a method for determining the lengths of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 will be described with reference to FIG. The first column in FIG. 4 shows an example of the frequency employed in the DDR3 memory. The second column shows the half period of each frequency. The third column shows a time (minimum change interval X) obtained by subtracting a predetermined margin time (6% of the half cycle) from the half cycle of the operation clock. The fourth column shows a time (maximum change interval Y) obtained by adding a predetermined margin time (6% of the half cycle) to the half cycle of the operation clock.

  The fifth column in FIG. 4 shows an example of the second propagation delay time B of the second signal line L2. The second DDR memory 7 is a DIMM board, and the wiring length in the DIMM board is fixed. Therefore, the second propagation delay time B is a fixed value. That is, the second propagation delay time B is determined based on the wiring length in the memory module substrate 71 including the propagation delay time in the socket 72. The second propagation delay time B varies depending on the byte lane, such as 130 ps to 190 ps. In order to confirm the value of the second propagation delay time B under the most severe conditions, the maximum value of 190 ps is used for the inequality related to X, and the minimum value of 130 ps is used for the inequality related to Y. In the example of FIG. 4 (first combination), the maximum value of 190 ps is used as the value of the second propagation delay time B in the expressions (2) and (3) regarding X.

（３）’の式に基づき、第１信号線Ｌ１は、第１伝搬遅延時間Ａが（Ｘ−２Ｂ）×１／２よりも小さくなる信号線の長さとする。また、（２）’の式に基づき、第３信号線Ｌ３は、第３伝搬遅延時間Ｃが（Ｘ−２Ｂ）×１／２よりも小さくなる信号線の長さとする。図４の第６列に各周波数での（Ｘ−２Ｂ）を、第７列に各周波数での（Ｘ−２Ｂ）×１／２を記載している。また、（１）’式も満たすように第３信号線Ｌ３の信号線の長さを定める必要がある。 Here, the formulas included in the first combination are organized as follows.

Based on the expression (3) ′, the first signal line L1 has a signal line length with which the first propagation delay time A is smaller than (X−2B) × ½. Further, based on the expression (2) ′, the third signal line L3 has a signal line length with which the third propagation delay time C is smaller than (X−2B) × ½. The (X-2B) at each frequency is described in the sixth column of FIG. 4, and (X-2B) × 1/2 at each frequency is described in the seventh column. Further, it is necessary to determine the length of the signal line of the third signal line L3 so as to satisfy the expression (1) ′.

  Here, the first signal line L1 has a length that should be physically secured. On the other hand, the first signal line L1 should not be too long from the viewpoint of substrate miniaturization. The length of the first signal line L1 is set such that the first propagation delay time A is longer than the delay time based on the physically minimum wiring length of the first signal line L1, and the first propagation delay time A is determined in advance. In order to make the length less than the first upper limit time, a condition is provided.

条件式１は、第１信号線Ｌ１を物理的に第１伝搬遅延時間Ａが１２０ｐｓとなる長さよりも長くする必要がある一方で、小型化のため、第１伝搬遅延時間Ａが４２０ｐｓよりも短くなる長さとすることを定めている。図４の第１０列に各周波数で（Ｘ−２Ｂ）×１／２で求められた値が、条件式１を満たすか否かを記載している。また、図４の第１１列には、式（３）’を満たし、かつ、条件式１を満たすＡの範囲を記載している。このＡの範囲内の第１伝搬遅延時間Ａとなるように、第１信号線Ｌ１の信号線の長さを定める。 For example, the condition for the first propagation delay time A can be determined as follows.

Conditional expression 1 requires that the first signal line L1 be physically longer than the length at which the first propagation delay time A is 120 ps, while the first propagation delay time A is less than 420 ps for miniaturization. The length is set to be shorter. The tenth column in FIG. 4 describes whether or not the value obtained by (X−2B) × ½ at each frequency satisfies the conditional expression 1. The eleventh column of FIG. 4 describes the range of A that satisfies the expression (3) ′ and satisfies the conditional expression 1. The length of the signal line of the first signal line L1 is determined so that the first propagation delay time A is within the range of A.

  In the example of FIG. 4, the first propagation delay time A is less than 104 ps and 933 MHz when the operating frequency of the DDR memory is 800 MHz based on the values of the expressions (3) ′ and (X−2B) × 1/2. In the case of 1066 MHz, it is necessary to be less than 30 ps. In these cases, Conditional Expression 1 (120 ps <A <420 ps) is not satisfied. Therefore, when the operating frequency of the DDR memory is 800 MHz, 933 MHz, and 1066 MHz, the line length of each signal line is not determined by the first combination.

  Further, the third signal line L3 has a length that should be physically secured at a minimum. On the other hand, the third signal line L3 should not be too long from the viewpoint of substrate miniaturization. That is, the length of the third signal line L3 is set so that the third propagation delay time C is longer than the delay time based on the physically minimum wiring length of the third signal line L3, and the third propagation delay time C is set in advance. A condition is provided to make the length less than the predetermined second upper limit time.

条件式２は、第３信号線Ｌ３を物理的に第３伝搬遅延時間Ｃが６０ｐｓとなる長さよりも長くする必要がある一方で、小型化のため、第３伝搬遅延時間Ｃが１３０ｐｓよりも短くなる長さとすることを定めている。さらに、小型化のため、第３伝搬遅延時間ＣをＤＩＭＭ基板の第２伝搬遅延時間Ｂの最小値未満とする（第３信号線の長さを第２信号線以下とする）。つまり、第３信号線Ｌ３は、第３伝搬遅延時間Ｃが６０ｐｓとなる長さよりも長くし、小型化のため、第３伝搬遅延時間Ｃが１３０ｐｓよりも短くなる長さとする。図４の第１２列に各周波数で（Ｘ−２Ｂ）×１／２で求められた値が、条件式２を満たすか否かを記載している。また、図４の第１３列には、式（２）’を満たし、かつ、条件式２を満たすＣの範囲を記載している。この範囲内の第３伝搬遅延時間Ｃとなるように、第３信号線Ｌ３の信号線の長さを定めればよい。 For example, the condition for the third propagation delay time C can be determined as follows.

Conditional expression 2 requires that the third signal line L3 be physically longer than the length at which the third propagation delay time C is 60 ps, while the third propagation delay time C is less than 130 ps for miniaturization. The length is set to be shorter. Further, in order to reduce the size, the third propagation delay time C is set to be shorter than the minimum value of the second propagation delay time B of the DIMM substrate (the length of the third signal line is set to be equal to or shorter than the second signal line). That is, the third signal line L3 is longer than the length at which the third propagation delay time C is 60 ps, and has a length at which the third propagation delay time C is shorter than 130 ps for miniaturization. The twelfth column of FIG. 4 describes whether or not the value obtained by (X−2B) × ½ at each frequency satisfies the conditional expression 2. Further, the 13th column of FIG. 4 describes a range of C that satisfies Expression (2) ′ and satisfies Conditional Expression 2. What is necessary is just to determine the length of the signal line of the 3rd signal line L3 so that it may become the 3rd propagation delay time C in this range.

B. Regarding the second combination (A + B) + X in the right term of the expressions (4) and (5) included in the second combination changes from the reference time point to the signal level of the terminal on the transmission side at the minimum change interval X. Yes (there is a change in the (n + 1) th signal level), and then indicates the time until the change in the (n + 1) th signal level reaches the terminal on the receiving side. In other words, the length from the reference time point to the arrival time point when the signal level change reaches the receiving terminal at the earliest time point in the reachable time zone is shown.

  When the length of each signal line is determined based on the second combination, the (nth) transmission side half a cycle before the change in the signal level of the (n + 1) th transmission side terminal reaches the reception side terminal. Among the reflected waves generated by the change in the signal level at the terminal, the reflected waves of A + B + 2C and A + 3B + 2C reach the terminal on the receiving side.

  On the other hand, (A + B) + Y in the right term of Expression (6) included in the second combination has a change in the signal level of the terminal on the transmission side at the maximum change interval Y from the reference time (n + 1th signal level). After that, the time until the (n + 1) th signal level change arrives at the receiving terminal is shown. In other words, the length from the reference time point to the arrival time point when the signal level change reaches the terminal on the receiving side at the latest time point in the reachable time zone is shown.

  If the length of each signal line is determined based on the second combination, after the signal level change of the transmission side terminal reaches the reception side terminal (the possibility that the signal level change reaches the reception side terminal) After a certain period of time, a reflected wave of 3A + 3B generated by a change in the signal level of the (n-th) transmission-side terminal half a cycle before reaches the reception-side terminal.

  A method for determining the length of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 based on the second combination will be described with reference to FIG. The first column in FIG. 5 shows an example of the frequency employed in the DDR3 memory. The second column shows the half period of each frequency. The third column shows a time (minimum change interval X) obtained by subtracting a predetermined margin time (6% of the half cycle) from the half cycle of the operation clock. The fourth column shows the time (maximum change interval Y) obtained by adding a predetermined margin time (6% of the half cycle) from the half cycle of the operation clock.

  The fifth column in FIG. 5 shows an example of the second propagation delay time B of the second signal line L2 determined by the second DDR memory 7. The second propagation delay time B varies from 130 ps to 190 ps depending on the byte lane. In the example of FIG. 5 (second combination), the value of the second propagation delay time B in Expression (5) relating to X uses the maximum value of 190 ps, and the second propagation delay time in Expression (6) relating to Y is used. The value of B uses a minimum value of 130 ps.

（６）’の式に基づき、第１信号線Ｌ１は、第１伝搬遅延時間Ａが（Ｙ−２Ｂ）×１／２よりも大きくなる信号線の長さとする。また、（５）’の式に基づき、第３信号線Ｌ３は、第３伝搬遅延時間Ｃが（Ｘ−２Ｂ）×１／２よりも小さくなる信号線の長さとする。図５の第６列に各周波数での（Ｘ−２Ｂ）を、第７列に各周波数での（Ｘ−２Ｂ）×１／２を記載している。図５の第８列に各周波数での（Ｙ−２Ｂ）を、第９列に各周波数での（Ｙ−２Ｂ）×１／２を記載している。また、（４）’式も満たすように第３信号線Ｌ３の信号線の長さを定める必要がある。 Here, the formulas included in the second combination are organized as follows.

Based on the expression (6) ′, the first signal line L1 has a signal line length that makes the first propagation delay time A longer than (Y−2B) × ½. Further, based on the expression (5) ′, the third signal line L3 has a signal line length with which the third propagation delay time C is smaller than (X−2B) × ½. The (X-2B) at each frequency is described in the sixth column of FIG. 5, and (X-2B) × 1/2 at each frequency is described in the seventh column. In FIG. 5, (Y−2B) at each frequency is described in the eighth column, and (Y−2B) × ½ at each frequency is described in the ninth column. Further, it is necessary to determine the length of the signal line of the third signal line L3 so as to satisfy the expression (4) ′.

  Even in the second combination, the first signal line L1 has a first propagation delay time A longer than the delay time based on the physically minimum wiring length of the first signal line L1. Conditions are provided so that A is a length that is less than a predetermined first upper limit time.

条件式１は、第２の組み合わせの場合でも、第１信号線Ｌ１を物理的に第１伝搬遅延時間Ａが１２０ｐｓとなる長さよりも長くする必要がある一方で、小型化のため、第１伝搬遅延時間Ａが４２０ｐｓよりも短くなる長さとすることを定めている。図５の第１０列に各周波数で（Ｙ−２Ｂ）×１／２で求められた値が、条件式１を満たすか否かを記載している。また、図５の第１１列には、式（６）’を満たし、かつ、条件式１を満たすＡの範囲を記載している。各周波数において、図５に示すＡの範囲内の第１伝搬遅延時間Ａとなるように、第１信号線Ｌ１の信号線の長さを定めればよい。 When the length of the signal line is determined by the second combination, the same condition as that of the first combination shown below can be given.

Conditional expression 1 requires that the first signal line L1 be physically longer than the length at which the first propagation delay time A is 120 ps even in the second combination. It is defined that the propagation delay time A has a length shorter than 420 ps. The tenth column in FIG. 5 describes whether or not the value obtained by (Y−2B) × ½ at each frequency satisfies the conditional expression 1. The eleventh column in FIG. 5 describes the range of A that satisfies Expression (6) ′ and satisfies Conditional Expression 1. What is necessary is just to determine the length of the signal line of the 1st signal line L1 so that it may become the 1st propagation delay time A in the range of A shown in FIG. 5 in each frequency.

  In the example of FIG. 5, when the operating frequency of the DDR memory is 400 MHz, the first propagation delay time A needs to be 533 ps or more based on the values of Equation (6) ′ and (Y−2B) × ½. There is. When the operating frequency is 400 MHz, Conditional Expression 1 (120 ps <A <420 ps) is not satisfied. Therefore, when the operating frequency of the DDR memory is 400 MHz, the line length of each signal line is not determined by the second combination.

  Also in the second combination, the third signal line L3 has a third propagation delay time C that is longer than the delay time based on the physically minimum wiring length of the third signal line L3. Conditions are provided so that C has a length that is less than a predetermined second upper limit time.

条件式２は、第３信号線Ｌ３を物理的に第３伝搬遅延時間Ｃが６０ｐｓとなる長さよりも長くする必要がある一方で、小型化のため、第３伝搬遅延時間Ｃが１３０ｐｓよりも短くなる長さとすることを定めている。さらに、小型化のため、第３伝搬遅延時間ＣをＤＩＭＭ基板の第２伝搬遅延時間Ｂの最小値未満とする（第３信号線の長さを第２信号線以下とする）。図５の第１２列に各周波数で（Ｘ−２Ｂ）×１／２で求められた値が、条件式２を満たすか否かを記載している。また、図５の第１３列には、式（５）’を満たし、かつ、条件式２を満たすＣの範囲を記載している。第２の組み合わせでは、この範囲内の第３伝搬遅延時間Ｃとなるように、第３信号線Ｌ３の信号線の長さを定めればよい。なお、動作周波数が１０６６ＭＨｚの場合、式（５）’及び（Ｘ−２Ｂ）×１／２の値に基づき第３伝搬遅延時間Ｃは、３０ｐｓ未満とする必要がある。この場合、条件式２を満たさない。そのため、動作周波数が１０６６ＭＨｚの場合、第２の組み合わせによって各信号線の線路長は定めない。 For example, the same condition as the first combination shown below can be attached to the third propagation delay time C.

Conditional expression 2 requires that the third signal line L3 be physically longer than the length at which the third propagation delay time C is 60 ps, while the third propagation delay time C is less than 130 ps for miniaturization. The length is set to be shorter. Further, in order to reduce the size, the third propagation delay time C is set to be shorter than the minimum value of the second propagation delay time B of the DIMM substrate (the length of the third signal line is set to be equal to or shorter than the second signal line). The twelfth column in FIG. 5 describes whether or not the value obtained by (X−2B) × ½ at each frequency satisfies the conditional expression 2. Further, the 13th column of FIG. 5 describes the range of C that satisfies Expression (5) ′ and satisfies Conditional Expression 2. In the second combination, the length of the signal line of the third signal line L3 may be determined so that the third propagation delay time C is within this range. When the operating frequency is 1066 MHz, the third propagation delay time C needs to be less than 30 ps based on the values of Expression (5) ′ and (X−2B) × ½. In this case, conditional expression 2 is not satisfied. Therefore, when the operating frequency is 1066 MHz, the line length of each signal line is not determined by the second combination.

C. Regarding the third combination (A + B) + X in the right term of the equation (7) included in the third combination has a change in the signal level of the terminal on the transmission side at the minimum change interval X from the reference time (n + 1th) After that, the time until the (n + 1) th signal level change arrives at the receiving terminal is shown. In other words, the length from the reference time point to the arrival time point when the signal level change reaches the receiving terminal at the earliest time point in the reachable time zone is shown.

  When the length of each signal line is determined based on the third combination, the (nth) transmission side half a cycle before the change in the signal level of the (n + 1) th transmission side terminal reaches the reception side terminal. The reflected wave (A + B + 2C) generated by the change of the signal level at the terminal reaches the terminal on the receiving side.

  On the other hand, (A + B) + Y in the right term of the expressions (8) and (9) included in the third combination has a change in the signal level of the terminal on the transmission side at the maximum change interval Y from the reference time (n + 1). Indicates the time until the signal level change reaches the receiving terminal. In other words, the length from the reference time point to the arrival time point when the signal level change reaches the terminal on the receiving side at the latest time point in the reachable time zone is shown.

  When the length of each signal line is determined based on the third combination, after the signal level change of the transmission side terminal reaches the reception side terminal (the signal level change may reach the reception side terminal). After a certain period of time, a reflected wave (A + 3B + 2C, 3A + 3B) generated by a change in the signal level at the (n-th) transmission-side terminal half a cycle before reaches the reception-side terminal.

  A method for determining the lengths of the signal lines of the first signal line L1, the second signal line L2, and the third signal line L3 based on the third combination will be described with reference to FIG. The first column in FIG. 6 shows an example of the frequency employed in the DDR3 memory. The second column shows the half period of each frequency. The third column shows a time (minimum change interval X) obtained by subtracting a predetermined margin time (6% of the half cycle) from the half cycle of the operation clock. The fourth column shows the time (maximum change interval Y) obtained by adding a predetermined margin time (6% of the half cycle) from the half cycle of the operation clock.

  The fifth column in FIG. 6 shows an example of the second propagation delay time B of the second signal line L2 determined by the second DDR memory 7. The second propagation delay time B varies from 130 ps to 190 ps depending on the byte lane. In the example of FIG. 6 (third combination), the value of the second propagation delay time B in the expressions (8) and (9) relating to Y uses the minimum value of 130 ps.

（９）’の式に基づき、第１信号線Ｌ１は、第１伝搬遅延時間Ａが（Ｙ−２Ｂ）×１／２よりも大きくなる信号線の長さとする。また、（８）’の式に基づき、第３信号線Ｌ３は、第３伝搬遅延時間Ｃが（Ｙ−２Ｂ）×１／２よりも大きくなる信号線の長さとする。図６の第６列に各周波数での（Ｘ−２Ｂ）を、第７列に各周波数での（Ｘ−２Ｂ）×１／２を記載している。図６の第８列に各周波数での（Ｙ−２Ｂ）を、第９列に各周波数での（Ｙ−２Ｂ）×１／２を記載している。また、（７）’式も満たすように第３信号線Ｌ３の信号線の長さを定める必要がある。 Here, the formulas included in the third combination are organized as follows.

Based on the expression (9) ′, the first signal line L1 has a signal line length that makes the first propagation delay time A longer than (Y−2B) × ½. Further, based on the expression (8) ′, the third signal line L3 has a signal line length that makes the third propagation delay time C longer than (Y−2B) × ½. The (X-2B) at each frequency is described in the sixth column of FIG. 6, and (X-2B) × 1/2 at each frequency is described in the seventh column. The (Y-2B) at each frequency is shown in the eighth column of FIG. 6, and (Y-2B) × 1/2 at each frequency is shown in the ninth column. Further, it is necessary to determine the length of the signal line of the third signal line L3 so as to satisfy the expression (7) ′.

  Even in the third combination, the first signal line L1 has a first propagation delay time A longer than the delay time based on the physically minimum wiring length of the first signal line L1. Conditions are provided so that A is a length that is less than a predetermined first upper limit time.

条件式１は、第３の組み合わせの場合でも、第１信号線Ｌ１を物理的に第１伝搬遅延時間Ａが１２０ｐｓとなる長さよりも長くする必要がある一方で、小型化のため、第１伝搬遅延時間Ａが４２０ｐｓよりも短くなる長さとすることを定めている。図６の第１０列に各周波数で（Ｙ−２Ｂ）×１／２で求められた値が、条件式１を満たすか否かを記載している。また、図６の第１１列には、式（９）’を満たし、かつ、条件式１を満たすＡの範囲を記載している。各周波数において、図６に示すＡの範囲内の第１伝搬遅延時間Ａとなるように、第１信号線Ｌ１の信号線の長さを定めればよい。 For example, when the length of the signal line is determined by the third combination, the same conditions as other combinations as described below can be given.

Conditional expression 1 requires that the first signal line L1 be physically longer than the length at which the first propagation delay time A is 120 ps even in the third combination. It is defined that the propagation delay time A has a length shorter than 420 ps. The tenth column in FIG. 6 describes whether or not the value obtained by (Y−2B) × ½ at each frequency satisfies the conditional expression 1. The eleventh column in FIG. 6 describes the range of A that satisfies the expression (9) ′ and satisfies the conditional expression 1. What is necessary is just to determine the length of the signal line of the 1st signal line L1 so that it may become the 1st propagation delay time A in the range of A shown in FIG.

  In the example of FIG. 6, when the operating frequency of the DDR memory is 400 MHz, the first propagation delay time A needs to be set to 533 ps or more based on the values of Expression (6) ′ and (Y−2B) × ½. There is. When the operating frequency is 400 MHz, Conditional Expression 1 (120 ps <A <420 ps) is not satisfied. Therefore, when the operating frequency of the DDR memory is 400 MHz, the line length of each signal line is not determined by the third combination.

  Even in the third combination, the third signal line L3 has a third propagation delay time C longer than the delay time based on the physically minimum wiring length of the third signal line L3. Conditions are provided so that C has a length that is less than a predetermined second upper limit time.

条件式２は、第３信号線Ｌ３を物理的に第３伝搬遅延時間Ｃが６０ｐｓとなる長さよりも長くする必要がある一方で、小型化のため、第３伝搬遅延時間Ｃが１３０ｐｓよりも短くなる長さとすることを定めている。さらに、小型化のため、第３伝搬遅延時間ＣをＤＩＭＭ基板の第２伝搬遅延時間Ｂの最小値未満とする（第３信号線の長さを第２信号線以下とする）。図６の第１２列に各周波数で（Ｙ−２Ｂ）×１／２で求められた値が、条件式２を満たすか否かを記載している。また、図６の第１３列には、式（８）’を満たし、かつ、条件式２を満たすＣの範囲を記載している。第３の組み合わせでは、この範囲内の第３伝搬遅延時間Ｃとなるように、第３信号線Ｌ３の信号線の長さを定めればよい。 For example, the same conditions as the first combination shown below can be attached.

Conditional expression 2 requires that the third signal line L3 be physically longer than the length at which the third propagation delay time C is 60 ps, while the third propagation delay time C is less than 130 ps for miniaturization. The length is set to be shorter. Further, in order to reduce the size, the third propagation delay time C is set to be shorter than the minimum value of the second propagation delay time B of the DIMM substrate (the length of the third signal line is set to be equal to or shorter than the second signal line). The twelfth column in FIG. 6 describes whether or not the value obtained by (Y−2B) × ½ at each frequency satisfies the conditional expression 2. Further, the 13th column of FIG. 6 describes a range of C that satisfies Expression (8) ′ and satisfies Conditional Expression 2. In the third combination, the length of the signal line of the third signal line L3 may be determined so that the third propagation delay time C is within this range.

  In the example of FIG. 6, the third propagation delay time C is larger than 533 ps when the operating frequency is 400 MHz based on the values of the equations (8) ′ and (Y−2B) × ½, In the case of 667 MHz, it must be larger than 267 ps, in the case of 800 MHz, larger than 201 ps, and in the case of 933 MHz, larger than 154 ps. When the operating frequency is 400 MHz to 933 MHz, Conditional Expression 2 (60 ps <C <130 ps) is not satisfied. Therefore, when the operating frequency of the DDR memory is 400 MHz to 933 MHz, the line length of each signal line is not determined by the third combination.

(About combinations other than the above)
Next, combinations other than the above will be described. All of the above formulas (1), (4), and (7) satisfy A + B + 2C <(A + B) + X. Here, Formula (10) in which X in Formula (1), Formula (4), and Formula (7) is replaced with Y is A + B + 2C> (A + B) + Y.

  When this equation (10) is rearranged, C> Y / 2. At each frequency, Y / 2 exceeds the maximum value 130 ps of conditional expression 2 (Y is about 500 ps even at 1066 MHz). Therefore, the line length cannot be determined by a combination of expressions including the expression A + B + 2C> (A + B) + Y.

Further, the following combinations are excluded from the combinations that determine the line length because either of the conditional expressions 1 and 2 cannot be satisfied at any frequency.

  Thus, the transmission apparatus 1 according to the embodiment includes the device (ASIC 22), the first DDR memory 6, the second DDR memory 7, the first signal line L1, the second signal line L2, and the third signal line L3. The first DDR memory 6 exchanges signals with the device. The second DDR memory 7 also exchanges signals with the device. The first signal line L1 is a signal line from the device to the branch point P. The second signal line L2 is a signal line from the branch point P to the second DDR memory 7. The third signal line L3 is a signal line from the branch point P to the first DDR memory 6. The first propagation delay time that is the propagation delay time of the first signal line L1 is A, the second propagation delay time that is the propagation delay time of the second signal line L2 is B, and the propagation delay time of the third signal line L3 is the first. 3 Let C be the propagation delay time. Further, X is a time obtained by subtracting a predetermined margin time from the half cycle of the operation clock, and Y is a time obtained by adding the margin time to the half cycle of the operation clock. The first signal line L1, the second signal line L2, and the third signal line L3 have the relationship between the first propagation delay time A, the second propagation delay time B, and the third propagation delay time C. It is the length which satisfy | fills any combination among these combinations (1st-3rd combination).

  Each expression included in each combination indicates that the reflected wave of the one-time reflection and the two-time reflection is transferred to the second DDR memory 7 within a time period in which a change in the signal level of the terminal of the device can reach the terminal of the second DDR memory 7. This is an equation for determining the length (delay time) of each signal line corresponding to A, B, and C so as not to reach.

  As a result, even if the signal line length from the branch point P to each DDR memory is not equal, the reflected wave (reflected wave) is simultaneously or almost simultaneously with the change in the signal level at the terminal of the second DDR memory 7. Can be prevented from reaching the terminal of the second DDR memory 7. That is, the influence of the reflected wave can be reduced without making the length of the signal line from the branch point P to each DDR memory equal. Further, the substrate on which the DDR memory is provided can be reduced in size as compared with the case of equal length wiring. Thereby, manufacturing cost can be reduced. In addition, the reliability of the transmitted signal can be ensured without using equal length wiring.

  The first DDR memory 6 is mounted on the substrate. The second DDR memory 7 is included in a memory module substrate 71 attached to a memory expansion socket 72 provided on the substrate. The second propagation delay time B is determined based on the propagation delay time in the socket 72 and the wiring length in the memory module substrate 71. As a result, when the memory module substrate 71 (DIMM substrate) is used for the second DDR memory 7, the wiring length of the DIMM substrate or the socket 72 to which the DIMM substrate is attached cannot be changed, so that the length of the fixed signal line and the propagation delay time can be reduced. The second propagation delay time B is determined in consideration. Thereby, the second signal line L2 can be fixedly determined.

  The first signal line L1 has a first propagation delay time A longer than a delay time based on a physically minimum wiring length of the first signal line L1, and the first propagation delay time A is predetermined. The length is less than the first upper limit time (corresponding to conditional expression 1). This imposes a condition that the first propagation delay time A (first signal line L1) does not become longer than a certain value for miniaturization while ensuring the physically necessary length, and the first signal. The lengths of the line L1, the second signal line L2, and the third signal line L3 can be determined.

  In addition, the third propagation delay time C of the third signal line L3 is longer than the delay time based on the physically minimum wiring length of the third signal line L3, and the third propagation delay time C is predetermined. The length is less than the second upper limit time and the third propagation delay time C is equal to or shorter than the second propagation delay time B (corresponding to conditional expression 2). Thus, conditions are imposed so that the third propagation delay time C (third signal line L3) does not become long, and the lengths of the first signal line L1, the second signal line L2, and the third signal line L3 are determined. Can do. Further, for the purpose of miniaturization, the length of the signal line of the third signal line L3 is set so that the third propagation delay time C is shorter than the signal propagation delay time (second propagation delay time B) in the memory module substrate 71. Can be determined. That is, the length of the signal line of the third signal line L3 can be made shorter than the length of the signal line of the second signal line L2.

  Further, the image forming apparatus (multifunction peripheral 100) includes the transmission apparatus 1 described above. Accordingly, it is possible to provide an image forming apparatus that is less affected by reflection without having an equal length wiring. Further, a low-cost image forming apparatus with a small substrate size can be provided.

  Moreover, although the embodiment of the present invention has been described, the scope of the present invention is not limited to this, and various modifications can be made without departing from the spirit of the invention.

  For example, in the above description, an example has been described in which the ASIC 22 is the transmission side, the second DDR memory 7 is the reception side, and the signal level of the DQ terminal or DQS terminal of the ASIC 22 is changed to write data to the second DDR memory. . According to the present invention, since the length of each signal line is determined so that the arrival of the reflected wave and the arrival of the change in the signal level do not overlap at the terminal on the reception side, the second DDR memory 7 is the transmission side and the ASIC 22 is the reception side. Even when the second DDR memory changes the signal level of the DQ terminal or the DQS terminal for reading data from the second DDR memory, the arrival of the reflected wave at the DQ terminal or the DQS terminal of the ASIC 22 and the change of the signal level Reaching does not overlap.

  The present invention can be used for a transmission apparatus and an image forming apparatus including the transmission apparatus.

DESCRIPTION OF SYMBOLS 100 MFP (image forming apparatus) 1 Transmission apparatus 22 ASIC (device) 6 1st DDR memory 7 2nd DDR memory 71 Memory module board 72 Socket A 1st propagation delay time B 2nd propagation delay time C 3rd propagation delay time L1 1st 1 signal line L2 2nd signal line L3 3rd signal line P Branch point

Claims (5)

The device,
A first DDR memory for exchanging signals with the device;
A second DDR memory for exchanging signals with the device;
A first signal line that is a signal line from the device to a branch point;
A second signal line from the branch point to the second DDR memory;
A third signal line from the branch point to the first DDR memory,
The first propagation delay time that is the propagation delay time of the first signal line is A, the second propagation delay time that is the propagation delay time of the second signal line is B, and the first propagation delay time is the propagation delay time of the third signal line. 3 Let C be the propagation delay time.
X is a time obtained by subtracting a predetermined margin time from a half cycle of the operation clock, and Y is a time obtained by adding the margin time to the half cycle of the operation clock.
In the first signal line, the second signal line, and the third signal line, the relationship between the first propagation delay time, the second propagation delay time, and the third propagation delay time is a combination of the following three expressions: The transmission apparatus has a length satisfying any one of the combinations.

The first DDR memory is mounted on a substrate;
The second DDR memory is included in a memory module substrate attached to a memory expansion socket provided on the substrate,
The transmission apparatus according to claim 1, wherein the second propagation delay time is determined based on a propagation delay time in the socket and a wiring length in the memory module substrate.   In the first signal line, the first propagation delay time is longer than a delay time based on a physically minimum wiring length of the first signal line, and the first propagation delay time is predetermined. The transmission apparatus according to claim 1, wherein the transmission apparatus has a length that is less than the upper limit time.   In the third signal line, the third propagation delay time is longer than a delay time based on a physically minimum wiring length of the third signal line, and the third propagation delay time is determined in advance. 3. The transmission device according to claim 1, wherein the transmission apparatus is less than an upper limit time and has a length such that the third propagation delay time is equal to or shorter than the second propagation delay time.   An image forming apparatus comprising the transmission device according to claim 1.

Images