JP2008252374A - Circuit board - Google Patents

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JP2008252374A
JP2008252374A JP2007089531A JP2007089531A JP2008252374A JP 2008252374 A JP2008252374 A JP 2008252374A JP 2007089531 A JP2007089531 A JP 2007089531A JP 2007089531 A JP2007089531 A JP 2007089531A JP 2008252374 A JP2008252374 A JP 2008252374A
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transmission
signal
semiconductor device
receiving
wiring
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Masaru Tokiwa
勝 常盤
Kan Shimizu
簡 清水
Koji Kuroda
浩二 黒田
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Toshiba Corp
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress deterioration in signal waveform quality caused by an impedance discontinuous part that exists in the middle of a transmission path in a fast-speed signal transmission system for transmitting and receiving a synchronous high-speed pulse signal through one transmission path. <P>SOLUTION: In the signal transmission system for transmitting and receiving a synchronous high-speed pulse signal through one transmission path 13 between a transmitting side board 11, on which a transmitting side semiconductor device 112 is mounted, and a receiving side board 12, on which a receiving side semiconductor device 122 is mounted, In the transmitting side substrate 11, a connector 113 is mounted and a PCB wiring 114 is formed in a transmission path from the transmitting side semiconductor device 112 to the connector 113. The wiring length of the PCB wiring is set so as to make the round-trip transmission time of a signal propagating on the PCB wiring to be 1/4 or 1/4+n/2 (n is a positive integer) of a switching period of a pulse signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、回路基板に係り、特に半導体装置および伝送路接続用コネクタを搭載した回路基板に関するもので、例えばパーソナルコンピュータと周辺装置との間で1本のUSBケーブルを介して同期型のパルス信号を送受信する信号伝送システムに使用されるものである。   The present invention relates to a circuit board, and more particularly to a circuit board on which a semiconductor device and a transmission line connector are mounted. For example, a synchronous pulse signal is transmitted between a personal computer and a peripheral device via a single USB cable. It is used for a signal transmission system for transmitting and receiving.

一般に、送信側半導体装置を搭載した送信側基板と受信側半導体装置を搭載した受信側基板との間で有線伝送路を介して信号を送受信する信号伝送システム、あるいは、送受信用半導体装置を搭載した送受信基板相互間で有線伝送路を介して高速信号を送受信する信号伝送システムが用いられている。このような高速信号伝送システムにおいて、伝送路のインピーダンスと終端抵抗のインピーダンスとが異なる場合には入射波に相似な反射波が生じる。   In general, a signal transmission system for transmitting / receiving a signal via a wired transmission path between a transmission side substrate on which a transmission side semiconductor device is mounted and a reception side substrate on which a reception side semiconductor device is mounted, or a transmission / reception semiconductor device is mounted 2. Description of the Related Art A signal transmission system that transmits and receives high-speed signals between transmission / reception boards via a wired transmission path is used. In such a high-speed signal transmission system, when the impedance of the transmission line and the impedance of the terminating resistor are different, a reflected wave similar to the incident wave is generated.

伝送路を往復する反射波に起因する信号の時間的揺らぎを抑え、ジッタを低減するために、伝送路にチップ抵抗を接続した高速信号伝送配線実装構造が特許文献1に開示されている。特許文献1の構造では、出力信号波形中の入力波と反射波との合成ポイントが信号波形のエッジ付近になるので、このエッジ付近で信号波形に対してジッタ(jitter)、ディップ(dip) などの影響を及ぼし、信号波形品質の低下をまねく原因となる。   Patent Document 1 discloses a high-speed signal transmission wiring mounting structure in which a chip resistor is connected to a transmission path in order to suppress temporal fluctuation of a signal due to a reflected wave traveling back and forth in the transmission path and reduce jitter. In the structure of Patent Document 1, since the synthesis point of the input wave and the reflected wave in the output signal waveform is near the edge of the signal waveform, jitter (jitter), dip (dip), etc. with respect to the signal waveform near this edge This may cause a decrease in signal waveform quality.

ところで、前記したような高速信号伝送システムの1つの類型として、同期型の高速のパルス信号を1本の伝送路を介して送受信するシステムがある。そして、このシステムにおいて、送信側基板上では送信側半導体装置からコネクタまでの伝送路に印刷配線が形成され、受信側基板上ではコネクタから受信側半導体装置までの伝送路に印刷配線が形成された構成のものがある。なお、上記システムにおいて、送信側回路および受信側回路が内蔵された半導体装置を搭載した送受信基板上で半導体装置から送受信用コネクタまでの伝送路に印刷配線が形成され、送信側回路および受信側回路が切替回路によって選択的に前記印刷配線に接続される構成のものがある。   By the way, as one type of the high-speed signal transmission system as described above, there is a system that transmits and receives a synchronous high-speed pulse signal via a single transmission line. In this system, the printed wiring is formed on the transmission path from the transmission side semiconductor device to the connector on the transmission side substrate, and the printed wiring is formed on the transmission path from the connector to the reception side semiconductor device on the reception side substrate. There is a configuration one. In the above system, a printed wiring is formed in a transmission path from the semiconductor device to the transmission / reception connector on the transmission / reception substrate on which the semiconductor device incorporating the transmission side circuit and the reception side circuit is mounted. Is configured to be selectively connected to the printed wiring by a switching circuit.

これらの伝送路においては、半導体装置パッケージの端子接続部、基板上に実装されるコネクタ(例えばUSB規格のコネクタ)が存在する。一般的に、コネクタは、インピーダンス制御ができるものを入手することが難しいので、伝送路上に実装するコネクタや半導体装置パッケージの端子接続部などはインピーダンス不連続部となることが多い。このようなインピーダンス不連続部は、信号の反射を発生させる要因となり、信号波形に対してジッタ、ディップなどの影響を及ぼし、信号波形品質の低下をまねく原因となる。例えば、コネクタは、容量の付加、あるいは削減の効果を有し、コネクタで反射される波形は、入射波を微分した成分を多く含む。これは、前述した特許文献1に記載されている伝送路に反射波が生じる問題とは異なり、特許文献1とは異る対策が必要となる。
特開2001−111408号公報
In these transmission lines, there are a terminal connection portion of a semiconductor device package and a connector (for example, a USB standard connector) mounted on a substrate. In general, since it is difficult to obtain a connector that can control impedance, a connector mounted on a transmission line, a terminal connection portion of a semiconductor device package, and the like often have impedance discontinuities. Such impedance discontinuity causes signal reflection, affects the signal waveform such as jitter and dip, and causes signal waveform quality to deteriorate. For example, the connector has an effect of adding or reducing capacitance, and the waveform reflected by the connector includes many components obtained by differentiating the incident wave. This is different from the problem that a reflected wave is generated in the transmission line described in Patent Document 1 described above, and a measure different from that of Patent Document 1 is required.
JP 2001-111408 A

本発明は前記した事情に鑑みてなされたもので、同期型のパルス信号を1本の伝送路を介して送信または受信する場合に、伝送路の途中に存在するインピーダンス不連続部に起因する信号波形品質の低下を抑制し得る回路基板を提供することを目的とする。   The present invention has been made in view of the above-described circumstances. When a synchronous pulse signal is transmitted or received via a single transmission line, a signal caused by an impedance discontinuity existing in the middle of the transmission line. An object of the present invention is to provide a circuit board capable of suppressing a decrease in waveform quality.

本発明の回路基板の第1の態様は、パルス信号を送信する送信回路を内蔵した送信側半導体装置を搭載し、前記送信側半導体装置に接続された出力配線および当該出力配線に接続されたコネクタが配設された送信側基板を有し、前記送信側半導体装置から前記コネクタまでの伝送路に印刷配線が形成されており、前記印刷配線の長さは、当該印刷配線上を伝搬する信号の往復伝送時間が前記パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるように設定されていることを特徴とする。   According to a first aspect of the circuit board of the present invention, a transmission-side semiconductor device including a transmission circuit that transmits a pulse signal is mounted, an output wiring connected to the transmission-side semiconductor device, and a connector connected to the output wiring The printed wiring is formed in the transmission path from the transmitting semiconductor device to the connector, and the length of the printed wiring is the length of the signal propagating on the printed wiring. The round-trip transmission time is set to be ¼ or ¼ + n / 2 (n is a positive integer) of the switching period of the pulse signal.

本発明の回路基板の第2の態様は、パルス信号を受信する受信回路を内蔵した受信側半導体装置を搭載し、前記受信側半導体装置に接続された入力配線および当該入力配線に接続されたコネクタが配設された受信側基板を有し、前記受信側半導体装置から前記コネクタまでの伝送路に印刷配線が形成されており、前記印刷配線の長さは、当該印刷配線上を伝搬する信号の往復伝送時間が前記パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるように設定されていることを特徴とする。   According to a second aspect of the circuit board of the present invention, a receiving-side semiconductor device including a receiving circuit that receives a pulse signal is mounted, an input wiring connected to the receiving-side semiconductor device, and a connector connected to the input wiring. And a printed wiring is formed in a transmission path from the receiving semiconductor device to the connector, and the length of the printed wiring is the length of the signal propagating on the printed wiring The round-trip transmission time is set to be ¼ or ¼ + n / 2 (n is a positive integer) of the switching period of the pulse signal.

本発明の回路基板によれば、同期型のパルス信号を1本の伝送路を介して送信または受信する場合に、伝送路の途中に存在するインピーダンス不連続部に起因する信号波形品質の低下を抑制することができる。   According to the circuit board of the present invention, when a synchronous pulse signal is transmitted or received via one transmission line, the signal waveform quality is reduced due to an impedance discontinuity existing in the middle of the transmission line. Can be suppressed.

以下、図面を参照して本発明の実施形態を説明する。この説明に際して、全図にわたり共通する部分には共通する参照符号を付す。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<第1の実施形態>
図1は、本発明の回路基板を適用した信号伝送システムの第1の実施形態の構成を示す回路図である。この信号伝送システムは、送信回路111を内蔵した送信側半導体装置112および第1のコネクタ113を搭載した送信側基板11と、受信回路121を内蔵した受信側半導体装置122および第2のコネクタ123を搭載した受信側基板12との間で、1本の伝送路(例えばケーブル)13を介して同期型の高速パルス信号を送受信する。ここで、高速パルス信号の切替周期は、例えば2nS程度である。
<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a signal transmission system to which a circuit board of the present invention is applied. This signal transmission system includes a transmission-side substrate 11 having a transmission-side semiconductor device 112 and a first connector 113 with a transmission circuit 111 built-in, and a reception-side semiconductor device 122 and a second connector 123 with a reception circuit 121 built-in. A synchronous high-speed pulse signal is transmitted / received to / from the receiving substrate 12 mounted via a single transmission line (for example, cable) 13. Here, the switching period of the high-speed pulse signal is, for example, about 2 nS.

そして、送信側基板11には、送信側半導体装置112から第1のコネクタ113までの伝送路に印刷配線(PRINTED CIRCUIT BOAD配線、以下、PCB配線と記す)114が形成されている。そして、このPCB配線114の配線長は、このPCB配線114を伝搬する信号の往復伝送時間が前記パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)となるように設定されている
また、受信側基板12には、受信側半導体装置122から第2のコネクタ123までの伝送路にPCB配線124が形成されている。そして、このPCB配線124の配線長は、このPCB配線124を伝搬する信号の往復伝送時間が前記パルス信号の切替周期の1/4または1/4+1/2の整数倍となるように設定されている。
In the transmission side substrate 11, printed wiring (PRINT CIRCUIT BOAD wiring, hereinafter referred to as PCB wiring) 114 is formed on the transmission path from the transmission side semiconductor device 112 to the first connector 113. The wiring length of the PCB wiring 114 is such that the round-trip transmission time of the signal propagating through the PCB wiring 114 is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the pulse signal. In addition, PCB wiring 124 is formed on the transmission path from the reception-side semiconductor device 122 to the second connector 123 on the reception-side substrate 12. The wiring length of the PCB wiring 124 is set such that the round-trip transmission time of the signal propagating through the PCB wiring 124 is an integral multiple of 1/4 or 1/4 + 1/2 of the switching period of the pulse signal. Yes.

次に、送信側基板11のPCB配線114および受信側基板12のPCB配線124について、信号波形品質の低下防止の観点から最適な配線長を求める。   Next, an optimum wiring length is obtained for the PCB wiring 114 of the transmission side substrate 11 and the PCB wiring 124 of the reception side substrate 12 from the viewpoint of preventing deterioration of signal waveform quality.

図2は、図1中の送信側基板11においてPCB配線長と伝送信号に生じるジッタ量との関係を実測した際の波形測定回路を概略的に示している。ここで、115は送信側半導体装置112内の配線部(パッケージのリード部分を含む)、21は伝送路13の終端回路、22および23はジッタ測定機能付きのデジタルオシロスコープおよびその測定入力プローブである。   FIG. 2 schematically shows a waveform measurement circuit when the relationship between the PCB wiring length and the amount of jitter generated in the transmission signal is actually measured in the transmission side substrate 11 in FIG. Here, 115 is a wiring part (including the lead part of the package) in the transmission side semiconductor device 112, 21 is a termination circuit of the transmission line 13, 22 and 23 are digital oscilloscopes with a jitter measurement function and their measurement input probes. .

いま、切替周期が2.083nS の高速パルス信号が1nS 間にPCB配線上を進む距離を140mm とすると、
切替周期の1/2の期間に信号が進む距離は2.083nS/2 ×140mm=145.81mm
切替周期の1/4の期間に信号が進む距離は2.083nS/4 ×140mm=72.905mm
切替周期の(1/4)+(1/2)×1の期間に信号が進む距離は218.72mm
切替周期の(1/4)+(1/2)×2の期間に信号が進む距離は364.53mm
になる。
Now, if the distance that a high-speed pulse signal with a switching period of 2.083nS travels on the PCB wiring in 1nS is 140mm,
The distance that the signal travels in the half of the switching cycle is 2.083nS / 2 × 140mm = 145.81mm
The distance that the signal travels during a quarter of the switching cycle is 2.083nS / 4 × 140mm = 72.905mm
The distance the signal travels in the period of (1/4) + (1/2) x 1 of the switching cycle is 218.72mm
The distance that the signal travels in the period of (1/4) + (1/2) x 2 of the switching cycle is 364.53 mm
become.

そこで、図1中の送信側基板11および受信側基板12においてPCB配線長をそれぞれ20、30、60、90、130 、200 、300 、450mm に設定し、各基板に同じ半導体装置を実装した場合のそれぞれのジッタ量を実測した。   Therefore, when the PCB wiring length is set to 20, 30, 60, 90, 130, 200, 300, and 450 mm on the transmission side substrate 11 and the reception side substrate 12 in FIG. 1, and the same semiconductor device is mounted on each substrate Each jitter amount was actually measured.

図3に示す実測データによれば、PCB配線上を伝搬する信号の往復伝送時間がパルス信号の切替周期の1/5、1/4、1/2、3/4にそれぞれ対応するようにPCB配線長が設定されている場合に、ジッタ量は約35pS、約20pS、約27pS、約20pSであった。この実測データから、PCB配線上を伝搬する信号の往復伝送時間がパルス信号の切替周期の1/4または1/4+n/2(nは正の整数)の場合にジッタ量が低減する現象を確認することができる。ここで、現実的には、n=0またはn=1が望ましい。その理由は、信号がPCB配線上を進む際に信号の減衰が発生し、信号の減衰量は周波数特性を有することから、PCB配線長が長いと信号減衰量の周波数特性が低下して信号歪みが増大するので、PCB配線長は短い方が好ましいからである。   According to the actual measurement data shown in FIG. 3, the round trip transmission time of the signal propagating on the PCB wiring corresponds to 1/5, 1/4, 1/2, 3/4 of the switching period of the pulse signal, respectively. When the wiring length was set, the jitter amount was about 35 pS, about 20 pS, about 27 pS, and about 20 pS. From this measured data, we confirmed the phenomenon that the jitter amount is reduced when the round-trip transmission time of the signal propagating on the PCB wiring is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the pulse signal. can do. Here, in reality, n = 0 or n = 1 is desirable. The reason is that the signal attenuation occurs when the signal travels on the PCB wiring, and the signal attenuation amount has a frequency characteristic. Therefore, if the PCB wiring length is long, the frequency characteristic of the signal attenuation amount decreases and signal distortion occurs. This is because a shorter PCB wiring length is preferable.

なお、従来例の特許文献1の構成において、仮に伝送路の長さを上記したような高速パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)に設定すると、出力信号波形中の入力波と反射波との合成ポイントが信号波形に対してジッタ、ディップなどの影響を及ぼし、信号波形品質の低下をまねく。   In the configuration of Patent Document 1 of the conventional example, if the length of the transmission line is set to 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the high-speed pulse signal as described above, The synthesis point of the input wave and the reflected wave in the output signal waveform affects the signal waveform, such as jitter and dip, leading to a decrease in signal waveform quality.

図4は、図1の信号伝送システムにおいて、PCB配線上を伝搬する信号の往復伝送時間がパルス信号の切替周期の1/4になるようにPCB配線長が設定された場合に、送信側基板11の出力信号波形中で入力波と反射波との合成ポイントが信号波形の中央付近になる様子を示す。このように、信号波形に対してジッタ、ディップなどの影響を及ぼす程度が軽減され、信号品質の低下を抑制することができる。   FIG. 4 shows the transmission side substrate when the PCB wiring length is set so that the round-trip transmission time of the signal propagating on the PCB wiring becomes 1/4 of the switching period of the pulse signal in the signal transmission system of FIG. 11 shows a state in which the composite point of the input wave and the reflected wave is near the center of the signal waveform among the 11 output signal waveforms. In this way, the degree of influence of jitter, dip, etc. on the signal waveform is reduced, and deterioration in signal quality can be suppressed.

上記したように本実施形態によれば、送信側基板11において、PCB配線上を伝搬する信号の往復伝送時間が高速パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるようにPCB配線長を設定することによって、送信側基板11の伝送路の途中に存在するインピーダンス不連続部でのインピーダンス不整合を軽減することができ、信号波形に与える要因を軽減し、信号波形品質を最良に調整し、信号波形品質の低下を防止することができる。すなわち、コネクタ部での送信波(進行波)と反射波の位相(時間関係)を最良(適切)に調整することができ、結果として、第1のコネクタ113でのインピーダンス不整合を軽減することができる。   As described above, according to the present embodiment, in the transmission side substrate 11, the round-trip transmission time of the signal propagating on the PCB wiring is 1/4 or 1/4 + n / 2 of the switching period of the high-speed pulse signal (n is positive) By setting the PCB wiring length to be an integer), impedance mismatch at the impedance discontinuity existing in the middle of the transmission path of the transmission side substrate 11 can be reduced, and the factor given to the signal waveform is reduced. Thus, the signal waveform quality can be optimally adjusted, and the deterioration of the signal waveform quality can be prevented. That is, the phase (time relationship) between the transmitted wave (traveling wave) and the reflected wave at the connector portion can be adjusted to the best (appropriate), and as a result, impedance mismatch at the first connector 113 can be reduced. Can do.

同様に、受信側基板12において、PCB配線上を伝搬する信号の往復伝送時間が高速パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるようにPCB配線長を設定することによって、受信側基板12の伝送路の途中に存在するインピーダンス不連続部でのインピーダンス不整合を軽減することができ、信号波形に与える要因を軽減し、信号波形品質を最良に調整し、信号波形品質の低下を防止することができる。すなわち、受信回路入力ノード部における受信波と反射波の時間関係を適切に調整することができ、結果として、受信回路入力ノード部でのインピーダンス不整合を軽減することができる。   Similarly, the PCB wiring so that the round-trip transmission time of the signal propagating on the PCB wiring is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the high-speed pulse signal in the receiving-side substrate 12. By setting the length, impedance mismatch at the impedance discontinuity existing in the middle of the transmission path of the receiving side substrate 12 can be reduced, the factor given to the signal waveform is reduced, and the signal waveform quality is optimized. It is possible to prevent the signal waveform quality from being degraded. That is, the time relationship between the received wave and the reflected wave at the receiving circuit input node unit can be adjusted appropriately, and as a result, impedance mismatch at the receiving circuit input node unit can be reduced.

なお、本実施例形態においては、PCB配線に直列に結合容量を挿入してもよい。また、送信側半導体装置112は伝送信号用の同期クロック信号の出力端子を有しておらず、送信側基板11も伝送信号用の同期クロック信号の出力端子を有していない。同様に、受信側半導体装置122は伝送信号用の同期クロック信号の入力端子を有しておらず、受信側基板12も伝送信号用の同期クロック信号の入力端子を有していない。   In this embodiment, a coupling capacitor may be inserted in series with the PCB wiring. Further, the transmission-side semiconductor device 112 does not have an output terminal for a synchronous clock signal for transmission signals, and the transmission-side substrate 11 also has no output terminal for a synchronous clock signal for transmission signals. Similarly, the receiving-side semiconductor device 122 does not have an input terminal for a synchronous clock signal for a transmission signal, and the receiving-side substrate 12 also does not have an input terminal for a synchronous clock signal for a transmission signal.

また、送信側半導体装置11には、送信回路111の出力側で所定電位ノードとの間にPCB配線114のインピーダンスと整合する終端抵抗(図示せず)が内蔵され、受信側半導体装置12にも、受信回路121の入力ノード側で所定電位ノードとの間にPCB配線124のインピーダンスと整合する終端抵抗(図示せず)が内蔵されることが望ましい。   Further, the transmission side semiconductor device 11 has a built-in termination resistor (not shown) that matches the impedance of the PCB wiring 114 between the output side of the transmission circuit 111 and a predetermined potential node. A termination resistor (not shown) that matches the impedance of the PCB wiring 124 is preferably built in between the input node side of the receiving circuit 121 and the predetermined potential node.

また、送信側基板11や受信側基板12のPCB配線には、従来例の特許文献1のようなチップ抵抗が接続されていないので、チップ抵抗接続部に半田付けランド、半田等のインピーダンス不連続要素が存在するという問題は発生しない。   In addition, since the chip resistance as in Patent Document 1 of the conventional example is not connected to the PCB wiring of the transmission side substrate 11 and the reception side substrate 12, impedance discontinuity such as soldering land and solder is not connected to the chip resistance connection portion. The problem that the element exists does not occur.

<第1の実施形態の一具体例>
図5は、第1の実施形態の一具体例を示す。送信側基板11は、多層配線構造を有し、送信回路を内蔵した送信側半導体装置(IC)112および第1のUSBコネクタ113aを搭載している。この場合、送信側基板11上には送信側半導体装置112と第1のUSBコネクタ113aとの間を接続する第1のPCB配線114が形成されている。このPCB配線114上を伝搬する信号の往復伝送時間が高速パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるように、PCB配線長が設定されている。
<One specific example of the first embodiment>
FIG. 5 shows a specific example of the first embodiment. The transmission side substrate 11 has a multilayer wiring structure, and is equipped with a transmission side semiconductor device (IC) 112 having a transmission circuit built therein and a first USB connector 113a. In this case, a first PCB wiring 114 is formed on the transmission side substrate 11 to connect the transmission side semiconductor device 112 and the first USB connector 113a. The PCB wiring length is set so that the round-trip transmission time of the signal propagating on the PCB wiring 114 is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the high-speed pulse signal. .

受信側基板12は、多層配線構造を有し、受信回路を内蔵した受信側半導体装置(IC)122および第2のUSBコネクタ123aを搭載している。この場合、受信側基板12上には受信側半導体装置122と第2のUSBコネクタ123aとの間を接続する第2のPCB配線124が形成されている。このPCB配線124上を伝搬する信号の往復伝送時間が高速パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるように、PCB配線長が設定されている。   The reception side substrate 12 has a multilayer wiring structure, and is mounted with a reception side semiconductor device (IC) 122 incorporating a reception circuit and a second USB connector 123a. In this case, a second PCB wiring 124 that connects the receiving-side semiconductor device 122 and the second USB connector 123 a is formed on the receiving-side substrate 12. The PCB wiring length is set so that the round-trip transmission time of the signal propagating on the PCB wiring 124 is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the high-speed pulse signal. .

そして、第1のUSBコネクタ113aと第2のUSBコネクタ123aとの間は、両端にUSBコネクタ13aが取り付けられた1本のUSBケーブル13により接続されている。   The first USB connector 113a and the second USB connector 123a are connected by a single USB cable 13 having USB connectors 13a attached to both ends.

<第2の実施形態>
第2の実施形態では、送受信用の半導体装置および送受信兼用のコネクタを搭載した2つの送受信基板相互間で1本の伝送路を介して同期型の高速パルス信号を送受信する。各半導体装置は、送信回路と、受信回路と、これらの送信回路および受信回路を送受信兼用の外部端子に切替接続するための切替回路を内蔵している。
<Second Embodiment>
In the second embodiment, a synchronous high-speed pulse signal is transmitted / received between two transmission / reception boards equipped with a transmission / reception semiconductor device and a transmission / reception connector via a single transmission line. Each semiconductor device includes a transmission circuit, a reception circuit, and a switching circuit for switching and connecting the transmission circuit and the reception circuit to an external terminal that is used for both transmission and reception.

各送受信基板上では、半導体装置からコネクタまでの伝送路にPCB配線が形成され、このPCB配線は切替回路によって送信回路および受信回路に選択的に接続される。このPCB配線の配線長は、このPCB配線上を伝搬する信号の往復伝送時間が高速パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるように設定されている。   On each transmission / reception board, PCB wiring is formed in the transmission path from the semiconductor device to the connector, and this PCB wiring is selectively connected to the transmission circuit and the reception circuit by the switching circuit. The wiring length of the PCB wiring is set so that the round-trip transmission time of the signal propagating on the PCB wiring is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the high-speed pulse signal. ing.

第2の実施形態において、切替回路によってPCB配線が送信回路に接続されている期間には、前述した第1の実施形態と同様に、伝送路の途中に存在するコネクタ部でのインピーダンス不整合を軽減することができ、信号波形に与える要因を軽減し、信号波形品質を最良に調整し、信号波形品質の低下を防止することができる。また、切替回路によってPCB配線が受信回路に接続されている期間には、前述した第1の実施形態と同様に、伝送路の途中に存在する受信回路入力ノード部でのインピーダンス不整合を軽減することができ、信号波形に与える要因を軽減し、信号波形品質を最良に調整し、信号波形品質の低下を防止することができる。   In the second embodiment, during the period in which the PCB wiring is connected to the transmission circuit by the switching circuit, the impedance mismatch in the connector portion existing in the middle of the transmission path is caused as in the first embodiment described above. It is possible to reduce the factors that are given to the signal waveform, to optimally adjust the signal waveform quality, and to prevent the signal waveform quality from deteriorating. Further, during the period in which the PCB wiring is connected to the receiving circuit by the switching circuit, the impedance mismatch at the receiving circuit input node portion existing in the middle of the transmission path is reduced as in the first embodiment described above. Therefore, it is possible to reduce the factor given to the signal waveform, optimally adjust the signal waveform quality, and prevent the deterioration of the signal waveform quality.

本発明の信号伝送システムの第1の実施形態の構成を示す回路図。1 is a circuit diagram showing a configuration of a first embodiment of a signal transmission system of the present invention. 図1中の送信側基板および受信側基板においてPCB配線長と伝送信号に生じるジッタ量との関係を実測した際の波形測定回路の回路図。The circuit diagram of the waveform measurement circuit at the time of measuring the relationship between PCB wiring length and the amount of jitter which arises in a transmission signal in the transmission side board | substrate and reception side board | substrate in FIG. 図1中の送信側基板および受信側基板においてPCB配線長を種々の値に設定し、各基板に同一ICを実装した場合のそれぞれのジッタ量を実測した結果を示す図。The figure which shows the result of having actually measured each jitter amount when PCB wiring length is set to various values in the transmission side board | substrate in FIG. 1, and a receiving side board | substrate, and the same IC is mounted in each board | substrate. 図1の信号伝送システムにおいて、PCB配線長上を伝搬する信号の往復伝送時間がパルス切替周期の1/4になるように設定された場合に出力信号波形中の入力波と反射波との合成ポイントが信号波形の中央付近になる様子を示すタイミング波形図。In the signal transmission system of FIG. 1, when the round-trip transmission time of a signal propagating over the PCB wiring length is set to be ¼ of the pulse switching period, the input wave and the reflected wave in the output signal waveform are combined. The timing waveform figure which shows a mode that a point becomes the center vicinity of a signal waveform. 第1の実施形態の一具体例を示す回路図。FIG. 3 is a circuit diagram showing a specific example of the first embodiment.

符号の説明Explanation of symbols

11…送信側基板、111…送信回路、112…送信側半導体装置、113…第1のコネクタ、114…PCB配線、12…受信側基板、121…受信回路、122…受信側半導体装置、123…第2のコネクタ、124…PCB配線、13…伝送路。 DESCRIPTION OF SYMBOLS 11 ... Transmission side board | substrate, 111 ... Transmission circuit, 112 ... Transmission side semiconductor device, 113 ... 1st connector, 114 ... PCB wiring, 12 ... Reception side board | substrate, 121 ... Reception circuit, 122 ... Reception side semiconductor device, 123 ... Second connector, 124 ... PCB wiring, 13 ... transmission path.

Claims (4)

パルス信号を送信する送信回路を内蔵した送信側半導体装置を搭載し、前記送信側半導体装置に接続された出力配線および当該出力配線に接続されたコネクタが配設された送信側基板を有し、
前記送信側半導体装置から前記コネクタまでの伝送路に印刷配線が形成されており、
前記印刷配線の長さは、当該印刷配線上を伝搬する信号の往復伝送時間が前記パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるように設定されていることを特徴とする回路基板。
A transmission-side semiconductor device that includes a transmission circuit that transmits a pulse signal is mounted, has an output wiring connected to the transmission-side semiconductor device and a transmission-side substrate on which a connector connected to the output wiring is disposed,
Printed wiring is formed in the transmission path from the transmission-side semiconductor device to the connector,
The length of the printed wiring is set so that the round-trip transmission time of the signal propagating on the printed wiring is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the pulse signal. A circuit board characterized by the above.
前記送信側半導体装置および前記送信側基板は、それぞれ伝送信号用の同期クロック信号の出力端子を有さず、前記送信側半導体装置には、前記送信回路の出力ノード側で所定電位ノードとの間に前記印刷配線のインピーダンスと整合する終端抵抗が内蔵されていることを特徴とする請求項1記載の回路基板。   Each of the transmission-side semiconductor device and the transmission-side substrate does not have a synchronous clock signal output terminal for a transmission signal, and the transmission-side semiconductor device is connected to a predetermined potential node on the output node side of the transmission circuit. The circuit board according to claim 1, further comprising a termination resistor that matches the impedance of the printed wiring. パルス信号を受信する受信回路を内蔵した受信側半導体装置を搭載し、前記受信側半導体装置に接続された入力配線および当該入力配線に接続されたコネクタが配設された受信側基板を有し、
前記受信側半導体装置から前記コネクタまでの伝送路に印刷配線が形成されており、
前記印刷配線の長さは、当該印刷配線上を伝搬する信号の往復伝送時間が前記パルス信号の切替周期の1/4または1/4+n/2(nは正の整数)になるように設定されていることを特徴とする回路基板。
A receiving-side semiconductor device having a built-in receiving circuit that receives a pulse signal is mounted, and has a receiving-side substrate on which an input wiring connected to the receiving-side semiconductor device and a connector connected to the input wiring are arranged,
Printed wiring is formed in the transmission path from the receiving semiconductor device to the connector,
The length of the printed wiring is set so that the round-trip transmission time of the signal propagating on the printed wiring is 1/4 or 1/4 + n / 2 (n is a positive integer) of the switching period of the pulse signal. A circuit board characterized by the above.
前記受信側半導体装置および前記受信側基板は、それぞれ伝送信号用の同期クロック信号の入力端子を有さず、前記受信側半導体装置には、前記受信回路の入力ノード側で所定電位ノードとの間に前記印刷配線のインピーダンスと整合する終端抵抗が内蔵されていることを特徴とする請求項3記載の回路基板。   The receiving-side semiconductor device and the receiving-side substrate each do not have a synchronous clock signal input terminal for a transmission signal, and the receiving-side semiconductor device is connected to a predetermined potential node on the input node side of the receiving circuit. 4. The circuit board according to claim 3, wherein a termination resistor matching the impedance of the printed wiring is incorporated in the circuit board.
JP2007089531A 2007-03-29 2007-03-29 Circuit board Pending JP2008252374A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105873355A (en) * 2016-04-26 2016-08-17 浪潮电子信息产业股份有限公司 PCB laminating method and PCB
JP2017146736A (en) * 2016-02-16 2017-08-24 京セラドキュメントソリューションズ株式会社 Transmitting device and image forming apparatus including the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017146736A (en) * 2016-02-16 2017-08-24 京セラドキュメントソリューションズ株式会社 Transmitting device and image forming apparatus including the same
CN105873355A (en) * 2016-04-26 2016-08-17 浪潮电子信息产业股份有限公司 PCB laminating method and PCB

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