JP2001111408A - Structure for packaging high speed signal transmission wire - Google Patents

Structure for packaging high speed signal transmission wire

Info

Publication number
JP2001111408A
JP2001111408A JP28768899A JP28768899A JP2001111408A JP 2001111408 A JP2001111408 A JP 2001111408A JP 28768899 A JP28768899 A JP 28768899A JP 28768899 A JP28768899 A JP 28768899A JP 2001111408 A JP2001111408 A JP 2001111408A
Authority
JP
Japan
Prior art keywords
wiring
output
circuit
input
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28768899A
Other languages
Japanese (ja)
Inventor
Takeshi Nakano
健 中野
Tatsuya Nagata
達也 永田
Masayuki Shirai
優之 白井
Noboru Shiozawa
昇 塩沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP28768899A priority Critical patent/JP2001111408A/en
Publication of JP2001111408A publication Critical patent/JP2001111408A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Noise Elimination (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide high speed signal transmission wire packaging structure capable of reducing jitters by suppressing the timewise oscillation of a signal caused by a reflected wave reciprocally transmitted through a transmission wire for connecting a transmitting side semiconductor device to a receiving side semiconductor device especially in a signal transmission system consisting of the transmitting side and the receiving side. SOLUTION: A distance from a node between an output circuit of a semiconductor device 15a to be an impedance mismatched position of a transmitting substrate 100 and an output wire 16a to a node 26 to be an impedance mismatched position of a receiving substrate 200 is determined so that signal transmission time becomes integer times a half of a signal switching period. Consequently the influence of jitters due to a signal reflected by each of impedance mismatched positions of both the substrates 100, 200, is restrained so that the high speed signal transmission wire packaging structure capable of resisting signal transmission of a short signal switching period can be provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は送信側と受信側にそ
れぞれ信号処理用の半導体素子をもつ信号伝送配線実装
構造に係り、特に、送信側及び受信側のそれぞれにイン
ピーダンス不整合個所をもつ高速信号伝送配線実装構造
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission wiring mounting structure having a semiconductor element for signal processing on each of a transmission side and a reception side, and more particularly, to a high-speed circuit having impedance mismatching portions on each of a transmission side and a reception side. The present invention relates to a signal transmission wiring mounting structure.

【0002】[0002]

【従来の技術】高速信号伝送配線構造で、信号反射を抑
え、送信側回路と受信側回路との整合を取るには、通常
は送信側信号伝送回路と、受信側信号伝送回路と、伝送
用配線の特性インピーダンスを等しくする方法が取られ
ている。信号伝送配線構造に関しては、例えば特開平5
−27697号公報に記載のように、広帯域駆動回路を
備えた受像管に対する信号伝送回路で、駆動回路基板上
の電圧増幅トランジスタの出力インピーダンスと、伝送
線のインピーダンスと、受像管基板上の受端インピーダ
ンスとが等しくなる伝送配線構造が報告されている。
2. Description of the Related Art In a high-speed signal transmission wiring structure, a signal transmission circuit, a reception signal transmission circuit, a transmission signal transmission circuit, a reception signal transmission circuit, and a transmission signal transmission circuit are usually used in order to suppress signal reflection and match the transmission circuit and the reception circuit. A method of equalizing the characteristic impedance of the wiring has been adopted. Regarding the signal transmission wiring structure, for example,
As described in JP-A-27697, a signal transmission circuit for a picture tube provided with a broadband drive circuit, the output impedance of a voltage amplification transistor on a drive circuit board, the impedance of a transmission line, and the receiving end on a picture tube substrate A transmission wiring structure having the same impedance has been reported.

【0003】[0003]

【発明が解決しようとする課題】コンピュータ等の電子
装置は動作の高速化が求められており、高速で大規模な
処理を可能とする信号処理回路、及び処理された信号を
高速に伝送するインターフェース及び信号伝送配線構造
が必要となっている。特に、高速信号伝送で反射波があ
ると、本来の伝送信号に反射波が重畳し波形の乱れが生
じ、ジッタとよばれる信号の時間的な揺らぎが増加す
る。このジッタは電子装置の誤動作の原因となるため極
力小さくする必要がある。そのため、反射波の影響を小
さくする信号伝送配線実装構造を設計する必要がある。
An electronic device such as a computer is required to operate at a high speed. A signal processing circuit capable of performing a high-speed and large-scale processing, and an interface for transmitting a processed signal at a high speed. In addition, a signal transmission wiring structure is required. In particular, if there is a reflected wave in high-speed signal transmission, the reflected wave is superimposed on the original transmission signal, causing waveform distortion, and the temporal fluctuation of the signal called jitter increases. Since this jitter causes a malfunction of the electronic device, it is necessary to minimize the jitter. Therefore, it is necessary to design a signal transmission wiring mounting structure that reduces the influence of the reflected wave.

【0004】信号伝送系で、送信した信号を受信側基板
に伝送する際には、伝送用配線の長さに比例して伝播す
る信号に遅延が生じる。伝送系の特性インピーダンスが
すべて等しく、整合が取れている回路では波形の乱れを
生じることなく信号を伝送することができる。特開平5
−27697号公報では、前記理想的な信号伝送系を構
成することで、信号反射波を抑えることができることを
示している。しかし、例えばCMOSトランジスタを用
いた高速信号伝送系では、CMOSトランジスタの出力
インピーダンスを、基板配線やケーブル等の伝送系を構
成する他の要素の特性インピーダンスと一致させること
は難しい。そのため、CMOSトランジスタの出力段で
インピーダンス不整合となり、信号反射波を完全に抑え
ることはできない。また、受信側の半導体装置の入力回
路は容量性の負荷となり、受信した信号は全反射する。
半導体装置の入力回路近傍に終端抵抗を取り付けても、
この容量性の負荷があるため完全には信号反射を防止す
ることはできない。
When a transmitted signal is transmitted to a receiving substrate in a signal transmission system, a delay occurs in a signal propagated in proportion to the length of a transmission line. In a circuit in which the characteristic impedances of the transmission systems are all equal and are matched, signals can be transmitted without causing waveform disturbance. JP 5
Japanese Unexamined Patent Publication (Kokai) No. -27697 discloses that by configuring the ideal signal transmission system, a signal reflected wave can be suppressed. However, for example, in a high-speed signal transmission system using a CMOS transistor, it is difficult to match the output impedance of the CMOS transistor with the characteristic impedance of other elements constituting the transmission system such as a substrate wiring and a cable. For this reason, impedance mismatch occurs at the output stage of the CMOS transistor, and it is not possible to completely suppress the signal reflected wave. Further, the input circuit of the semiconductor device on the receiving side becomes a capacitive load, and the received signal is totally reflected.
Even if a termination resistor is attached near the input circuit of the semiconductor device,
Due to this capacitive load, signal reflection cannot be completely prevented.

【0005】本発明の目的は、送信側及び受信側の信号
配線基板のそれぞれにインピーダンス不整合個所をも
ち、両方の信号配線基板が伝送線で接続される高速信号
伝送配線実装構造に関し、インピーダンス不整合個所の
存在による反射波、特に送信側及び受信側の信号配線基
板を接続する伝送線を往復する反射波の影響を小さくす
るため、送信側及び受信側の信号配線基板を接続する伝
送線の構造及び長さを定義し、ジッタを低減できる高速
信号伝送配線実装構造を提供することにある。
An object of the present invention is to provide a high-speed signal transmission wiring mounting structure in which each of the signal wiring boards on the transmission side and the reception side has an impedance mismatching portion and both signal wiring boards are connected by transmission lines. To reduce the effect of reflected waves due to the presence of matching points, especially reflected waves that reciprocate on the transmission line connecting the transmission side and reception side signal wiring boards, the transmission line connecting the transmission side and reception side signal wiring boards An object of the present invention is to provide a high-speed signal transmission wiring mounting structure capable of defining a structure and a length and reducing jitter.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、出力回路を有する第1の半導体装置を搭載し、前記
出力回路と接続する出力配線及び前記出力配線に接続す
る送端手段を設けた第1の基板からなる送信基板と、入
力回路を有する第2の半導体装置を搭載し、前記入力回
路と接続する入力配線及び前記入力配線に接続する終端
手段を設けた第2の基板からなる受信基板と、前記出力
配線と前記入力配線を接続したケーブルとからなり、前
記出力回路の出力インピーダンスは前記出力配線、前記
ケーブル及び前記入力配線の特性インピーダンスと異な
る高速信号伝送配線実装構造において、前記送端手段は
反射波に対して整合であり、かつ前記出力回路と前記出
力配線の接続点と、前記入力配線と前記終端手段の接続
点との間を伝播する信号の往復伝送時間は、前記信号の
切替周期の整数倍としたものである。
In order to achieve the above object, a first semiconductor device having an output circuit is mounted, and an output wiring connected to the output circuit and a sending end means connected to the output wiring are provided. And a second substrate on which a second semiconductor device having an input circuit is mounted, and an input wiring connected to the input circuit and a terminating means connected to the input wiring are provided. A receiving board, comprising a cable connecting the output wiring and the input wiring, wherein an output impedance of the output circuit is different from a characteristic impedance of the output wiring, the cable and the input wiring, and a high-speed signal transmission wiring mounting structure; The sending end means is matched to the reflected wave and propagates between a connection point between the output circuit and the output wiring and a connection point between the input wiring and the termination means. Round-trip transmission time of the signal is obtained by an integral multiple of the switching period of the signal.

【0007】また、上記目的を達成するために、前記送
端抵抗は反射波に対して不整合であり、かつ前記送端手
段と前記出力配線の接続点と、前記入力配線と前記終端
手段の接続点との間を伝播する信号の往復伝送時間が、
前記信号の切替周期の整数倍としたものである。
In order to achieve the above object, the transmitting end resistance is mismatched with respect to a reflected wave, and a connection point between the transmitting end means and the output wiring, and a connection point between the input wiring and the terminating means are provided. The round trip transmission time of the signal propagating between the connection points is
This is an integral multiple of the signal switching period.

【0008】また、前記送信基板の反射波に対するイン
ピーダンス不整合の最大の点と、前記受信基板の進行波
に対するインピーダンス不整合の最大の点との間を伝播
する信号の往復伝送時間は、前記信号の切替周期の整数
倍としたものである。
The round-trip transmission time of a signal propagating between the point of maximum impedance mismatch with respect to the reflected wave of the transmitting board and the maximum point of impedance mismatch with respect to the traveling wave of the receiving board is the signal round-trip time. Is an integral multiple of the switching period.

【0009】また、前記出力回路及び送端手段及び配線
の接続点のうち、反射波に対するインピーダンス不整合
の最大の点と、前記配線と終端抵抗の接続点との間を伝
播する信号の往復伝送時間が、前記信号の切替周期の整
数倍としたものである。
[0009] Also, of the connection points of the output circuit, the transmitting end means and the wiring, a round-trip transmission of a signal propagating between the maximum point of impedance mismatch with respect to the reflected wave and the connection point of the wiring and the terminating resistor. The time is an integer multiple of the signal switching period.

【0010】[0010]

【発明の実施の形態】以下、本発明の高速信号伝送配線
実装構造の一実施例を図1から図3を用いて説明する。
まず、本実施例の回路及び構造を、それぞれ図1の回路
図及び図2の構造斜視図を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a high-speed signal transmission wiring mounting structure according to the present invention will be described below with reference to FIGS.
First, the circuit and structure of the present embodiment will be described with reference to the circuit diagram of FIG. 1 and the structural perspective view of FIG. 2, respectively.

【0011】第1の基板11aに出力回路21を設けた
第1の半導体装置15aを搭載し、第1の基板11a上
に配置した出力配線16aを介して送端回路24に接続
する。さらに、出力配線16aに接続して、送信基板1
00を構成する。出力配線16aにケーブル300を介
して、受信基板200を構成している、第2の基板11
b上に配置した受信配線16bに接続する。さらに、受
信配線16bに終端手段25を接続し、受信配線16b
を介して第2の半導体装置15bに設けた入力回路23
に接続する。
A first semiconductor device 15a provided with an output circuit 21 is mounted on a first substrate 11a, and is connected to a sending terminal circuit 24 via an output wiring 16a disposed on the first substrate 11a. Further, the transmission board 1 is connected to the output wiring 16a.
00. The second substrate 11 constituting the receiving substrate 200 via the cable 300 to the output wiring 16a
b, and is connected to the receiving wiring 16b. Further, the terminating means 25 is connected to the receiving wiring 16b,
Via the input circuit 23 provided in the second semiconductor device 15b
Connect to

【0012】図1に示すように、出力回路21から送端
手段24及び終端手段25は、抵抗18を用いて構成す
る。送端回路24は、出力配線16aに直列に抵抗18
を配置すると共に、ケーブル300側の出力配線16a
との接続点から基準電位に抵抗18を配置する。一方、
終端手段25は入力配線16bと基準電位との間を抵抗
18によって接続する構成としている。
As shown in FIG. 1, the output circuit 21 to the sending end means 24 and the terminating means 25 are constituted by using a resistor 18. The sending end circuit 24 includes a resistor 18 connected in series with the output wiring 16a.
And the output wiring 16a on the cable 300 side.
A resistor 18 is arranged at a reference potential from a connection point with the resistor 18. on the other hand,
The terminating means 25 is configured to connect the input wiring 16b and the reference potential by the resistor 18.

【0013】図2の実装斜視図に示すように、実装しや
すいように、第1及び第2の半導体装置15a、15b
を半導体パッケージ14a、14bに搭載した。また、
送信基板100とケーブル300と受信基板200と
を、コネクタ17を用いて接続しているが、不可欠な構
成ではない。
As shown in the mounting perspective view of FIG. 2, first and second semiconductor devices 15a and 15b
Was mounted on the semiconductor packages 14a and 14b. Also,
Although the transmission board 100, the cable 300, and the reception board 200 are connected using the connector 17, this is not an essential configuration.

【0014】次に、本実施例の動作を説明する。出力回
路21より送信されたディジタル信号は、出力配線16
a、送端手段24、出力配線16a、コネクタ17、ケ
ーブル300、入力配線16b、終端手段25、入力配
線16bを通って入力回路23に伝送される。この間、
各部分のインピーダンスの異なる部分で信号の一部が反
射されるが、接続点前後の部分のインピーダンスの違い
が大きいほど反射波の振幅は大きくなる。特に終端手段
25と入力配線16bとの接続点26で両者が並列接続
となりインピーダンスが大きく低下するため、大きな反
射波が送信基板100に戻ることになる。
Next, the operation of this embodiment will be described. The digital signal transmitted from the output circuit 21 is output from the output wiring 16.
a, the transmission end means 24, the output wiring 16a, the connector 17, the cable 300, the input wiring 16b, the terminating means 25, and the input wiring 16b are transmitted to the input circuit 23. During this time,
Although a part of the signal is reflected by the portions having different impedances of the respective portions, the amplitude of the reflected wave increases as the difference in impedance between the portions before and after the connection point increases. In particular, since the two are connected in parallel at the connection point 26 between the terminating means 25 and the input wiring 16b and the impedance is greatly reduced, a large reflected wave returns to the transmission board 100.

【0015】反射波は逆の経路を戻り出力回路21に至
る。この間、送端手段は反射波に対して整合しており、
ここではさらなる反射は発生しない。出力回路21に至
った反射波は、出力回路21の出力インピーダンスが出
力配線16aと異なっている。このため、さらにこれら
の接続点で反射される。この往復反射波は、同じ時刻に
送信されたディジタル信号と重畳して入力回路23に至
り、電圧変動を生じて好ましくないジッタを発生させ
る。
The reflected wave returns to the output circuit 21 through the reverse route. During this time, the sending end means is aligned with the reflected wave,
No further reflections occur here. The reflected wave reaching the output circuit 21 has an output impedance of the output circuit 21 different from that of the output wiring 16a. Therefore, the light is further reflected at these connection points. The reciprocating reflected wave is superimposed on the digital signal transmitted at the same time and reaches the input circuit 23, causing a voltage fluctuation to generate an undesirable jitter.

【0016】本実施例の高速信号伝送配線実装構造に切
替周期、即ち、信号が1から0、あるいは0から1に切
替る時の0あるいは1の最小の時間が1nsのディジタ
ル信号を入力したとき、ケーブル300の長さを100
cmから114cmの範囲で変化させてジッタ量を解析
した結果の一例を図3に示す。
When a digital signal of 1 ns is input to the high-speed signal transmission wiring mounting structure of this embodiment, the switching period, that is, the minimum time of 0 or 1 when the signal is switched from 1 to 0 or from 0 to 1 , The length of the cable 300 to 100
FIG. 3 shows an example of the result of analyzing the jitter amount while changing the range from cm to 114 cm.

【0017】長さ13cmの周期でジッタが周期的に変
化することがわかった。往復長さの周期26cmは、本
実施例で信号が時間1nsの間に伝播する距離に相当す
る。ジッタが極小となるケーブル13の長さ106cm
の場合で、出力回路21と受信側配線分岐26との往復
経路の信号伝送遅延時間を算出すると、1Gbit/s
ディジタル信号の切替周期1nsの整数倍の時間とな
る。すなわち、出力回路21と受信側配線分岐26との
間の距離を、信号伝送時間が信号切替周期の半分の時
間、500psの整数倍となるように定めることによ
り、ジッタを極小にすることができることがわかった。
It has been found that the jitter periodically changes with a period of 13 cm in length. The cycle of the reciprocating length of 26 cm corresponds to the distance over which the signal propagates during a time of 1 ns in this embodiment. The length of the cable 13 that minimizes jitter is 106cm
, The signal transmission delay time of the reciprocating path between the output circuit 21 and the receiving-side wiring branch 26 is calculated as 1 Gbit / s
This is an integral multiple of the digital signal switching period of 1 ns. That is, the jitter can be minimized by determining the distance between the output circuit 21 and the receiving-side wiring branch 26 so that the signal transmission time is half the signal switching period and an integral multiple of 500 ps. I understood.

【0018】本実施例では送信基板及び受信基板はそれ
ぞれ1つであり、また、出力回路、入力回路も半導体装
置に1つある場合を示したが、これに限定されるもので
はなく、複数の信号配線基板をもち、伝送用配線及びケ
ーブルで接続され、高速な信号を伝送する配線実装構造
に適用可能であることは言うまでもない。
In this embodiment, there is shown a case where the number of the transmission board and the number of the reception board are one, and the output circuit and the input circuit are also one in the semiconductor device. However, the present invention is not limited to this. It goes without saying that the present invention is applicable to a wiring mounting structure that has a signal wiring board, is connected by transmission wiring and a cable, and transmits high-speed signals.

【0019】次に、本発明の他の一実施例を図4の回路
図を用いて説明する。この回路図では、図1の回路図と
比較すると、送端手段24の構成のみ異なっているた
め、重複する説明は省略する。
Next, another embodiment of the present invention will be described with reference to the circuit diagram of FIG. This circuit diagram differs from the circuit diagram of FIG. 1 only in the configuration of the sending end means 24, and therefore, duplicate description will be omitted.

【0020】本実施例の送端手段24では、抵抗の配置
を変えて出力回路21から入力回路23へ送信する信号
波との整合をとっており、反射波に対しては不整合とな
っている点が異なる。出力回路21から送信された信号
の一部は、先の実施例と同じく終端手段25と入力配線
16bとの接続点26で反射され、送端手段24に向か
って伝送される。送端手段24は反射波に対して不整合
のため、伝送された反射波は送端手段24でさらに反射
されて入力回路23に向かって伝送される。この往復反
射波は同じ時刻に伝送されるディジタル信号に重畳して
入力回路23に至り、電圧変動を生じて好ましくないジ
ッタを発生させる。
In the transmitting means 24 of this embodiment, the arrangement of the resistors is changed to match the signal wave transmitted from the output circuit 21 to the input circuit 23, and the signal wave is mismatched with respect to the reflected wave. Are different. A part of the signal transmitted from the output circuit 21 is reflected at the connection point 26 between the terminating means 25 and the input wiring 16b as in the previous embodiment, and transmitted toward the transmitting end means 24. Since the transmitting end unit 24 is not matched with the reflected wave, the transmitted reflected wave is further reflected by the transmitting end unit 24 and transmitted toward the input circuit 23. This reciprocating reflected wave is superimposed on the digital signal transmitted at the same time and reaches the input circuit 23, which causes a voltage fluctuation and generates undesirable jitter.

【0021】本実施例では、ケーブル300側の出力配
線16aと送端手段24との接続点と、受信側配線分岐
26が主な反射点となる。すなわち、送信側配線分岐4
1と受信側配線分岐26との間の距離を、信号伝送時間
が信号切替周期の半分の時間の整数倍となるように定め
ることにより、ジッタを極小にすることができる。本実
施例では、送信基板及び受信基板はそれぞれ1つであ
る。また、出力回路、入力回路も半導体装置に1つの場
合を示したが、これに限定されるものではなく、複数の
信号配線基板をもち、伝送用配線及びケーブルで接続さ
れ、高速な信号を伝送する配線実装構造に適用可能であ
ることは言うまでもない。
In this embodiment, the connection point between the output wiring 16a on the cable 300 side and the sending end means 24 and the receiving wiring branch 26 are the main reflection points. That is, the transmission side wiring branch 4
Jitter can be minimized by setting the distance between 1 and the receiving-side wiring branch 26 such that the signal transmission time is an integral multiple of half the signal switching period. In this embodiment, there is one transmission board and one reception board. In addition, although one output circuit and one input circuit are shown in the semiconductor device, the present invention is not limited to this case. The semiconductor device has a plurality of signal wiring boards, is connected by transmission wiring and cables, and transmits high-speed signals. It is needless to say that the present invention can be applied to a wiring mounting structure.

【0022】先の2つの実施例で共通であるのは、送信
基板100の反射波に対するインピーダンスの不整合の
最大の点と、受信基板200の進行波に対するインピー
ダンス不整合の最大となる点との間の距離を、両者の間
を伝播する信号の往復伝送時間が信号の切替周期の整数
倍とすることによってジッタを低減できると言うことで
ある。
The two embodiments have in common that the point of maximum impedance mismatch for the reflected wave of the transmitting board 100 and the point of maximum impedance mismatch for the traveling wave of the receiving board 200. Jitter can be reduced by setting the distance between them to be an integral multiple of the signal switching period for the round trip transmission time of the signal propagating between them.

【0023】次に、本発明の他の一実施例の回路図を図
5に示す。図1で説明した実施例と構成及び効果はほと
んど同じであるので、図1と同一の部分の説明は省略す
る。出力回路21、入力回路23のそれぞれが実装され
た半導体装置15a、15b及び伝送用配線16、送端
手段24、終端手段25が同一の実装基板71に実装さ
れてケーブルが無くなっており、この点を除けば図1の
回路図と等しい配置である。本実施例では、出力回路2
1と配線16との接続点が主な反射点となる。すなわ
ち、この接続点と、終端手段25と配線16との接続点
26との間の長さを、信号伝送時間が信号切替周期の半
分の時間の整数倍となるように定めることにより、ジッ
タを極小にすることができる。本発明は図7に示す配線
実装構造に限定されるものではなく、一般に信号伝送系
の送信側及び受信側に反射の原因となるインピーダンス
不整合個所をもつ高速信号伝送配線実装構造に適用可能
である。
Next, a circuit diagram of another embodiment of the present invention is shown in FIG. Since the configuration and effects are almost the same as those of the embodiment described with reference to FIG. 1, the description of the same parts as in FIG. 1 will be omitted. The semiconductor devices 15a and 15b on which the output circuit 21 and the input circuit 23 are mounted, the transmission wiring 16, the transmitting end means 24, and the terminating means 25 are mounted on the same mounting substrate 71, and the cable is eliminated. The arrangement is the same as that of the circuit diagram of FIG. In this embodiment, the output circuit 2
The connection point between 1 and the wiring 16 is the main reflection point. That is, by determining the length between this connection point and the connection point 26 between the terminating means 25 and the wiring 16 so that the signal transmission time is an integral multiple of half the signal switching period, jitter can be reduced. Can be minimal. The present invention is not limited to the wiring mounting structure shown in FIG. 7, but is generally applicable to a high-speed signal transmission wiring mounting structure having impedance mismatching points on the transmission side and the reception side of a signal transmission system that cause reflection. is there.

【0024】次に、先に述べた実施例の共通する別の応
用実施例を図6及び図7を用いて説明する。
Next, another applied embodiment common to the above-described embodiment will be described with reference to FIGS. 6 and 7. FIG.

【0025】図6の実施例では終端手段25を基板11
ではなく、第2の半導体装置に設けた構成となってお
り、他の構造及び効果は先の実施例と同一であるので省
略する。本実施例によれば終端手段25を第2の半導体
装置に設けているので、小型の実装が可能となる効果が
ある。
In the embodiment shown in FIG.
Instead, the configuration is provided in the second semiconductor device, and the other structures and effects are the same as those of the previous embodiment, and a description thereof will be omitted. According to the present embodiment, since the terminating means 25 is provided in the second semiconductor device, there is an effect that small mounting is possible.

【0026】また、図7の実施例では図1の実施例と比
較して、送端手段24と終端手段25の間にコンデンサ
61a、61bを設けている点が異なっている。本実施
例によれば図1の実施例の効果に加えて、送信基板10
0と受信基板200とは交流でのみ接続されるため、送
信基板100と受信基板200の直流電圧を異なる値で
使用できる効果がある。
The embodiment shown in FIG. 7 is different from the embodiment shown in FIG. 1 in that capacitors 61a and 61b are provided between the sending means 24 and the terminating means 25. According to this embodiment, in addition to the effects of the embodiment of FIG.
Since 0 and the receiving board 200 are connected only by alternating current, there is an effect that the DC voltages of the transmitting board 100 and the receiving board 200 can be used with different values.

【0027】[0027]

【発明の効果】前述の構成とすることにより、送信側及
び受信側の信号配線基板のそれぞれにインピーダンス不
整合個所をもち、両方の信号配線基板が伝送線で接続さ
れる高速信号伝送配線実装構造に関し、インピーダンス
不整合個所の存在による反射波、特に送信側及び受信側
の信号配線基板を接続する伝送線を往復する反射波の影
響を小さくするため、送信側及び受信側の信号配線基板
を接続する伝送線の構造及び長さを定義し、ジッタを低
減できる高速信号伝送配線実装構造を実現した。
According to the above-described structure, the high-speed signal transmission wiring mounting structure in which each of the signal wiring substrates on the transmission side and the reception side has an impedance mismatching portion and both signal wiring substrates are connected by transmission lines. In order to reduce the effect of reflected waves due to the presence of impedance mismatching points, particularly reflected waves reciprocating in the transmission line connecting the signal wiring boards on the transmitting and receiving sides, connect the signal wiring boards on the transmitting and receiving sides. We defined the structure and length of the transmission line to be used, and realized a high-speed signal transmission wiring mounting structure that can reduce jitter.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of one embodiment of the present invention.

【図2】本発明の一実施例の斜視図である。FIG. 2 is a perspective view of one embodiment of the present invention.

【図3】本発明の一実施例のケーブル長さとジッタとの
関係を表した図である。
FIG. 3 is a diagram illustrating a relationship between a cable length and a jitter according to an embodiment of the present invention.

【図4】本発明の他の一実施例の回路図である。FIG. 4 is a circuit diagram of another embodiment of the present invention.

【図5】本発明の他の一実施例の回路図である。FIG. 5 is a circuit diagram of another embodiment of the present invention.

【図6】本発明の他の一実施例の回路図である。FIG. 6 is a circuit diagram of another embodiment of the present invention.

【図7】本発明の他の一実施例の回路図である。FIG. 7 is a circuit diagram of another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11…基板、11a…第1の基板、11b…第2の基
板、14…半導体パッケージ、15a…第1の半導体装
置、15b…第2の半導体装置、16…配線、16a…
出力配線、16b…入力配線、17…コネクタ、18…
チップ抵抗、19…スルーホール、21…出力回路、2
3…入力回路、24…送端手段、25…終端手段、26
…入力配線分岐、41…出力配線分岐、61…コンデン
サ、71…実装基板、100…送信基板、200…受信
基板、300…ケーブル。
11 ... substrate, 11a ... first substrate, 11b ... second substrate, 14 ... semiconductor package, 15a ... first semiconductor device, 15b ... second semiconductor device, 16 ... wiring, 16a ...
Output wiring, 16b Input wiring, 17 Connector, 18
Chip resistor, 19: through hole, 21: output circuit, 2
3 input circuit, 24 transmission end means, 25 termination means, 26
... input wiring branch, 41 ... output wiring branch, 61 ... capacitor, 71 ... mounting board, 100 ... transmission board, 200 ... reception board, 300 ... cable.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 白井 優之 東京都青梅市新町六丁目16番地の3 株式 会社日立製作所デバイス開発センタ内 (72)発明者 塩沢 昇 東京都青梅市新町六丁目16番地の3 株式 会社日立製作所デバイス開発センタ内 Fターム(参考) 5J056 AA01 AA04 AA40 BB23 BB24 DD13 FF08 HH03 KK02 5K029 AA03 CC01 DD04 GG07 HH01 JJ08 5K046 AA01 BA06 CC21 5K052 AA02 AA11 BB14 BB21 DD03 DD07 FF26 FF38 GG01 GG12 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Yuyuki Shirai 6-16-16, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Noboru 6-16, Shinmachi, Ome-shi, Tokyo F-term in Hitachi, Ltd. Device Development Center Co., Ltd. (reference)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】出力回路を有する第1の半導体装置を搭載
し、前記出力回路と接続する出力配線及び前記出力配線
に接続する送端手段を設けた第1の基板からなる送信基
板と、入力回路を有する第2の半導体装置を搭載し、前
記入力回路と接続する入力配線及び前記入力配線に接続
する終端手段を設けた第2の基板からなる受信基板と、
前記出力配線と前記入力配線を接続したケーブルとから
なり、前記出力回路の出力インピーダンスは前記出力配
線、前記ケーブル及び前記入力配線の特性インピーダン
スと異なる高速信号伝送配線実装構造において、 前記送端手段は反射波に対して整合であり、かつ前記出
力回路と前記出力配線の接続点と、前記入力配線と前記
終端手段の接続点との間を伝播する信号の往復伝送時間
は、前記信号の切替周期の整数倍であることを特徴とす
る高速信号伝送配線実装構造。
1. A transmission board comprising a first substrate on which a first semiconductor device having an output circuit is mounted, an output wiring connected to the output circuit, and a sending end means connected to the output wiring. A receiving substrate including a second semiconductor device having a circuit, a second substrate provided with an input wiring connected to the input circuit, and a termination unit connected to the input wiring;
A high-speed signal transmission wiring mounting structure comprising a cable connecting the output wiring and the input wiring, wherein an output impedance of the output circuit is different from a characteristic impedance of the output wiring, the cable and the input wiring. The round-trip transmission time of a signal that is matched to the reflected wave and propagates between the connection point of the output circuit and the output wiring and the connection point of the input wiring and the terminating means is the switching cycle of the signal. A high-speed signal transmission wiring mounting structure characterized by being an integral multiple of.
【請求項2】出力回路を有する第1の半導体装置を搭載
し、前記出力回路と接続する出力配線及び前記出力配線
に接続する送端手段を設けた第1の基板からなる送信基
板と、入力回路を有する第2の半導体装置を搭載し、前
記入力回路と接続する入力配線及び前記入力配線に接続
する終端手段を設けた第2の基板からなる受信基板と、
前記出力配線と前記入力配線を接続したケーブルとから
なる高速信号伝送配線実装構造において、 前記送端抵抗は反射波に対して不整合であり、かつ前記
送端手段と前記出力配線の接続点と、前記入力配線と前
記終端手段の接続点との間を伝播する信号の往復伝送時
間が、前記信号の切替周期の整数倍であることを特徴と
する高速信号伝送配線実装構造。
2. A transmission board comprising a first substrate on which a first semiconductor device having an output circuit is mounted, an output wiring connected to the output circuit, and a sending end means connected to the output wiring are provided. A receiving substrate including a second semiconductor device having a circuit, a second substrate provided with an input wiring connected to the input circuit, and a termination unit connected to the input wiring;
In the high-speed signal transmission wiring mounting structure including the output wiring and the cable connected to the input wiring, the sending end resistance is mismatched with respect to a reflected wave, and a connection point between the sending end means and the output wiring. A high-speed signal transmission wiring mounting structure, wherein a round-trip transmission time of a signal propagating between the input wiring and a connection point of the terminating means is an integral multiple of a switching cycle of the signal.
【請求項3】出力回路を有する第1の半導体装置を搭載
し、前記出力回路と接続する出力配線及び前記出力配線
に接続する送端手段を設けた第1の基板からなる送信基
板と、入力回路を有する第2の半導体装置を搭載し、前
記入力回路と接続する入力配線及び前記入力配線に接続
する終端手段を設けた第2の基板からなる受信基板と、
前記出力配線と前記入力配線を接続したケーブルとから
なる高速信号伝送配線実装構造において、 前記送信基板の反射波に対するインピーダンス不整合の
最大の点と、前記受信基板の進行波に対するインピーダ
ンス不整合の最大の点との間を伝播する信号の往復伝送
時間は、前記信号の切替周期の整数倍であることを特徴
とする高速信号伝送配線実装構造。
3. A transmission board comprising a first substrate on which a first semiconductor device having an output circuit is mounted, and an output wiring connected to the output circuit, and a sending end means connected to the output wiring are provided. A receiving substrate including a second semiconductor device having a circuit, a second substrate provided with an input wiring connected to the input circuit, and a termination unit connected to the input wiring;
In the high-speed signal transmission wiring mounting structure including the output wiring and the cable connected to the input wiring, the maximum point of the impedance mismatch with respect to the reflected wave of the transmission board and the maximum of the impedance mismatch with respect to the traveling wave of the reception board. Wherein the round-trip transmission time of a signal propagating between the point and the point is an integral multiple of the signal switching period.
【請求項4】出力回路を有する第1の半導体装置と、入
力回路を有する第2の半導体装置とを搭載し、前記出力
回路と前記入力回路とを接続する配線を設け、前記出力
回路近傍に前記配線に接続する送端手段を設け、前記入
力回路近傍に前記配線に接続する終端手段を設けた基板
とからなる高速信号伝送配線実装構造において、 前記出力回路及び送端手段及び配線の接続点のうち、反
射波に対するインピーダンス不整合の最大の点と、前記
配線と終端抵抗の接続点との間を伝播する信号の往復伝
送時間が、前記信号の切替周期の整数倍であることを特
徴とする高速信号伝送配線実装構造。
4. A first semiconductor device having an output circuit and a second semiconductor device having an input circuit are mounted, and a wiring connecting the output circuit and the input circuit is provided. A high-speed signal transmission wiring mounting structure comprising: a substrate provided with transmitting means connected to the wiring; and a substrate provided with a terminating means connected to the wiring near the input circuit; a connection point of the output circuit, the transmitting means and the wiring; Among them, the maximum point of impedance mismatch with respect to the reflected wave, and the round-trip transmission time of the signal propagating between the wiring and the connection point of the terminating resistor, is an integral multiple of the signal switching period, High-speed signal transmission wiring mounting structure.
JP28768899A 1999-10-08 1999-10-08 Structure for packaging high speed signal transmission wire Pending JP2001111408A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28768899A JP2001111408A (en) 1999-10-08 1999-10-08 Structure for packaging high speed signal transmission wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28768899A JP2001111408A (en) 1999-10-08 1999-10-08 Structure for packaging high speed signal transmission wire

Publications (1)

Publication Number Publication Date
JP2001111408A true JP2001111408A (en) 2001-04-20

Family

ID=17720453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28768899A Pending JP2001111408A (en) 1999-10-08 1999-10-08 Structure for packaging high speed signal transmission wire

Country Status (1)

Country Link
JP (1) JP2001111408A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005085267A (en) * 2003-09-04 2005-03-31 Hewlett-Packard Development Co Lp Circuit for memory module address bus and system for addressing memory module
JP2006220660A (en) * 2005-02-11 2006-08-24 Advantest Corp Test device and test method
JP2006270935A (en) * 2005-02-25 2006-10-05 Mitsubishi Electric Corp Signal transmission circuit, ic package, and mounting board
WO2007046268A1 (en) * 2005-10-18 2007-04-26 Tama-Tlo Ltd. Semiconductor device and method for adjusting characteristics of semiconductor device
JP2007134685A (en) * 2005-10-12 2007-05-31 Canon Inc Printed circuit board
US7902938B2 (en) 2004-03-29 2011-03-08 Nec Corporation Data transmitter, data transmission line, and data transmission method
WO2012040468A2 (en) * 2010-09-22 2012-03-29 Texas Instruments Incorporated Low impedance transmission line
JP2017146736A (en) * 2016-02-16 2017-08-24 京セラドキュメントソリューションズ株式会社 Transmitting device and image forming apparatus including the same
JP2018107704A (en) * 2016-12-27 2018-07-05 ルネサスエレクトロニクス株式会社 Semiconductor device
CN112216615A (en) * 2019-07-09 2021-01-12 澜起科技股份有限公司 Substrate packaging method capable of adjusting signal transmission time and structure thereof
EP4300575A1 (en) * 2022-06-29 2024-01-03 INTEL Corporation Interconnect bridge with similar channel lengths
JP7446209B2 (en) 2020-12-03 2024-03-08 株式会社日立製作所 signal transmission equipment

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005085267A (en) * 2003-09-04 2005-03-31 Hewlett-Packard Development Co Lp Circuit for memory module address bus and system for addressing memory module
US7902938B2 (en) 2004-03-29 2011-03-08 Nec Corporation Data transmitter, data transmission line, and data transmission method
JP2006220660A (en) * 2005-02-11 2006-08-24 Advantest Corp Test device and test method
JP2006270935A (en) * 2005-02-25 2006-10-05 Mitsubishi Electric Corp Signal transmission circuit, ic package, and mounting board
US7595546B2 (en) 2005-10-12 2009-09-29 Canon Kabushiki Kaisha Printed circuit board
JP2007134685A (en) * 2005-10-12 2007-05-31 Canon Inc Printed circuit board
JP2007115737A (en) * 2005-10-18 2007-05-10 Tama Tlo Kk Semiconductor device and characteristic adjusting method thereof
US7804111B2 (en) 2005-10-18 2010-09-28 Tama-Tlo Ltd. Semiconductor device and method for adjusting characteristics thereof
WO2007046268A1 (en) * 2005-10-18 2007-04-26 Tama-Tlo Ltd. Semiconductor device and method for adjusting characteristics of semiconductor device
WO2012040468A2 (en) * 2010-09-22 2012-03-29 Texas Instruments Incorporated Low impedance transmission line
WO2012040468A3 (en) * 2010-09-22 2012-08-16 Texas Instruments Incorporated Low impedance transmission line
US8476687B2 (en) 2010-09-22 2013-07-02 Texas Instruments Incorporated Low impedance transmisson line
JP2017146736A (en) * 2016-02-16 2017-08-24 京セラドキュメントソリューションズ株式会社 Transmitting device and image forming apparatus including the same
JP2018107704A (en) * 2016-12-27 2018-07-05 ルネサスエレクトロニクス株式会社 Semiconductor device
US10027311B1 (en) 2016-12-27 2018-07-17 Renesas Electronics Corporation Semiconductor device
CN112216615A (en) * 2019-07-09 2021-01-12 澜起科技股份有限公司 Substrate packaging method capable of adjusting signal transmission time and structure thereof
CN112216615B (en) * 2019-07-09 2023-09-22 澜起科技股份有限公司 Substrate packaging method capable of adjusting signal transmission time and structure thereof
JP7446209B2 (en) 2020-12-03 2024-03-08 株式会社日立製作所 signal transmission equipment
EP4300575A1 (en) * 2022-06-29 2024-01-03 INTEL Corporation Interconnect bridge with similar channel lengths

Similar Documents

Publication Publication Date Title
JP3828652B2 (en) Differential signal transmission circuit
US8866282B2 (en) Semiconductor apparatus, signal transmission system and signal transmission method
JP2001111408A (en) Structure for packaging high speed signal transmission wire
JPH10190747A (en) Signal transmission system and transmission line driving circuit
US7595546B2 (en) Printed circuit board
EP1014615B1 (en) Full duplex transmission
SK10432000A3 (en) Impedance modulation signalling
US6249142B1 (en) Dynamically terminated bus
US8369369B2 (en) Systems, methods, and circuits for driving large off-chip loads
JP2008259093A (en) Output buffer circuit, and signal transmission interface circuit and apparatus
US7843281B2 (en) Circuit topology for multiple loads
US7746195B2 (en) Circuit topology for multiple loads
US6587907B1 (en) System and method for generating a clock delay within an interconnect cable assembly
EP0836302B1 (en) Communication system having a closed loop bus structure
JP4472274B2 (en) Signal transmission system and integrated circuit used therefor
US6246721B1 (en) Termination structure based on the cancellation of the reflected wave
JP2001094032A (en) Semiconductor device
US20060132577A1 (en) Circuit topology for high-speed printed circuit board
US8338992B2 (en) Transmission device using a plurality of elementary return conductors
KR100904845B1 (en) A transmission lines arrangement
US20240097948A1 (en) Connecting circuit and communication interface
JP2000292491A (en) Two branch transmission line and two branch driver circuit and semiconductor tester employing it
US20030147222A1 (en) Circuit board having an integrated circuit for high-speed data processing
JP2008252374A (en) Circuit board
US6509811B2 (en) Method for reducing the effects of signal reflections in a data communications network