JP2017127038A - Imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging device which can prevent decrease of a readout charging period when pixel signals are added.SOLUTION: An imaging device includes: plural pixel circuits (1) which are arranged in a matrix and generate pixel signals by photoelectric conversion; plural readout circuits (50) which are provided for each column of the plural pixel circuits and read out pixel signals of the pixel circuits of each column; 2n first output lines (5-1 to 5-8) which are commonly connected to output terminals of the readout circuits of every 2n column; and an adder for adding the pixel signals of plural pixel circuits of different columns. Only the readout circuits of any one column of the readout circuits of plural columns which are connected to the set of the pixel circuits to be added by the adder perform readout, and all of the 2n first output lines are supplied with pixel signals from any of the plural readout circuits.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an imaging apparatus and a driving method thereof.

  A high-speed readout method has been proposed for an area-type solid-state imaging device with multiple pixels (see, for example, Patent Document 1). In Patent Document 1, when signals from a plurality of readout circuits are read out to a plurality of horizontal output lines, a readout charge period (a settling time) for a plurality of columns is secured with respect to a signal for one column, and the signals are multiplexed. Thus, high-speed signal reading with low power consumption is possible.

JP 2005-143078 A

  However, in Patent Document 1, in a configuration in which there are even horizontal output lines, when thinning driving is performed such that reading is performed every even number of columns, a specific horizontal output line is driven at a high frequency, and a read charging period is set during normal reading. As a result, the signal amplitude is reduced.

  An object of the present invention is to provide an imaging apparatus and a driving method thereof that can prevent the readout charging period from being reduced when thinning driving or addition driving is performed.

  An imaging device according to the present invention is arranged in a matrix and is provided for each of a plurality of pixel circuits that generate pixel signals by photoelectric conversion, and for each column of the plurality of pixel circuits, and reads a pixel signal of the pixel circuit for each column. A plurality of readout circuits; 2n first output lines connected in common to output terminals of the readout circuits every 2n columns; and an adder that adds pixel signals of a plurality of pixel circuits in different columns. Then, only one column readout circuit among the plurality of readout circuits connected to the set of pixel circuits added by the addition unit performs readout, and the 2n first outputs All of the lines are characterized in that pixel signals are input from any of the plurality of readout circuits.

  When thinning driving or addition driving is performed, it is possible to prevent a reduction in the charging period of the first output line and a reduction in signal amplitude.

It is a block diagram of the imaging device by 1st Embodiment. 5 is a timing chart of all pixel readout according to the first embodiment. It is a figure which shows the structural example of a pixel circuit. It is a circuit diagram of addition thinning-out readout mode every two columns. It is a timing chart of addition thinning-out reading every two columns. It is a figure which shows the horizontal and vertical addition by 2nd Embodiment. It is a timing chart of addition thinning-out reading every two columns.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of an imaging apparatus according to the first embodiment of the present invention. The imaging device includes a plurality of pixel circuits 1 arranged in a two-dimensional matrix, and vertical signal lines 111-1 to 118-1 and 111-2 to 118-2 connected to output terminals of the pixel circuits 1 in the same column. Etc. The pixel circuit 1 generates a pixel signal by photoelectric conversion. The current source 4 of the pixel circuit 1 is connected to the vertical signal lines 111-1 to 118-1, 111-2 to 118-2, and the like. The plurality of readout circuits 50 are provided for each column of the plurality of pixel circuits 1 and read out pixel signals of the pixel circuits 1 for each column. Each column read circuit 50 includes an input transistor 2, current sources 3-1 to 3-11, and the like, and column selection switches 101-1 to 108-1, 101-2 to 108-2, and the like. The input transistor 2, the current source 3-1 and the like constitute a source follower circuit. The input transistor 2 has a gate connected to the vertical signal line 111-1 and the like, and a drain connected to the power supply potential node. The current sources 3-1 to 3-11 are connected between the source of the input transistor 2 and the ground potential node. The column selection switches 101-1 to 108-1, 101-2 to 108-2, etc. have their gates connected to the control lines 21-1 to 28-1, 21-2 to 28-2, etc., and their drains to the input transistor 2. Are connected to the first horizontal output lines 5-1 to 5-8. The sources of the column selection switches 101-1 to 108-1 are connected to the first horizontal output lines 5-1 to 5-8, respectively. The sources of the column selection switches 101-2 to 108-2 are connected to the first horizontal output lines 5-1 to 5-8, respectively. The column selection switches 101-1 to 108-1, 101-2 to 108-2, etc. are switches for connecting the source follower circuits 2, 3-1, etc. to the first horizontal output lines 5-1 to 5-8. It is. A plurality of pixel circuits 1 and readout circuits 50 are grouped into groups of 8 columns. For example, the first group includes vertical signal lines 111-1 to 118-1 and column selection switches 101-1 to 108-1. The second group includes vertical signal lines 111-2 to 118-2 and column selection switches 101-2 to 108-2. The number of first horizontal output lines 5-1 to 5-8 is not limited to eight, and may be 2n. n is an integer of 1 or more. The 2n first horizontal output lines 5-1 to 5-8 are commonly connected to the output terminals of the read circuit 50 every 2n columns.

  The current sources 3-1 to 3-8 and the column selection switches 101-1 to 108-1 and the like are turned on (conductive) / off by the control lines 21-1 to 28-1 and the like from the column selection switch control circuit 20. (Non-conducting) controlled. When the current source 3-1 and the like are controlled to be turned on, the read circuit 50 performs a read operation and the column selection switches 101-1 to 108-1 and the like are turned on. Are read out to the first horizontal output lines 5-1 to 5-8. Since the read circuit 50 stops operating due to the off control of the current source 3-1, etc., power consumption does not occur. The signals read to the first horizontal output lines 5-1 to 5-8 are held until the next column selection switch 101-1 is turned on. The signals read to the first horizontal output lines 5-1 to 5-8 are read to the second horizontal output line 6 by the group selection switches 31 to 38. The group selection switches 31 to 38 are controlled by the group selection control circuit 30 in units of groups. The column selection switch control circuit 20 and the group selection control circuit 30 are controlled by a read mode switching circuit 40 that controls a signal read mode. The signal readout mode includes an all-pixel readout mode for reading out signals from all the pixel circuits 1 and a thinning-out readout mode for reading out signals from some of the pixel circuits 1. When the readout mode switching circuit 40 designates the all-pixel readout mode, the column selection switch control circuit 20 drives the column selection switches 101-1 and the like of all groups. When designating the thinning readout mode, the column selection switch control circuit 20 drives only the readout circuit 50 of the group to be read out, the column selection switch 101-1, or the like.

  FIG. 2 is a flowchart illustrating the driving method in the all-pixel readout mode according to the first embodiment. In the present embodiment, eight columns are grouped into one group and overlapped while shifting the ON time of the adjacent readout circuits 50. Thus, for example, in the first column, the source follower circuit constituted by the input transistor 2 and the current source 3-1 charges the first horizontal output lines 5-1 to 5-8 having a large parasitic capacitance. To secure time. The signals on the first horizontal output lines 5-1 to 5-8 are read at high speed to the second horizontal output line 6 having a small parasitic capacitance.

  At time t1, the column selection switch control circuit 20 sets the control line 21-1 to the high level and turns on the column selection switch 101-1 and the current source 3-1. At this time, other current sources other than the current source 3-1 may be completely stopped, or a small current may flow. Since no signal is output to the second horizontal output line 6 until time t4 when the group selection switch 31 is turned on, the potential of the first horizontal output line 5-1 depends on the pixel signal of the pixel circuit 1. To the next level.

  Next, at time t2, the column selection switch control circuit 20 sets the control line 22-1 to a high level and turns on the column selection switch 102-1 and the current source 3-2. The potential of the first horizontal output line 5-2 transitions to a level corresponding to the pixel signal of the pixel circuit 1. Next, at time t3, the column selection switch control circuit 20 sets the control line 23-1 to the high level, and turns on the column selection switch 103-1 and the current source 3-3. The potential of the first horizontal output line 5-3 transitions to a level corresponding to the pixel signal of the pixel circuit 1. Although omitted in FIG. 2, the column selection switch 108-1 and the current source 3-8 are turned on at a constant time difference, and the first horizontal output lines 5-1 to 5-8 are turned on. Precharge to a potential corresponding to the pixel signal. Pixel signals of other groups are not read out to the first horizontal signal lines 5-1 to 5-8 because the current sources 3-9 and the column selection switch 101-2 and the like are off.

  Next, at time t4, the group selection switch 31 is turned on, and the signal in the first column of the first group charged in the first horizontal signal line 5-1 is read out to the second horizontal signal line 6. And output through the output amplifier 7.

  Next, at time t5, the column selection switch control circuit 20 sets the control line 21-1 to a low level, and turns off the column selection switch 101-1, the current source 3-1, and the group selection switch 31. At the same time or a little later, the column selection switch control circuit 20 sets the control line 21-2 to the high level, turns on the column selection switch 101-2 and the current source 3-9 of the second group, and outputs the first horizontal output. Charging is started at the potential of the line 5-1 to the potential corresponding to the signal of the vertical signal line 111-2.

  Next, at time t6, the column selection switch control circuit 20 sets the control line 22-1 to the low level, and turns off the column selection switch 102-1, the current source 3-2, and the group selection switch 32. At the same time or a little later, the column selection switch control circuit 20 sets the control line 22-2 to the high level, turns on the column selection switch 102-2 and the current source 3-10 of the second group, and the first horizontal output line The charging of the potential 5-2 is started to a potential corresponding to the signal of the vertical signal line 112-2.

  Next, at time t7, the column selection switch control circuit 20 sets the control line 23-1 to the low level and turns off the column selection switch 103-1, the current source 3-3, and the group selection switch 33. At the same time or a little later, the column selection switch control circuit 20 sets the control line 23-2 to high level, turns on the column selection switch 103-2 and the current source 3-11 of the second group, and outputs the first horizontal output line. The charging of the potential 5-3 is started to a potential corresponding to the signal of the vertical signal line 113-2. Thereafter, the same is repeated.

  As described above, the charging time of the pixel signals to the first horizontal output lines 5-1 to 5-8 is multiplexed between the groups. As a result, the settling time (charging time) of the first horizontal output lines 5-1 to 5-8 is secured, the data is read out to the second horizontal output line 6 at a high speed, and the current source is supplied only for the necessary minimum period. Since 3-1 etc. are turned on, there exists an effect which can reduce power consumption.

  The n pixel circuits 1 and n readout circuits 50 in the horizontal direction are configured in one group, and the drive start shift time of the source follower circuits 2, 3-1, etc. of each group is one column, and n Ensure driving time. Thereby, the read time of the final pixel signal of one column can be reduced to one column. In the present embodiment, eight columns are defined as one group, but one group may be configured by an arbitrary number of columns of two or more according to the number of pixels in the horizontal direction and the required driving speed. The readout circuit 50 described above is not limited to this, and may be a voltage follower circuit or a differential amplifier.

  Next, the thinning readout mode will be described. FIG. 3 is a circuit diagram illustrating a configuration example of the pixel circuits 1-1 to 1-3. The pixel circuits 1-1 to 1-3 correspond to the pixel circuit 1 in FIG. The photoelectric conversion element 81 is, for example, a photodiode, and generates pixel signals by converting incident light into electric charges. The pixel signal of the photoelectric conversion element 81 is sampled and held in the memory 82 through a pixel source follower and a clamp circuit. The addition switch (addition unit) 83 is a switch for connecting a plurality of pixel circuits 1-1, 1-2, and the like. In the thinning readout mode, the number of readout circuits 50 that become active is smaller than in the all-pixel readout mode. Here, an example in which pixel signals from pixels in different columns are added in the thinning readout mode will be described. In this case, the addition switch 83 is turned on by the control line 95-1, the signals of the memories 82 of the adjacent pixel circuits 1-1 and 1-2 are averaged, and the same averaged signal is the same for both pixel circuits 1. -1 and 1-2. The addition switch 83 adds the pixel signals of the plurality of pixel circuits 1-1 and 1-2 in different columns. The signal held in the memory 82 is output to the vertical signal lines 96-1 and 96-2 through the source follower by the control signal of the row selection line 93. The vertical signal lines 66-1 and 96-2 correspond to the vertical signal lines 111-1 and 112-1 in FIG.

  FIG. 4 shows a diagram in which the readout circuit 50 to be selected and the first horizontal output lines 5-1 to 5-8 are connected in the case of reading out by thinning out one column every two columns in order from the first column. . In order to make thinning easy to understand, in FIG. 4, the reading circuit 50 that does not perform thinning readout is not connected to the first horizontal output lines 5-1 to 5-8. The read circuit 50 includes the input transistor 2 of FIG. 1, the current source 3-1, etc., the column selection switch 101-1, and the like. In FIG. 4, thinning readout is performed by adding two pixels, and the first horizontal output line to be selected is first selected in the order of 5-1, 5-3, 5-5, 5-7, Next, selection is made in the order of 5-2, 5-4, 5-6, and 5-8. If 5-1, 5-3, 5-5, and 5-7 are selected repeatedly, the settling time (charging time) of the signal read from the first horizontal output line is halved. As a result, a correct signal may not be obtained. On the other hand, in the thinning readout in which one group of eight pixel columns is read out to the eight first horizontal output lines 5-1 to 5-8, the signal of the odd column readout circuit 50 is an odd number in the odd number group. The first horizontal output lines 5-1, 5-3, 5-5, and 5-7 are read out. In the even-numbered group, the signal of the even-numbered column readout circuit 50 is read out to the even-numbered first horizontal output lines 5-2, 5-4, 5-6, and 5-8. In other words, the first group (odd-numbered group) of the plurality of readout circuits 50 is the first group 5-1, 5-5 of the 2n first horizontal output lines 5-1 to 5-8. 3, 5-5 and 5-7 are output as pixel signals. The second group (even-numbered group) of the plurality of readout circuits 50 is the second group 5-2, 5- of the 2n first horizontal output lines 5-1 to 5-8. The pixel signals are output to 4, 5-6, and 5-8.

  FIG. 5 is a timing chart showing a driving method in the two-pixel addition thinning readout mode including the driving of the pixel circuit 1. At time t41, the pMOS transistor of the pixel enable line 91 is turned on by the low level of the pixel enable line 91, the pMOS transistor of the reset control line 94 is turned on by the low level of the reset control line 94, and the photodiode 81 is reset. To do. Thereafter, the pMOS transistor of the reset control line 94 is turned off by the high level of the reset control line 94.

  Next, at time t <b> 42, the pMOS transistor of the sample hold control line 92 is turned on by the low level of the sample hold control line 92, and the pixel signal of the photodiode 81 is sampled in the memory 82. Thereafter, the pMOS transistor of the sample hold control line 92 is turned off by the high level of the sample hold control line 92, and the signal is held in the memory 82.

  Next, at time t43, the pixel addition switch 83 is turned on by the low level of the control line 95-1, and the pixel signals in the memories 82 of the two adjacent pixel circuits 1-1 and 1-2 are added. For example, the signals of the pixels 1-1 and 1-2 are added, the signals of the pixels 1-3 and 1-4 are added, and thereafter, similarly, two pixels are added.

  Next, at time t44, the high level of the row selection line 93 turns on the nMOS transistor of the row selection line 93, and a signal corresponding to the signal of the memory 82 is output to the vertical signal line 96-1.

  Next, at time t45, the control line 21-1 becomes a high level, and the column selection switch 101-1 and the current source 3-1 of the read circuit 50 in the first column of the first group are turned on. Next, at time t46, the control line 23-1 becomes high level, and the column selection switch 103-1 and the current source 3-3 of the readout circuit 50 in the third column are turned on. Since the control line 22-1 is maintained at the low level, the column selection switch 102-1 and the current source 3-2 of the read circuit 50 in the second column remain off. Next, at time t47, the control line 25-1 becomes high level, and the column selection switch 105-1 and the current source 3-5 of the read circuit 50 in the fifth column are turned on. Since the control line 24-1 is maintained at the low level, the column selection switch 104-1 and the current source 3-4 of the read circuit 50 in the fourth column remain off. Next, the control line 27-1 becomes a high level, and the column selection switch 107-1 and the current source 3-7 of the readout circuit 50 in the seventh column are turned on. Since the control line 26-1 is maintained at the low level, the column selection switch 106-1 and the current source 3-6 of the readout circuit 50 in the sixth column remain off. In the odd-numbered group, the odd-numbered read circuit 50 is sequentially turned on.

  Next, at time t48, the control line 22-2 becomes high level, the column selection switch 102-2 and the current source 3-10 of the read circuit 50 in the second column (tenth column) of the second group. Turns on. Next, the control line 24-2 becomes a high level, and the column selection switch 104-2 and the current source 3-12 of the read circuit 50 in the fourth column (12th column) of the second group are turned on. Next, the control line 26-2 becomes high level, and the column selection switch 106-2 and the current source 3-14 of the readout circuit 50 in the sixth column (14th column) of the second group are turned on. Next, at time t49, the control line 28-2 becomes high level, the column selection switch 108-2 and the current source 3-16 of the readout circuit 50 in the eighth column (sixteenth column) of the second group. Turns on. In the even-numbered group, the even-numbered read circuit 50 is sequentially turned on.

  As described above, the plurality of readout circuits 50 perform readout in the order of the first, third, fifth, seventh, tenth, twelfth, fourteenth, and sixteenth columns.

  At time t49, the group selection switch 31 is turned on, and the signal on the vertical signal line 5-1 is read out to the second vertical signal line 6 and output through the output amplifier 7. Next, at time t <b> 50, the group selection switch 33 is turned on, and the signal on the vertical signal line 5-3 is read out to the second vertical signal line 6 and output via the output amplifier 7. Next, the group selection switch 35 is turned on, and the signal on the vertical signal line 5-5 is read out to the second vertical signal line 6 and output via the output amplifier 7. Next, the group selection switch 37 is turned on, and the signal on the vertical signal line 5-7 is read out to the second vertical signal line 6 and output through the output amplifier 7.

  At time t50, the control line 21-3 becomes high level, and the column selection switch 101-3 and the current source 3-17 of the read circuit 50 in the first column of the third group are turned on. Similar to the first group, the odd-numbered read circuits 50 are sequentially turned on in the odd-numbered group.

  Further, after the group selection switch 37 is turned off, the group selection switch 32 is turned on, and the signal of the vertical signal line 5-2 is read out to the second vertical signal line 6 and output through the output amplifier 7. . Next, the group selection switch 34 is turned on, and the signal on the vertical signal line 5-4 is read out to the second vertical signal line 6 and output via the output amplifier 7. Next, the group selection switch 36 is turned on, and the signal of the vertical signal line 5-6 is read out to the second vertical signal line 6 and output via the output amplifier 7. Next, the group selection switch 38 is turned on, and the signal on the vertical signal line 5-8 is read out to the second vertical signal line 6 and output via the output amplifier 7.

  In the present embodiment, the odd-numbered read circuits 50 are sequentially turned on in the odd-numbered group, and the even-numbered read circuits 50 are sequentially turned on in the even-numbered group. If the odd-numbered readout circuits 50 are sequentially turned on in all groups, the thinning readout mode is equal to the static time (charging) of the signals on the first horizontal output lines 5-1 to 5-8 in comparison with the all-pixel readout mode. Time) is halved and the signal amplitude is reduced. In this embodiment, even in the thinning readout mode, thinning readout can be performed at high speed while ensuring the same settling time (charging time) as in the all pixel readout mode.

  In the present embodiment, the thinning readout of the first group is started from the odd-numbered columns, but may be started from the even-numbered columns. In that case, the second group starts reading from the odd-numbered columns.

  In addition, if the drive time of the column selection switch 101-1 or the like is halved and the signal amplitude may be small, thinning-out reading of only odd columns or even columns may always be performed. In addition, the drive time may be secured for 8 columns, but in this case, the thinning readout time is doubled.

  Further, in the above description, thinning-out reading is performed for every two columns, but the above-described reading method can be applied when the number of thinning-out columns is one for every even number of columns. Next, a method of driving at high speed while ensuring the longest stabilization time when reading out one column every d columns from the pixel circuit 1 (integer of d> 0) will be described. In the method, the columns connected to the same first horizontal output lines 5-1 to 5-8 are not driven until the driving of the columns connected to the first horizontal output lines 5-1 to 5-8 is finished. Control not to select. At this time, the signal readout period (for example, t25-t24) and the drive start shift time between the readout groups (for example, t46-t45) are set as {the first horizontal output line stabilization period (for example, t50-t45). } / N, optimal driving can be performed.

  In this embodiment, only one column readout circuit 50 among the plurality of readout circuits 50 connected to the set of pixel circuits 1-1 and 1-2 added by the addition switch 83 performs readout. Do. All of the 2n first horizontal output lines 5-1 to 5-8 receive a pixel signal from one of the plurality of readout circuits 50.

  In this embodiment, an example in which pixel signals from pixels in adjacent columns are added in the thinning readout mode has been described. However, pixel signals from pixels in some columns are read without adding pixel signals. It does not have to be.

(Second Embodiment)
FIG. 6 is a diagram illustrating a configuration example of a pixel circuit according to the second embodiment of the present invention, and pixel addition in the horizontal direction and the vertical direction can be performed. FIG. 6 shows pixel circuits 1-1, 1-2, 1-5, and 1-6 in 2 rows and 2 columns, but the actual number of pixel circuits is composed of several hundred to several thousand pixels in a matrix. . Pixel signals of the pixel circuits 1-1, 1-2, 1-5, and 1-6 adjacent in the horizontal direction and the vertical direction are added in the memory 82. When the horizontal addition switch (adder) 83 is turned on by the control line 95-1, the memories 82 of the pixel circuits 1-1 and 1-2 adjacent in the horizontal direction are connected, and the pixel circuits 1-5 adjacent in the horizontal direction and 1-6 memory 82 is connected. When the vertical addition switch (adder) 85 is turned on by the control line 97-1, the memory 82 of the pixel circuits 1-2 and 1-2 and the memory 82 of the pixel circuits 1-5 and 1-6 are connected. . As a result, the memories 82 of the four pixels 1-1, 1-2, 1-5, and 1-6 are connected to each other, and the four pixel signals are added. The addition switches 83 and 85 add pixel signals of a plurality of pixel circuits 1-1, 1-2, 1-5, and 1-6 in different columns and different rows. The 4-pixel addition result is accumulated in the memory 82. Otherwise, the present embodiment is the same as the first embodiment.

  FIG. 7 is a timing chart showing a driving method in the thinning readout mode. From time t51 to t53, the driving is the same as from time t41 to t43 in FIG. At time t53, the horizontal addition switch 83 and the vertical addition switch 85 are turned on by setting the control lines 95-1 and 97-1 to the low level, and the four pixel circuits 1-1, 1-2, 1-5. , 1-6 are added. From time t54 to t61, the driving is the same as after time t44 in FIG. However, at time t54, the nMOS transistor of the row selection line 93-1 is turned on by the high level of the first row selection line 93-1. After the addition reading of the pixel circuits 1-1, 1-2, 1-5, and 1-6 in the first row and the second row is completed, at time t61, the low level of the row selection line 93-1 in the first row. Thus, the nMOS transistor of the row selection line 93-1 is turned off, and the pixel source follower output of the first row is stopped. Next, at time t62, the nMOS transistor of the row selection line 93-3 is turned on by the high level of the row selection line 93-3 of the third row (not shown in FIG. 6), and four pixels in the third and fourth rows. Are output to the vertical signal line. Subsequent driving is performed for the fifth and sixth rows in the same manner as the driving for the first and second rows. In the present embodiment, the number of first horizontal output lines 5-1 to 5-8, the number of added pixels, and the number of thinning readouts are the same as those in the first embodiment. The number of pixels in the vertical direction and the number of added pixels are not limited to the above example.

  In the configuration of FIG. 6, since adjacent pixel circuits 1-1, 1-2, 1-5, and 1-6 are connected to each other by switches 83 and 85, for example, signals are added by 2 × 2 four pixels. In this case, signals for four pixels can be added even if one of the switches fails and does not operate. Further, by providing a switch in parallel with each of the switches 83 and 85, pixel signals can be added even if the switch 83 or 85 fails. That is, the switches 83 and 85 are connected in parallel between the plurality of pixel circuits. The switches provided in parallel may be controlled by the same control line.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 pixel circuit, 5-1 to 5-8 first horizontal output line, 50 readout circuit, 83 addition switch

The present invention relates to an imaging equipment.

An object of the present invention is to provide an imaging equipment which can prevent the readout charge period is decreased in the case of performing the thinning drive and addition driving.

The imaging device according to the present invention is arranged in a matrix, and each pixel circuit generates a pixel signal by photoelectric conversion, and is provided for each column, and reads the pixel signal of the first pixel circuit for each column. A first group having a plurality of first readout circuits; a second pixel circuit that is arranged in a matrix and that generates a pixel signal by photoelectric conversion; and is provided for each column; A second group having a second readout circuit for reading out pixel signals of a two-pixel circuit; and the output terminals of the first and second readout circuits for each of a plurality of columns with respect to the first readout circuit and the second readout circuit. A plurality of first output lines connected in common; a first adder that adds pixel signals of a plurality of columns of first pixel circuits; and a second adder that adds pixel signals of a plurality of columns of second pixel circuits; And the first group includes the first pixel circuit and the first pixel circuit. A first set having a plurality of sets of readout circuits and a second set having a plurality of sets of the first pixel circuits and the first readout circuits, unlike the first set, and the second group A third set having a plurality of sets of the second pixel circuit and the second read circuit, and a fourth set having a plurality of sets of the second pixel circuit and the second read circuit unlike the third set, And when the first adder and the second adder do not add, a plurality of first output lines to which pixel signals of the first pixel circuits in the first set are respectively output, and The plurality of first output lines to which the pixel signals of the second pixel circuits in the third set are respectively output are the same, and the plurality of the first output lines to which the pixel signals of the first pixel circuits in the second set are respectively output. 1 output line and a plurality of pixel signals of the second pixel circuit in the fourth set are respectively output The first output lines are the same, and a plurality of first output lines from which the pixel signals of the first pixel circuits in the first set are respectively output and the pixel signals of the first pixel circuits in the second set are Unlike the plurality of first output lines that are respectively output, the first adder adds the pixel signals of the first pixel circuits in the first set, and the pixels of the first pixel circuits in the second set When adding the signals, and the second adding unit adds the pixel signals of the second pixel circuits in the third set, and adds the pixel signals of the plurality of second pixel circuits in the fourth set A first output line from which the pixel signal of the first pixel circuit in the first set is added by the first adder, and a second output in the third set by the second adder. Unlike the first output line that outputs the pixel signal obtained by adding the pixel signals of the pixel circuit, the first adder adds the second signal to the second set. A first output line for outputting a pixel signal obtained by adding the pixel signals of the first pixel circuit, and a pixel signal obtained by adding the pixel signals of the second pixel circuit in the fourth set by the second adder. It is different from the output first output line.

When performing the thinning drive and addition driving to prevent a decrease in the charging period of the first output line, it is possible to prevent a reduction in the signal amplitude.

Claims (1)

A plurality of pixel circuits arranged in a matrix and generating pixel signals by photoelectric conversion;
A plurality of readout circuits provided for each column of the plurality of pixel circuits, for reading out pixel signals of the pixel circuits for each column;
2n first output lines connected in common to output terminals of the readout circuit every 2n columns;
An adder for adding pixel signals of a plurality of pixel circuits in different columns;
Only one column readout circuit among the plurality of readout circuits connected to the set of pixel circuits added by the addition unit performs readout,
An image pickup apparatus, wherein a pixel signal is input from any of the plurality of readout circuits to all of the 2n first output lines.

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