JP2017093658A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a dishonest act in which one performs a game by making a game machine misunderstand that normal game media are used on the game machine.SOLUTION: A medal selector 201 comprises: a medal rail 210 for forming a passage where medals pass; a CMOS image sensor 232 for imaging medals which pass the passage; and a control LSI 234 for performing various kinds of determination processing based on imaged image data of medals. The control LSI 234 performs count processing, color determination processing and engraving determination processing using the image data, and then outputs determination results to a main control board 71. The control LSI 234 has image conversion means which converts the image data into an edge gradient image and creates a histogram related to the edge gradient image. An image recognition DSP circuit 242 for determining whether or not, an object which has passed the passage is a normal game medium, based on whether or not, the histogram and template data related to normal game media which is stored in advance, match or are similar at a prescribed degree, is also provided.SELECTED DRAWING: Figure 34

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachislot, comprising a plurality of reels each having a plurality of symbols arranged on each surface, a start switch, a stop switch, a stepping motor provided for each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player after a game medium such as a medal has been inserted into the gaming machine (hereinafter also referred to as “start operation”), and starts the rotation of all reels. Output the requested signal. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, a lottery process using random numbers on the program (hereinafter referred to as “internal lottery process”) is performed, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and the symbol combination related to the winning is displayed, a privilege corresponding to the symbol combination is given to the player.

  In addition, such a gaming machine is provided with a medal selector for detecting a medal inserted at the end of the medal slot. In addition, for this medal selector, a medal (illegal medal) that is not a proper medal (regular medal) is inserted into the medal insertion slot, or a device is inserted into the medal insertion slot, so that a regular medal is inserted into the gaming machine. Measures are taken against fraudulent acts of misrecognizing that the game has been thrown into the game.

  For example, in Patent Document 1, two medal detection proximity sensors are provided in a medal passage, and it is determined whether a game medal has passed through the medal passage based on the output of each proximity sensor. A slot machine is described that detects fraud using a tool such as a body.

JP 2002-342814 A

  However, the slot machine described in Patent Document 1 cannot detect an illegal act performed using an illegal medal without using an instrument such as a plate-like body. For example, if the lending unit loaned in the hall where this slot machine is installed is a medals with 20 yen per piece and medals with 5 yen per piece having the same diameter and only different colors and stamps (patterns), Cannot be determined. For this reason, a gaming machine that handles a medal with a lending unit price of 20 yen as a regular medal could not detect an illegal act of playing a game using a medal with a lending unit price of 5 yen (unauthorized medal). .

  In addition, the slot machine described in Patent Document 1 is attached to a medal lent out in a hall in which a gaming machine is installed, a medal lent out in another hall, or a gaming machine purchased at a used machine dealer. If a medal or a counterfeit medal (including an instrument pretending to be a medal) has the same diameter and differs only in color or stamp (pattern), these cannot be discriminated. For this reason, it has been difficult to detect (detect) an illegal act of playing a game using medals other than regular medals (unauthorized medals).

  The present invention has been made to solve the above-described problems, and an object of the present invention is to detect an illegal act of playing a game by misidentifying that a regular gaming medium is used in the gaming machine. It is to provide a gaming machine.

  In order to achieve the above object, the present invention provides a gaming machine having the following configuration.

An insertion slot (for example, a medal insertion slot 21 described later) for inserting a game medium;
A gaming machine comprising gaming medium detection means (for example, a medal selector 201 described later) for detecting gaming media inserted from the insertion slot;
The game medium detection means includes
A passage forming section (for example, a medal rail 210 described later) that forms a passage through which the game medium passes;
Imaging means for imaging the passage (for example, a camera unit 209 described later);
Passage determination means (for example, a medal count circuit 246 described later) for determining whether or not an object has passed through the passage based on image data obtained via the imaging means;
Image conversion means for converting the image data (for example, an ISP circuit 245 and an image recognition DSP circuit 242 described later);
Based on the image data converted by the image conversion means, a game medium determination means (for example, an image recognition DSP circuit 242 to be described later) for determining whether or not an object that has passed through the passage is a regular game medium; Have
The image conversion means converts the image data into an edge gradient image, and creates a histogram related to the edge gradient image,
The game medium determination means determines whether or not the histogram created by the image conversion means and template data (for example, a HOG template described later) stored in advance on the regular game medium match or are similar to a predetermined degree. And determining whether or not the object that has passed through the passage is the regular game medium.

  According to the present invention, it is possible to detect an illegal act of playing a game by misidentifying that a regular gaming medium is used in the gaming machine.

It is explanatory drawing explaining the functional flow in the game machine of one Embodiment of this invention. It is a perspective view which shows the example of an external appearance structure in the game machine of one Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an internal structure of a gaming machine according to an embodiment of the present invention, with a middle door closed. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an internal structure of a gaming machine according to an embodiment of the present invention, with a middle door opened. It is explanatory drawing which shows the inside of the cabinet in the game machine of one Embodiment of this invention. It is explanatory drawing which shows the back surface side of the front door in the game machine of one Embodiment of this invention. It is the perspective view which looked at the medal selector in the gaming machine of one embodiment of the present invention from the slanting back of the gaming machine. It is an exploded view of the medal selector in the gaming machine of one embodiment of the present invention. It is the perspective view which looked at the medal selector in the gaming machine of one embodiment of the present invention from the diagonal front of the gaming machine. It is a rear view of the base board part of the medal selector in the gaming machine of one embodiment of the present invention. It is a perspective view of the select plate of the medal selector in the gaming machine of one embodiment of the present invention. It is a figure which shows the path | route of a medal when the medal selector in the game machine of one Embodiment of this invention guides a medal to a hopper apparatus. It is a figure which shows the path | route of a medal when the medal selector in the gaming machine of one embodiment of the invention guides the medal to the medal shoot. It is a block diagram which shows the control system in the game machine of one Embodiment of this invention. It is a block diagram which shows the structural example of the main control circuit in the game machine of one Embodiment of this invention. It is a block diagram which shows the structural example of the sub control circuit in the game machine of one Embodiment of this invention. It is a block diagram which shows the circuit structural example of the medal selector in the game machine of one Embodiment of this invention. It is a block diagram which shows the circuit structural example of control LSI in the game machine of one Embodiment of this invention. It is a figure for demonstrating distortion of the lens in the game machine of one Embodiment of this invention. It is a figure for demonstrating the projective transformation process in the game machine of one Embodiment of this invention, A shows the RGB Bayer image before projective transformation, B shows the RGB Bayer image after projective transformation. It is a figure for demonstrating the threshold value graph in the game machine of one Embodiment of this invention. It is FIG. (1) for demonstrating the determination area | region in the gaming machine of one Embodiment of this invention. It is FIG. (2) for demonstrating the determination area | region in the gaming machine of one Embodiment of this invention. It is FIG. (3) for demonstrating the determination area | region in the gaming machine of one Embodiment of this invention. It is FIG. (4) for demonstrating the determination area | region in the gaming machine of one Embodiment of this invention. It is a figure which shows an example of the determination area | region determination result data memorize | stored in SRAM in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the medal count determination table in the game machine of one Embodiment of this invention. It is a figure for demonstrating the Gaussian filter in the game machine of one Embodiment of this invention. It is a figure for demonstrating the circular area | region detection process in the game machine of one Embodiment of this invention. It is a figure for demonstrating the 3σ correction process in the gaming machine of one embodiment of the present invention. It is a figure for demonstrating the filter process in the game machine of one Embodiment of this invention, A represents typically the circular area image data after a 3σ correction process, B shows the coefficient for edge images X, C represents an edge image Y coefficient. It is a figure which shows an example of the regular medal used for the game machine of one Embodiment of this invention, A shows one side of a regular medal, B shows the gradient average image data of a regular medal. It is a figure for demonstrating the HOG conversion process in the game machine of one Embodiment of this invention. It is a flowchart of the process which the control LSI in the game machine of one Embodiment of this invention performs. It is a timing chart (the 1) of the processing which control LSI in the gaming machine of one execution form of this invention performs. It is a timing chart (the 2) of the processing which control LSI in the gaming machine of one execution form of this invention performs.

  Hereinafter, a pachislot machine that is a gaming machine according to an embodiment of the present invention will be described with reference to FIGS.

<Function flow>
First, the functional flow of the pachislot will be described with reference to FIG.
In the pachislot of this embodiment, medals are used as game media for playing games. In addition to the medals, coins, game balls, game point data, tokens, or the like can be applied as game media.

  When a player inserts a medal and operates the start lever, one value (hereinafter, random number value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is carried out by a main control circuit described later. By determining the internal winning combination, a combination of symbols that permits display along a winning determination line described later is determined. The types of symbol combinations include those related to “winning” in which benefits such as paying out medals, re-games, bonuses, etc. are given to players, and other so-called “loses”. Is provided.

  Further, when the start lever is operated, a plurality of reels are rotated. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is responsible for a main control circuit described later.

  In the pachislot, basically, a control for stopping the rotation of the corresponding reel is performed within a specified time (190 msec or 75 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding symbols”. When the specified period is 190 msec, the maximum number of sliding symbols is set to 4 symbols, and when the specified period is 75 msec, the maximum number of sliding symbols is set to 1 symbol.

  When the internal winning combination allowing the symbol combination display related to winning is determined, the reel stop control means usually displays the symbol combination within the specified time of 190 msec (four symbols) for the winning determination line. The rotation of the reel is stopped so as to display as much as possible. In addition, the reel stop control means is defined for one or more reels when, for example, a challenge bonus (CB), which is a second-type special accessory, and a middle bonus (MB) for continuously operating the CB are operated. The reel rotation is stopped so that the combination of symbols is displayed as much as possible along the winning determination line within a time of 75 msec (for one symbol). Furthermore, the reel stop control means uses various specified times corresponding to the gaming state to rotate the reels so that combinations of symbols that are not permitted to be displayed by the internal winning combination are not displayed along the winning determination line. Stop.

  Thus, when the rotation of the plurality of reels is all stopped, the winning determination means determines whether or not the combination of symbols displayed along the winning determination line is related to winning. This winning determination means is carried out by a main control circuit described later. When it is determined by the winning determination means that it is related to winning, a privilege such as paying out medals is given to the player. In the pachislot, a series of flows as described above is performed as one game.

  Further, in the pachislot, in the above-described series of flows, video display performed by a display device such as a liquid crystal display device, light output performed by various lamps, sound output performed by a speaker, or a combination thereof is used. Various productions are performed.

  When the start lever is operated, an effect random number value (hereinafter referred to as effect random number value) is extracted separately from the random number value used for determining the internal winning combination. When the effect random number value is extracted, the effect content determining means determines, by lottery, what is to be executed this time from among a plurality of types of effect contents associated with the internal winning combination. This effect content determination means is carried out by a sub-control circuit described later.

  When the contents of the effect are determined, the effect executing means executes the corresponding effect in conjunction with each opportunity, such as when the rotation of the reels starts, when the rotation of each reel stops, or when determining whether there is a winning. In this way, in the pachislot machine, the player has the opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) by executing the production contents associated with the internal winning combination. It is possible to improve the player's interest.

<Pachislot structure>
Next, the structure of the pachislot machine 1 according to one embodiment will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi-slot 1.

As shown in FIG. 2, the pachi-slot 1 includes an exterior body 2. The exterior body 2 includes a cabinet 2a that houses a hopper device 51, a medal auxiliary storage 52, and the like (see FIG. 5), which will be described later, and a front door 2b that is attached to the cabinet 2a so as to be opened and closed.
Handles 7 are provided on both side surfaces of the cabinet 2a (only one handle 7 is shown in FIG. 2). The handle 7 is a recess that is put on when carrying the pachi-slot 1.

  Inside the exterior body 2, three reels 3L, 3C, 3R are provided side by side. Hereinafter, the reels 3L, 3C, and 3R are referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction.

  The front door 2b includes a door body 9, a front panel 10, and a liquid crystal display device 11 showing a specific example of the display device.

  The door body 9 is attached to the cabinet 2a using a hinge (not shown), and opens and closes the opening of the cabinet 2a. The hinge is provided at the left end of the door body 9 when the door body 9 is viewed from the front of the pachi-slot 1. The liquid crystal display device 11 is attached to the upper part of the door body 9. The liquid crystal display device 11 includes a display unit (display screen) 11a, and the liquid crystal display device 11 performs an effect by displaying an image.

  The front panel 10 is disposed so as to overlap the display unit 11 a side of the liquid crystal display device 11, and is formed in a frame shape having a panel opening 10 a that exposes the display unit 11 a of the liquid crystal display device 11. A lamp group 18 is provided on the front panel 10. The lamp group 18 is configured by an LED (Light Emitting Diode) or the like, and turns on and off the light in a pattern corresponding to the effect content.

  A pedestal 12 is formed in the center of the front door 2b. The pedestal portion 12 is provided with a symbol display area 4 and various devices to be operated by the player.

  The symbol display area 4 is arranged on the front side superimposed on the three reels 3L, 3C, 3R when viewed from the front, and is provided corresponding to the three reels 3L, 3C, 3R. The symbol display area 4 functions as a display window, and has a configuration capable of transmitting through the reels 3L, 3C, 3R provided behind the display window. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  When the reels 3L, 3C, and 3R provided behind the reel display window 4 stop rotating, the reel display window 4 has an upper stage, a middle stage, and a lower stage within the frame among a plurality of types of symbols of the reels 3L, 3C, and 3R. One symbol (three in total) is displayed in each area. In the present embodiment, a target for determining whether or not to win a pseudo line configured by combining any one of the three regions including the upper, middle and lower regions of the reel display window 4 is determined. Is defined as a line (winning determination line).

  The reel display window 4 is formed by a frame member 13 provided on the pedestal portion 12. The frame member 13 has a reel display window 4, an information display window 14, and a stop button attachment portion 15.

  The information display window 14 is provided continuously below the reel display window 4 and opens upward. That is, the reel display window 4 and the information display window 14 are formed as one continuous opening. The information display window 14 and the reel display window 4 are covered with a transparent window cover 16.

  The window cover 16 is disposed on the inner surface side of the frame member 13 and cannot be removed from the front side of the front door 2b. In addition, the frame member 13 includes a sheet placement portion 17 that faces the opening of the information display window 14 with the window cover 16 interposed therebetween. And between the sheet | seat mounting part 17 and the window cover 16, the sheet | seat member (information sheet) in which the information regarding a game was described is arrange | positioned. Therefore, the information sheet is covered with the window cover 16 having a smooth surface without unevenness or gaps.

  The window cover 16 that constitutes the information sheet attachment portion cannot be removed from the front side of the front door 2b, and has a smooth surface with no irregularities or gaps. Can prevent fraudulent access to the inside.

  The stop button mounting portion 15 is provided below the information display window 14 and is formed on a plane facing the front. The stop button mounting portion 15 is provided with a through hole through which the stop buttons 19L, 19C, 19R pass. Stop buttons 19L, 19C, 19R are associated with each of the three reels 3L, 3C, 3R, and are provided to stop the rotation of the corresponding reels. Hereinafter, the stop buttons 19L, 19C, and 19R are referred to as a left stop button 19L, a middle stop button 19C, and a right stop button 19R, respectively.

  The stop buttons 19L, 19C, and 19R show examples of various devices that are targets of operations by the player. In addition, the pedestal portion 12 is provided with a medal slot 21, a BET button 22, and a start lever 23 as various devices to be operated by the player.

  The medal slot 21 is provided to accept a medal dropped from the outside by the player. The medals accepted by the medal slot 21 are inserted into one game with a predetermined number (for example, three) as the upper limit, and the amount exceeding the specified number is deposited inside the pachislot 1. (So-called credit function).

  The BET button 22 is provided to determine the number of coins to be inserted into one game from medals deposited inside the pachislot 1. The start lever 23 is provided to start rotation of all reels (3L, 3C, 3R).

  In addition, a 7-segment display 24 including a 7-segment LED (Light Emitting Diode) is provided on the left side of the reel display window 4 when the front door 2b is viewed from the front. The 7-segment display 24 digitally displays information such as the number of medals to be paid out to the player as a privilege (hereinafter referred to as payout number) and the number of medals deposited in the pachislot (hereinafter referred to as credit number). .

  A settlement button 27 is provided on the left side of the base 12 when the front door 2b is viewed from the front. The checkout button 27 is provided to pull out (discharge) the outside stored in the interior of the pachislot machine 1. A lower panel unit 31 is provided below the pedestal 12. The waist panel unit 31 includes a decorative panel on which an arbitrary image is drawn and a light source that emits light for illuminating the decorative panel from the back side.

  Below the waist panel unit 31, a medal payout port 32, speaker holes 33L and 33R, and a medal tray unit 34 are provided. The medal payout port 32 guides medals discharged from a medal selector 201 described later and medals discharged by driving a hopper device 51 described later to the outside. The medals discharged from the medal payout opening 32 are stored in the medal tray unit 34. The speaker holes 33L and 33R are provided for outputting sound such as sound effects and music corresponding to the contents of the performance.

[Internal structure]
3 and 4 are perspective views showing the internal structure of the pachi-slot 1. FIG. 3 shows a state in which the front door 2b is opened and the middle door 41 provided on the back side of the front door 2b is closed with respect to the front door 2b. FIG. 4 shows a state where the front door 2b is opened and the middle door 41 is opened with respect to the front door 2b.
FIG. 5 is an explanatory diagram showing the inside of the cabinet 2a. FIG. 6 is an explanatory view showing the back side of the front door 2b.

  The cabinet 2a includes a top plate 20a, a bottom plate 20b, left and right side plates 20c and 20d, and a back plate 20e (see FIG. 5). A cabinet-side speaker 42 is disposed on the upper side inside the cabinet 2a. The cabinet-side speaker 42 is attached to the back plate 20e of the cabinet 2a via attachment brackets 43L and 43R. The cabinet side speaker 42 is, for example, a speaker for outputting sound effects.

  A cabinet-side relay board 44 is disposed on the left side of the cabinet-side speaker 42 when the inside of the cabinet 2a is viewed from the front. The cabinet side relay board 44 is attached to the left side plate 20c of the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 14), which will be described later, attached to the middle door 41 (see FIGS. 3 and 4), a hopper device 51, a medal auxiliary storage switch (not shown), and a medal payout. The wiring connecting the count switch (not shown) is relayed.

  An amplifier board 45 that controls the output of sound from the cabinet-side speaker 42 is disposed in the center of the cabinet 2a. The amplifier board 45 is attached to a mounting shelf 46 fixed to the left and right side plates 20c, 20d.

  Further, an external concentrated terminal plate 47 is disposed on the right side of the amplifier board 45 when the inside of the cabinet 2a is viewed from the front (see FIG. 5). The external concentrated terminal plate 47 is attached to the right side plate 20d of the cabinet 2a. The external concentration terminal board 47 is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1.

  A sub power supply device 48 is disposed on the left side of the amplifier board 45 when the inside of the cabinet 2a is viewed from the front. The sub power supply 48 is attached to the left side plate 20c of the cabinet 2a. The sub power supply device 48 supplies power with an AC voltage of 100 V to the power supply device 53 described later. Further, the power of the AC voltage 100V is converted into the power of the DC voltage and supplied to the amplifier board 45.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are disposed on the lower side of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 20b in the cabinet 2a. This hopper device 51 can accommodate a large amount of medals, and has a structure capable of discharging them one by one. For example, when the settlement button 27 (see FIG. 2) is pressed to settle the medals stored in the pachislot, the hopper device 51 discharges the stored medals by the number of credits. The medals paid out by the hopper device 51 are discharged from the medal payout port 32 (see FIG. 2).

  The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is engaged with the bottom plate 20b of the cabinet 2a, and is configured to be detachable from the bottom plate 20b.

  The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 20c. The power supply device 53 includes a power switch 53a and a power supply board 53b (see FIG. 14). The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device 48 into the power of the DC voltage necessary for each part, and supplies the converted power to each part.

  As shown in FIGS. 3, 4 and 6, the middle door 41 is arranged at the center of the back surface of the front door 2b, and is configured such that the reel display window 4 (see FIG. 4) can be opened and closed from the back side. Door stoppers 41a, 41b, and 41c are provided on the upper and lower portions of the middle door 41. The door stoppers 41a, 41b and 41c fix (prohibit) the opening operation of the middle door 41 in a state where the reel display window 4 is closed from the back side. That is, in order to open the middle door 41, it is necessary to rotate the door stoppers 41a, 41b, and 41c to release the middle door 41 from being fixed.

  A main control board case 55 that houses a main control board 71 (see FIG. 14) and three reels 3L, 3C, and 3R are attached to the middle door 41. Stepping motors are connected to the three reels 3L, 3C, 3R through gears having a predetermined reduction ratio.

As shown in FIG. 6, the main control board case 55 is provided with a setting key type switch 56. The setting key type switch 56 is used when changing the setting of the pachislot 1 or confirming the setting of the pachislot 1.
In the present embodiment, a main control board unit is configured by the main control board case 55 and the main control board 71 accommodated in the main control board case 55.

  The main control board 71 accommodated in the main control board case 55 constitutes a main control circuit 91 (see FIG. 15) described later. The main control circuit 91 is a circuit that controls the main flow of the game in the pachislot 1 such as determination of an internal winning combination, rotation and stop of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. A specific configuration of the main control circuit 91 will be described later.

  A sub control board case 57 that accommodates the sub control board 72 (see FIG. 14) is disposed above the middle door 41, and a center speaker 58 is disposed above the sub control board case 57. The sub control board 72 housed in the sub control board case 57 constitutes the sub control circuit 101 (see FIG. 16). The sub-control circuit 101 is a circuit that controls execution of effects by displaying images. A specific configuration of the sub control circuit 101 will be described later.

  A sub relay board 61 is disposed on the right side of the sub control board case 57 when the front door 2b is viewed from the back side. The sub relay board 61 relays the wiring connecting the sub control board 72 and the main control board 71. Further, it is a board that relays the wiring that connects the sub-control board 72 and the board disposed around the sub-control board 72. In addition, as a board | substrate arrange | positioned around the sub control board 72, LED board 62A, 62B, 62C mentioned later is mentioned.

  The LED boards 62A, 62B, and 62C are disposed on both sides of the sub control board case 57 when viewed from the back side of the front door 2b. These LED boards 62A, 62B, and 62C have a plurality of LEDs (Light Emitting Diodes) 85 (see FIG. 14) showing a specific example of the light source according to the effects executed by the control of the sub-control circuit 101 (see FIG. 16). ) To display a blinking pattern. Note that the pachislot machine 1 of the present embodiment includes a plurality of LED boards in addition to the LED boards 62A, 62B, and 62C.

  Below the sub-relay board 61, a 24h door opening / closing monitoring unit 63 is disposed. The 24h door opening / closing monitoring unit 63 stores the opening / closing history of the middle door 41. When the middle door 41 is opened, a signal for displaying an error on the liquid crystal display device 11 is output to the sub control board 72 (sub control circuit 101).

  Below the middle door 41, a board speaker 64 and lower speakers 65L and 65R are arranged. The board speaker 64 faces the waist panel unit 31 (see FIG. 2), and the lower speakers 65L and 65R face the speaker holes 33L and 33R (see FIG. 2), respectively.

  Above the lower speaker 65L, a medal selector 201, a medal chute 202, and a door open / close monitoring switch 67 are disposed. The medal selector 201 is a device that determines whether or not the material and shape of the medal are appropriate, and guides the medal inserted into the medal insertion slot 21 to the hopper device 51 via the slope 203 or the medal. Guide to the chute 202. A specific configuration of the medal selector 201 will be described later.

  The medal chute 202 is a substantially Y-shaped cylindrical member, and guides the medal guided by the medal selector 201 and the medal discharged from the hopper device 51 to the medal payout opening 32 (see FIG. 2).

  The door open / close monitoring switch 67 is disposed on the left side of the medal selector 201 when the front door 2b is viewed from the back side. The door open / close monitoring switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachi-slot 1.

  Further, a door relay terminal plate 68 is disposed in a region below the reel display window 4 and opened and closed by the middle door 41 (see FIG. 4). The door relay terminal board 68 includes a main control board 71 (see FIG. 14) in the main control board case 55, various buttons and switches, a sub-control board 72 (see FIG. 14), a medal selector 201, and a game operation display board. It is a board | substrate which relays wiring with 81 (refer FIG. 14). Examples of the various buttons and switches include a BET button 22, a settlement button 27, a door open / close monitoring switch 67, a BET switch 77, a start switch 79, and the like, which will be described later.

<Composition of medal selector>
Next, a specific configuration of the medal selector 201 will be described with reference to FIGS. FIG. 7 is a perspective view of the medal selector 201 when viewed from an oblique rear side of the pachi-slot 1. FIG. 8 is an exploded view of the medal selector 201. FIG. 9 is a perspective view of the medal selector 201 as viewed obliquely from the front of the pachi-slot 1. FIG. 10 is a rear view of a base plate portion 204 (to be described later) of the medal selector 201. FIG. 11 is a perspective view of a later-described select plate 207 of the medal selector 201. FIG. 12 is a diagram showing a medal path when the medal selector 201 guides the medal to the hopper device 51. FIG. 13 is a diagram showing a medal path when the medal selector 201 guides the medal to the medal chute 202. In addition, the arrow X shown in FIGS. 7-13 shows the left-right direction of the pachislot 1, the arrow Y shows the front-back direction of the pachislot 1, and the arrow Z shows the up-down direction.

  As shown in FIGS. 7 to 9, the medal selector 201 includes a base plate portion 204, a sub plate 205, a cancel shooter 206, a select plate 207, a medal solenoid 208 (see FIG. 9), a camera unit 209, It has.

  The base plate portion 204 is a substantially plate-like member that constitutes the outer frame housing of the medal selector 201, and is molded so that both left and right end portions of the pachi-slot 1 bend to the rear of the pachi-slot 1. The base plate portion 204 has a rear surface 204b that is one plane orthogonal to the front-rear direction of the pachislot 1 and a front surface 204a (see FIG. 9) that is the other plane. On the rear surface 204b, a medal rail 210 is formed so as to be recessed forward of the pachi-slot 1 and in a substantially L shape. A plurality of ridges are formed on the surface of the medal rail 210.

  At the upper end portion of the base plate portion 204, a medal entrance portion 211 that receives a medal inserted from the medal insertion port 21 (see FIG. 2) is provided. A medal inserted into the medal selector 201 from the medal entrance 211 moves along the medal rail 210 from above to below. A medal outlet portion 204c (see FIG. 8) is provided at the lower portion of the base plate portion 204. The medals that have moved in the medal selector 201 are discharged from the medal outlet 204c and are accommodated in the hopper device 51 via the slope 203 (see FIG. 4).

  A central hole 212 penetrating in the front-rear direction is formed at a substantially intermediate position of the medal rail 210, and an end of the medal pressure 213 (see FIG. 8) is exposed from the central hole 212. As shown in FIG. 9, the medal pressure 213 is rotatably supported by a shaft portion 214 provided on the front surface 204 a of the base plate portion 204. A coil spring 215 is attached to the shaft portion 214, and the medal pressure 213 is urged by the coil spring 215 so that the medal pressure 213 protrudes from the central hole 212.

  As shown in FIG. 9, a magnet 217 is provided on the front surface 204 a of the base plate portion 204. The magnet 217 attracts (magnetizes) an illegal medal that is not an appropriate material among medals moving on the medal rail 210.

  As shown in FIG. 8, an upper exposure hole 219 that penetrates in the front-rear direction and exposes a rear end portion of an after-medal pressure 218, which will be described later, is formed in a substantially central portion of the downstream region of the medal rail 210. . Further, a lower exposure hole 220 that penetrates in the front-rear direction and exposes a later-described medal stopper portion 227 of the select plate 207 is formed in the lower portion of the downstream area of the medal rail 210.

  Further, as shown in FIG. 10, six reference markers 260 are formed on the medal rail 210. The reference marker 260 is arranged in an imaging area A1 (indicated by a one-dot chain line in FIG. 10) that is an area on the medal rail 210 that the camera unit 209 images.

  The reference marker 260 includes an upper reference marker 261 and a lower reference marker 262. The upper reference marker 261 is arranged on the top of the medal rail 210 so as to be aligned in the left-right direction while being inclined. Further, the lower reference markers 262 are arranged at the lower part of the medal rail 210 so as to be arranged in the left-right direction while being inclined.

  In the image data of the imaging area captured by the camera unit 209, the reference marker 260 includes the luminance related to the pixel at the location where the reference marker 260 is formed, the luminance related to the pixel where the reference marker 260 is not formed, Are formed so as to be different from each other by a predetermined value or more. In the present embodiment, each reference marker 260 is formed by making a triangular hole in the medal rail 210. In addition, the formation aspect of the reference | standard marker 260 is not restricted to this, The shape of a hole can be selected suitably. Further, for example, the reference marker 260 may be formed on the medal rail 210 by printing a graphic having a color different from the color of the ground of the medal rail 210.

  As shown in FIG. 9, the after medal pressure 218 is pivotally supported on the front surface 204 a of the base plate portion 204 so as to be rotatable. When the front end of the after medal pressure 218 is pressed rearward of the pachislot 1 by the medal solenoid 208, the after medal pressure 218 rotates, and the rear end of the after medal pressure 218 passes through the upper exposure hole 219 (see FIG. 8). Exposed.

  As shown in FIGS. 7 and 8, the cancel shooter 206 is a substantially plate-like member, and is molded so that both ends in the left-right direction of the pachislot 1 bend forward of the pachislot 1. The cancel shooter 206 is detachably fixed to the base plate portion 204 and covers the lower portion of the base plate portion 204 from the rear. The cancel shooter 206 guides the medals discharged without going through the medal outlet 204c to the medal chute 202 (see FIG. 4). A cutout portion 206 a that is cut out in a substantially rectangular shape is formed at the upper portion of the substantially central portion in the left-right direction of the cancel shooter 206.

  As shown in FIGS. 7 and 8, the sub plate 205 is a plate-like member that covers the medal rail 210 from behind. The sub-plate 205 has a flat plate-like main body part 221 and a shaft part 222 provided on the upper part of the main body part 221. A through hole 221a penetrating in the front-rear direction is provided in a substantially central portion of the main body portion 221, and a downstream region is exposed from the substantially central portion of the medal rail 210 from the through hole 221a.

  The shaft portion 222 is supported by the base plate portion 204, and the sub-plate 205 is attached to the base plate portion 204 so as to be rotatable about the shaft portion 222. A coil spring 223 is attached to the shaft portion 222. Under normal conditions, the sub plate 205 is pressed against the base plate portion 204 side by the biasing force of the coil spring 223. At this time, a space through which medals can pass is formed between the sub plate 205 and the upper part of the medal rail 210 covered with the sub plate 205. That is, the sub plate 205 functions as a guide plate that allows the medal to pass therethrough.

Here, for example, when a medal jam occurs in the medal selector 201, the sub plate 205 can be rotated against the urging force of the coil spring 223 to eliminate the medal jam.

  As shown in FIG. 7, the select plate 207 is a member that guides a medal that moves in a substantially central portion of the medal rail 210 that is not covered by the sub plate 205. As shown in FIG. 11, the select plate 207 includes a substantially trapezoidal plate main body 224 and a pair of bearing portions formed by bending both left and right end portions of the plate main body 224 forward of the pachislot 1. 225. A flange portion 226 is formed on the upper portion of the plate main body 224. The flange portion 226 is formed by bending the pachislot 1 forward and bending the rear end portion upward. One bearing portion 225 is formed with a medal stopper portion 227 extending downward.

  As shown in FIG. 7, the plate main body 224 faces the substantially central portion of the medal rail 210 not covered by the sub plate 205 in the front-rear direction of the pachislot 1.

  As shown in FIG. 9, the select plate 207 is rotatably supported by a shaft portion 228 provided on the front surface 204 a of the base plate portion 204. The shaft portion 228 is provided with a coil spring 229 and biases the flange portion 226 forward of the pachislot 1. The flange portion 226 is in contact with one end portion of the medal solenoid 208. When the medal solenoid 208 is in the ON state, the flange portion 226 is pressed by one end of the medal solenoid 208 and moves to the rear of the pachislot 1 against the urging force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “guide position”. The distance between the plate body 224 of the select plate 207 at the guide position and the medal rail 210 is set to a predetermined distance that allows the medal to be guided to the hopper device 51 without discharging the medal to the cancel shooter 206 side. At this time, the medal stopper portion 227 does not protrude from the lower exposure hole 220 (see FIG. 8).

  When the medal solenoid 208 is in the OFF state, the flange portion 226 is released from the pressing of the medal solenoid 208 and moves forward of the pachislot 1 by the biasing force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “discharge position”. The distance between the plate body 224 of the select plate 207 at the discharge position and the medal rail 210 is set to be longer than a predetermined distance. At this time, the flange portion 226 that moves forward of the pachislot 1 is pressed, and one end of the medal solenoid 208 moves forward of the pachislot 1. Along with this, the other end of the medal solenoid 208 moves to the rear of the pachislot 1 and presses the front end of the after medal pressure 218. As a result, the after medal pressure 218 rotates and the rear end of the after medal pressure 218 is exposed from the upper exposure hole 219 (see FIG. 8).

  The medal stopper 227 does not protrude from the lower exposure hole 220 (see FIG. 8) when the select plate 207 is at the guide position, and protrudes from the lower exposure hole 220 when at the discharge position.

  As shown in FIG. 12, when the medal moving on the medal rail 210 meets the standard dimension, the select plate 207 at the guide position contacts the upper part of the moving medal, and the medal exit portion 204c (see FIG. 8). ) When the medal is guided by the select plate 207, the medal pressure 213 is pressed forward of the pachislot 1. In FIG. 12, illustration of the sub plate 205 and the cancel shooter 206 of the medal selector 201 is omitted.

  On the other hand, as shown in FIG. 13, the select plate 207 at the discharge position has a distance between the plate main body 224 and the medal rail 210 even when the medal moving on the medal rail 210 satisfies the standard dimension. Therefore, the medal cannot be guided to the medal outlet 204c (see FIG. 8). The medal is pushed out by the medal pressure 213, the after medal pressure 218 protruding from the upper exposure hole 219, or the medal stopper portion 227 protruding from the lower exposure hole 220, and discharged toward the cancel shooter 206. In FIG. 13, as in FIG. 12, illustration of the sub plate 205 and the cancel shooter 206 of the medal selector 201 is omitted.

  In this embodiment, the select plate 207 is normally positioned at the guide position. However, under a predetermined condition (for example, when a predetermined number of medals are inserted, when an error occurs, when a game starts, etc.), the select plate 207 is positioned at the discharge position. It is positioned.

  If the medal moving on the medal rail 210 has a smaller diameter than the standard dimension, even if the select plate 207 is in the guide position, the medal is not guided to the select plate 207 but pushed out to the medal pressure 213 and the cancel shooter 206 It is discharged toward

  As shown in FIGS. 7 and 8, the camera unit 209 includes a first substrate 230, a second substrate 231 and a lens (not shown), and whether or not an object moving on the medal rail 210 is a regular medal. Is a unit that outputs the determination result to the main control circuit 91. The first substrate 230 is provided with a CMOS image sensor 232 (see FIG. 17) and an LED 233 (see FIG. 17). The second substrate 231 is provided with a control LSI 234 (see FIG. 17) that is communicably connected to the CMOS image sensor 232 and the LED 233 and is controllably connected.

  The first board 230 and the second board 231 are connected by a BtoB (Board-to-Board) type connector (not shown), and by legs 235 provided at the corners of the boards 230 and 231. It is fixed. The specific configuration of the camera unit 209 circuit will be described later. In this embodiment, the camera unit 209 is described as having two substrates 230 and 231 and a lens. However, instead of this, a single substrate having the CMOS image sensor 232, the LED 233, and the control LSI 234 is provided. You may comprise a camera unit. An aperture mechanism may be added.

  The camera unit 209 is fixed by screwing the first substrate 230 into a screw hole 206b provided around a notch 206a at the top of the cancel shooter 206.

  The CMOS image sensor 232 (see FIG. 17) is provided at a substantially central portion of the first substrate 230. The CMOS image sensor 232 images the imaging area A1 (see FIG. 10) on the medal rail 210 via the notch portion 206a (see FIG. 8) of the cancel shooter 206, and controls the captured image data to the control LSI 234 (FIG. 17). Output).

  The LED 233 (see FIG. 17) emits light around the CMOS image sensor 232, and irradiates the object moving on the medal rail 210 with light. The control LSI 234 (see FIG. 17) determines whether the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232 and outputs the determination result to the main control circuit 91. To do. In this embodiment, the mode in which the camera unit 209 is fixed to the cancel shooter 206 by screwing in the screw hole 206b formed around the notch portion 206a has been described. However, the camera unit fixing mode is limited to this. Not. For example, an attachment rail is provided between the first substrate 230 and the second substrate 231, and a recess is provided in the upper part of the cancel shooter 206. The attachment rail and the cancel shooter 206 are fitted in the recess. May be fixed with screws or an adhesive.

<Configuration of circuits provided in pachislot>
Next, a configuration of a circuit included in the pachislo 1 will be described with reference to FIGS.
First, the outline of the entire circuit provided in the pachislot machine 1 will be described with reference to FIG. FIG. 14 is a block configuration diagram of the entire circuit provided in the pachislot 1.

The pachi-slot 1 has a main control board 71 disposed on the middle door 41 and a sub-control board 72 disposed on the front door 2b.
The main control board 71 includes a reel relay terminal board 74, a setting key switch 56, an external concentration terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, and a power supply board 53b of the power supply 53. It is connected. The setting key switch 56, the external concentration terminal board 47, the hopper device 51, and the medal auxiliary storage switch 75 are connected to the main control board 71 via the cabinet-side relay board 44. Since the external concentration terminal board 47 and the hopper device 51 have been described above, description thereof will be omitted.

  The reel relay terminal plate 74 is disposed inside the reel body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to stepping motors (not shown) of the reels 3L, 3C, 3R, and relays signals output from the main control board 71 to the stepping motors.

  The medal auxiliary storage switch 75 passes through a switch through hole (not shown) of the medal auxiliary storage 52. The medal auxiliary storage switch 75 detects whether or not the medal auxiliary storage 52 is full of medals.

  A power switch 53 a is connected to the power supply board 53 b of the power supply device 53. The power switch 53a is turned on when supplying necessary power to the pachislot machine 1.

  The main control board 71 has a medal selector 201, a door open / close monitoring switch 67, a BET switch 77, a settlement switch 78, a start switch 79, a stop switch board 80, and a game operation display board 81 via a door relay terminal board 68. The sub-relay board 61 is connected. Since the door opening / closing monitoring switch 67 and the sub relay board 61 have been described above, the description thereof will be omitted. The circuit configuration of the medal selector 201 will be described later.

  The BET switch 77 detects that the BET button 22 has been pressed by the player. The settlement switch 78 detects that the settlement button 27 has been pressed by the player. The start switch 79 detects that the start lever 23 has been operated by the player (start operation).

  The stop switch substrate 80 is a substrate constituting a circuit for stopping the rotating reel and a circuit for displaying the stopable reel by an LED or the like. The stop switch substrate 80 is provided with a stop switch. The stop switch detects that each stop button 19L, 19C, 19R has been pressed by the player (stop operation).

  The game operation display board 81 displays the number of inserted medals on the 7-segment display 24 when accepting insertion of medals, when the three reels 3L, 3C, 3R are rotatable and when replaying. It is a substrate for making it. A 7-segment display 24 and an LED 82 are connected to the game operation display board 81. The LED 82 lights, for example, a mark for displaying the start of a game or a mark for performing a re-game.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. A sound I / O board 84, LED boards 62A, 62B, 62C, and a 24h door open / close monitoring unit 63 are connected to the sub control board 72 via a sub relay board 61. Since these LED boards 62A, 62B, 62C and the 24h door opening / closing monitoring unit 63 have been described above, the description thereof will be omitted.

  The sound I / O board 84 outputs sound to a center speaker 58, a board speaker 64, lower speakers 65L and 65R, and a speaker (not shown) provided on the front door 2b.

The sub-control board 72 is connected to a ROM cartridge board 86 and a liquid crystal relay board 87. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are housed in the sub control board case 57 together with the sub control board 72.
The ROM cartridge substrate 86 is a substrate for managing production images (video), sound, LED substrates 62A and 62B, other LED substrates (not shown), and communication data. The liquid crystal relay substrate 87 is a substrate that relays wiring that connects the sub-control board 72 and the liquid crystal display device 11.

<Main control circuit>
Next, the main control circuit 91 constituted by the main control board 71 will be described with reference to FIG.
FIG. 15 is a block diagram illustrating a configuration example of the main control circuit 91 of the pachi-slot 1.

  The main control circuit 91 includes a microcomputer 92 installed on the main control board 71 as a main component. The microcomputer 92 includes a main CPU 93, a main ROM 94, and a main RAM 95. The main CPU 93 and the hopper device 51 described above constitute a game medium payout device of the present invention.

  The main ROM 94 is used to transmit various control commands (commands) to the control program executed by the main CPU 93 (for example, the program for executing the internal lottery process described above), the data table, and the sub-control circuit 101. Data etc. are stored. The main RAM 95 is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program.

  The main CPU 93 is connected to a clock pulse generation circuit 96, a frequency divider 97, a random number generator 98, and a sampling circuit 99. The clock pulse generation circuit 96 and the frequency divider 97 generate clock pulses. The main CPU 93 executes a control program based on the generated clock pulse. The random number generator 98 generates a random number in a predetermined range (for example, 0 to 65535). The sampling circuit 99 extracts one value from the generated random numbers.

The main CPU 93 counts the number of times pulses are output to the stepping motors of the reels 3L, 3C, 3R after detecting the reel index. Thereby, the main CPU 93 manages the rotation angle of each reel 3L, 3C, 3R (mainly, how many symbols the reel has rotated).
The reel index is information indicating that the reel has made one revolution. This reel index is provided at a predetermined position of each of the reels 3L, 3C, 3R, for example, with a light emitting unit and a light receiving unit, and between the light emitting unit and the light receiving unit by the rotation of each reel 3L, 3C, 3R. Detection is performed by a reel position detection unit (not shown) including a detection piece interposed therebetween.

  Here, the management of the rotation angle of each reel 3L, 3C, 3R will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 95. Each time the output of a predetermined number of pulses (for example, 16 times) necessary for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 95 is incremented by one. The symbol counter is provided for each reel 3L, 3C, 3R. The value of the symbol counter is cleared when a reel index is detected by a reel position detector (not shown).

  In other words, in the present embodiment, by managing the symbol counter, it is possible to manage how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel 3L, 3C, 3R is detected with reference to the position where the reel index is detected.

  As described above, when the maximum number of sliding symbols is set to four symbols, the symbol of the left reel 3L in the middle of the reel display window 4 when the left stop button 19L is pressed, and the four symbols. Each symbol within the range up to the previous symbol becomes a symbol that can be stopped at the middle stage of the reel display window 4.

  Further, when a determination result is input from the control LSI 234 of the medal selector 201 as will be described later, the main CPU 93 causes the gaming machine to mistakenly recognize that a regular gaming medium is used based on the input determination result. Detect fraudulent acts that play games.

<Sub control circuit>
Next, the sub control circuit 101 constituted by the sub control board 72 will be described with reference to FIG.
FIG. 16 is a block diagram illustrating a configuration example of the sub control circuit 101 of the pachi-slot 1.

  The sub control circuit 101 is electrically connected to the main control circuit 91 and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 91. The sub control circuit 101 basically includes a sub CPU 102, a sub RAM 103, a rendering processor 104, a drawing RAM 105, and a driver 106.

  The sub CPU 102 controls the output of video, sound, and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 91. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  A control program executed by the sub CPU 102 is stored in the program storage area. For example, the control program includes a main board communication task for controlling communication with the main control circuit 91 and an effect registration task for extracting and registering effect contents (effect data) by extracting effect random numbers. Is included. In addition, a drawing control task for controlling display of an image by the liquid crystal display device 11 (see FIG. 2) based on the determined contents of the effect, a lamp control task for controlling light output by a light source such as the LED 85, and the speakers 58, 64, and 65L. , 65R, etc., and a voice control task for controlling the sound output from the speaker.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to creation of video. Also included are a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to the light on / off pattern, and the like.

  The sub-RAM 103 is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 91.

  The sub CPU 102, the rendering processor 104, the drawing RAM (including the frame buffer) 105, and the driver 106 create a video according to the animation data designated by the content of the presentation, and display the created video on the liquid crystal display device 11.

  Further, the sub CPU 102 causes a sound such as BGM to be output from a speaker such as speakers 58, 64, 65L, and 65R in accordance with the sound data specified by the contents of the effect. Further, the sub CPU 102 controls the turning on and off of the light source such as the LED 85 in accordance with the lamp data designated by the contents of the effect.

<Circuit configuration of medal selector>
Next, the circuit configuration of the medal selector 201 will be described with reference to FIG.
FIG. 17 is a block diagram illustrating a circuit configuration example of the medal selector 201.

As shown in FIG. 17, the medal selector 201 includes a camera unit 209 and a medal solenoid 208.
The medal selector 201 is connected to the main control board 71 via the door relay terminal board 68. That is, the medal selector 201 is electrically connected to the main control circuit 91. Therefore, the main control circuit 91 can set the medal solenoid 208 of the medal selector 201 to the ON state or the OFF state.

  The camera unit 209 includes a control LSI 234, a CMOS image sensor 232, and an LED 233. The control LSI 234 of the camera unit 209 is configured by an ASIC (Application Specific Integrated Circuit), and is electrically connected to the CMOS image sensor 232 and the LED 233. The control LSI 234 controls the light emission of the LED 233. Further, the control LSI 234 determines whether or not the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232, and the determination result is output from the output PORT assigned to the GPIO 250. When a predetermined output condition described later is satisfied, the signal is output to the main control board 71 via the door relay terminal board 68. In the present embodiment, the adopted CMOS image sensor 232 is a CMOS image sensor having a resolution of 648 × 488 pixels and a frame rate of 240 fps (Frames Per Second).

<Circuit configuration of control LSI>
Next, the circuit configuration of the control LSI 234 will be described with reference to FIG.
FIG. 18 is a block diagram illustrating a circuit configuration example of the control LSI 234.

  The control LSI 234 includes a host controller 241, an image recognition DSP (digital signal processor) circuit 242, an SRAM (Static Random Access Memory) 243 to which a backup power supply (not shown) is connected, a flash memory 244, an ISP (Image Signal Processing) circuit 245. And a medal count circuit 246. The control LSI 234 includes a color recognition circuit 247, a fisheye correction scaler circuit 248, an image recognition accelerator circuit 249, and a GPIO (General Purpose Input / Output) 250. These devices constituting the control LSI 234 are connected to each other via a bus, and the control LSI 234 of this embodiment employs AXI (Advanced eXtensible Interface) as a bus protocol.

  The control LSI 234 includes an ISI (Image Sensor Interface) circuit 251. The ISI circuit 251 is electrically connected to the CMOS image sensor 232 and the ISP circuit. The ISI circuit 251 converts the image data output from the CMOS image sensor 232 by the LVDS (Low voltage differential signaling) method into an RGB Bayer image and outputs the RGB data to the ISP circuit 245.

<ISP circuit>
When the ISP circuit 245 receives an RGB Bayer image from the ISI circuit 251 (inputting an RGB Bayer image), the ISP circuit 245 outputs a VSYNC (Vertical Synchronization) interrupt signal to the host controller 241.
Further, the ISP circuit 245 performs image correction processing for subjecting the RGB Bayer image output from the ISI circuit 251 to lens distortion correction processing and projective transformation (homography) processing.

  The lens distortion correction process is a process for correcting distortion caused by the characteristics of the lens in the camera unit 209 on the image data captured by the CMOS image sensor 232 in order to increase the accuracy of various determination / determination processes described later. is there.

  For example, when a convex lens is employed as the lens of the camera unit 209, the thickness of the lens end is thinner than the thickness of the central portion of the lens, so that distortion as shown in FIG. 19 occurs. In FIG. 19, the imaging area A1 of the CMOS image sensor 232 and the image data G1 of the imaging area A1 captured by the CMOS image sensor 232 are schematically shown. The black dots in the image data G1 represent locations corresponding to the vertices of each grid in the imaging area A1.

  As shown in FIG. 19, in the image data G1, a relatively large distortion occurs at the end compared to the center. The ISP circuit 245 performs lens distortion correction processing based on various correction parameters set in advance to process the image data G1 (received RGB Bayer image). Specifically, the image data G1 is complemented so that the position of the black dot of the image data G1 is the same position as the vertex of the grid of the corresponding imaging region A1. This suppresses the influence of this distortion on various types of discrimination processing described later.

  Note that the various correction parameters are defined in advance in the program based on the prior characteristic evaluation for the lens employed in the camera unit 209. The various correction parameters may be stored in the flash memory 244 and referred to the ISP circuit 245 during the lens distortion correction process.

The projective transformation process is a process of correcting the image data so that the displacement of the mounting position of the camera unit 209 does not affect the accuracy of various determination / determination processes described later.
For example, when the camera unit 209 is attached to the cancel shooter 206 at an angle other than a suitable angle, as shown in FIG. 20A, an image area A2 required for various determination / determination processes described later is distorted and imaged. There is a case. In the projective transformation process, this distortion is corrected, and the image data is complemented with a mode suitable for various discrimination / determination processes to be described later.

  Specifically, in the projective transformation process, the ISP circuit 245 analyzes the RGB Bayer image after the lens distortion correction process, and detects the positions (coordinates: x, y) of at least four reference markers 260 in the RGB Bayer image. To do.

Next, the position of the reference marker 260 (coordinates: u, v) in image data suitable for improving the accuracy of various determination processes described later, which are defined in advance in the program, corresponding to the detected four reference markers. Based on the following formulas 1 and 2, conversion coefficients a, b, c, d, e, f, g, and h are calculated.
u = (x * a + y * b + c) / (x * g + y * h + 1) Formula (1)
v = (x × d + y × e + f) / (x × g + y × h + 1) (2)

  Then, the calculated conversion coefficients a, b, c, d, e, f, g, h, and the coordinate values of each pixel in the RGB Bayer image after the lens distortion correction process are substituted into the above-described Expression 1 and Expression 2. The coordinates after conversion for each pixel are calculated, and this RGB Bayer image is processed so that each pixel is positioned at the calculated coordinates after conversion. FIG. 20B schematically shows the image area A2 shown in FIG. 20A in the RGB Bayer image after the projective transformation processing.

  In the present embodiment, the mode in which the position (coordinates: u, v) of the reference marker 260 in image data suitable for improving the accuracy of various determination processes is defined on the program has been described. However, instead of this, for example, the position of the reference marker 260 may be stored in the flash memory 244 and referred to by the ISP circuit 245 during the projective transformation process.

  Next, the ISP circuit 245 performs color conversion processing for converting the RGB Bayer image after the lens distortion correction processing and the projective conversion processing into various formats. In the color conversion process, the ISP circuit 245 converts the RGB Bayer image into image data (YUV image data) corresponding to the YUV color space, and data relating to luminance in the YUV image data (hereinafter “grayscale image data”). Is output to the medal count circuit 246. Further, the gray scale image data is stored in the SRAM 243. The SRAM 243 is provided with a storage area capable of storing a predetermined number of gray scale image data. When the number of grayscale image data stored in the SRAM 243 reaches the upper limit, the stored order is overwritten from the old grayscale image data.

  In the color conversion process, the ISP circuit 245 converts the RGB Bayer image into image data (HSV color space) corresponding to a color space (HSV color space) composed of three components (H: hue, S: saturation, V: lightness). Image data) and output the HSV image data to the color recognition circuit 247.

<Color recognition circuit>
The color recognition circuit 247 performs color determination processing based on the hue and saturation in the HSV image data output from the ISP circuit 245. The color determination processing includes medal detection processing, threshold determination processing, saturation / hue multiplication processing, color template generation processing, and color template comparison processing.

(1) Medal Detection Processing In the color determination processing, the color recognition circuit 247 stores the HSV image data received (input) from the ISP circuit 245 in the SRAM 243. The SRAM 243 is provided with a storage area capable of storing a predetermined number of HSV image data. When the number of HSV image data stored in the SRAM 243 reaches the upper limit, the stored order is overwritten from the old HSV image data.

  Further, the color recognition circuit 247 performs a medal detection process for determining whether or not a medal image is included in the HSV image data received from the ISP circuit 245. Specifically, the difference between the HSV image data received from the ISP circuit 245 this time and the background HSV image data stored in the SRAM 243 is detected, and if the difference portion matches the medal shape, It is determined that an image is included. The background HSV image data is HSV image data that does not include an image of a medal. When the medal is not moving on the medal rail 210, for example, an image captured by the CMOS image sensor 232 immediately after the power is turned on. The data is obtained by the ISP circuit 245 converting the data into HSV image data. In the present embodiment, the ISP circuit 245 stores the obtained background HSV image data in the SRAM 243. Whether or not the detected difference portion matches the medal shape is determined by comparing with the medal shape HSV image data stored in the flash memory 244 in advance.

(2) Threshold Determination Processing When it is determined that the medal image is included in the HSV image data, the color recognition circuit 247 performs threshold determination processing based on the HSV image data. In the threshold determination processing, the color recognition circuit 247 is in a predetermined area of the medal image in the HSV image data, for example, a substantially square area including the center of the medal in the present embodiment (hereinafter, sometimes referred to as “medal area”). The saturation values of all the pixels are integrated, and the hue values are integrated. Then, the average saturation value and the average hue value are calculated by dividing the integrated value by the number of pixels in the medal area, and the position on the threshold graph shown in FIG. 21 is specified based on the calculated values.

  Here, the threshold graph of FIG. 21 is a graph in which the vertical axis represents the saturation value and the horizontal axis represents the hue value. In the threshold graph, the graph is divided into an allowable region and a non-permissible region based on a predetermined formula. In FIG. 21, the background of the allowable area is represented by a white background, and the background of the non-allowable area is represented by shading.

  If the position on the threshold graph based on the average saturation value and the average hue value is within the allowable region, the color determination process is continued. On the other hand, if it is within the non-allowable area, “threshold value determination impossible” is stored in the color determination area storage area of the SRAM 243 as the determination result of the color determination process, and the color determination process ends.

  Instead of the above, the color recognition circuit 247 specifies the position on the threshold graph shown in FIG. 21 based on the saturation value and the hue value of each pixel in the medal area. Also good. In this case, it is determined whether or not the number of pixels positioned in the non-allowable area exceeds a predetermined number, for example, 20% of the number of pixels in the medal area. If not, the color determination process is continued and exceeded. In this case, “threshold value determination impossible” may be stored in the SRAM 243 as the determination result of the color determination process, and the color determination process may be terminated.

  In addition, the allowable region and the non-permissible region in the threshold graph can be set as appropriate. For example, in addition to the non-permissible area in FIG. 21, when the saturation value is equal to or greater than a predetermined value, for example, 90 or greater, a non-permissible area positioned in the non-permissible area may be provided.

(3) Saturation / Hue Multiplication Processing After the threshold determination processing, the color recognition circuit 247 performs saturation / hue multiplication processing in the threshold determination processing. In the saturation / hue multiplication process, the saturation value of each pixel in the medal area is multiplied by the hue value, and the value calculated by the multiplication is stored in the SRAM 243 in association with the position of the pixel. In the following description, a group of data stored by associating the multiplication value of the saturation value and the hue value of each pixel in the medal area with the position of the pixel is referred to as “color determination data”. There is.

(4) Color template generation process The color template generation process is a process of generating a color template used in a color template comparison process described later. In the color template generation process, the color recognition circuit 247 compares the color determination data relating to each medal until the number of medals inserted after power-on reaches the specified initial number of inserted medals, 50 in this embodiment, and matches. Or color determination data similar to a predetermined degree are grouped.

  For example, the color recognition circuit 247 compares the multiplication value of the saturation value and the hue value with respect to the data for color determination related to 50 medals for each position of the associated pixel. Then, when the number of multiplication values that coincide or fall within a predetermined error range (for example, ± 5) is a predetermined number or more (for example, 80% or more of all the multiplication values), these color determination data are grouped. .

  Next, the color recognition circuit 247 selects the upper four groups in the descending order of the number of color determination data to which they belong. Then, for each of the selected top four groups, one arbitrary color determination data is selected, and the four color determination data are stored as color templates in the storage area for storing the color template in the SRAM 243. For each of the selected top four groups, instead of selecting any one color determination data, the average value of the color determination data belonging to the same group (the average value of the multiplication values for each pixel) ) May be generated to generate a color template. Further, the color template stored in the SRAM 243 may be erased by initialization processing (not shown) of the host controller 241 when the gaming machine is turned on.

  As described above, by generating a color template, for example, when two kinds of medals having different markings (patterns) and colors on the front and back are used as regular medals, and the color template is stored in the storage area of the SRAM 243. If not stored, by inserting 50 of these regular medals after the power is turned on, four types of color templates relating to the front and back of these two types of medals can be generated. In addition, when the color template is not stored in the storage area of the SRAM 243 and there are one kind of 50 regular medals inserted after the power is turned on, two kinds of colors related to the front and back of the regular medals A template is generated, and two types of generated color templates are used in the color template comparison process described later.

  In addition, when the color template is not stored in the storage area of the SRAM 243, the color determination data relating to each medal until the number of medals inserted after power-on reaches the specified initial number of sheets, in this embodiment, 50 is It is generated in response to an instruction from the host controller 241. When the medal count circuit 246 described later determines that the medal has passed on the medal rail 210, the host controller 241 triggers HSV image data a predetermined time before (ie, a predetermined frame before) the determination. Is used to instruct the color recognition circuit 247 to generate color determination data. The predetermined time is set in advance based on experiments and simulations so that the HSV image data before the predetermined time always includes a medal image.

  The color determination data is generated through the above-described medal detection process, threshold determination process, and saturation / hue multiplication process, and is stored in the color determination data storage area of the SRAM 243. When the number of color determination data stored in the color determination data storage area reaches 50, that is, when color determination data relating to 50 medals is created, the color recognition circuit 247 executes color template generation processing. To do.

(5) Color template comparison processing If the medal detection processing after the color template generation processing determines that a medal image is included, the color recognition circuit 247 performs color template comparison processing.

  In the color template comparison process, for the HSV image data determined to contain the medal image, the color determination data created through the threshold determination process and the saturation / hue multiplication process are compared with the color template. Then, it is determined whether or not they match or are similar to a predetermined degree, and “Yes” or “No” is stored in the color determination storage area of the SRAM 243 as the determination result. In this embodiment, since up to four color templates are used, determination results for up to four templates are stored in the SRAM 243. In the color template comparison process, the color determination result is stored in the color determination storage area of the SRAM 243. Here, as a color determination result, if “Yes” is stored as one of the determination results for up to four templates, “Yes” is stored, and if all “No” is stored. “No” is stored. Therefore, in one color template comparison process, a maximum of four determination results for a maximum of four color templates and a single color determination result based on these determination results are stored. Note that a predetermined number of determination results can be stored in the color determination storage area of the SRAM 243, and when the stored determination results reach the upper limit number, the stored determination results are overwritten from the earlier determination results.

  For example, the color recognition circuit 247 compares the product of the color determination data, the saturation value in the color template, and the hue value for each associated pixel position. Then, when the number of multiplication values that match or are within a predetermined error range (for example, ± 5) is equal to or greater than a predetermined number (for example, 80% or more of all the multiplication values), it is determined that they match or are similar to a certain degree. It should be noted that the criteria for determining whether or not they match or are similar to a predetermined degree in this process can be set as appropriate.

  As described above, in the color determination process, the threshold value determination process is performed, and the color template comparison process is performed, and the color determination data is compared with the color template to determine whether they match or are similar to a predetermined degree. The color recognition circuit 247 constitutes a game medium determination unit that determines whether an object that has passed on the medal rail 210 is a regular medal.

<Medal count circuit>
The medal count circuit 246 performs count processing based on the gray scale image data output from the ISP circuit 245. The count process includes a medal image determination process, a medal position detection process, and an order determination process.

(1) Medal image discrimination process In the count process, the medal count circuit 246 first performs a medal image discrimination process. In the medal image determination process, the medal count circuit 246 determines whether or not a medal image is included in the input grayscale image data. Specifically, this time, a difference is detected for each pixel of the grayscale image data input from the ISP circuit 245 and the background grayscale image data stored in the SRAM 243, and formed by a plurality of pixels from which the difference is detected. If the shape to be matched matches the medal shape template data stored in the flash memory 244, it is determined that a medal image is included. The background grayscale image data is grayscale image data that does not include an image of a medal. When the medal is not moving on the medal rail 210, for example, immediately after the power is turned on, the CMOS image sensor 232 captures an image. The obtained image data is obtained by the ISP circuit 245 converting it to gray scale image data. In the present embodiment, the ISP circuit 245 stores the obtained background grayscale image data in the SRAM 243. In this embodiment, the medal count circuit 246 detects the difference between the background grayscale image data and the input grayscale image data, and the medal image is included depending on whether or not the detected difference matches the medal shape. It was determined whether or not. However, the present invention is not limited to this, and it may be determined that a medal image is included when the number of detected difference pixels is equal to or greater than a certain number.

(2) Medal Position Detection Processing Next, the medal count circuit 246 performs medal position detection processing on the received grayscale image data. In the medal position detection process, the medal count circuit 246 determines whether or not a medal image exists in a predetermined determination area in the received grayscale image data, and stores the determination result in the SRAM 243.

  The predetermined determination area is a plurality of rectangular areas in the grayscale image data G2. In this embodiment, as shown in FIGS. 22 to 24, the determination areas A1 to A4, B1 to B4, C1, and C2 are used. , D1 to D4, E, and F, a total of 16 determination areas are set. 22A to 22C, FIGS. 23D to F, and FIG. 24G are diagrams for explaining the relationship between the determination area and the medal M that passes on the medal rail 210 and is discharged from the medal outlet portion 204c. FIG. 24H is a diagram for explaining the relationship between the medal guided by the medal chute 202 and the determination area.

  Each determination area is preliminarily defined on the program by defining the coordinate value (X, Y) of the corner of each determination area in the grayscale image data G2 so that a plurality of pixels are included in the determination area. ing. For example, as shown in FIG. 25, the determination region of C1 includes eight pixels in the region, and the coordinate values (450, 95), (454, 95), (450, 96), ( 454, 96) define the position. In FIG. 25, one square of the grid represents one pixel.

  As shown in FIGS. 22A to C, FIGS. 23D to F, and FIG. 24G, the determination areas A1 to A4 and B1 to B4 pass on the medal rail 210 and are below the image of the medal M that is discharged from the medal outlet portion 204c. It is arranged to overlap. In addition, the determination areas C1 and C2 are arranged so as to pass on the medal rail 210 and overlap with the upper part of the image of the medal M discharged from the medal outlet 204c. The determination areas E and F are arranged so as not to overlap the image of the medal M passing through the medal rail 210 and discharged from the medal exit portion 204c.

  Further, as shown in FIG. 24H, the determination area F is arranged below the grayscale image data G2 so as to overlap the image of the medal M when the medal is guided to the medal chute 202. The determination area E is located above the route of the medal M, and is arranged above the grayscale image data G2 so as to overlap images of various instruments used for fraud.

  The medal count circuit 246 calculates a luminance difference value of each pixel in each determination region of the grayscale image data and background grayscale image data to be processed, and calculates the number of pixels having the calculated difference value equal to or larger than a threshold value. Count for each judgment area. Then, the medal count circuit 246 determines whether or not the number of counted pixels is greater than or equal to a predetermined number for each determination area. If it is determined that the number is greater than or equal to the predetermined number, the medal image is displayed in the determination area. Is present (there is a medal). On the other hand, when it is determined that the number of counted pixels is less than the predetermined number, it is determined that there is no medal image (no medal) in the determination area. In this embodiment, the aspect of using grayscale image data in this processing has been described. However, the present invention is not limited to this. For example, for color determination generated by multiplying the saturation and hue used in the color determination processing described above. Data may be used.

  In addition, the medal count circuit 246 performs medal edge detection processing on a determination region in which it is determined that a medal image is present (there is a medal) in the medal position detection processing.

  The medal edge detection process is a process for detecting an outer edge (edge) of a medal based on an arrangement of pixels whose luminance difference value is less than a threshold value in a determination area where it is determined that a medal image exists. In the present embodiment, the movement direction of medals is from left to right in FIGS. Therefore, in the determined determination area where the medal image exists, if there is at least one pixel on the right side whose luminance difference value does not satisfy the threshold value, the medal count circuit 246 determines the front edge in the movement direction of the medal (movement destination direction). It is determined that there is a medal edge.

  On the other hand, if there is at least one pixel on the left side whose luminance difference value is less than the threshold value in the determined determination area where a medal image exists, the medal count circuit 246 determines the rear edge (after movement) in the movement direction of the medal. (Direction medal edge) is determined to exist. When there is no pixel whose luminance difference value does not satisfy the threshold value, the medal count circuit 246 determines that there is no outer edge of the medal in the determination area.

  For example, in the determination area C1 illustrated in FIG. 25, in any of the pixels 5C to 8C that are pixels on the right side, if there is even one pixel whose luminance difference value does not satisfy the threshold value, the movement direction medals It is determined that there is an edge. On the other hand, if any one of the pixels 1C to 4C located on the left side has a luminance difference value less than the threshold value, it is determined that there is a post-movement direction medal edge.

  For determination areas E and F, the movement direction of medals or various instruments is considered to be the downward direction from the top in FIGS. When there is even one pixel whose difference value is less than the threshold value, the medal count circuit 246 determines that there is a lower outer edge (moving destination direction medal edge) in the medal movement direction. On the other hand, when there is at least one pixel whose luminance difference value is lower than the threshold value above the pixel whose luminance difference value is equal to or higher than the threshold value, the medal counting circuit 246 determines that the medal counting circuit 246 has an upper outer edge (after movement) (Direction medal edge) is determined to exist. If there is no pixel whose luminance difference value is less than or equal to the threshold value for pixels located below or above the pixel whose luminance difference value is greater than or equal to the threshold value, the medal counting circuit 246 displays the medal in the determination area. It is determined that the image exists but there is no outer edge of the medal.

  The medal count circuit 246 then determines, for each determination area of the input grayscale image data, the determination result, that is, the determination result of whether or not a medal image exists in the determination area, and the movement direction medals edge. Alternatively, the determination result as to whether or not the post-movement medal edge exists is stored in the SRAM 243 in the order of input. For example, the medal count circuit 246 stores data “OFF” for the determination region where it is determined that there is no medal image. In addition, data “IN” is determined for a determination area where it is determined that a movement direction medal edge exists, data “OUT” is determined for a determination area where it is determined that a movement direction medal edge exists, and a medal image. “ON” is stored in the determination area determined that there is no outer edge of the medal. If it is determined in the medal image determination process that the medal image is not included, the medal count circuit 246 omits the medal position detection process and stores data “OFF” for all determination areas. May be.

  Further, the medal count circuit 246 omits the determination of the determination areas A1 to A4, B1 to B4, C1, C2, and D1 to D4 when the medal cannot be inserted, for example, when the credit counter is the maximum value as described later. To do. Further, in this case, the medal count circuit 246 indicates to the SRAM that the above determination is omitted for the determination areas A1 to A4, B1 to B4, C1, C2, and D1 to D4, that is, “not determined”. * ”Data (a specific numerical value is hexadecimal“ FF ”).

  Therefore, the determination area determination result data as shown in FIG. 26 is stored in the SRAM 243 for the eight gray scale image data G2 shown in FIGS. For example, for the grayscale image data G2 in FIG. 22A, since it is determined that there is a moving direction medal edge for the determination areas A1 and A2, data “IN” (specific numerical values are hexadecimal numbers). “01”) is stored, and it is determined that no medal image exists for the other determination areas. Therefore, data “OFF” (specifically, “00” in hexadecimal) is stored. Remembered.

  For the grayscale image data in FIG. 23E, since it is determined that no medal image exists for the determination areas A1 to A4, E, and F, data “OFF” is stored. For the determination areas B1, B2, C1, and C2, since it is determined that there is a post-movement medal edge, data “OUT” (specifically, “02” in hexadecimal) is stored. Is done. In addition, for the determination areas B3, B4, D1 to D4, there is a medal image, but it is determined that there is no outer edge of the medal. Therefore, data “ON” (specific numerical values are hexadecimal “ 03 ") is stored.

  In addition, regarding the grayscale image data G2 shown in FIG. 24H, it is determined that there is a medal image in the determination area F, but there is no outer edge of the medal, so data “ON” is stored. For the determination areas A1 to A4, B1 to B4, C1, C2, and D1 to D4, data “*” indicating that the determination is not made is stored.

  Note that the grayscale image data G2 in FIGS. 22A to 22C, 23D to 24F, and 24G is obtained from the ISP circuit 245 to the medal count circuit when the medal passes on the medal rail 210 and is ejected from the medal exit 204c. Among the grayscale image data G2 received by the H.246, seven grayscale image data G2 are extracted for convenience of explanation. That is, in this case, the grayscale image data received by the medal count circuit 246 exists in addition to the grayscale image data G2 shown in FIGS. 22A to 22C, FIGS. 23D to F, and FIG.

  In addition, the SRAM 243 is provided with a storage area for storing the determination results relating to a predetermined number of grayscale image data as determination area determination result data. When the determination result stored in the SRAM 243 reaches the upper limit number, the stored order is overwritten from the determination result related to the old grayscale image data.

(3) Order determination process After the medal image detection process and the medal position detection process, the medal count circuit 246 performs the order determination process. In the order determination process, in a predetermined number of grayscale image data arranged in time series, the transition mode of data “IN”, “OUT”, “ON”, “OFF” for each determination region is a predetermined transition. It is determined whether or not the medals match, and if they match, it is determined that the medals have passed on the medal rail 210.

  Here, as a predetermined transition mode, in this embodiment, the medal count determination table shown in FIG. 27 is converted into a numerical value and stored in the flash memory 244. In the medal count determination table, “IN” and “IN” in each determination area on the 14 grayscale image data arranged in time series when the medal passes on the medal rail 210 and is ejected from the medal exit portion 204c. The mode of data transition of “OUT”, “ON”, “OFF” is defined. Note that these data transition modes are defined in advance by simulations and experiments.

  In the order determination process, the medal count circuit 246 displays the data transition mode in each determination area of the latest 14 grayscale image data stored in the SRAM 243 and the time series 1 defined by the medal count determination table. The data transition modes corresponding to ˜14 are compared, and when they completely match, it is determined that “the medal has passed”. If they do not match, it is determined that “abnormality has occurred”. If they do not match, for example, the first half of the data transition mode (hereinafter referred to as “transition mode of data to be compared” in some cases) in each determination region of the latest 14 grayscale image data Is consistent with the data transition mode corresponding to the time series 1 to 8 specified in the medal count determination table, but the following part is the data corresponding to the time series 8 to 4 specified in the medal count determination table. There is a case where it coincides with the mode of transition (hereinafter, this case may be referred to as “reverse in time series”). In addition, if they do not match, for example, the first half of the transition mode of the comparison target data matches the transition mode of the data corresponding to the time series 1 to 7 defined in the medal count determination table. When the subsequent portion matches the data transition mode corresponding to the time series 10 to 14 specified in the medal count determination table, that is, the data corresponding to the time series 8 and 9 specified in the medal count determination table May be missing. In the case where they do not match, for example, the first half part of the transition mode of the data to be compared matches the transition mode of the data corresponding to the time series 1 to 8 defined in the medal count determination table. When the subsequent portions all match the data transition mode corresponding to the time series 9 defined in the medal count determination table, that is, the same transition mode may overlap. Note that the above-mentioned time-series retrograde corresponds to an existing medal retrograde error, and if the same transition mode overlaps, it corresponds to an existing medal jamming error. Further, when the above data is missing, it is an error that could not be detected by the existing medal selector, and the medal selector 201 that can detect the error has better error detection performance than the existing medal selector. It can be said.

  Further, the medal count circuit 246 is defined by the data transition mode in each determination region of the latest four gray scale image data stored in the SRAM 243 and the medal count determination table when the medal cannot be inserted. The data transition modes corresponding to the current time series E1 to E4 are compared, and if they completely match, it is determined that “the medal is guided to the medal chute 202”.

  Note that when the number of grayscale image data stored in the SRAM 243 is less than a predetermined number, for example, less than 4 or 14, the transition mode does not match due to the lack of the number of data. In the comparison processing, it is not determined that “the medal has passed” or “the medal has been guided to the medal chute 202”. In this case, the comparison process may be omitted.

  In addition, the medal count circuit 246 stores data “IN”, “OUT”, or “ON” for the determination region E of the latest grayscale image data stored in the SRAM 243. It is determined that an abnormality has occurred.

  In the order determination process, the medal count circuit 246 stores the determination result in the order determination process in the SRAM 243 as the determination result of the count process. That is, in the SRAM 243, as the determination result of the count process, “medal has passed” (a specific value is hexadecimal “01”), “a medal is guided to the medal chute 202” (specific value) Three types of determination results are stored: “02” in hexadecimal number) and “abnormality has occurred” (specific numerical value is “10” in hexadecimal number). Here, the case where it is determined that “a medal has passed” is, for example, a case where a medal is inserted in a state where the main control circuit 91 can insert a medal. The case where it is determined that “the medal has been guided to the medal chute 202” means that the main control circuit 91 is in a state where the medal can be inserted and an illegal medal having an outer diameter smaller than the prescribed medal is inserted, This is a case where a medal is inserted while the control circuit 91 cannot insert a medal. In addition, the case where it is determined that “abnormality has occurred” is compared with the case where some foreign object is detected outside the range where the medal passes or the data transition mode defined in the medal counter determination table described above. This is a case where the transition mode of the target data does not match.

  As a result of the comparison, instead of determining that “the medal has passed” or “the medal has been guided to the medal chute 202” in the case of a perfect match, the degree of match is 80% or more, for example. In this case, it may be determined in consideration of a predetermined determination margin that “the medal has passed” or “the medal chute 202 has been guided”.

  In the medal position detection process, the medal edge detection process may be omitted. In this case, the medal count circuit 246 stores data “OFF” in the SRAM 243 for the determination area determined that the medal image does not exist, and “ON” for the determination area determined that the medal image exists. Is stored. Then, the mode of transition of “ON” and “OFF” data in each determination area is defined in the medal count determination table shown in FIG.

  Further, in the order determination process, instead of the comparison using the medal count determination table shown in FIG. 27, the order of the determination areas in which “ON” data is stored is specified in advance, and the predetermined order and the actual It is also possible to determine the passage of medals by comparing the order of the determination areas in which the data “ON” is stored. In this case, the predetermined order is grouped into the determination areas A1 to A4 as the A area, the determination areas B1 to B4 as the B area, the determination areas C1 and C2 as the C area, and the determination areas D1 to D4 as the D area. It may be defined by For example, in a predetermined order, all of the A to D areas are “OFF”, then only the A area is “ON”, then the A area, the B area, and the C area are “ON”, and then the B area, the C area, and the D area. May be “ON”, then only the D region may be “ON”, and finally any of the A to D regions may be “OFF”. In this case, the A area is “ON” means that “ON” data is stored in any of the determination areas A1 to A4.

  Further, the number, shape, and arrangement location of the determination areas set on the gray scale image data can be set as appropriate according to the allowable determination required time and the accuracy of the determination to be obtained. For example, a determination region extending in the vertical direction from the upper end portion to the lower end portion of the grayscale image data G2 in FIGS. 22A to 22C, FIGS. 23D to 24F, and FIGS.

<Fisheye correction scaler circuit>
The fisheye correction scaler circuit 248 acquires the grayscale image data from the SRAM 243, and performs fisheye correction processing for correcting the acquired grayscale image data with fisheye.

  The fisheye correction scaler circuit 248 performs equalization processing on the grayscale image data that has been subjected to fisheye correction processing. In the equalization processing, the fisheye correction scaler circuit 248 creates reduced image data reduced to 1/2, 1/4, and 1/8.

  In addition, the fisheye correction scaler circuit 248 performs bilateral conversion processing on each of the created reduced image data in the equalization processing. In this embodiment, a Gaussian filter of a 3 × 3 kernel (a kernel in image processing, not a kernel indicating an OS function) shown in FIG. 28 is used to remove noise from reduced image data. However, the Gaussian filter has a drawback that the edges in the image data are not noticeable (blur). Therefore, in order to eliminate this drawback, a bilateral filter represented by the following Expression 3 is adopted as a processing algorithm for bilateral conversion processing. That is, the bilateral filter is a filter that removes noise of image data and performs edge correction and enhancement using a Gaussian filter kernel.

  In Equation 1, the array of image data before bilateral conversion processing is f (i, j), and the array of image data after processing is g (i, j). In addition, w represents a kernel size, σ represents a standard deviation, and d represents a difference in luminance value.

  Then, the fish-eye correction scaler circuit 248 stores the reduced image data subjected to equalization processing in the SRAM 243. The SRAM 243 is provided with a storage area capable of storing a predetermined number of reduced image data. When the number of reduced image data stored in the SRAM 243 reaches the upper limit, the stored order is overwritten from the old reduced image data.

<Image recognition DSP circuit>
When the medal count circuit 246 determines that the medal has passed on the medal rail 210, the host controller 241 uses the reduced image data a predetermined time before (ie, a predetermined frame before) the determination. The image recognition DSP circuit is instructed to perform preprocessing. Note that the predetermined time is set in advance based on experiments and simulations so that a reduced image before the predetermined time always includes a medal image.

  In the preprocessing, the image recognition DSP circuit 242 acquires reduced image data (in this embodiment, reduced image data reduced to ¼) from the SRAM 243, and detects a circular area from the acquired reduced image data. Processing and non-linear diffusion filter processing are performed to create an edge image and store it in the SRAM 243. The image recognition DSP circuit 242 performs various determination processes described later. In this embodiment, the image data reduced to ¼ is used. However, the present invention is not limited to this, and the setting for selecting the reduced image data to be used is stored in the flash memory 244, and according to the setting. Thus, the image data reduced to ½ or the image data reduced to ８ may be selected.

(1) Circle Area Detection Processing In the circle area detection process, the image recognition DSP circuit 242 generates a background difference image indicating a difference between the acquired reduced image data and reduced background grayscale image data corresponding to the reduced image data. To do. Here, the reduced background grayscale image data is image data obtained by performing fisheye correction processing and equalization processing by the fisheye correction scaler circuit 248 on the background grayscale image data stored in the SRAM 243. Previously stored in SRAM 243.

  Next, the image recognition DSP circuit 242 binarizes the generated background difference image. Then, as shown in FIG. 29, template matching is performed on the binary background difference image G3 using a binary outline template T1 indicating the outline of the medal. That is, the image recognition DSP circuit 242 specifies where in the background difference image G3 a region similar to the outer shape template T1 exists. In other words, the image recognition DSP circuit 242 specifies where in the background difference image G3 there is an area that matches the outline of the medal indicated by the outline template T1. Note that the outline template T1 is stored in the flash memory 244 in advance.

  In template matching, the outline template T1 is moved little by little (for example, one pixel (pixel) at a time) in the raster scan direction on the background difference image G3. In other words, the image recognition DSP circuit 242 raster scans the outer shape template T1 on the background difference image G3. At this time, the image recognition DSP circuit 242 generates an AND image of the outline template T1 and the partial region of the background difference image G3 that overlaps the outline template T1 at each position of the outline template T1. Thereby, a plurality of binary AND images are generated. Then, the image recognition DSP circuit 242 calculates the background difference of the outline template T1 used in generating the AND image having the largest number of pixels (high luminance pixels) having the pixel value “1” among the plurality of generated AND images. A position on the image G3 is specified. This position is a position where a region similar to the outline template T1 exists in the background difference image G3.

  Then, the image recognition DSP circuit 242 detects a partial area in the acquired reduced image data that exists at the same position as the specified position as a circular area. In other words, the image recognition DSP circuit 242 detects a partial region in the reduced image data that overlaps the outer shape template T1 as a circular region when the outer shape template T1 is arranged in the reduced image data at the same position as the specified position. . At this time, in the partial area, a circular area may be defined by setting the pixel value of each pixel outside the circle indicated by the outer shape template T1 above to zero. The circular area extracted by the image recognition DSP circuit 242 is a gray scale image. In the present embodiment, the outer shape of the circular region is a quadrangle, but may be another shape such as a circle.

  It should be noted that other methods may be employed as a method for extracting the circular area from the acquired reduced image data. For example, you may employ | adopt the extraction method using that the external shape of a medal is circular. In this extraction method, first, edge detection is performed on the acquired reduced image data to generate an edge image. As an edge image generation method, for example, Sobel method, Laplacian method, Canny method and the like are used. Next, a circular area is extracted from the generated edge image. For example, Hough transform is used as a method for extracting a circular region. A circular area in the acquired reduced image data that exists at the same position as the position of the circular area in the edge image is set as a circular area.

  Further, an extraction method for extracting a circular region from reduced image data acquired using the background difference method and labeling may be employed. In this extraction method, first, a background difference image indicating a difference between the acquired reduced image data and reduced background grayscale image data is generated, and the generated background difference image is binarized. Then, labeling such as 4-connection is performed on the binary background difference image. A partial area of the acquired reduced image data that exists at the same position as the connected area (independent area) obtained as a result of labeling in the binary background difference image is set as a circular area.

(2) Filter processing The image recognition DSP circuit 242 performs filter processing after the circular area detection processing. The filter process includes a 3σ correction process and a non-linear diffusion filter process.
First, in the 3σ correction process, the image recognition DSP circuit 242 cuts out the image data of the circular area in the acquired reduced image data based on the circular area detected by the circular area detection process. Hereinafter, the cut-out image data may be referred to as circle area image data.

Next, the image recognition DSP circuit 242 creates a normal distribution (see FIG. 30) centering on the average value of the data in a certain range for the luminance value in the extracted circular area image data. Here, 3σ is three times the standard deviation, and almost all data belongs within the range of the average value ± 3σ (if the variation is a normal distribution, 99.7% of the data falls within this range. Belonging).
Then, the luminance of a pixel having a luminance value smaller than −3σ, for example, the luminance of a pixel of −4σ is replaced with a luminance value of −3σ. Further, the luminance of a pixel having a luminance value larger than 3σ, for example, the luminance of a pixel of 4σ is replaced with a luminance value of 3σ. By doing so, pixels that have extremely large luminance values (pixels that are too bright) or pixels that have extremely small luminance values (pixels that are too dark), which are irregular data, affect subsequent processing. Can be suppressed.

  Next, the image recognition DSP circuit 242 performs non-linear diffusion filter processing on the circular region image data after the 3σ correction processing, and generates an edge image X in the X (vertical) direction and an edge image Y in the Y (horizontal) direction. To do.

FIG. 31A schematically shows the circular area image data after the 3σ correction processing. In FIG. 31A, one square of the grid indicates a pixel. FIG. 31B shows edge image X coefficients. Here, when the luminance values of the pixels A1 to A8 and P in FIG. 31A are a1 to a8 and p, respectively, the luminance value of the pixel of interest P in the edge image X is as follows using the coefficient for the edge image X: It is calculated by the following formula 4.
P brightness (PX) = a1 × (−3) + a2 × 0 + a3 × 3 + a4 × (−10) + p × 0 + a5 × 10 + a6 × (−3) + a7 × 0 + a8 × 3 (4)

  The image recognition DSP circuit 242 creates the edge image X by calculating the luminance using the above equation 4 for all the pixels of the circular area image data after the 3σ correction process.

FIG. 31C shows the edge image Y coefficient. Here, assuming that the luminance values of the pixels A1 to A8 and P in FIG. 31A are a1 to a8 and p, respectively, the luminance value of the target pixel P in the edge image Y is as follows using the edge image Y coefficient. It is calculated by the following formula 5.
P brightness (PY) = a1 × (−3) + a2 × (−10) + a3 × (−3) + a4 × 0 + P × 0 + a5 × 0 + a6 × 3 + a7 × 10 + a8 × 3 (5)

  The image recognition DSP circuit 242 creates the edge image Y by calculating the luminance using the above equation 5 for all the pixels of the circular area image data after the 3σ correction processing.

  After creating the edge image X and the edge image Y, the image recognition DSP circuit 242 creates the edge image XY from both images. The luminance PXY of each pixel in the edge image XY is calculated by the following formula 6 when the luminance value of the pixel in the edge image X is PX and the luminance value of the pixel in the edge image Y at the same position is PY. be able to.

The image recognition DSP circuit 242 creates the edge image XY by calculating the luminance PXY using the above equation 6 for all the pixels of the edge image X and the edge image Y, and stores the created edge image XY in the SRAM 243. Let
Various determination processes performed by the image recognition DSP circuit 242 will be described later.

<Image recognition accelerator circuit>
The image recognition accelerator circuit 249 performs processing related to the gradient average image data and processing related to the edge gradient image.

[Processing related to gradient average image data]
The process related to the gradient average image data includes a rotation image generation process, a gradient average image data generation process, and a gradient average image template generation process.

(1) Rotated Image Generation Processing In the rotated image generation processing, the image recognition accelerator circuit 249 acquires the edge image XY from the SRAM 243, rotates the acquired edge image XY in units of 1 degree, and generates a rotated image for 360 degrees. Generate.

(2) Gradient average image data generation processing In the gradient average image data generation processing, the image recognition accelerator circuit 249 cumulatively adds (superimposes) the 360-degree rotated images generated in the rotated image generation processing, and then calculates the gradient average. Generate image data. As an example of the gradient average image data, the average medal gradient average image data shown in FIG. 32A is shown in FIG. 32B. Then, the image recognition accelerator circuit 249 stores the generated gradient average image data in the SRAM 243.

(3) Gradient average image template generation process The gradient average image template generation process is a process of generating a gradient average image template that is image data used in the determination process of the image recognition DSP circuit 242 described later.

  In the gradient average image template generation processing, the image recognition accelerator circuit 249 compares the 50 gradient average image data stored in the SRAM 243 (that is, related to 50 medals) with each other and matches or is similar to a predetermined degree. The gradient average image data to be grouped. Next, the image recognition accelerator circuit 249 selects the top four groups in descending order of the number of gradient average image data to which the image recognition accelerator circuit 249 belongs. Then, for each of the selected top four groups, any one gradient average image data is selected, and the four gradient average image data are used as the gradient average image template in the storage area for storing the gradient average image template of the SRAM 243. Remember. For each of the selected top four groups, instead of selecting any one gradient average image template, the average value of the gradient average image data belonging to the same group (the average value of the luminance associated with each pixel) May be used to generate a gradient average image template. Further, the gradient average image template stored in the SRAM 243 may be deleted by initialization processing (not shown) of the host controller 241 when the gaming machine is turned on.

  As described above, by generating a gradient average image template, for example, when two kinds of medals with different markings (patterns) on the front and back are used as regular medals, 50 regular medals are inserted after the power is turned on. By doing so, it is possible to generate a maximum of four types of gradient average image templates related to the front and back of these two types of medals. When there is one type of 50 regular medals inserted after power-on, two types of gradient average image templates related to the front and back of the regular medals are generated, and a gradient average image template comparison process described later is performed. Then, the two types of generated gradient average image templates are used.

  Here, in the gradient average image template generation process, when the gradient average image template is not stored in the storage area of the SRAM 243, until the number of medals inserted after power-on reaches the specified initial number, in this embodiment, 50. The gradient average image data is used. The image recognition accelerator circuit 249 stores the generated gradient average image data in the gradient average image template generation data storage area of the SRAM 243 until the gradient average image data generated in the gradient average image data generation process reaches 50 pieces. Further, when 50 gradient average image data are stored in the gradient average image template generation data storage area of the SRAM 243, the image recognition accelerator circuit 249 performs gradient average image template generation processing. The image recognition accelerator circuit 249 stores the gradient average image data generated by the gradient average image data generation process in the determination target gradient average image data storage area of the SRAM 243 after the execution of the gradient average image template generation process. In the present embodiment, when 50 gradient average image data are stored in the SRAM 243, the gradient average image template is generated by grouping the gradient average image data that coincides or is similar to a predetermined degree. However, the present invention is not limited to this. Every time gradient average image data is generated, the gradient average image data is compared with the previously stored gradient average image data, and the gradient average image data that matches or is similar to a certain degree is grouped to obtain the gradient average. An image template may be generated.

[Processing related to edge gradient image]
The processing related to the edge gradient image includes polar coordinate conversion processing, Charrr conversion processing, HOG conversion processing, and HOG template generation processing.

(1) Polar Coordinate Conversion Processing In the polar coordinate conversion processing, the image recognition accelerator circuit 249 acquires the edge image XY from the SRAM 243, converts the orthogonal coordinates into polar coordinates for the acquired edge image XY, and creates polar coordinate image data. Specifically, the image recognition accelerator circuit 249 displays polar coordinates (r, φ) representing the orthogonal coordinates (x, y) of each pixel of the edge image XY by the length r of the moving radius and the angle φ from the reference position. ). The relationship between polar coordinates (r, φ) and orthogonal coordinates (x, y) is expressed by the following equations 7 and 8.
x = r cos (φ) (7)
y = r sin (φ) (8)

  Then, the image recognition accelerator circuit 249 stores the created polar coordinate image data in the SRAM 243.

(2) Charr Conversion Processing In the Charr conversion processing, the image recognition accelerator circuit 249 obtains polar coordinate image data from the SRAM 243 and creates an edge polar coordinate image X in the X (vertical) direction and an edge polar coordinate image Y in the Y (horizontal) direction. To do. Therefore, the image recognition accelerator circuit 249 that performs the Charr conversion process constitutes a directional image separation unit that separates the polar coordinate image into a vertical image and a horizontal image.
In addition, since the aspect which creates the edge polar coordinate image X and the edge polar coordinate image Y in the Scherr transform process is the same as the aspect in which the edge image X and the edge image Y are created in the nonlinear diffusion filter process described above, The description is omitted here.

(3) HOG Conversion Processing In the HOG conversion processing, the image recognition accelerator circuit 249 creates an edge gradient image and performs HOG conversion on the created edge gradient image. Here, HOG (Histograms of Oriented Gradients) conversion is a histogram of the luminance gradient direction of a local region (cell) in image data. For image matching accompanied by HOG conversion, local shape change ( It has a feature that it is resistant to geometric transformation and is not easily influenced by fluctuations in illumination.

  Specifically, an edge gradient image is created from the edge polar coordinate image X and the edge polar coordinate image Y created by the Charrr conversion process. The brightness of each pixel in the edge gradient image, that is, the gradient strength, is expressed by the following formula 9 when the pixel brightness value in the edge polar coordinate image X is QX and the pixel brightness value in the edge polar coordinate image Y at the same position is QY. Can be calculated.

In addition, the gradient angle of each pixel in the edge gradient image can be calculated by the following Expression 10.
Gradient angle = tan ⁻¹ (QY / QX) (10)

  In FIG. 33, the created edge gradient image G4 is schematically shown. The image recognition accelerator circuit 249 creates a histogram of the luminance gradient direction in the local area for each local area, with the rectangular frame S indicated by the two-dot chain line in the created edge gradient image G4 as the local area (cell). . Then, the created histogram set is stored in the SRAM 243.

[HOG template generation processing]
The HOG template generation process is a process for generating an HOG template used in the determination process of the image recognition DSP circuit 242 described later.

  In the HOG template generation process, the image recognition accelerator circuit 249 compares the above set of histograms stored in the SRAM 243 (that is, related to 50 medals) with each other, and a set of histograms that match or are similar to a predetermined degree. Group. Next, the image recognition accelerator circuit 249 selects the top four groups in descending order of the number of histogram sets to which the image recognition accelerator circuit belongs. Then, for each of the selected top four groups, an arbitrary set of histograms is stored as a HOG template in a storage area for storing the HOG template in the SRAM 243. For each of the selected top four groups, instead of selecting an arbitrary set of histograms, the average value of the set of histograms belonging to the same group (the average value of the gradient strength in the same local region) is calculated. Thus, the HOG template may be generated. In this embodiment, when 50 sets of histograms are stored in the SRAM 243, the stored histograms are compared with each other, and a set of histograms that match or are similar to a certain degree are grouped to generate a HOG template. The embodiment has been described. However, the present invention is not limited to this, and each time a set of histograms is generated, a set of histograms that are matched or similar to a predetermined degree may be grouped by comparing with a previously stored set of histograms to generate a HOG template. .

  As described above, by generating the HOG template, for example, when two types of medals with different markings (patterns) on the front and back are used as regular medals, the HOG template is stored in the storage area of the SRAM 243. If not, 50 types of regular medals are inserted after the power is turned on, so that four types of HOG templates related to the front and back of these two types of medals can be generated. In addition, when the HOG template is not stored in the storage area of the SRAM 243 and there are one type of 50 regular medals inserted after power-on, two types of HOGs related to the front and back of the regular medals A template is generated, and two types of generated HOG templates are used in the HOG template comparison process described later.

  Note that the matching or similarity determination of a set of histograms is performed by comparing histograms for the same position (local region at the same position in the edge gradient image) in the set of histograms. Moreover, the criterion of determination can be set as appropriate. For example, it may be determined that both sets of histograms match on condition that all histograms match completely. Alternatively, it may be determined that both sets of histograms are similar on the condition that there is no histogram having a degree of coincidence of a predetermined degree or less, for example, 80% or less.

  Here, the HOG template generation process is performed using a set of histograms related to the edge gradient image until the number of medals inserted after power-on reaches the specified initial number of sheets, in this embodiment, 50 sheets. The image recognition accelerator circuit 249 stores the created histogram set in the HOG template generation data storage area of the SRAM 243 until the set of histograms created in the HOG conversion process reaches 50 sets. The image recognition accelerator circuit 249 performs HOG template generation processing when 50 sets of histograms are stored in the HOG template generation data storage area of the SRAM 243. The image recognition accelerator circuit 249 stores the set of histograms created by the HOG conversion process in the determination target histogram storage area of the SRAM 243 after executing the HOG template generation process.

<Determination Processing by Image Recognition DSP Circuit>
Next, determination processing executed by the image recognition DSP circuit 242 will be described. The determination process includes a gradient average image template comparison process and a HOG template comparison process.

(1) Gradient average image template comparison process In the gradient average image template comparison process, the image recognition DSP circuit 242 acquires the gradient average image data generated by the image recognition accelerator circuit 249 from the determination target gradient average image data storage area of the SRAM 243. .

  Next, the image recognition DSP circuit 242 calculates a difference between the acquired gradient average image data and the gradient average image template stored in the SRAM 243. Then, the image recognition DSP circuit 242 determines whether or not the gradient average image data and the gradient average image template match or are similar to each other based on the calculated difference value and the threshold value for marking determination. Then, “Yes” or “No” is stored in the SRAM 243 as the determination result. In this embodiment, since up to four gradient average image templates are used, up to four determination results are stored in the SRAM 243. In the gradient average image template comparison process, the gradient average determination result is stored in the SRAM 243. Here, when at least one “Yes” is stored as the determination result for the maximum of four templates, “Yes” is stored in the SRAM 243 as the gradient average determination result, and all “No” is stored. Is stored in the SRAM 243 as the gradient average determination result. Accordingly, in one gradient average image template comparison process, a maximum of four determination results for up to four gradient average image templates and one gradient average determination result based on these determination results are stored.

  For example, the image recognition DSP circuit 242 compares the luminance of each pixel of the acquired gradient average image data and the gradient average image template (calculates a difference), and determines whether the luminance of these pixels matches from the difference value. Alternatively, it is determined whether or not the difference is within a predetermined range. If there is a certain number of pixels that match or the difference is within the predetermined range, it is determined that the gradient average image data and the gradient average image template match or are similar to a predetermined degree. . On the other hand, if the number of matching pixels is less than a certain number, it is determined that the gradient average image data and the gradient average image template are identical or not similar to a predetermined degree.

(2) HOG Template Comparison Processing In the HOG template comparison processing, the image recognition DSP circuit 242 acquires a set of determination target histograms from the determination target histogram storage area. Next, it is determined whether or not the acquired histogram set matches the HOG template stored in the SRAM 243 or is similar to a predetermined degree, and “Yes” or “No” is stored in the SRAM 243 as a determination result. In the present embodiment, since a maximum of four HOG templates are used, a maximum of four determination results are stored in the SRAM 243. In the HOG template comparison process, the HOG determination result is stored in the SRAM 243. Here, when at least one “Yes” is stored as the determination result for the maximum of four templates, “Yes” is stored as the HOG determination result in the SRAM 243 and all “No” is stored. “NO” is stored in the SRAM 243 as the HOG determination result. Therefore, in one HOG template comparison process, a maximum of four determination results for a maximum of four HOG templates and a single HOG determination result based on these determination results are stored.

  Note that the determination of the match or similarity between the acquired histogram set and the HOG template is the same as the determination of the match or similarity between the histogram sets in the HOG template generation process described above, and thus the description thereof is omitted here.

  As described above, the image recognition DSP circuit 242 that performs the gradient average image template comparison process and the HOG template comparison process constitutes a game medium determination unit that determines whether or not an object that has passed on the medal rail 210 is a regular medal. To do.

<GPIO>
GPIO 250 (see FIG. 18) is a device for input / output with each device connected to medal selector 201. For example, the medal count output PORT and the medal determination output PORT of the GPIO 250 are connected to the main control circuit 91 via the door relay terminal board 68. Further, the LED control output PORT of the GPIO 250 is connected to the LED 233 so that the medal selector 201 can control the turning on and off of the LED 233.

<Host controller>
The host controller 241 controls each device constituting the control LSI 234, for example, the medal count circuit 246, the color recognition circuit 247, the fisheye correction scaler circuit 248, the image recognition DSP circuit 242, the image recognition accelerator circuit 249, and the GPIO 250.

  In addition, the host controller 241 outputs a signal relating to a lighting instruction or a lighting instruction to the LED 233 via the GPIO 250. Further, the host controller 241 determines the determination result related to the count processing stored in the SRAM 243 via the GPIO 250, that is, “medal passed”, “medal guided to the medal chute 202”, and “abnormal” Is output ”. Specifically, when the determination result is “medal has passed”, the medal count signal is output from the medal count output PORT, and when “the abnormality has occurred”, the medal abnormality signal is output from the medal determination output PORT. Is output. In addition, a determination result related to the color determination process is output. Specifically, when “threshold determination impossible” is stored in the SRAM 243 as the determination result of the threshold determination process, or when “not” is stored as the color determination result, the medal determination output assigned to the GPIO 250 A medal abnormality signal is output from the PORT when a predetermined output condition is satisfied. In addition, a determination result related to the determination process by the image recognition DSP circuit 242 is output. Specifically, when “No” is stored in the SRAM 243 as the gradient average determination result or the HOG determination result, the medal abnormality signal is output from the medal determination output PORT assigned to the GPIO 250 under a predetermined output condition. Output when established.

  The predetermined output condition can be set as appropriate. For example, the predetermined output condition may be set as when “abnormality has occurred” is stored in the SRAM 243 as the determination result of the count process. Alternatively, it may be set that “threshold determination impossibility” is stored in the SRAM 243 as a determination result of the threshold determination process continuously or cumulatively for a prescribed number (for example, 10 times) or more. Further, even when “NO” is stored in the SRAM 243 as the gradient average determination result or the HOG determination result continuously or cumulatively, a predetermined number (for example, 10 times) or more is stored. Good.

  The SRAM 243 is connected to a backup power source (not shown), and the contents stored in the SRAM 243 are retained for a certain period (for example, about one week) even when the power of the pachislot machine 1 is turned off. Further, the host controller 241 receives an initialization switch (not shown) disposed on a switch board (not shown) provided at an arbitrary location of the medal selector 201 (for example, in the vicinity of the first board 231) via the GPIO 250. Various templates stored in the SRAM 243 such as a color template, a gradient average image template, and a HOG template can be deleted. Specifically, by turning on the power of the pachislot 1 while the initialization switch is pressed, the initialization area of the SRAM 243 in which various templates are stored is initialized (a value of 0 is set) during the initialization process of the host controller 241. Write), that is, erase various templates.

<Flash memory>
In the flash memory 244, various devices constituting the control LSI 234, for example, a host controller 241, an image recognition DSP circuit 242, a fisheye correction scaler circuit 248, an image recognition accelerator circuit 249, parameters used for various processes and necessary for various processes. Data is stored.

<Processing flow of control LSI>
Next, processing performed by the control LSI 234 will be described with reference to FIG. FIG. 34 is a processing flowchart for explaining the processing performed by the control LSI 234.
As shown in FIG. 34, the control LSI 234 roughly performs input processing, conversion processing, color determination processing, count processing, and marking determination processing.

<Input processing>
Input processing is performed by the ISI circuit 251. In the input process, as described above, the ISI circuit 251 converts the image data transmitted from the CMOS image sensor 232 by the LVDS method into an RGB Bayer image and outputs the RGB Bayer image to the ISP circuit 245.

<Conversion processing>
The conversion process is performed by the ISP circuit 245. In the conversion process, the ISP circuit 245 performs an image correction process that performs a lens distortion correction process and a projective conversion (homography) process on the RGB Bayer image output from the ISI circuit 251. Next, the ISP circuit 245 performs color conversion processing for converting the corrected RGB Bayer image into YUV image data and outputting the grayscale image data to the medal count circuit 246. Further, the RGB Bayer image is converted into HSV image data, and color conversion processing for outputting the HSV image data to the color recognition circuit 247 is performed.

  After the conversion processing, the control LSI 234 performs color determination processing, count processing, and marking determination processing. These processes are executed in parallel at each executable timing because the circuits for executing the processes are configured as separate circuits.

<Color judgment processing>
The color determination process is performed by the color recognition circuit 247. The color determination processing includes medal detection processing, threshold determination processing, saturation / hue multiplication processing, color template generation processing, and color template comparison processing.

  First, the color recognition circuit 247 performs a medal detection process for determining whether the HSV image data received from the ISP circuit 245 includes a medal image. When it is determined that a medal image is included in the HSV image data, the color recognition circuit 247 performs a threshold determination process based on the HSV image data. In the threshold determination process, if the position on the threshold graph (see FIG. 21) based on the average saturation value and the average hue value is within the allowable region, the color determination process is continued. On the other hand, if it is within the non-permissible region, “threshold value determination impossible” is stored in the SRAM 243 as the determination result, and the color determination process is terminated.

  After the threshold determination processing, the color recognition circuit 247 performs saturation / hue multiplication processing to create color determination data. Then, the created color determination data is compared with the color template to determine whether they match or are similar to a predetermined degree, and the determination result is stored in the SRAM 243.

  It should be noted that the color template comparison process is not executed until the number of medals inserted after power-on reaches the specified initial insertion number, which is 50 in this embodiment, since no color template has been generated.

  Further, the color recognition circuit 247 determines that when the number of medals inserted after power-on reaches the prescribed initial insertion number of 50 and the number of color determination data stored in the color determination data storage area reaches 50, that is, 50 sheets. When the color determination data relating to the medal is created, a color template generation process is executed.

<Count processing>
The count process is performed by the medal count circuit 246. The count process includes a medal detection process and an order determination process. The medal detection process and the medal position detection process described above correspond to the medal detection process. In the medal detection process, the medal count circuit 246 determines whether the received grayscale image data includes a medal image. Further, it is determined whether or not a medal image exists in a predetermined determination area in the received grayscale image data, and the determination result (data of “IN”, “OUT”, “ON”, “OFF”) is stored in the SRAM 243. Remember.

  In the order determination process, the medal count circuit 246 changes the data of “IN”, “OUT”, “ON”, and “OFF” for each determination region in a predetermined number of grayscale image data arranged in time series. It is determined whether or not the mode of is consistent with a predetermined mode of transition. Then, the determination result is stored in the SRAM 243 as “medal has passed”, “medal was guided to the medal chute 202”, or “abnormality has occurred”. Further, when “S medal passed” is stored in the SRAM 243, the host controller 241 outputs a medal count signal from the medal count output PORT allocated to the GPIO 250. Based on the medal count signal, the main control circuit 91 detects that a medal has been inserted, and counts the number of inserted coins or the number of credits.

<Engraving process>
The marking determination processing includes fisheye correction processing and equalization processing performed by the fisheye correction scaler circuit 248, circle region detection processing performed by the image recognition DSP circuit 242, filter processing, gradient average image template comparison processing, and HOG template comparison. Processing is included. Also included are a rotation image generation process, a gradient average image data generation process, a gradient average image template generation process, a polar coordinate conversion process, a Charr conversion process, a HOG conversion process, and a HOG template generation process performed by the image recognition accelerator circuit 249.

  In the fisheye correction process, the fisheye correction scaler circuit 248 acquires the grayscale image data from the SRAM 243 and performs a fisheye correction process for correcting the acquired grayscale image data with a fisheye. Next, in the equalization processing, the fisheye correction scaler circuit 248 performs equalization processing on the grayscale image data that has been subjected to fisheye correction processing, creates reduced image data, and stores the reduced image data in the SRAM 243.

  When the host controller 241 determines that the medal has passed on the medal rail 210 in the counting process, the host controller 241 instructs the image recognition DSP circuit 242 and the image recognition accelerator circuit 249 to execute the process after the circular area detection process in the marking determination process. To do.

  In the circular area detection processing, the image recognition DSP circuit 242 acquires reduced image data from the SRAM 243 and detects a circular area from the reduced image data. In the filter processing, the image recognition DSP circuit 242 performs non-linear diffusion filter processing on the detected circular area to create an edge image XY, and stores it in the SRAM 243.

  Next, in the rotated image generation process, the image recognition accelerator circuit 249 acquires the edge image XY from the SRAM 243 and generates a rotated image of 360 degrees from the edge image XY. In the gradient average image data generation process, the image recognition accelerator circuit 249 cumulatively adds (superimposes) 360-degree rotated images to generate gradient average image data, and stores the gradient average image data in the SRAM 243. Let The image recognition accelerator circuit 249 stores the gradient average image data in the gradient average image template generation data storage area before generating the gradient average image template, and after generating the gradient average image template, Store in the gradient average image data storage area.

  Next, in the gradient average image template comparison process, the image recognition DSP circuit 242 determines whether or not the gradient average image data to be determined matches the gradient average image template, or is similar to a predetermined degree, and the determination result is stored in the SRAM 243. Remember. Here, when the gradient average image template is not generated at the time of executing the gradient average image template comparison process (in this embodiment, when the number of medals inserted after power-on is less than 50), the gradient average image template is used. The comparison process is not executed.

  Note that, as described above, the number of medals inserted after power-on reaches the prescribed initial insertion number of 50, and 50 gradient average image data is stored in the gradient average image data generation data storage area of the SRAM 243. The image recognition accelerator circuit 249 performs gradient average image template generation processing.

  In parallel with the rotation image generation processing, the image recognition accelerator circuit 249 performs polar coordinate conversion processing. In the polar coordinate conversion process, the edge image XY is acquired from the SRAM 243, the orthogonal coordinates are converted into polar coordinates for the acquired edge image XY, polar coordinate image data is created, and the polar coordinate image data is stored in the SRAM 243.

  Next, in the Scherr transform process, the image recognition accelerator circuit 249 acquires polar coordinate image data from the SRAM 243, performs nonlinear diffusion filter processing, and creates an edge polar coordinate image X and an edge polar coordinate image Y.

  Next, in the HOG conversion process, the image recognition accelerator circuit 249 generates an edge gradient image based on the edge polar coordinate image X and the edge polar coordinate image Y, performs HOG conversion on the generated edge gradient image, and performs local region-by-local region. A histogram of the gradient direction of the brightness is created. Then, the created histogram set is stored in the SRAM 243. The image recognition accelerator circuit 249 stores the set of histograms in the HOG template generation data storage area before generating the HOG template, and stores the histogram set in the determination target histogram storage area after generating the HOG template.

  Next, in the HOG template comparison process, the image recognition DSP circuit 242 determines whether the set of determination target histograms matches the HOG template stored in the SRAM 243 or is similar to a predetermined degree. Then, the determination result is stored in the SRAM 243. Note that when the HOG template is not generated (in this embodiment, the number of medals inserted after power-on is less than 50), the HOG template comparison process is not executed.

  As described above, the image recognition accelerator circuit 249 receives the HOG at the timing when 50 medals are inserted after the power is turned on and 50 sets of histograms are stored in the HOG template generation data storage area of the SRAM 243. Perform template generation processing.

<Control LSI processing timing>
Next, timing of various processes performed by the control LSI 234 will be described with reference to FIG.
FIG. 35 shows the relationship of processing in the host controller 241, ISP circuit 245, medal count circuit 246, and color recognition circuit 247, which are devices constituting the control LSI 234, in time series. A relatively thick line in the line extending below each device name indicates that the device is performing the various processes described above.

  In addition, broken-line arrows between lines corresponding to the devices indicate signals input / output between the devices. A broken line arrow between a line extending below “IN” and a line extending below “OUT” in the host controller indicates a signal detected by the host controller 241 and a signal output from the host controller 241. The correspondence relationship is shown.

  First, when the CMOS image sensor 232 (see FIG. 17) outputs image data to the control LSI 234, the ISP circuit 245 acquires (receives) the image data via the ISI circuit 251, and receives a VSYNC (Vertical Synchronization) interrupt signal #. 0 (1IH) is output to the host controller 241. Further, the ISP circuit 245 performs conversion processing for converting the RGB Bayer image into various formats. Then, the gray scale image data and HSV image data are output to the SRAM 243, the medal count circuit 246, and the color recognition circuit 247. The detailed description of the conversion process has been described above, and will not be repeated.

  When the VSYNC interrupt signal # 0 is input, the host controller 241 outputs an activation request signal (1HC, 1HM) to the color recognition circuit 247 and the medal count circuit 246 after a predetermined time has elapsed. This predetermined time is set longer than the time required for the conversion process in the ISP circuit 245 based on experiments and simulations.

  The color recognition circuit 247 performs color determination processing when the activation request signal is input or when HSV image data is input from the ISP circuit 245, stores the determination result in the SRAM 243, and causes the host controller 241 to perform color determination. A judgment interrupt signal (1CH) is output. Note that the detailed description of the color determination process has been described above, and will be omitted.

  The medal count circuit 246 performs a count process when the activation request signal is input or when data is input from the ISP circuit 245, stores the determination result in the SRAM 243, and also interrupts the medal count interrupt to the host controller 241. A signal (1MH) is output. Note that the detailed description of the count process has been described above, and is therefore omitted.

  When the host controller 241 detects the color determination interrupt signal and the count interrupt signal, the host controller 241 acquires the determination result of the count process from the SRAM 243. Then, as a determination result, it is determined whether or not “medal has passed”, “medal was guided to medal chute 202”, or “abnormality has occurred” is stored. If neither is stored, the host controller 241 omits the process of outputting the determination result to the main control board 71 (main control circuit 91) via the GPIO 250. Here, in the present embodiment, as described above, in the order determination process of the count process, it is necessary to store the data transition mode in each determination region of the plurality of grayscale image data in the SRAM 243. Until at least the number of grayscale image data received by the medal count circuit 246 reaches a predetermined number (14 or 4 when medals cannot be inserted), the process of outputting the determination result to the main control board 71 is omitted. There is a case.

  The processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signals # 1 to 4 (2IH to 5IH) shown in FIG. 35 are the same as the input of the VSYNC interrupt signal # 0 (1IH). ) Is the same as the processing timing and signal input / output of each device, and the description is omitted here.

  Next, the processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signal #n (nIH), which is the nth VSYNC interrupt signal after power-on, shown in FIG. 35 will be described. . Note that processing and signal input / output from when the ISP circuit 245 outputs the VSYNC interrupt signal #n to the host controller 241 (nIH) until the host controller 241 obtains the determination result of the count processing from the SRAM 243. Since this is the same as the processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signal # 0 (1IH) described above, description thereof is omitted here.

  When the host controller 241 stores, as the determination result of the count process, any one of “medal has passed”, “medal was guided to the medal chute 202”, and “abnormality has occurred”, The determination result and the determination result of the color determination process are acquired from the SRAM 243, and these determination results are output to the allocation PORT of the GPIO 250 (nHG). That is, the host controller 241 outputs the determination result of the count determination process and the determination result of the color determination process to the main control board 71 (main control circuit 91) via the GPIO 250. The determination result of the color determination process output here may be plural.

  In addition, when the determination result of the count processing is “medal has passed”, the host controller 241 relates to each medal until the medal inserted into the gaming machine reaches the specified initial inserted number, in this embodiment, 50. In order to generate color determination data, the color recognition circuit 247 is instructed to generate color determination data using HSV image data of a predetermined time ago. In addition, the host controller 241 instructs the image recognition DSP circuit to perform preprocessing using the reduced image data of a predetermined time ago.

  In addition, the host controller 241 deletes the determination result output to the main control board 71 from the SRAM 243.

  When the determination result of the count processing is “medal has passed”, the main CPU 93 of the main control circuit 91 detects the medal count signal output from the medal count output PORT of the GPIO 250 and determines the number of inserted medals. The main CPU 93 adds 1 to the value of the insertion number counter, which is a counter provided for counting. When the value of the inserted number counter is the maximum value (for example, 3), 1 is added to the value of a credit counter that is a counter provided for the main CPU 93 to count the number of credited medals. When the credit counter is the maximum value (for example, 50), the main control circuit 91 sets the medal solenoid 208 of the medal selector 201 to the OFF state. As a result, the select plate 207 is positioned at the “discharge position”, the medal cannot be inserted, and the medal inserted after the credit counter reaches the maximum value is guided to the medal chute 202 and the medal tray through the medal payout port 32. The unit 34 is discharged. In the present embodiment, when the value of the insertion number counter is a specified value (for example, 2 or 3), when the start lever is operated, the main CPU 93 performs the above-described internal lottery process.

  Further, when the determination result of the color determination process is “threshold determination impossible”, the color determination result is “no”, or the count determination result is “abnormal”, the medal determination output of the GPIO 250 Based on a medal abnormality signal (Judgment in FIG. 35) that is output when a predetermined output condition is established from the PORT, the main control circuit 91 misrecognizes that a regular gaming medium is used in the gaming machine and plays a game. Detects fraudulent activity. Then, various processes are performed when there is an illegal act. Here, the various processes when there is an illegal act are, for example, that the main control circuit 91 forcibly interrupts the game, displays an error code on the 7-segment display 24, and causes an error on the sub-control circuit 101. This is a process of transmitting a command and notifying that an illegal act has occurred via the sub-control circuit 101 (for example, displaying that an illegal act has occurred on the liquid crystal display device 11).

Next, the timing of other processing performed by the control LSI 234 will be described with reference to FIG.
FIG. 36 shows the processing relationship in time series in the host controller 241, the ISP circuit 245, the fisheye correction scaler circuit 248, the image recognition DSP circuit 242, and the image recognition accelerator circuit 249 that are devices constituting the control LSI 234. . Note that the meanings of various notations in FIG. 36 are the same as those in FIG. FIG. 36 shows the processing timing after the VSYNC interrupt signal #m, which is the m-th VSYNC interrupt signal after the power is turned on, is output from the ISP circuit 245.

  First, when the CMOS image sensor 232 (see FIG. 17) outputs image data to the control LSI 234, the ISP circuit 245 acquires (receives) the image data via the ISI circuit 251, and receives a VSYNC (Vertical Synchronization) interrupt signal #. m (1IH) is output to the host controller 241. Further, the ISP circuit 245 performs conversion processing for converting the RGB Bayer image into various formats. Then, the gray scale image data is stored in the SRAM 243. The detailed description of the conversion process has been described above, and will not be repeated.

  When the VSYNC interrupt signal #m is input, the host controller 241 detects the end of the conversion process of the ISP circuit 245, and at the timing when the conversion process is completed, the host controller 241 sends a start request signal (1HG) to the fisheye correction scaler circuit 248. Is output. This predetermined time is set longer than the time required for the conversion process in the ISP circuit 245 based on experiments and simulations.

  When the activation request signal is input, the fisheye correction scaler circuit 248 acquires grayscale image data from the SRAM 243, performs fisheye correction processing and equalization processing, stores the generated reduced image data in the SRAM 243, and A reduction end interrupt signal (1GH) is output to the host controller 241. Note that the detailed description of the fisheye correction process and the equalization process has been described above, and will be omitted.

  The host controller 241 outputs the determination result of the count process “medal has passed” to the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interrupt signal. On the condition, a signal (1HD) instructing the image recognition DSP circuit 242 to start preprocessing is input. Note that the determination result of the color determination process output to the main control circuit 91 is “threshold determination impossible”, or does not match any of the four color templates or is not similar to a predetermined degree, under the condition for instructing the start of preprocessing. It may be added as a condition that it is not included, that is, a determination result is included that matches any one of the color templates or is similar to a predetermined degree.

  The image recognition DSP circuit 242 performs preprocessing when the signal is input from the host controller 241. As described above, the preprocessing includes a circular area detection process and a filter process. The edge image XY created by the preprocessing is stored in the SRAM 243, and a preprocessing end interrupt signal (1DH1) is output to the host controller 241. Note that the detailed description of the pre-processing has been described above and is omitted.

  When the pre-processing completion interrupt signal is input, the host controller 241 outputs a signal (1HA) instructing the start of correction processing to the image recognition accelerator circuit 249. Here, the correction processing is the above-described rotation image generation processing, gradient average image data generation processing, polar coordinate conversion processing, Charrr conversion processing, and HOG conversion processing. Note that a detailed description of these processes has been described above, and will be omitted.

  The image recognition accelerator circuit 249 performs correction processing when the signal is input from the host controller 241. If the gradient average image template has already been generated, the generated gradient average image data is stored in the determination target gradient average image data storage area of the SRAM 243, while the gradient average image template has not yet been generated. Are stored in the gradient average image template generation data storage area. If the HOG template has already been generated, the generated histogram set is stored in the determination target histogram storage area of the SRAM 243. On the other hand, if the HOG template has not yet been generated, the HOG template generation data storage area is stored. Remember.

  Next, when the gradient average image template and the HOG template have already been generated, the image recognition accelerator circuit 249 outputs a correction processing end interrupt signal (1AD) to the image recognition DSP circuit 242. On the other hand, if the gradient average image template and the HOG template have not yet been generated, the process of outputting the correction process end interrupt signal to the image recognition DSP circuit 242 is omitted. The image recognition accelerator circuit 249 performs gradient average image template generation processing when 50 gradient average image data are stored in the gradient average image data generation data storage area of the SRAM 243. The image recognition accelerator circuit 249 performs HOG template generation processing when 50 sets of histograms are stored in the HOG template generation data storage area of the SRAM 243.

  When the correction processing end interrupt signal is input, the image recognition DSP circuit 242 performs a marking determination process. The marking determination process here includes a gradient average image template comparison process and a HOG template comparison process. Specifically, the image recognition DSP circuit 242 acquires gradient average image data from the determination target gradient average image data storage area of the SRAM 243, and performs gradient average image template comparison processing for comparison with the gradient average image template. Then, the determination result of the gradient average image template comparison process is stored in the SRAM 243. Further, a set of histograms is acquired from the determination target histogram storage area of the SRAM 243, and a HOG template comparison process for comparing with the HOG template is performed. Then, the determination result of the HOG template comparison process is stored in the SRAM 243. Thereafter, the image recognition DSP circuit 242 outputs a marking determination end interrupt signal (1DH2) to the host controller 241.

  When the stamp determination end interrupt signal is input, the host controller 241 acquires the gradient average determination result and the HOG determination result as the determination result of the stamp determination process stored in the SRAM 243. Further, when “No” is stored as the acquired gradient average determination result, or when “No” is stored as the HOG determination result, the host controller 241 satisfies the above-described predetermined output condition. Then, a medal abnormality signal (Judgment in FIG. 36) is output from the medal determination output PORT of the GPIO 250 to the main control circuit 91 (1HG). That is, the host controller 241 outputs the determination result of the marking determination process to the main control board 71 (main control circuit 91) via the GPIO 250. In addition, the host controller 241 deletes the determination result of the marking determination process output to the main control board 71 from the SRAM 243. In this embodiment, the same output PORT of the GPIO 250 is assigned to the output of the determination result of the color determination process to the main control circuit 91 and the output of the determination result of the marking determination process to the main control circuit 91. However, the present invention is not limited to this, and it may be assigned to different output PORTs. In this case, the main control circuit 91 can determine whether it is a medal abnormality signal based on the determination result of the color determination process or a medal abnormality signal based on the determination result of the stamp determination process.

  The main control circuit 91 misidentifies that a regular gaming medium is used in the gaming machine when either of the determination results of the input marking determination processing, that is, the gradient average determination result or the HOG determination result is “No”. It detects that there was an illegal act to play a game. Then, various processes are performed when there is an illegal act. Here, the various processes when there is an illegal act are, for example, that the main control circuit 91 forcibly interrupts the game, displays an error code on the 7-segment display 24, and causes an error on the sub-control circuit 101. This is a process of transmitting a command and notifying that an illegal act has occurred via the sub-control circuit 101 (for example, displaying that an illegal act has occurred on the liquid crystal display device 11).

  In FIG. 36, VSYNC # m, VSYNC # m + 2, VSYNC # m + 3, VSYNC # m + 4, VSYNC # m + 5, and VSYNC # m + 6 following VSYNC # m are triggered by the above-mentioned VSHYC # m. For the same processing as those described above, the various signals output in accordance with the processing are denoted by reference numerals for changing only the leading numerals, and detailed description thereof is omitted.

  Here, after processing to output a reduction end interrupt signal (2GH, 3GH, 4GH, 6GH) from the fisheye correction scaler circuit 248 to the host controller 241, the preprocessing is started from the host controller 241 to the image recognition DSP circuit 242. The process of outputting a signal for instructing is not performed.

  This is because the host controller 241 displays the determination result of the count process “medal has passed” to the main control circuit 91 from when the previous reduction end interrupt signal is input until the current reduction interrupt signal is input. This is because they are not output. In this example, the host controller 241 indicates that “the medal has passed” to the main control circuit 91 between the time when the reduction end interrupt signal according to 4GH is input and the time when the reduction end interrupt signal according to 5GH is input. Is output. For this reason, after the 5GH reduction end interrupt signal is input, the host controller 241 outputs a signal (2HD) instructing the image recognition DSP circuit 242 to start preprocessing.

  In the present embodiment, it is preferable that the marking determination process is performed for all medals inserted. However, when the host controller 241 outputs a signal instructing the image recognition DSP circuit 242 to start preprocessing, the host controller 241 checks whether the image recognition DSP circuit 242 or the image recognition accelerator circuit 249 is processing (busy state). However, the signal may not be output when any of the signals is being processed, and may be output when none of the signals is being processed. In this case, the marking determination process is intermittently performed for medals continuously inserted. For example, when three medals are inserted in succession, the marking determination process is performed on the first and third sheets.

  The processing timing of each device in the control LSI 234 shown in FIGS. 35 and 36 is merely an example. The regular medal determination process can be performed at various processing timings according to the processing capability, processing content, and processing procedure of each device.

<First action>
In the pachi-slot 1 of the present embodiment, the result of the color determination process based on the image data output from the CMOS image sensor 232 performed by the color recognition circuit 247 matches “no threshold determination” or any of the four color templates. Alternatively, when the similarity is included to a predetermined degree, that is, when the color of the inserted medal does not match the color of the regular medal, the main control circuit 91 indicates that a regular gaming medium is used for the gaming machine. Detects that there was an illegal act of misrecognizing and playing a game.

  Further, when the result of the count process based on the image data output from the CMOS image sensor 232 is “abnormality has occurred”, the main control circuit 91 misidentifies that a regular game medium is used for the game machine. Detecting that there was an illegal act of playing games.

  In addition, the result of the marking determination process performed by the image recognition DSP circuit 242 based on the image data output from the CMOS image sensor 232 (in this embodiment, the gradient average determination result or the HOG determination result) is “No”. In this case, that is, when the stamp of the inserted medal is different from the stamp of the regular medal, the main control circuit 91 confirms that the gaming machine has misconducted to play a game by misidentifying that the regular gaming medium is used. Detect.

  Therefore, the main control circuit 91 performs cheating performed by inserting a special instrument into the medal slot, or cheating performed using a medal having the same diameter and color and stamp (pattern) as the regular medal. It can be detected with high accuracy.

  When it is detected that there has been a cheating, the main control circuit 91 forcibly interrupts the game and notifies the sub-control circuit 101 that there has been a cheating. Therefore, it is possible to suppress the spread of damage due to the fraud.

<Second action>
Further, in the pachi-slot 1 of this embodiment, the control LSI 234 of the medal selector 201 passes medals that pass on the medal rail 210 until the number of inserted medals reaches the specified initial number of inserted coins, that is, 50 in this embodiment. A color template used for the color determination process is generated based on the image including. Similarly, a gradient average image template and an HOG template used for the marking determination process are generated.

  Therefore, when there is a change in a medal used as a regular medal at an amusement store, after the power is turned on, by inserting 50 regular medals after the change, the color template related to the regular medals after the change, Gradient average image templates and HOG templates can be easily created. In addition, even if the regular medal is deteriorated due to, for example, insertion into a gaming machine, payout, or washing at a gaming store, the color template corresponding to the current state of the regular medal even if the stamp is less noticeable than the original, Since the gradient average image template and the HOG template can be generated, the accuracy of various determination results can be maintained.

<Third action>
In the pachislot machine 1 of this embodiment, the medal count circuit 246 of the control LSI 234 performs a count process based on the grayscale image data output from the ISP circuit 245. In the order determination process in the count process, the medal count circuit 246 performs “IN” based on a change in luminance for a plurality (16 in the present embodiment) of determination areas for a predetermined number of grayscale image data arranged in time series. ”,“ OUT ”,“ ON ”,“ OFF ”data transition mode is determined whether it matches the transition mode of the medal count determination table (see FIG. 27). If they match, it is determined that “medal has passed” on the medal rail 210 or “medal was guided to the medal chute 202”. Further, if any of the data “IN”, “OUT”, and “ON” is stored for the determination area E, it is determined that an abnormality has occurred.

  As described above, since the passage of medals is determined based on the change in luminance in the plurality of determination regions, the determination accuracy can be improved.

  In addition, the number of determination regions set on the grayscale image data can be set as appropriate according to the allowable determination required time and the accuracy of determination to be obtained. Therefore, for example, even when the number of determination regions is increased in order to further increase the accuracy of determination, it is not necessary to newly install components such as a photo sensor for medal counting. For this reason, the increase in manufacturing cost can be suppressed.

  In addition, when the determination result of the count processing is “abnormality has occurred”, the main control circuit 91 has misconducted that the gaming machine misidentifies that a legitimate gaming medium is used and plays a game. Is detected. That is, an illegal act can be detected based on the determination result of the count process.

<Fourth action>
Also, in the pachislot machine 1 of the present embodiment, the ISP circuit 245 of the control LSI 234 performs image correction processing that performs lens distortion correction processing and projective transformation (homography) processing on the RGB Bayer image output from the ISI circuit 251.

  For this reason, it is possible to complement the RGB Bayer image so that the lens characteristics of the camera unit 209 and the displacement of the mounting position of the camera unit 209 do not affect the various determination / determination processes, thereby improving the accuracy of the various determination processes.

<Fifth action>
In the pachislot machine 1 of the present embodiment, the color recognition circuit 247 of the control LSI 234 performs threshold value determination processing. As a result, it is possible to suppress an erroneous determination that a hue or saturation value that is clearly different from a regular medal matches the color template or is similar to a predetermined degree. That is, in addition to the determination based on the degree of coincidence with the color template, it can be determined whether or not the determination target color itself is an effective color, so the accuracy of the determination result of the color determination process can be improved.

<Sixth action>
Further, in the pachislot machine 1 of the present embodiment, the fish-eye correction scaler circuit 248 of the control LSI 234 performs bilateral conversion processing on each of the created reduced image data in the equalization processing.
As a result, noise in the grayscale image data can be reduced, and edges in the grayscale image data can be emphasized. For this reason, the accuracy of the determination result in the marking determination process can be increased.

<Seventh action>
Further, in the pachislot machine 1 of the present embodiment, the image recognition accelerator circuit 249 of the control LSI 234 performs HOG conversion processing. Further, the image recognition DSP circuit 242 determines whether or not the set of determination target histograms created by the HOG conversion process and the HOG template match or are similar to a predetermined degree in the marking determination process.

  Therefore, the marking determination processing is performed by performing image matching with HOG conversion processing having strength in local shape change (geometric conversion) on the imaging data of the medal passing on the medal rail 210 while rotating. The accuracy of the determination result can be improved.

<Eighth action>
In the pachislot machine 1 of this embodiment, the image recognition accelerator circuit 249 of the control LSI 234 performs polar coordinate conversion processing before the HOG conversion processing.
As a result, the feature of the outer peripheral area of the regular medal is easily reflected in the set of histograms created by the HOG conversion process. Therefore, it is possible to improve the accuracy of the determination result of the subsequent stamp determination process for medals having a characteristic stamp (pattern) on the outer peripheral region.

<Ninth action>
In a conventional gaming machine, the detection of a count of medals inserted, a clogging of medals in a selector of inserted medals, and the like is performed by the main CPU in the main control circuit executing a program stored in the main ROM. It was done. However, in the pachi-slot 1 of the present embodiment, the control LSI 234 of the medal selector 201 performs these detections with higher accuracy than before. Accordingly, since it is not necessary to store these detection programs in the main ROM 94, the storage capacity of the main ROM 94 is reduced.

<Modification>
The gaming machine according to one embodiment of the present invention has been described above including the effects thereof. However, the gaming machine of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described in the claims.

  For example, in the present embodiment, a mode in which four color templates, a gradient average image template, and a HOG template are generated has been described. However, the number of these templates can be set as appropriate according to an allowable determination required time and a required determination accuracy. It is.

  Further, in the present embodiment, a mode has been described in which the color determination process and the marking determination process are executed for all medals that have been input. However, the present invention is not limited to this, and a switch board is provided at an arbitrary location of the medal selector 201 (for example, in the vicinity of the first board 231), and the color determination ON / OFF switch and the stamp determination ON / OFF switch are provided on the switch board. And the host controller 241 reads the state of the switch so that it can be selected whether or not to execute the color determination process and the marking determination process.

  In the present embodiment, when “NO” is input as the gradient average determination result to the main control circuit 91 or when “NO” is input as the HOG determination result, the main control circuit 91 An aspect of detecting that there has been a fraud has been described. However, instead of this, when “NO” is input as the gradient average determination result and “NO” is input as the HOG determination result to the main control circuit 91, the main control circuit 91 performs an illegal act. You may detect that there was.

  In the present embodiment, the color template, the gradient average image template, and the HOG template stored in the SRAM 243 are deleted when the initialization switch is pressed when the gaming machine is turned on. However, instead of this, an arbitrary operation may be set in order to delete various templates stored in the SRAM 243. For example, various templates in the SRAM 243 may be deleted in conjunction with a change in the setting of the gaming machine.

  Further, in the order determination process in the case where medals cannot be inserted, the data transition mode in each determination area of the latest four grayscale image data stored in the SRAM 243 and the medal count determination table are defined. If the data transition modes corresponding to E1 to E4 do not match, it may be determined that “abnormality has occurred” and the determination result may be stored in the SRAM 243.

  Further, in the present embodiment, the host controller 241 performs a count process that “the medal has passed” to the main control circuit 91 from when the previous reduction end interrupt signal is input to when the current reduction interrupt signal is input. In the above description, the image recognition DSP circuit 242 is instructed to start preprocessing on the condition that the determination result is output. That is, when it is determined that the medal has passed on the medal rail 210 in the counting process, the host controller 241 executes the processing subsequent to the circular area detection process in the marking determination process to perform the image recognition DSP circuit 242 and the image recognition accelerator circuit 249. The mode instructed to have been described. However, instead of this, the determination result of some count processing (that is, “medal is medal shot” is applied to the main control circuit 91 from when the previous reduction end interrupt signal is input to when the current reduction interrupt signal is input. The image recognition DSP circuit 242 may be instructed to start pre-processing on the condition that “instructed to 202” or “an error has occurred” is output.

Further, the threshold determination process in the color determination process may be omitted.
Further, the present invention may be employed in other gaming machines that use gaming media, such as pachinko machines.

  DESCRIPTION OF SYMBOLS 1 ... Pachislot, 3L ... Left reel, 3C ... Middle reel, 3R ... Right reel, 4 ... Reel display window, 21 ... Medal insertion slot, 23 ... Start lever, 32 ... Medal paying exit, 51 ... Hopper device, 71 ... Main Control board 72 ... Sub control board 79 ... Start switch 80 ... Stop switch board 91 ... Main control circuit 101 ... Sub control circuit 140 ... Cancel shooter 201 ... Medal selector 202 ... Medal chute 203 ... Slope 204 ... Base plate part 205 ... Sub plate 206 ... Cancel shooter 207 ... Select plate 208 ... Medal solenoid 209 ... Camera unit 210 ... Medal rail 211 ... Medal entrance part 212 ... Central hole 213 ... Medal pressure, 217 ... Magnet, 218: After medal pressure, 227: Medal stopper unit, 230: First substrate, 231: Second substrate, 232 ... CMOS image sensor, 233 ... LED, 234 ... Control LSI, 235 ... Leg, 241 ... Host controller 242 ... Image recognition DSP circuit 243 ... SRAM 244 ... Flash memory 245 ... ISP circuit 246 ... Medal count circuit 247 ... Color recognition circuit 248 ... Fisheye correction scaler circuit 249 ... Image recognition accelerator circuit 250 ... GPIO, 251 ... ISI circuit

Claims (1)

A slot for gaming media;
A game medium detecting means for detecting a game medium thrown from the slot,
The game medium detection means includes
A passage forming portion that forms a passage through which the game medium passes;
Imaging means for imaging the passage;
Passage determining means for determining whether an object has passed through the passage based on image data obtained through the imaging means;
Image conversion means for converting the image data;
Game medium determination means for determining whether or not the object that has passed through the passage is the regular game medium based on the image data converted by the image conversion means;
The image conversion means converts the image data into an edge gradient image, and creates a histogram related to the edge gradient image,
The game medium determination means passes through the passage based on whether the histogram created by the image conversion means and template data relating to the regular game medium stored in advance match or are similar to a predetermined degree. It is determined whether or not an object is the regular game medium.

Images