JP6794013B2 - Game machine - Google Patents

Description

The present invention relates to a game machine.

Conventionally, a game called pachislot equipped with a plurality of reels in which a plurality of symbols are arranged on each surface, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter, also referred to as "start operation") after the game medium such as a medal is inserted into the game machine, and starts the rotation of all reels. Output the requested signal. The stop switch detects that the stop button provided corresponding to each reel is pressed by the player (hereinafter, also referred to as "stop operation"), and outputs a signal requesting that the rotation of the corresponding reel be stopped. To do. The stepping motor transmits its driving force to the corresponding reels. Further, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

In such a game machine, when a start operation is detected, a lottery process using random numbers (hereinafter referred to as "internal lottery process") is performed on the program, and the result of the lottery (hereinafter, "internal winning combination") is performed. The rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all reels is stopped and the combination of symbols related to the establishment of the winning is displayed, the player is given a privilege corresponding to the combination of the symbols.

Further, such a game machine is provided with a medal selector for detecting a medal inserted at the tip of the medal insertion slot. In addition, for this medal selector, a medal that is not a proper medal (regular medal) (illegal medal) is inserted into the medal slot, or an instrument is inserted into the medal slot to insert a regular medal into the game machine. Measures have been taken against fraudulent acts in which the game is played by mistaking it as being thrown.

For example, in Patent Document 1, two proximity sensors for detecting medals are provided in the medal passage, and it is determined whether or not a medal for a game has passed through the medal passage based on the output of each proximity sensor. A slot machine that detects fraudulent activity using a device such as a physical object is described.

JP-A-2002-342814

However, the slot machine described in Patent Document 1 cannot detect fraudulent acts performed using fraudulent medals without using an instrument such as a plate-shaped body. For example, if the unit price of medals rented in the hall where this slot machine is installed is the same diameter for a medal of 20 yen per piece and a medal of 5 yen per piece, but the color and engraving (pattern) are different, these are used in this slot machine. Cannot be determined. For this reason, it was not possible to detect fraudulent acts in which a medal with a lending unit price of 20 yen is treated as a regular medal and a game is played using a medal with a lending unit price of 5 yen (illegal medal). ..

Further, the slot machine described in Patent Document 1 is attached to a medal rented in the hall where the game machine is installed, a medal rented in another hall, or a game machine purchased at a used machine store. If the medals or counterfeit medals (including instruments disguised as medals) have the same diameter but differ only in color and engraving (pattern), these cannot be identified. For this reason, it has been difficult to detect (detect) fraudulent acts of playing games using medals other than regular medals (illegal medals).

The present invention has been made to solve the above problems, and an object of the present invention is to detect fraudulent acts in which a game machine misunderstands that a legitimate game medium is used and plays a game. It is to provide a game machine.

In order to achieve the above object, the present invention provides a gaming machine having the following configuration.

An insertion slot for inserting a game medium (for example, a medal insertion slot 21 described later) and
A game machine including a game medium detecting means (for example, a medal selector 201 described later) for detecting a game medium inserted from the slot.
The game medium detecting means is
A passage forming portion (for example, a medal rail 210 described later) forming a passage through which the game medium passes, and
An imaging means for imaging the passage (for example, a camera unit 209 described later) and
A passage determining means (for example, a medal counting circuit 246 described later) for determining whether or not an object has passed through the passage based on image data obtained via the imaging means, and
Based on the image data, a game medium determination means (for example, a color recognition circuit 247 and an image recognition DSP circuit 242 described later) for determining whether or not an object passing through the passage is a legitimate game medium, and
A reference image storage means (for example, SRAM 243 described later) that stores in advance a reference image data value (for example, a brightness value described later) when an object does not pass through each of the plurality of determination areas arranged on the image data. And have
The passage determination means is
The image data values (for example, the luminance values described later) of the plurality of determination regions in the plurality of image data captured within a predetermined period are compared with the corresponding reference image data values, and the plurality of determination regions are compared. An object presence / absence detecting means for detecting the presence / absence of an object in each of the above (for example, a medal count circuit 246 that performs a medal position detection process described later) and
The change mode information indicating the mode of change in the presence or absence of the object in each of the plurality of determination regions in the plurality of image data and the mode of the change when the object passes through the passage are stored in advance. It has a passage order determination means (for example, a medal counting circuit 246 that performs an order determination process described later) that compares the information with the reference change mode information and determines that the object has passed through the passage when they match. ,
In the plurality of determination areas, when the game medium passing through the passage is the regular game medium, a plurality of non-passage determination areas (for example, described later) provided at positions not overlapping with the game medium. A plurality of passage determination areas (for example, determination areas A1 to be described later ) provided at positions overlapping the determination areas E and F) and capable of detecting the transition mode of the game medium according to the progress of the game medium. A game machine characterized in that D4) and are included.

According to the present invention, it is possible to detect fraudulent acts in which a game is played by mistaking the game machine to use a legitimate game medium.

It is explanatory drawing explaining the functional flow in the gaming machine of one Embodiment of this invention. It is a perspective view which shows the appearance composition example in the game machine of one Embodiment of this invention. It shows the internal structure in the gaming machine of one Embodiment of this invention, and is the perspective view in the state which the middle door is closed. It shows the internal structure in the gaming machine of one Embodiment of this invention, and is the perspective view in the state which the middle door is opened. It is explanatory drawing which shows the inside of the cabinet in the game machine of one Embodiment of this invention. It is explanatory drawing which shows the back surface side of the front door in the gaming machine of one Embodiment of this invention. It is a perspective view of the medal selector in the gaming machine of one Embodiment of this invention seen from the oblique rear of the gaming machine. It is an exploded view of the medal selector in the gaming machine of one Embodiment of this invention. It is a perspective view of the medal selector in the gaming machine of one Embodiment of this invention seen from the oblique front of the gaming machine. It is a rear view of the base plate part of the medal selector in the gaming machine of one Embodiment of this invention. It is a perspective view of the select plate of the medal selector in the gaming machine of one Embodiment of this invention. It is a figure which shows the path of the medal when the medal selector in the gaming machine of one Embodiment of the invention guides a medal to a hopper device. It is a figure which shows the path of the medal when the medal selector in the gaming machine of one Embodiment of the invention guides a medal to a medal shoot. It is a block diagram which shows the control system in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the structural example of the main control circuit in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the structural example of the auxiliary control circuit in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the circuit structure example of the medal selector in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the circuit structure example of the control LSI in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the distortion of the lens in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the projection conversion processing in the gaming machine of one Embodiment of this invention, A shows the RGB Bayer image before projection conversion, and B shows the RGB Bayer image after projection conversion. It is a figure for demonstrating the threshold graph in the gaming machine of one Embodiment of this invention. It is a figure (the 1) for demonstrating the determination area in the gaming machine of one Embodiment of this invention. It is a figure (the 2) for demonstrating the determination area in the gaming machine of one Embodiment of this invention. It is a figure (the 3) for demonstrating the determination area in the gaming machine of one Embodiment of this invention. It is a figure (the 4) for demonstrating the determination area in the gaming machine of one Embodiment of this invention. It is a figure which shows an example of the determination area determination result data stored in SRAM in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the medal count determination table in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the Gaussian filter in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the circular area detection process in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating 3σ correction processing in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the filter processing in the gaming machine of one Embodiment of this invention, A shows typically the circular area image data after 3σ correction processing, B shows the coefficient for edge image X, and it shows. C indicates a coefficient for edge image Y. It is a figure which shows an example of the regular medal used in the gaming machine of one Embodiment of this invention, A shows one side of the regular medal, B shows the gradient average image data of the regular medal. It is a figure for demonstrating the HOG conversion process in the gaming machine of one Embodiment of this invention. It is a flow chart of the process performed by the control LSI in the gaming machine of one Embodiment of this invention. It is a timing chart (No. 1) of the processing performed by the control LSI in the gaming machine of one embodiment of the present invention. It is a timing chart (No. 2) of the processing performed by the control LSI in the gaming machine of one embodiment of the present invention. It is a figure for demonstrating the medal selector in the game machine of the modification 1 of this invention. It is a block diagram which shows the circuit structure example of the medal selector in the game machine of the modification 2 of this invention. It is a block diagram which shows the circuit structure example of the control LSI in the game machine of the modification 2 of this invention.

Hereinafter, a pachi-slot machine, which is a gaming machine showing an embodiment of the present invention, will be described with reference to FIGS. 1 to 36.

<Function flow>
First, the functional flow of the pachislot machine will be described with reference to FIG.
In the pachislot machine of this embodiment, a medal is used as a game medium for playing a game. In addition to medals, coins, game balls, point data for games, tokens, and the like can also be applied as the game medium.

When a medal is inserted by the player and the start lever is operated, one value (hereinafter, random number value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

The internal lottery means draws a lot based on the extracted random number value, and determines the internal winning combination. The main control circuit described later is responsible for this internal lottery means. By determining the internal winning combination, the combination of symbols that are allowed to be displayed along the winning determination line described later is determined. The types of symbol combinations include those related to "winning" in which benefits such as medal payout, re-game operation, and bonus operation are given to the player, and those related to other so-called "loss". Is provided.

Further, when the start lever is operated, a plurality of reels are rotated. After that, when the stop button corresponding to the predetermined reel is pressed by the player, the reel stop control means controls to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is carried by a main control circuit described later.

In pachislot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec or 75 msec) from the time when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the "number of sliding pieces". When the specified period is 190 msec, the maximum number of sliding pieces is set for 4 symbols, and when the specified period is 75 msec, the maximum number of sliding pieces is set for 1 symbol.

When the internal winning combination that allows the combination display of the symbols related to the winning is determined, the reel stop control means usually sets the combination of the symbols within the specified time of 190 msec (for 4 symbols) on the winning determination line. Stop the rotation of the reel so that it is displayed as much as possible along. Further, the reel stop control means is specified for one or more reels, for example, when the challenge bonus (CB) which is a second type special accessory and the middle bonus (MB) which continuously operates the CB are operated. Within the time of 75 msec (for one symbol), the rotation of the reel is stopped so that the combination of the symbols is displayed as much as possible along the winning determination line. Further, the reel stop control means uses various specified times corresponding to the gaming state to rotate the reel so that the combination of symbols whose display is not permitted by the internal winning combination is not displayed along the winning determination line. Stop it.

When all the rotations of the plurality of reels are stopped in this way, the winning determination means determines whether or not the combination of symbols displayed along the winning determination line is related to winning. The main control circuit described later is responsible for the winning determination means. When it is determined by the winning determination means that the prize is related to the prize, the player is given a privilege such as paying out a medal. In pachislot, the above series of flows is performed as one game.

Further, in pachislot, in the series of flows described above, video display performed by a display device such as a liquid crystal display device, light output performed by various lamps, sound output performed by a speaker, or a combination thereof is used. Various productions are performed.

When the start lever is operated, a random value for effect (hereinafter, random value for effect) is extracted in addition to the random value used for determining the internal winning combination described above. When the effect random value is extracted, the effect content determining means determines by lottery what to execute this time from a plurality of types of effect contents associated with the internal winning combination. A sub-control circuit, which will be described later, is responsible for determining the content of the effect.

When the content of the effect is determined, the effect executing means executes the corresponding effect in conjunction with each opportunity such as when the rotation of the reels starts, when the rotation of each reel stops, and when it is determined whether or not there is a prize. In this way, in pachislot, by executing the production content associated with the internal winning combination, the player has an opportunity to know or anticipate the determined internal winning combination (in other words, the combination of symbols to be aimed at). It is provided and can improve the interest of the player.

<Structure of pachislot>
Next, the structure of the pachi-slot machine 1 in one embodiment will be described with reference to FIGS. 2 to 6.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachislot machine 1.

As shown in FIG. 2, the pachislot machine 1 includes an exterior body 2. The exterior body 2 has a cabinet 2a for accommodating a hopper device 51 and a medal auxiliary storage 52 (see FIG. 5), which will be described later, and a front door 2b that can be opened and closed with respect to the cabinet 2a.
Handles 7 are provided on both side surfaces of the cabinet 2a (only one side handle 7 is shown in FIG. 2). The handle 7 is a recess for carrying the pachi-slot machine 1.

Inside the exterior body 2, three reels 3L, 3C, and 3R are provided side by side. Hereinafter, each reel 3L, 3C, 3R will be referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. On the surface of the sheet material, a plurality of (for example, 20) patterns are drawn at predetermined intervals along the circumferential direction.

The front door 2b includes a door body 9, a front panel 10, and a liquid crystal display device 11 showing a specific example of the display device.

The door body 9 is attached to the cabinet 2a using a hinge (not shown), and opens and closes the opening of the cabinet 2a. The hinge is provided at the left end of the door body 9 when the door body 9 is viewed from the front of the pachislot machine 1. The liquid crystal display device 11 is attached to the upper part of the door body 9. The liquid crystal display device 11 includes a display unit (display screen) 11a, and the liquid crystal display device 11 is used to perform an effect of displaying an image.

The front panel 10 is arranged so as to be superimposed on the display unit 11a side of the liquid crystal display device 11, and is formed in a frame shape having a panel opening 10a that exposes the display unit 11a of the liquid crystal display device 11. A lamp group 18 is provided on the front panel 10. The lamp group 18 is composed of LEDs (Light Emitting Diodes) and the like, and turns on and off the light in a pattern corresponding to the content of the effect.

A pedestal portion 12 is formed in the center of the front door 2b. The pedestal portion 12 is provided with a symbol display area 4 and various devices to be operated by the player.

The symbol display area 4 is arranged on the front side overlapping the three reels 3L, 3C, 3R when viewed from the front, and is provided corresponding to the three reels 3L, 3C, 3R. The symbol display area 4 functions as a display window, and has a configuration capable of transmitting the reels 3L, 3C, and 3R provided behind the display window 4. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

When the rotation of the reels 3L, 3C, 3R provided behind the reel display window 4 is stopped, the upper, middle, and lower stages of the plurality of types of the reels 3L, 3C, and 3R in the frame thereof are displayed. One symbol (three in total) is displayed in each area of. In the present embodiment, a pseudo line formed by combining any of three predetermined areas of the upper, middle, and lower stages of the reel display window 4 is used to determine whether or not a prize is won. It is defined as a line (winning judgment line).

The reel display window 4 is formed by a frame member 13 provided on the pedestal portion 12. The frame member 13 has a reel display window 4, an information display window 14, and a stop button mounting portion 15.

The information display window 14 is continuously provided at the lower part of the reel display window 4 and opens upward. That is, the reel display window 4 and the information display window 14 are formed as one continuous opening. The information display window 14 and the reel display window 4 are covered with a transparent window cover 16.

The window cover 16 is arranged on the inner surface side of the frame member 13 and cannot be removed from the front side of the front door 2b. Further, the frame member 13 has a sheet mounting portion 17 facing the opening of the information display window 14 with the window cover 16 interposed therebetween. A seat member (information sheet) on which information about the game is described is arranged between the seat mounting portion 17 and the window cover 16. Therefore, the information sheet is covered with a window cover 16 having a smooth surface without irregularities or gaps.

Since the window cover 16 constituting the information sheet mounting portion is not removable from the front side of the front door 2b and has a smooth surface without irregularities or gaps, the pachislot machine 1 can be used by using the information sheet mounting portion. It is possible to prevent fraudulent activities that access the inside of the door.

The stop button mounting portion 15 is provided below the information display window 14, and is formed on a flat surface facing the front. The stop button mounting portion 15 is provided with a through hole through which the stop buttons 19L, 19C, and 19R penetrate. The stop buttons 19L, 19C, 19R are associated with each of the three reels 3L, 3C, 3R, and are provided to stop the rotation of the corresponding reels. Hereinafter, the stop buttons 19L, 19C, and 19R are referred to as a left stop button 19L, a middle stop button 19C, and a right stop button 19R, respectively.

The stop buttons 19L, 19C, and 19R show an example of various devices to be operated by the player. Further, the pedestal portion 12 is provided with a medal insertion slot 21, a BET button 22, and a start lever 23 as various devices to be operated by the player.

The medal slot 21 is provided to receive medals dropped from the outside by the player. The medals accepted in the medal slot 21 will be inserted into one game up to a predetermined number (for example, 3), and the amount exceeding the specified number will be deposited inside the pachislot machine 1. It becomes possible (so-called credit function).

The BET button 22 is provided to determine the number of medals deposited inside the pachislot machine 1 to be inserted into one game. The start lever 23 is provided to start the rotation of all reels (3L, 3C, 3R).

Further, a 7-segment display 24 composed of a 7-segment LED (Light Emitting Diode) is provided on the left side of the reel display window 4 when the front door 2b is viewed from the front. The 7-segment display 24 digitally displays information such as the number of medals to be paid out to the player as a privilege (hereinafter, the number of medals to be paid out) and the number of medals deposited inside the pachislot (hereinafter, the number of credits). ..

A checkout button 27 is provided on the left side of the pedestal portion 12 when the front door 2b is viewed from the front. The settlement button 27 is provided for pulling out (discharging) to the outside stored inside the pachislot machine 1. A waist panel unit 31 is provided below the pedestal portion 12. The waist panel unit 31 has a decorative panel on which an arbitrary image is drawn, and a light source that emits light for illuminating the decorative panel from the back side.

Below the waist panel unit 31, a medal payout outlet 32, speaker holes 33L and 33R, and a medal tray unit 34 are provided. The medal payout outlet 32 guides the medals discharged from the medal selector 201 described later and the medals discharged by driving the hopper device 51 described later to the outside. The medals discharged from the medal payout port 32 are stored in the medal tray unit 34. The speaker holes 33L and 33R are provided to output sound effects, music, and the like according to the content of the production.

[Internal structure]
3 and 4 are perspective views showing the internal structure of the pachi-slot machine 1. FIG. 3 shows a state in which the front door 2b is opened and the middle door 41 provided on the back surface side of the front door 2b is closed with respect to the front door 2b. Further, FIG. 4 shows a state in which the front door 2b is opened and the middle door 41 is opened with respect to the front door 2b.
Further, FIG. 5 is an explanatory view showing the inside of the cabinet 2a. FIG. 6 is an explanatory view showing the back surface side of the front door 2b.

The cabinet 2a has a top plate 20a, a bottom plate 20b, left and right side plates 20c and 20d, and a back plate 20e (see FIG. 5). A cabinet-side speaker 42 is arranged on the upper side inside the cabinet 2a. The cabinet-side speaker 42 is attached to the back plate 20e of the cabinet 2a via the mounting brackets 43L and 43R. The cabinet-side speaker 42 is, for example, a speaker for outputting a sound effect.

When the inside of the cabinet 2a is viewed from the front, the cabinet side relay board 44 is arranged on the left side of the cabinet side speaker 42. The cabinet-side relay board 44 is attached to the left side plate 20c of the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 14), which will be described later, attached to the middle door 41 (see FIGS. 3 and 4), a hopper device 51, a medal auxiliary storage switch (not shown), and medal payout. It relays the wiring that connects to the count switch (not shown).

An amplifier board 45 for controlling sound output by the cabinet-side speaker 42 is arranged in the central portion inside the cabinet 2a. The amplifier board 45 is attached to a mounting shelf 46 fixed to the left and right side plates 20c and 20d.

Further, when the inside of the cabinet 2a is viewed from the front, an external centralized terminal plate 47 is arranged on the right side of the amplifier board 45 (see FIG. 5). The external centralized terminal plate 47 is attached to the right side plate 20d of the cabinet 2a. The external centralized terminal plate 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1.

When the inside of the cabinet 2a is viewed from the front, the sub power supply device 48 is arranged on the left side of the amplifier board 45. The sub power supply device 48 is attached to the left side plate 20c of the cabinet 2a. The sub power supply device 48 supplies electric power having an AC voltage of 100 V to the power supply device 53 described later. Further, the power of AC voltage 100V is converted into the power of DC voltage and supplied to the amplifier board 45.

A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged below the inside of the cabinet 2a.

The hopper device 51 is attached to the central portion of the bottom plate 20b in the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large number of medals and ejecting them one by one. For example, when the settlement button 27 (see FIG. 2) is pressed and the medals deposited inside the pachislot are settled, the hopper device 51 ejects the stored medals for the number of credits. The medals paid out by the hopper device 51 are discharged from the medal payout outlet 32 (see FIG. 2).

The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is engaged with the bottom plate 20b of the cabinet 2a, and is configured to be removable from the bottom plate 20b.

The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side surface plate 20c. The power supply device 53 includes a power supply switch 53a and a power supply board 53b (see FIG. 14). The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device 48 into the power of the DC voltage required in each part, and supplies the converted power to each part.

As shown in FIGS. 3, 4, and 6, the middle door 41 is arranged at the center of the back surface of the front door 2b, and the reel display window 4 (see FIG. 4) can be opened and closed from the back side. Door stoppers 41a, 41b, 41c are provided on the upper part and the lower part of the middle door 41. The door stoppers 41a, 41b, 41c fix (prohibit) the opening operation of the middle door 41 in a state where the reel display window 4 is closed from the back side. That is, in order to open the middle door 41, it is necessary to rotate the door stoppers 41a, 41b, 41c to release the fixing of the middle door 41.

A main control board case 55 containing a main control board 71 (see FIG. 14) and three reels 3L, 3C, and 3R are attached to the middle door 41. A stepping motor is connected to the three reels 3L, 3C, and 3R via gears having a predetermined reduction ratio.

As shown in FIG. 6, the main control board case 55 is provided with a setting key type switch 56. This setting key type switch 56 is used when changing the setting of the pachi-slot 1 or confirming the setting of the pachi-slot 1.
In the present embodiment, the main control board unit is composed of the main control board case 55 and the main control board 71 housed in the main control board case 55.

The main control board 71 housed in the main control board case 55 constitutes a main control circuit 91 (see FIG. 15) described later. The main control circuit 91 is a circuit that controls the main flow of the game in the pachislot machine 1, such as determining the internal winning combination, rotating and stopping the reels 3L, 3C, and 3R, and determining whether or not there is a prize. The specific configuration of the main control circuit 91 will be described later.

A sub-control board case 57 for accommodating the sub-control board 72 (see FIG. 14) is disposed above the middle door 41, and a center speaker 58 is disposed above the sub-control board case 57. The sub-control board 72 housed in the sub-control board case 57 constitutes the sub-control circuit 101 (see FIG. 16). The sub-control circuit 101 is a circuit that controls the execution of an effect by displaying an image or the like. The specific configuration of the sub-control circuit 101 will be described later.

A sub-relay board 61 is arranged on the right side of the sub-control board case 57 when the front door 2b is viewed from the back side. The sub-relay board 61 relays the wiring connecting the sub-control board 72 and the main control board 71. Further, it is a board that relays the wiring connecting the sub-control board 72 and the boards arranged around the sub-control board 72. Examples of the substrate arranged around the sub-control substrate 72 include LED substrates 62A, 62B, and 62C, which will be described later.

The LED substrates 62A, 62B, and 62C are arranged on both sides of the sub-control substrate case 57 when viewed from the back surface side of the front door 2b. These LED substrates 62A, 62B, 62C are a plurality of LEDs (Light Emitting Diodes) 85 (see FIG. 14) showing a specific example of a light source according to the effect executed by the control of the sub-control circuit 101 (see FIG. 16). ) Is emitted to display the blinking pattern. The pachi-slot machine 1 of the present embodiment includes a plurality of LED substrates in addition to the LED substrates 62A, 62B, and 62C.

A 24h door open / close monitoring unit 63 is arranged below the sub-relay board 61. The 24h door open / close monitoring unit 63 stores the open / close history of the middle door 41. Further, when the middle door 41 is opened, a signal for displaying an error on the liquid crystal display device 11 is output to the sub control board 72 (sub control circuit 101).

A board speaker 64 and lower speakers 65L and 65R are arranged below the middle door 41. The board speaker 64 faces the lumbar panel unit 31 (see FIG. 2), and the lower speakers 65L and 65R face the speaker holes 33L and 33R (see FIG. 2), respectively.

A medal selector 201, a medal chute 202, and a door open / close monitoring switch 67 are arranged above the lower speaker 65L. The medal selector 201 is a device for determining whether or not the material and shape of the medal are appropriate, and guides the medal inserted into the medal insertion slot 21 to the hopper device 51 via the slope 203, or the medal. Guide to chute 202. The specific configuration of the medal selector 201 will be described later.

The medal chute 202 is a substantially Y-shaped tubular member, and guides medals guided by the medal selector 201 and medals discharged from the hopper device 51 to the medal payout outlet 32 (see FIG. 2).

The door open / close monitoring switch 67 is arranged on the left side of the medal selector 201 when the front door 2b is viewed from the back surface side. The door opening / closing monitoring switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachislot machine 1.

Further, a door relay terminal plate 68 is arranged below the reel display window 4 in a region opened and closed by the middle door 41 (see FIG. 4). The door relay terminal board 68 includes a main control board 71 (see FIG. 14) in the main control board case 55, various buttons and switches, a sub control board 72 (see FIG. 14), a medal selector 201, and a game operation display board. It is a board that relays the wiring with 81 (see FIG. 14). Examples of various buttons and switches include a BET button 22, a settlement button 27, a door open / close monitoring switch 67, a BET switch 77 described later, a start switch 79, and the like.

<Composition of medal selector>
Next, a specific configuration of the medal selector 201 will be described with reference to FIGS. 7 to 13. FIG. 7 is a perspective view of the medal selector 201 as viewed from diagonally rearward of the pachislot machine 1. FIG. 8 is an exploded view of the medal selector 201. FIG. 9 is a perspective view of the medal selector 201 as viewed diagonally from the front of the pachislot machine 1. FIG. 10 is a rear view of the base plate portion 204 described later of the medal selector 201. FIG. 11 is a perspective view of the select plate 207 described later of the medal selector 201. FIG. 12 is a diagram showing a medal path when the medal selector 201 guides the medal to the hopper device 51. FIG. 13 is a diagram showing a medal path when the medal selector 201 guides the medal to the medal shoot 202. The arrows X shown in FIGS. 7 to 13 indicate the left-right direction of the pachi-slot machine 1, the arrow Y indicates the front-back direction of the pachi-slot machine 1, and the arrow Z indicates the up-down direction.

As shown in FIGS. 7 to 9, the medal selector 201 includes a base plate portion 204, a sub plate 205, a cancel shooter 206, a select plate 207, a medal solenoid 208 (see FIG. 9), a camera unit 209, and the like. It has.

The base plate portion 204 is a substantially plate-shaped member that constitutes the outer frame housing of the medal selector 201, and is molded so that both ends of the pachislot 1 in the left-right direction are bent behind the pachislot 1. The base plate portion 204 has a rear surface 204b, which is one plane orthogonal to the front-rear direction of the pachislot machine 1, and a front surface 204a (see FIG. 9), which is the other plane. On the rear surface 204b, the medal rail 210 is formed so as to be recessed in front of the pachislot machine 1 and in a substantially L shape. A plurality of ridges 210a are formed on the surface of the medal rail 210.

At the upper end of the base plate portion 204, a medal entrance portion 211 for receiving medals inserted from the medal insertion slot 21 (see FIG. 2) is provided. The medals inserted into the medal selector 201 from the medal entrance portion 211 move from above to below along the medal rail 210. A medal outlet portion 204c (see FIG. 8) is provided at the lower portion of the base plate portion 204. The medal that has moved in the medal selector 201 is ejected from the medal outlet portion 204c and is housed in the hopper device 51 via the slope 203 (see FIG. 4).

A central hole 212 penetrating in the front-rear direction is formed at a substantially intermediate position of the medal rail 210, and an end portion of the medal pressure 213 (see FIG. 8) is exposed from the central hole 212. As shown in FIG. 9, the medal pressure 213 is rotatably supported by a shaft portion 214 provided on the front surface 204a of the base plate portion 204. A coil spring 215 is attached to the shaft portion 214, and the medal pressure 213 is urged by the coil spring 215 so that the medal pressure 213 protrudes from the central hole 212.

As shown in FIG. 9, a magnet 217 is provided on the front surface 204a of the base plate portion 204. The magnet 217 attracts (magnetizes) an illegal medal that is not an appropriate material among the medals that move on the medal rail 210.

Further, as shown in FIG. 8, an upper exposed hole 219 is formed in a substantially central portion of the downstream region of the medal rail 210 so as to penetrate in the front-rear direction and expose the rear end portion of the after-medal pressure 218 described later. .. Further, a lower exposed hole 220 is formed in the lower portion of the downstream region of the medal rail 210 so as to penetrate in the front-rear direction and expose the medal stopper portion 227 described later of the select plate 207.

Further, as shown in FIG. 10, six reference markers 260 are formed on the medal rail 210. The reference marker 260 is arranged in the imaging region A1 (indicated by the alternate long and short dash line in FIG. 10), which is the region on the medal rail 210 imaged by the camera unit 209.

The reference marker 260 includes an upper reference marker 261 and a lower reference marker 262, and the upper reference marker 261 is arranged on the upper part of the medal rail 210 so as to be arranged in three in the left-right direction while being inclined. Further, the lower reference markers 262 are arranged below the medal rail 210 so as to be arranged in three in the left-right direction while being inclined.

The reference marker 260 includes the brightness of the pixel at the location where the reference marker 260 is formed and the brightness of the pixel at the location where the reference marker 260 is not formed in the image data of the imaging region captured by the camera unit 209. Is formed so as to differ by a predetermined value or more. In this embodiment, each reference marker 260 is formed by making a triangular hole in the medal rail 210. The formation mode of the reference marker 260 is not limited to this, and the shape of the hole can be appropriately selected. Further, for example, the reference marker 260 may be formed by printing a figure having a color different from the ground color of the medal rail 210 on the medal rail 210.

As shown in FIG. 9, the after-medal pressure 218 is rotatably supported on the front surface 204a of the base plate portion 204. When the front end of the after medal pressure 218 is pressed backward by the medal solenoid 208 to the rear of the pachislot 1, the after medal pressure 218 rotates, and the rear end of the after medal pressure 218 comes from the upper exposed hole 219 (see FIG. 8). Be exposed.

As shown in FIGS. 7 and 8, the cancel shooter 206 is a substantially plate-shaped member, and is molded so that both ends of the pachi-slot 1 in the left-right direction are bent in front of the pachi-slot 1. The cancel shooter 206 is detachably fixed to the base plate portion 204 and covers the lower portion of the base plate portion 204 from the rear. The cancel shooter 206 guides the medal discharged without passing through the medal outlet portion 204c to the medal shoot 202 (see FIG. 4). A notch 206a notched downward in a substantially rectangular shape is formed in the upper part of the substantially central portion of the cancel shooter 206 in the left-right direction.

Further, the cancel shooter 206 is provided with a notification LED 206c. The notification LED 206c constitutes a notification means that lights and notifies that an error has occurred in the AE correction process described later.

As shown in FIGS. 7 and 8, the sub-plate 205 is a plate-shaped member that covers the medal rail 210 from behind. The sub-plate 205 has a flat plate-shaped main body portion 221 and a shaft portion 222 provided on the upper portion of the main body portion 221. A through hole 221a penetrating in the front-rear direction is provided in the substantially central portion of the main body portion 221, and a downstream region is exposed from the substantially central portion of the medal rail 210 from the through hole 221a.

The shaft portion 222 is supported by the base plate portion 204, and the sub-plate 205 is rotatably attached to the base plate portion 204 about the shaft portion 222. A coil spring 223 is attached to the shaft portion 222. Normally, the sub-plate 205 is pressed against the base plate portion 204 by the urging force of the coil spring 223. At this time, a space through which medals can pass is formed between the sub-plate 205 and the upper portion of the medal rail 210 covered by the sub-plate 205. That is, the sub-plate 205 functions as a guide plate for passing medals.

Here, for example, when a medal jam occurs in the medal selector 201, the sub-plate 205 can be rotated against the urging force of the coil spring 223 to clear the medal jam.

As shown in FIG. 7, the select plate 207 is a member that guides medals moving in a substantially central portion of the medal rail 210 that is not covered by the sub-plate 205. As shown in FIG. 11, the select plate 207 is formed by a substantially trapezoidal plate-shaped plate body 224 and a pair of bearing portions formed by bending both ends of the plate body 224 in the left-right direction to the front of the pachi-slot machine 1. It has 225 and. Further, a flange portion 226 formed by bending the pachislot machine 1 forward and the rear end portion upward is formed on the upper portion of the plate body 224. Further, one bearing portion 225 is formed with a medal stopper portion 227 extending downward.

As shown in FIG. 7, the plate main body 224 faces the substantially central portion of the medal rail 210 not covered by the sub-plate 205 in the front-rear direction of the pachi-slot machine 1.

As shown in FIG. 9, the select plate 207 is rotatably supported by a shaft portion 228 provided on the front surface 204a of the base plate portion 204. A coil spring 229 is provided on the shaft portion 228, and the flange portion 226 is urged to the front of the pachi-slot machine 1. The flange portion 226 is in contact with one end of the medal solenoid 208. When the medal solenoid 208 is in the ON state, the flange portion 226 is pressed against one end of the medal solenoid 208 and moves to the rear of the pachi-slot machine 1 against the urging force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a "guide position". The distance between the plate body 224 of the select plate 207 and the medal rail 210 at the guide position is set to a predetermined distance that can guide the medal to the hopper device 51 without ejecting the medal to the cancel shooter 206 side. At this time, the medal stopper portion 227 does not protrude from the lower exposed hole 220 (see FIG. 8).

Further, when the medal solenoid 208 is in the OFF state, the flange portion 226 is released from the pressure of the medal solenoid 208 and moves to the front of the pachislot 1 by the urging force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a "discharge position". The distance between the plate body 224 of the select plate 207 and the medal rail 210 at the discharge position is set to be longer than a predetermined distance. At this time, it is pressed by the flange portion 226 that moves forward of the pachi-slot 1, and one end of the medal solenoid 208 moves forward of the pachi-slot 1. Along with this, the other end of the medal solenoid 208 moves to the rear of the pachislot 1 and presses the front end of the after medal pressure 218. As a result, the after-medal pressure 218 rotates, and the rear end portion of the after-medal pressure 218 is exposed from the upper exposed hole 219 (see FIG. 8).

The medal stopper portion 227 does not protrude from the lower exposed hole 220 (see FIG. 8) when the select plate 207 is in the guide position, and protrudes from the lower exposed hole 220 when it is in the discharge position.

As shown in FIG. 12, the select plate 207 in the guide position contacts the upper part of the moving medal when the medal moving on the medal rail 210 meets the standard dimensions, and the medal is moved to the medal outlet portion 204c (see FIG. 8). ). When the medal is guided by the select plate 207, the medal pressure 213 is pressed forward of the pachislot machine 1. In FIG. 12, the sub-plate 205 of the medal selector 201 and the cancel shooter 206 are not shown.

On the other hand, as shown in FIG. 13, in the select plate 207 at the ejection position, the distance between the plate body 224 and the medal rail 210 is large even when the medal moving on the medal rail 210 meets the standard dimensions. Therefore, the medal cannot be guided to the medal exit portion 204c (see FIG. 8). Further, the medal is pushed out to the medal pressure 213, the after medal pressure 218 protruding from the upper exposed hole 219, or the medal stopper portion 227 protruding from the lower exposed hole 220, and is discharged toward the cancel shooter 206. Note that, in FIG. 13, as in FIG. 12, the sub-plate 205 and the cancel shooter 206 of the medal selector 201 are not shown.

Further, in the present embodiment, the select plate 207 is normally positioned at the guide position, but under predetermined conditions (for example, when a predetermined number of medals are inserted, when an error occurs, when a game starts, etc.), the select plate 207 is positioned at the ejection position. It is positioned.

Further, when the medal moving on the medal rail 210 has a diameter smaller than the standard size, even if the select plate 207 is in the guide position, the medal is not guided by the select plate 207 and is pushed out by the medal pressure 213, and the cancel shooter 206 is used. It is discharged toward.

As shown in FIGS. 7 and 8, the camera unit 209 is composed of a first substrate 230, a second substrate 231 and a lens (not shown), and whether or not the object moving on the medal rail 210 is a regular medal. Is a unit that determines and outputs the determination result to the main control circuit 91. A CMOS image sensor 232 (see FIG. 17) and an LED 233 (see FIG. 17) are provided on the first substrate 230. The second substrate 231 is provided with a control LSI 234 (see FIG. 17) that is communicatively and controllably connected to the CMOS image sensor 232 and the LED 233.

The first board 230 and the second board 231 are connected by a BtoB (Board-to-Board) type connector (not shown), and the legs 235 provided at the corners of the boards 230 and 231 respectively. It is fixed. The specific configuration of the circuit of the camera unit 209 will be described later. Further, in the present embodiment, the embodiment in which the camera unit 209 is composed of two substrates 230 and 231 and a lens has been described, but instead of this, one substrate provided with the CMOS image sensor 232, the LED 233 and the control LSI 234 is used. A camera unit may be configured. Further, an aperture mechanism may be added.

The camera unit 209 is fixed to the cancel shooter 206 by screwing the first substrate 230 into the screw holes 206b provided around the notch 206a at the top.

The CMOS image sensor 232 (see FIG. 17) is provided in a substantially central portion of the first substrate 230. The CMOS image sensor 232 images the imaging region A1 (see FIG. 10) on the medal rail 210 via the notch 206a (see FIG. 8) of the cancel shooter 206, and controls the captured image data 234 (FIG. 17). See).

The LED 233 (see FIG. 17) emits surface light around the CMOS image sensor 232 and irradiates an object moving on the medal rail 210 with light. The control LSI 234 (see FIG. 17) determines whether or not the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232, and outputs the determination result to the main control circuit 91. To do. In the present embodiment, the mode in which the camera unit 209 is fixed to the cancel shooter 206 by screwing into the screw hole 206b formed around the notch 206a has been described, but the fixing mode of the camera unit is limited to this. Not done. For example, a mounting rail is provided between the first substrate 230 and the second substrate 231 and a recess is provided in the upper part of the cancel shooter 206, and the mounting rail is fitted in the recess, and then the mounting rail and the cancel shooter 206 are provided. May be fixed with screws or an adhesive.

<Circuit configuration of pachislot>
Next, the configuration of the circuit included in the pachi-slot machine 1 will be described with reference to FIGS. 14 to 18.
First, an outline of the entire circuit included in the pachi-slot machine 1 will be described with reference to FIG. FIG. 14 is a block configuration diagram of the entire circuit included in the pachi-slot machine 1.

The pachi-slot machine 1 has a main control board 71 arranged on the middle door 41 and a sub control board 72 arranged on the front door 2b.
The main control board 71 includes a reel relay terminal board 74, a setting key type switch 56, an external centralized terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, and a power supply board 53b of the power supply device 53. It is connected. The setting key type switch 56, the external centralized terminal board 47, the hopper device 51, and the medal auxiliary storage switch 75 are connected to the main control board 71 via the cabinet side relay board 44. Since the external centralized terminal plate 47 and the hopper device 51 have been described above, the description thereof will be omitted.

The reel relay terminal plate 74 is arranged inside the reel main body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R, and relays a signal output from the main control board 71 to the stepping motor.

The medal auxiliary storage switch 75 penetrates the switch through hole (not displayed) of the medal auxiliary storage 52. The medal auxiliary storage switch 75 detects whether or not the medal auxiliary storage 52 is full of medals.

A power switch 53a is connected to the power supply board 53b of the power supply device 53. The power switch 53a is turned on when supplying the necessary power to the pachi-slot machine 1.

Further, the main control board 71 has a medal selector 201, a door open / close monitoring switch 67, a BET switch 77, a settlement switch 78, a start switch 79, a stop switch board 80, and a game operation display board 81 via a door relay terminal board 68. And the sub-relay board 61 are connected. Since the door open / close monitoring switch 67 and the sub-relay board 61 have been described above, the description thereof will be omitted. The circuit configuration of the medal selector 201 will be described later.

The BET switch 77 detects that the BET button 22 has been pressed by the player. The checkout switch 78 detects that the checkout button 27 has been pressed by the player. The start switch 79 detects that the start lever 23 has been operated by the player (start operation).

The stop switch board 80 is a board that constitutes a circuit for stopping a rotating reel and a circuit for displaying a stoptable reel by an LED or the like. A stop switch is provided on the stop switch board 80. The stop switch detects that each of the stop buttons 19L, 19C, 19R is pressed by the player (stop operation).

The game operation display board 81 displays the number of inserted medals on the 7-segment display 24 when accepting the insertion of medals, when the three reels 3L, 3C, and 3R are rotatable and when the replay is performed. It is a substrate for making it. A 7-segment display 24 and an LED 82 are connected to the game operation display board 81. The LED 82 lights, for example, a mark indicating the start of the game, a mark for replaying the game, and the like.

The sub-control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub-relay board 61. The sound I / O board 84, the LED boards 62A, 62B, 62C, and the 24h door open / close monitoring unit 63 are connected to the sub control board 72 via the sub relay board 61. Since the LED boards 62A, 62B, 62C and the 24h door open / close monitoring unit 63 have been described above, the description thereof will be omitted.

The sound I / O board 84 outputs sound to a center speaker 58, a board speaker 64, lower speakers 65L and 65R, and speakers (not shown) provided on the front door 2b.

Further, the ROM cartridge board 86 and the liquid crystal relay board 87 are connected to the sub-control board 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub-control board case 57 together with the sub-control board 72.
The ROM cartridge board 86 is a board for managing images (video) for production, audio, LED boards 62A and 62B and other LED boards (not shown), and communication data. The liquid crystal relay board 87 is a board that relays the wiring connecting the sub-control board 72 and the liquid crystal display device 11.

<Main control circuit>
Next, the main control circuit 91 composed of the main control board 71 will be described with reference to FIG.
FIG. 15 is a block diagram showing a configuration example of the main control circuit 91 of the pachislot machine 1.

The main control circuit 91 has a microcomputer 92 installed on the main control board 71 as a main component. The microcomputer 92 includes a main CPU 93, a main ROM 94, and a main RAM 95. The main CPU 93 and the above-mentioned hopper device 51 constitute the game medium payout device of the present invention.

The main ROM 94 is used to transmit various control commands (commands) to the control program (for example, the program for executing the internal lottery process described above), the data table, and the sub control circuit 101 executed by the main CPU 93. Data etc. are stored. The main RAM 95 is provided with a storage area for storing various data such as internal winning combinations determined by executing the control program.

A clock pulse generation circuit 96, a frequency divider 97, a random number generator 98, and a sampling circuit 99 are connected to the main CPU 93. The clock pulse generation circuit 96 and the frequency divider 97 generate a clock pulse. The main CPU 93 executes a control program based on the generated clock pulse. The random number generator 98 generates random numbers in a predetermined range (for example, 0 to 65535). The sampling circuit 99 extracts one value from the generated random numbers.

The main CPU 93 counts the number of times a pulse is output to the stepping motors of the reels 3L, 3C, and 3R after detecting the reel index. As a result, the main CPU 93 manages the rotation angles of the reels 3L, 3C, and 3R (mainly, how many symbols the reels have rotated).
The reel index is information indicating that the reel has made one revolution. This reel index is provided, for example, with an optical sensor having a light emitting unit and a light receiving unit, and is provided at a predetermined position on each reel 3L, 3C, 3R, and the light emitting unit and the light receiving unit are connected by rotation of each reel 3L, 3C, 3R. It is detected by a reel position detection unit (not shown) provided with a detection piece interposed between them.

Here, the management of the rotation angles of the reels 3L, 3C, and 3R will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 95. Then, each time the output of a predetermined number of pulses (for example, 16 times) required for rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 95 is added one by one. The symbol counter is provided according to each reel 3L, 3C, 3R. The value of the symbol counter is cleared when the reel index is detected by the reel position detection unit (not shown).

That is, in the present embodiment, by managing the symbol counter, it is possible to manage how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol of each reel 3L, 3C, 3R is detected with reference to the position where the reel index is detected.

As described above, when the maximum number of sliding pieces is set to 4 symbols, the symbol of the left reel 3L in the middle of the reel display window 4 when the left stop button 19L is pressed and the 4 symbols thereof. Each symbol within the range up to the previous symbol becomes a symbol that can be stopped in the middle of the reel display window 4.

Further, when the determination result is input from the control LSI 234 of the medal selector 201 as described later, the main CPU 93 causes the gaming machine to misunderstand that a regular game medium is used based on the input determination result. Detects fraudulent activity in playing games.

<Sub-control circuit>
Next, the sub-control circuit 101 composed of the sub-control board 72 will be described with reference to FIG.
FIG. 16 is a block diagram showing a configuration example of the sub-control circuit 101 of the pachi-slot machine 1.

The sub-control circuit 101 is electrically connected to the main control circuit 91, and performs processing such as determination and execution of the effect content based on the command transmitted from the main control circuit 91. The sub control circuit 101 basically includes a sub CPU 102, a sub RAM 103, a rendering processor 104, a drawing RAM 105, and a driver 106.

The sub CPU 102 controls the output of video, sound, and light according to the control program stored in the ROM cartridge board 86 in response to the command transmitted from the main control circuit 91. The ROM cartridge board 86 is basically composed of a program storage area and a data storage area.

A control program executed by the sub CPU 102 is stored in the program storage area. For example, the control program includes a main board communication task for controlling communication with the main control circuit 91, and an effect registration task for extracting an effect random value and determining and registering the effect content (effect data). Is included. Further, a drawing control task for controlling the display of an image by the liquid crystal display device 11 (see FIG. 2) based on the determined effect content, a lamp control task for controlling the output of light by a light source such as an LED85, and speakers 58, 64, 65L. , 65R and the like include voice control tasks that control the output of sound from speakers.

The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to video creation. Further, a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a pattern of turning on and off light, and the like are included.

The sub RAM 103 is provided with a storage area for registering the determined effect content and effect data, and a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 91.

The sub CPU 102, the rendering processor 104, the drawing RAM (including the frame buffer) 105, and the driver 106 create an image according to the animation data specified by the effect content, and display the created image on the liquid crystal display device 11.

Further, the sub CPU 102 causes the speakers such as the speakers 58, 64, 65L, and 65R to output sounds such as BGM according to the sound data specified by the effect content. Further, the sub CPU 102 controls turning on and off of a light source such as LED85 according to the lamp data specified by the effect content.

<Circuit configuration of medal selector>
Next, the circuit configuration of the medal selector 201 will be described with reference to FIG.
FIG. 17 is a block diagram showing a circuit configuration example of the medal selector 201.

As shown in FIG. 17, the medal selector 201 includes a camera unit 209 and a medal solenoid 208.
Further, the medal selector 201 is connected to the main control board 71 via the door relay terminal plate 68. That is, the medal selector 201 is electrically connected to the main control circuit 91. Therefore, the main control circuit 91 can set the medal solenoid 208 of the medal selector 201 to the ON state or the OFF state.

The camera unit 209 is composed of a control LSI 234, a CMOS image sensor 232, and an LED 233. The control LSI 234 of the camera unit 209 is composed of an ASIC (Application Specific Integrated Circuit) and is electrically connected to the CMOS image sensor 232 and the LED 233. The control LSI 234 controls the light emission of the LED 233. Further, the control LSI 234 determines whether or not the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232, and determines the determination result from the output PORT assigned to the GPIO250. When a predetermined output condition described later is satisfied, the data is output to the main control board 71 via the door relay terminal plate 68.

The CMOS image sensor 232 includes an exposure time setting mechanism that sets the exposure time (shutter speed) in 1 to 25 steps. The exposure time is set to be extended by 7 μs for each step up. In the present embodiment, the initial value of the exposure time (value at the time of turning on the power of the pachislot 1) is set to step 10, that is, 70 μsec. Therefore, in the present embodiment, the exposure time can be set in the range of 70 μsec to a maximum of 175 μsec (exposure time corresponding to step 25).
The CMOS image sensor 232 used in the present embodiment is a CMOS image sensor having a resolution of 648 × 488 pixels and a frame rate of 240 fps (Frames Per Second).

Further, the control LSI 234 is electrically connected to the notification LED 206c. The notification LED 206c is turned on and off in response to an instruction from the control LSI 234.

<Circuit configuration of control LSI>
Next, the circuit configuration of the control LSI 234 will be described with reference to FIG.
FIG. 18 is a block diagram showing a circuit configuration example of the control LSI 234.

The control LSI 234 includes a host controller 241 and an image recognition DSP (digital signal processor) circuit 242, a SRAM (Static Random Access Memory) 243 to which a backup power supply (not shown) is connected, a flash memory 244, and an ISP (Image Signal Processing) circuit 245. And a medal counting circuit 246 is provided. Further, the control LSI 234 includes a color recognition circuit 247, a fisheye correction scaler circuit 248, an image recognition accelerator circuit 249, and a GPIO (General Purpose Input / Output) 250. The devices constituting these control LSIs 234 are connected to each other via a bus, and in the control LSI 234 of the present embodiment, AXI (Advanced eXtensible Interface) is adopted as a bus protocol.

Further, the control LSI 234 includes an ISI (Image Sensor Interface) circuit 251. The ISI circuit 251 is electrically connected to the CMOS image sensor 232 and the ISP circuit. The ISI circuit 251 converts the image data transmitted from the CMOS image sensor 232 by the LVDS (Low voltage differential signaling) method into an RGB Bayer image and outputs the image data.

<ISP circuit>
When the RGB Bayer image is output from the ISI circuit 251 (the RGB Bayer image is input), the ISP circuit 245 outputs a VSYNC (Vertical Synchronization) interrupt signal to the host controller 241.
Further, the ISP circuit 245 performs an image correction process of performing a lens distortion correction process and a projective conversion (homography) process on the RGB bayer image output from the ISI circuit 251.

The lens distortion correction process is a process for correcting distortion caused by the characteristics of the lens in the camera unit 209 on the image data captured by the CMOS image sensor 232 in order to improve the accuracy of various discrimination / judgment processes described later. is there.

For example, when a convex lens is used as the lens of the camera unit 209, the thickness of the edge of the lens is thinner than the thickness of the central portion of the lens, so that distortion as shown in FIG. 19 occurs. In FIG. 19, the image pickup region A1 of the CMOS image sensor 232 and the image data G1 of the image pickup region A1 imaged by the CMOS image sensor 232 are schematically shown. The black dots in the image data G1 represent points corresponding to the vertices of each grid in the imaging region A1.

As shown in FIG. 19, in the image data G1, a relatively large distortion is generated at the end portion as compared with the central portion. The ISP circuit 245 performs lens distortion correction processing based on various preset correction parameters to process image data G1 (RGB bayer image output from the ISI circuit 251). Specifically, the image data G1 is complemented so that the position of the black spot of the image data G1 is the same as the apex of the grid of the corresponding imaging region A1. As a result, the influence of this distortion on various discrimination processes described later is suppressed.

The various correction parameters are pre-defined in the program based on the preliminary characteristic evaluation of the lens used in the camera unit 209. The various correction parameters may be stored in the flash memory 244 and referred to by the ISP circuit 245 during the lens distortion correction process.

The projective transformation process is a process of correcting image data so that the deviation of the mounting position of the camera unit 209 does not affect the accuracy of various discrimination / determination processes described later.
For example, when the camera unit 209 is tilted with respect to the cancel shooter 206 at an angle that is not suitable, as shown in FIG. 20A, the image area A2 required for various discrimination / judgment processes described later is distorted and imaged. May occur. In the projective transformation process, this distortion is corrected, and the image data is complemented in a mode suitable for various discrimination / determination processes described later.

Specifically, in the projective conversion process, the ISP circuit 245 analyzes the RGB Bayer image after the lens distortion correction process and detects the positions (coordinates: x, y) of at least four reference markers 260 in the RGB Bayer image. To do.

Next, at the position (coordinates: u, v) of the reference marker 260 in the image data suitable for improving the accuracy of various discrimination processes defined in advance in the program corresponding to the detected four reference markers. Based on this, the conversion coefficients a, b, c, d, e, f, g, and h in the following equations 1 and 2 are calculated.
u = (x × a + y × b + c) / (x × g + y × h + 1) ・ ・ ・ Equation (1)
v = (x × d + y × e + f) / (x × g + y × h + 1) ・ ・ ・ Equation (2)

Then, the calculated conversion coefficients a, b, c, d, e, f, g, h and the coordinate values of each pixel in the RGB bayer image after the lens distortion correction processing are substituted into the above equations 1 and 2. , The converted coordinates for each pixel are calculated, and the RGB bayer image is processed so that each pixel is located at the calculated converted coordinates. FIG. 20B schematically represents the image region A2 shown in FIG. 20A in the RGB bayer image after the projective transformation process.

In this embodiment, an embodiment in which the position (coordinates: u, v) of the reference marker 260 in the image data suitable for improving the accuracy of various discrimination processes is defined programmatically has been described. However, instead of this, for example, the position of the reference marker 260 may be stored in the flash memory 244 and referred to by the ISP circuit 245 during the projective transformation process.

Next, the ISP circuit 245 performs a color conversion process for converting the RGB bayer image after the lens distortion correction process and the projective conversion process into various formats. In the color conversion process, the ISP circuit 245 converts the RGB bayer image into image data (YUV image data) corresponding to the YUV color space, and data related to the brightness in the YUV image data (hereinafter, “grayscale image data””. (Sometimes referred to as) is output to the medal count circuit 246 (output to a predetermined area of the SRAM 243 referenced by the medal count circuit 246). Further, the grayscale image data is stored in the SRAM 243. The SRAM 243 is provided with a storage area that can store a predetermined number of grayscale image data. When the number of grayscale image data stored in the SRAM 243 reaches the upper limit, the stored order is overwritten from the oldest grayscale image data.

Further, in the color conversion process, the ISP circuit 245 converts the RGB bayer image into image data (HSV) corresponding to a color space (HSV color space) composed of three components (H: hue, S: saturation, V: brightness). It is converted into image data) and the HSV image data is output to the color recognition circuit 247 (output to a predetermined area of the SRAM 243 referred to by the color recognition circuit 247).

Further, in the ISP circuit 245, when the power of the pachislot 1 is turned on, when the RGB Bayer image is output from the ISI circuit 251 (the RGB Bayer image is input), whether or not the output image includes a predetermined image. Performs AE (Auto Exposure) determination processing to determine whether or not. In the present embodiment, the predetermined image is an image of the ridge portion 210a (see FIG. 8) formed on the surface of the medal rail 210. That is, in the present embodiment, the ISP circuit 245 constitutes an image determination means for determining whether or not a predetermined image is included in the image data.

When the ISP circuit 245 can extract a linear component having a predetermined length or more from the image output from the ISI circuit 251, the ISP circuit 245 determines that the output image includes an image of the ridge portion 210a and extracts the image. When it cannot be done, it is determined that the output image does not include the image of the ridge portion 210a. The extraction of linear components having a predetermined length or longer from the output image is performed, for example, by performing a Hough transform process on the output image, but the present invention is not limited to this, and other feature extraction methods are used. May be good.

When the ISP circuit 245 determines that the image output from the ISI circuit 251 includes the image of the ridge portion 210a, the ISP circuit 245 does not output the determination result of this AE determination process to the host controller, and thereafter, The AE determination process is not performed on the image output from the ISI circuit 251.

On the other hand, when the ISP circuit 245 determines that the image output from the ISI circuit 251 does not include the image of the ridge portion 210a, the ISP circuit 245 outputs the determination result of this AE determination process to the host controller. Further, when the ISP circuit 245 outputs an image from the ISI circuit 251 until the exposure time of the CMOS image sensor 232 is set to the upper limit of 175 μsec (exposure time corresponding to the step 25) in the present embodiment, The AE determination process is performed on the output image.

In this embodiment, an embodiment in which the predetermined image is a ridge portion 210a formed on the surface of the medal rail 210 has been described. However, the present invention is not limited to this, and a predetermined image may be, for example, a reference marker 260 formed on the medal rail 210. Further, although the mode of determining whether or not the linear component can be extracted from the output image has been described, the determination is not limited to this, and the determination may be made based on the angle of view intensity of the extracted linear component.

<Color recognition circuit>
The color recognition circuit 247 performs color determination processing based on the hue and saturation in the HSV image data output from the ISP circuit 245. The color determination process includes a medal detection process, a threshold value determination process, a saturation / hue multiplication process, a color template generation process, and a color template comparison process.

(1) Medal detection process In the color determination process, the color recognition circuit 247 stores the HSV image data output from the ISP circuit 245 in the SRAM 243. The SRAM 243 is provided with a storage area that can store a predetermined number of HSV image data. When the number of HSV image data stored in the SRAM 243 reaches the upper limit, the stored order is overwritten from the oldest HSV image data.

Further, the color recognition circuit 247 performs a medal detection process for determining whether or not the HSV image data output from the ISP circuit 245 includes a medal image. Specifically, this time, the difference between the HSV image data output from the ISP circuit 245 and the background HSV image data stored in the SRAM 243 is detected, and if the difference portion matches the shape of the medal, the medal It is determined that the image of is included. The background HSV image data is HSV image data that does not include the image of the medal, and is an image captured by the CMOS image sensor 232 when the medal is not moving on the medal rail 210, for example, immediately after the power is turned on. The data is obtained by converting the data into HSV image data by the ISP circuit 245. In the present embodiment, the ISP circuit 245 stores the obtained background HSV image data in the SRAM 243. Whether or not the detected difference portion matches the medal shape is determined by comparing with the HSV image data of the medal shape previously stored in the flash memory 244.

(2) Threshold determination process When it is determined that the HSV image data includes a medal image, the color recognition circuit 247 performs a threshold value determination process based on the HSV image data. In the threshold determination process, the color recognition circuit 247 is in a predetermined region of the medal image in the HSV image data, for example, in a substantially square region including the center of the medal in the present embodiment (hereinafter, may be referred to as a “medal region”). The saturation values of all the pixels of are integrated, and the hue values are integrated. Then, the integrated value is divided by the number of pixels in the medal region to calculate the average saturation value and the average hue value, and the position on the threshold graph shown in FIG. 21 is specified based on the calculated values.

Here, the threshold graph of FIG. 21 is a graph in which the vertical axis is the saturation value and the horizontal axis is the hue value. In the threshold graph, the graph is divided into an allowable area and a non-allowable area based on a predetermined formula. In FIG. 21, the background of the allowable area is represented by a white background, and the background of the non-allowable region is represented by shading.

If the position on the threshold graph based on the average saturation value and the average hue value is within the permissible region, the color determination process is continued. On the other hand, if it is within the non-allowable area, "threshold value determination impossible" is stored in the color determination storage area of SRAM 243 as the determination result of the color determination process, and the color determination process is terminated. A predetermined number of determination results can be stored in the color determination storage area of the SRAM 243, and when the stored determination results reach the upper limit number, the stored determination results are overwritten from the earliest determination result.

Instead of the above, the color recognition circuit 247 specifies the position of each pixel in the medal region on the threshold graph shown in FIG. 21 based on the saturation value and the hue value of the pixel. May be good. In this case, it is determined whether or not the number of pixels positioned in the non-allowable area exceeds a predetermined number, for example, 20% of the number of pixels in the medal area. If not, the color determination process is continued and exceeds. In this case, the SRAM 243 may store "threshold determination impossible" as the determination result of the color determination process, and the color determination process may be terminated.

Further, the allowable area and the non-allowable area in the threshold graph can be set as appropriate. For example, in addition to the non-allowable region of FIG. 21, when the saturation value is a predetermined value or more, for example, 90 or more, a non-allowable region may be provided so as to be located in the non-allowable region.

(3) Saturation / Hue Multiplication Process After the threshold value determination process, the color recognition circuit 247 performs the saturation / hue multiplication process in the threshold value determination process. In the saturation / hue multiplication process, the saturation value of each pixel in the medal area is multiplied by the hue value, and the value calculated by the multiplication is stored in SRAM 243 in association with the position of the pixel. In the following description, when the group of data stored by associating the multiplication value of the saturation value and the hue value of each pixel in the medal area with the position of the pixel is referred to as "color determination data". There is.

(4) Color template generation process The color template generation process is a process for generating a color template used in the color template comparison process described later. In the color template generation process, the color recognition circuit 247 mutually compares and matches the color determination data related to each medal up to the specified initial number of medals inserted after the power is turned on, and 50 medals in the present embodiment. Or group color determination data that are similar to a certain degree.

For example, the color recognition circuit 247 compares the multiplication value of the saturation value and the hue value for each of the positions of the associated pixels with respect to the color determination data related to 50 medals. Then, when the number of multiplication values that match or are within a predetermined error range (for example, ± 5) is a predetermined number or more (for example, 80% or more of all multiplication values), these color determination data are grouped. ..

Next, the color recognition circuit 247 selects the top four groups in descending order of the number of color determination data to which the color recognition circuit 247 belongs. Then, any one color determination data is selected for each of the selected top four groups, and the four color determination data are stored as color templates in the storage area for storing the color template of SRAM 243. For each of the top four selected groups, instead of selecting any one color determination data, the average value of the color determination data belonging to the same group (the average value of the multiplication values related to each pixel). ) May be generated to generate a color template. Further, the color template stored in the SRAM 243 may be erased by the initialization process (not shown) of the host controller 241 when the power of the game machine is turned on.

By generating the color template as described above, for example, when two types of medals having different markings (patterns) and colors on the front and back are used as regular medals, and the color template is stored in the storage area of SRAM 243. If it is not stored, by inserting 50 of these regular medals after turning on the power, it is possible to generate four types of color templates related to the front and back of these two types of medals. If the color template is not stored in the storage area of SRAM 243 and there is only one type of 50 regular medals inserted after the power is turned on, two types of colors related to the front and back of the regular medals are used. A template is generated, and in the color template comparison process described later, the two types of generated color templates are used.

When the color template is not stored in the storage area of the SRAM 243, the number of medals inserted after the power is turned on is the specified initial number of inserted medals, and in the present embodiment, the color determination data related to each medal up to 50 medals is obtained. It is generated according to the instruction of the host controller 241. When the medal counting circuit 246, which will be described later, determines that the medal has passed on the medal rail 210, the host controller 241 determines the HSV image data a predetermined time before (that is, before a predetermined frame) from the determination. Instructs the color recognition circuit 247 to generate color determination data using the above. The predetermined time is set in advance based on experiments and simulations so that the HSV image data before the predetermined time always includes the image of the medal.

Further, the color determination data is generated through the above-mentioned medal detection process, threshold value determination process, and saturation / hue multiplication process, and is stored in the color determination data storage area of SRAM 243. The color recognition circuit 247 executes a color template generation process when the number of color determination data stored in the color determination data storage area reaches 50, that is, when color determination data related to 50 medals is created. To do.

(5) Color template comparison process When the medal detection process after the color template generation process determines that the medal image is included, the color recognition circuit 247 performs the color template comparison process.

In the color template comparison process, the HSV image data determined to contain the image of the medal is compared with the color template and the color determination data created through the threshold determination process and the saturation / hue multiplication process. , Match or a predetermined degree of similarity is determined, and "OK" or "NO" is stored in the color determination storage area of SRAM 243 as the determination result. In the present embodiment, since a maximum of four color templates are used, the determination results for the maximum of four templates are stored in the SRAM 243. Further, in the color template comparison process, the color determination result is stored in the color determination storage area of the SRAM 243. Here, as the color determination result, "OK" is stored when at least one "OK" is stored as the judgment result for up to four templates, and "No" is stored when all "No" are stored. "No" is memorized. Therefore, in one color template comparison process, a maximum of four determination results for a maximum of four color templates and one color determination result based on these determination results are stored. A predetermined number of determination results can be stored in the color determination storage area of the SRAM 243, and when the stored determination results reach the upper limit number, the stored determination results are overwritten from the earliest determination result.

For example, the color recognition circuit 247 compares the multiplication value of the color determination data and the saturation value and the hue value in the color template for each position of the associated pixel. Then, when the number of multiplication values that match or are within a predetermined error range (for example, ± 5) is a predetermined number or more (for example, 80% or more of all multiplication values), it is determined that they match or are similar to a predetermined degree. In this process, the criteria for determining whether or not they match or are similar to a certain degree can be appropriately set.

As described above, in the color determination process, the threshold determination process is performed, the color template comparison process is performed, the color determination data is compared with the color template, and it is determined whether or not they match or are similar to a predetermined degree. The color recognition circuit 247 constitutes a game medium determination means for determining whether or not the object passing on the medal rail 210 is a regular medal.

<Medal count circuit>
The medal counting circuit 246 performs counting processing based on the grayscale image data output from the ISP circuit 245. The counting process includes a medal image discrimination process, a medal position detection process, and an order determination process.

(1) Medal image discrimination process In the count process, the medal count circuit 246 first performs a medal image discrimination process. In the medal image discrimination process, the medal count circuit 246 determines whether or not the grayscale image data output from the ISP circuit 245 includes a medal image. Specifically, this time, a difference is detected for each pixel of the grayscale image data output from the ISP circuit 245 and the background grayscale image data stored in the SRAM 243, and the difference is formed by a plurality of detected pixels. When the shape to be formed matches the template data of the medal shape stored in the flash memory 244, it is determined that the image of the medal is included. The background grayscale image data is grayscale image data that does not include the image of the medal, and is captured by the CMOS image sensor 232 when the medal is not moving on the medal rail 210, for example, immediately after the power is turned on. It is obtained by converting the image data obtained by the ISP circuit 245 into grayscale image data. In the present embodiment, the ISP circuit 245 stores the obtained background grayscale image data in the SRAM 243. In the present embodiment, the medal count circuit 246 detects the difference between the background grayscale image data and the grayscale image data output from the ISP circuit 245, and the medal is determined by whether or not the detected difference matches the medal shape. It was determined whether or not the image was included. However, the present invention is not limited to this, and when the number of detected difference pixels is a certain number or more, it may be determined that the image of the medal is included.

(2) Medal position detection process Next, the medal count circuit 246 performs medal position detection processing on the grayscale image data output from the ISP circuit 245. In the medal position detection process, the medal count circuit 246 determines whether or not a medal image exists in a predetermined determination area in the output grayscale image data, and stores the determination result in the SRAM 243.

The predetermined determination area is a plurality of rectangular areas in the grayscale image data G2, and in the present embodiment, as shown in FIGS. 22 to 24, the determination areas A1 to A4, B1 to B4, C1, C2 , D1 to D4, E and F, a total of 16 determination areas are set. 22A to 22C, 23D to F, and 24G are diagrams for explaining the relationship between the medal M passing over the medal rail 210 and being discharged from the medal outlet portion 204c and the determination region. Further, FIG. 24H is a diagram for explaining the relationship between the medal guided by the medal shoot 202 and the determination area.

Each determination area is predetermined in the program by defining the coordinate values (X, Y) of the corners of each determination area in the grayscale image data G2 so that a plurality of pixels are included in the determination area. ing. For example, as shown in FIG. 25, the determination region of C1 includes eight pixels in the region, and the coordinate values of the four corners (450, 95), (454, 95), (450, 96), ( The position is defined by 454,96). In FIG. 25, one square of the grid indicates one pixel.

As shown in FIGS. 22A to 22C, 23D to F, and 24G, the determination areas A1 to A4 and B1 to B4 pass on the medal rail 210, and the lower part of the image of the medal M discharged from the medal outlet portion 204c. It is arranged so as to overlap with. Further, the determination areas C1 and C2 are arranged so as to pass over the medal rail 210 and overlap the upper part of the image of the medal M discharged from the medal outlet portion 204c. Further, the determination areas E and F are arranged so as to pass over the medal rail 210 and not overlap with the image of the medal M discharged from the medal outlet portion 204c.

Further, as shown in FIG. 24H, the determination area F is arranged in the lower part of the grayscale image data G2 so as to overlap the image of the medal M when the medal is guided by the medal shoot 202. Further, the determination area E is located above the path of the medal M, and is arranged above the grayscale image data G2 so as to overlap the images of various instruments used for fraudulent activities.

The medal count circuit 246 calculates the difference value of the brightness of each pixel in each determination area of the grayscale image data to be processed and the background grayscale image data, and calculates the number of pixels whose calculated difference value is equal to or larger than the threshold value. Count for each judgment area. Then, the medal counting circuit 246 determines whether or not the number of counted pixels is equal to or greater than a predetermined number for each determination region, and if it is determined that the number is equal to or greater than a predetermined number, an image of a medal is displayed in the determination region. Is present (there is a medal). On the other hand, when it is determined that the number of counted pixels is less than a predetermined number, it is determined that the image of the medal does not exist in the determination area (there is no medal). In the present embodiment, the mode in which the grayscale image data is used in this process has been described, but the present invention is not limited to this, and for example, for color determination generated by multiplying the saturation and hue used in the above-mentioned color determination process. Data may be used.

In addition, the medal count circuit 246 performs the medal edge detection process on the determination area where it is determined that the image of the medal exists (there is a medal) in the medal position detection process.

The medal edge detection process is a process of detecting the outer edge (edge) of a medal based on the arrangement of pixels whose brightness difference value is less than the threshold value in the determination area where it is determined that the medal image exists. In the present embodiment, the moving direction of the medal is from left to right in FIGS. 22 to 25. Therefore, if there is at least one pixel on the right side where the difference value of the brightness is less than the threshold value in the determined determination area where the medal image exists, the medal counting circuit 246 will perform the outer edge (moving destination direction) on the front side in the moving direction of the medal. It is determined that the medal edge) exists.

On the other hand, if there is at least one pixel on the left side where the difference value of the brightness is less than the threshold value in the determined determination area where the medal image exists, the medal counting circuit 246 is the outer edge (after movement) on the rear side in the movement direction of the medal. It is determined that the direction medal edge) exists. If there is no pixel whose brightness difference value is less than the threshold value, the medal counting circuit 246 determines that there is no outer edge of the medal in the determination area.

For example, in the determination area C1 shown in FIG. 25, if any of the pixels 5C to 8C, which are the pixels located on the right side, has at least one pixel whose luminance difference value is less than the threshold value, the movement destination direction medal Judge that there is an edge. On the other hand, in any of the pixels 1C to 4C located on the left side, if there is at least one pixel whose luminance difference value does not meet the threshold value, it is determined that there is a medal edge in the post-movement direction.

Regarding the determination areas E and F, since the moving direction of the medal or various instruments is considered to be from the top to the bottom in FIGS. 22 to 24, the brightness difference value is lower than the pixel whose brightness is equal to or more than the threshold value. When there is at least one pixel whose difference value is less than the threshold value, the medal counting circuit 246 determines that the lower outer edge (medal edge in the moving destination direction) exists in the moving direction of the medal. On the other hand, when there is at least one pixel whose brightness difference value is above the threshold value and whose brightness difference value is less than the threshold value, the medal counting circuit 246 sets the upper outer edge (after movement) of the medal in the moving direction. It is determined that the direction medal edge) exists. Further, when there is no pixel whose brightness difference value is less than the threshold value for the pixels located below or above the pixel whose brightness difference value is equal to or higher than the threshold value, the medal counting circuit 246 will generate a medal in the determination area. It is determined that the image exists, but there is no outer edge of the medal.

Then, the medal count circuit 246 moves the above determination result, that is, the determination result of whether or not the medal image exists in the determination area, and the movement for each determination area of the grayscale image data output from the ISP circuit 245. The determination result of whether or not the forward medal edge or the backward medal edge is present is stored in the SRAM 243 in the order of input. For example, the medal counting circuit 246 stores data of "OFF" in the determination area where it is determined that the image of the medal does not exist. Further, the data "IN" is used for the judgment area determined to have the movement destination direction medal edge, the data "OUT" is used for the judgment area determined to have the moving destination direction medal edge, and the medal image. Is present, but the data "ON" is stored in the determination area where it is determined that there is no outer edge of the medal. If it is determined in the medal image determination process that the medal image is not included, the medal count circuit 246 omits the medal position detection process and stores data of "OFF" for all the determination areas. You may.

Further, the medal counting circuit 246 omits the determination of the determination areas A1 to A4, B1 to B4, C1, C2, D1 to D4 when the medal cannot be inserted, for example, when the credit counter has the maximum value as described later. To do. Further, in this case, the medal counting circuit 246 indicates to the SRAM that the above determination is omitted, that is, the determination is not made with respect to the determination areas A1 to A4, B1 to B4, C1, C2, and D1 to D4. * ”Data (specifically, the hexadecimal number“ FF ”) is stored.

Therefore, for the eight grayscale image data G2 shown in FIGS. 22A to C, 23D to F, and 24G and H, the determination area determination result data as shown in FIG. 26 is stored in the SRAM 243. For example, with respect to the grayscale image data G2 of FIG. 22A, since it is determined that the medal edge in the movement destination direction exists with respect to the determination areas A1 and A2, the data "IN" (specifically, a hexadecimal number). "01") is stored, and it is determined that the medal image does not exist for the other determination areas. Therefore, the data "OFF" (specifically, the hexadecimal number "00") is stored. It will be remembered.

Further, regarding the grayscale image data of FIG. 23E, since it is determined that the medal image does not exist in the determination areas A1 to A4, E and F, the data "OFF" is stored. Further, since it is determined that the medal edge in the post-movement direction exists for the determination areas B1, B2, C1 and C2, the data "OUT" (specifically, the hexadecimal number "02") is stored. Will be done. Further, for the determination areas B3, B4, D1 to D4, although the medal image exists, it is determined that there is no outer edge of the medal, so the data "ON" (specifically, the hexadecimal number "" 03 ") is stored.

Further, regarding the grayscale image data G2 shown in FIG. 24H, since it is determined that the medal image exists in the determination area F but the outer edge of the medal does not exist, the data “ON” is stored. Further, in the determination areas A1 to A4, B1 to B4, C1, C2, and D1 to D4, the data "*" indicating that the determination has not been made is stored.

The grayscale image data G2 of FIGS. 22A to 22C, 23D to F, and 24G is output from the ISP circuit 245 when the medal passes over the medal rail 210 and is discharged from the medal outlet portion 204c. Of the grayscale image data G2, seven grayscale image data G2 are extracted for convenience of explanation. That is, in the same case, the grayscale image data output from the ISP circuit 245 exists in addition to the grayscale image data G2 shown in FIGS. 22A to C, 23D to F, and 24G.

Further, the SRAM 243 is provided with a storage area for storing the determination results related to a predetermined number of grayscale image data as the determination area determination result data. When the determination result stored in the SRAM 243 reaches the upper limit number, the stored order is overwritten from the determination result related to the old grayscale image data.

(3) Order determination process After the medal image detection process and the medal position detection process, the medal count circuit 246 performs an order determination process. In the order determination process, in a predetermined number of grayscale image data arranged in chronological order, the transition mode of the data of "IN", "OUT", "ON", and "OFF" for each determination area is a predetermined transition. It is determined whether or not the mode matches the above aspect, and if they match, it is determined that the medal has passed on the medal rail 210.

Here, as a predetermined transition mode, in the present embodiment, the medal count determination table shown in FIG. 27 is converted into a numerical value and stored in the flash memory 244. In the medal count judgment table, "IN" and "IN" in each judgment area on the 14 grayscale image data arranged in chronological order when the medal passes on the medal rail 210 and is discharged from the medal exit portion 204c. The mode of data transition of "OUT", "ON", and "OFF" is defined. The mode of transition of these data is defined in advance by simulation, experiment, or the like.

In the order determination process, the medal count circuit 246 has a mode of data transition in each determination area of the latest 14 grayscale image data stored in the SRAM 243, and a time series 1 defined in the medal count determination table. The mode of data transition corresponding to ~ 14 is compared, and if the data is completely matched, it is determined that the medal has passed. If they do not match, it is determined that "an abnormality has occurred". If they do not match, for example, the first half of the mode of data transition in each determination area of the latest 14 grayscale image data (hereinafter, may be referred to as "mode of transition of data to be compared"). Is consistent with the mode of data transition corresponding to the time series 1 to 8 specified in the medal count judgment table, but the following part is the data corresponding to the time series 8 to 4 specified in the medal count judgment table. There are cases where it matches the mode of transition (hereinafter, this case may be referred to as "reverse of time series"). If they do not match, for example, the first half of the transition mode of the data to be compared matches the data transition mode corresponding to the time series 1 to 7 defined in the medal count determination table. When the following part matches the mode of data transition corresponding to the time series 10 to 14 specified in the medal count judgment table, that is, the data corresponding to the time series 8 and 9 specified in the medal count judgment table. May be missing. If they do not match, for example, the first half of the transition mode of the data to be compared matches the data transition mode corresponding to the time series 1 to 8 defined in the medal count determination table. When all the following parts match the mode of data transition corresponding to the time series 9 defined in the medal count determination table, that is, the same transition mode may overlap. The above-mentioned time-series retrograde corresponds to an existing medal retrograde error, and when the same transition mode overlaps, it corresponds to an existing medal jam error. Further, when the above data is missing, it is an error that could not be detected by the existing medal selector, and the medal selector 201 capable of detecting the error is superior in error detection performance to the existing medal selector. It can be said that.

Further, the medal count circuit 246 is defined by the mode of data transition in each determination area of the latest four grayscale image data stored in the SRAM 243 and the medal count determination table when the medal cannot be inserted. The data transition modes corresponding to the time series E1 to E4 are compared with each other, and if they completely match, it is determined that the medal has been guided by the medal shoot 202.

If the number of grayscale image data stored in SRAM 243 is less than a predetermined number, for example, 4 or 14, the transition modes do not match due to insufficient number of data. In the comparison process, it is not determined that "the medal has passed" or "the medal has been guided by the medal shoot 202". In this case, the above comparison process may be omitted.

Further, when the medal counting circuit 246 stores any data of "IN", "OUT", or "ON" with respect to the determination area E of the latest grayscale image data stored in the SRAM 243, , Judge that an abnormality has occurred.

Further, in the order determination process, the medal count circuit 246 stores the above-mentioned determination result in the order determination process in the SRAM 243 as the determination result of the count process. That is, in the SRAM 243, as the determination result of the counting process, "the medal has passed" (specifically, the hexadecimal number "01") and "the medal has been guided to the medal shoot 202" (the specific numerical value). As the hexadecimal number "02") and "an abnormality has occurred" (specifically, the hexadecimal number "10"), three types of determination results are stored. Here, the case where it is determined that "the medal has passed" is, for example, the case where the medal is inserted in the state where the medal can be inserted in the main control circuit 91. Further, the case where it is determined that "the medal has been guided to the medal shoot 202" is the case where an illegal medal having an outer diameter smaller than the specified medal is inserted while the medal can be inserted in the main control circuit 91, or the main This is a case where medals are inserted in a state where medals cannot be inserted in the control circuit 91. In addition, the case where it is determined that "an abnormality has occurred" is compared with the case where some foreign matter is detected outside the range through which the medal passes, or the mode of data transition specified in the above-mentioned medal counter judgment table. This is a case where the mode of transition of the target data does not match.

As a result of the above comparison, instead of determining that "the medal has passed" or "the medal has been guided by the medal shoot 202" in the case of an exact match, a predetermined degree, for example, the degree of match is 80% or more. In this case, it may be determined that "the medal has passed" or "guided by the medal shoot 202" in consideration of a predetermined determination margin.

Further, in the medal position detection process, the medal edge detection process may be omitted. In this case, the medal count circuit 246 stores data of "OFF" in the SRAM 243 for the determination area determined that the medal image does not exist, and "ON" for the determination area determined that the medal image does exist. To memorize the data. Then, the medal count determination table shown in FIG. 27 defines the mode of transition of “ON” and “OFF” data in each determination area.

Further, in the order determination process, instead of the comparison using the medal count determination table shown in FIG. 27, the order of the determination areas in which the “ON” data is stored is defined in advance, and the predetermined order and the actual order are specified. The passage of the medal may be determined by comparing the order of the determination areas in which the "ON" data is stored. In this case, the predetermined order is grouped with the judgment areas A1 to A4 as the A area, the judgment areas B1 to B4 as the B area, the judgment areas C1 and C2 as the C area, and the judgment areas D1 to D4 as the D area. May be specified in. For example, in a predetermined order, all of the A to D regions are "OFF", then only the A region is "ON", then the A region, the B region and the C region are "ON", and then the B region, the C region and the D region. May be "ON", then only the D region may be "ON", and finally any of the A to D regions may be "OFF". In this case, when the area A is "ON", the data of "ON" is stored in any of the determination areas A1 to A4.

Further, the number, shape, and arrangement location of the determination areas to be set on the grayscale image data can be appropriately set according to the allowable determination time required and the accuracy of the determination to be obtained. For example, in FIGS. 22A to 22C, 23D to F, and 24G, H, a determination region extending in the vertical direction from the upper end to the lower end of the grayscale image data G2 may be set.

<Fisheye correction scaler circuit>
The fisheye correction scaler circuit 248 acquires grayscale image data from SRAM 243 and performs fisheye correction processing for correcting the fisheye of the acquired grayscale image data.

Further, the fisheye correction scaler circuit 248 performs an equalization process on the grayscale image data that has undergone the fisheye correction process. In the equalization process, the fisheye correction scaler circuit 248 creates reduced image data reduced to 1/2, 1/4, 1/8.

In addition, the fisheye correction scaler circuit 248 performs bilateral conversion processing on each of the created reduced image data in the equalization processing. In this embodiment, in order to remove noise in the reduced image data, a Gaussian filter of a 3 × 3 kernel (kernel in image processing, not a kernel showing OS functions) shown in FIG. 28 is used. However, the Gaussian filter has a drawback that the edges in the image data become inconspicuous (blurred). Therefore, in order to eliminate this drawback, a bilateral filter represented by the following equation 3 is adopted as a processing algorithm for the bilateral conversion process. That is, the bilateral filter is a filter that uses the kernel of the Gaussian filter to remove noise in image data and perform edge correction and enhancement.

In Equation 1, let f (i, j) be the array of image data before the bilateral conversion process, and g (i, j) be the array of image data after the process. Further, w represents the kernel size, σ represents the standard deviation, and d represents the difference in the brightness value.

Then, the fisheye correction scaler circuit 248 stores the reduced image data that has undergone the equalization process in the SRAM 243. The SRAM 243 is provided with a storage area that can store a predetermined number of reduced image data. When the number of reduced image data stored in the SRAM 243 reaches the upper limit, the stored order is overwritten from the oldest reduced image data.

<Image recognition DSP circuit>
When the medal counting circuit 246 determines that the medal has passed on the medal rail 210, the host controller 241 uses the reduced image data a predetermined time before the determination (that is, before a predetermined frame). Then, the image recognition DSP circuit is instructed to perform the preprocessing. The predetermined time is set in advance based on experiments and simulations so that the reduced image before the predetermined time always includes the image of the medal.

In the preprocessing, the image recognition DSP circuit 242 acquires reduced image data (reduced image data reduced to 1/4 in this embodiment) from SRAM 243, and detects a circular area from the acquired reduced image data. The processing and the non-linear diffusion filter processing are performed to create an edge image, which is then stored in the SRAM 243. Further, the image recognition DSP circuit 242 performs various determination processes described later. In the present embodiment, the image data reduced to 1/4 is used, but the present invention is not limited to this, and the setting for selecting the reduced image data to be used in the flash memory 244 is stored, and the setting is adjusted according to the setting. Therefore, the image data reduced to 1/2 or the image data reduced to 1/8 may be selected.

(1) Circle area detection processing The image recognition DSP circuit 242 generates a background subtraction image showing the difference between the acquired reduced image data and the reduced background grayscale image data corresponding to the reduced image data in the circle area detection processing. To do. Here, the reduced background grayscale image data includes image data in which the background grayscale image data stored in the SRAM 243 is subjected to fisheye correction processing and equalization processing by the fisheye correction scaler circuit 248, and is used for circular area detection processing. Previously stored in SRAM 243.

Next, the image recognition DSP circuit 242 binarizes the generated background subtraction image. Then, as shown in FIG. 29, template matching is performed on the binary background subtraction image G3 using the binary outer shape template T1 showing the outer shape of the medal. That is, the image recognition DSP circuit 242 specifies where a region similar to the outer shape template T1 exists in the background subtraction image G3. In other words, the image recognition DSP circuit 242 specifies where in the background subtraction image G3 there is a region that matches the outer shape of the medal indicated by the outer shape template T1. The outer shape template T1 is stored in the flash memory 244 in advance.

In template matching, the outline template T1 is moved little by little (for example, one pixel at a time) in the raster scan direction on the background subtraction image G3. In other words, the image recognition DSP circuit 242 raster-scans the outline template T1 on the background subtraction image G3. At this time, the image recognition DSP circuit 242 generates an AND image of the outer shape template T1 and the partial region of the background subtraction image G3 that overlaps the outer shape template T1 at each position of the outer shape template T1. As a result, a plurality of binary AND images are generated. Then, the image recognition DSP circuit 242 has background subtraction of the external template T1 used in the generation of the AND image having the largest number of pixels (high-luminance pixels) having a pixel value of "1" among the generated plurality of AND images. Identify the position on image G3. This position is a position in the background subtraction image G3 where a region similar to the outer shape template T1 exists.

Then, the image recognition DSP circuit 242 detects a partial region in the acquired reduced image data existing at the same position as the specified position as a circular region. In other words, the image recognition DSP circuit 242 detects a partial area in the reduced image data that overlaps with the outer shape template T1 as a circular area when the outer shape template T1 is placed in the reduced image data at the same position as the specified position. .. At this time, in the partial region, the circle region may be the one in which the pixel value of each pixel outside the circle indicated by the outer shape template T1 is zero. The circular region extracted by the image recognition DSP circuit 242 is a grayscale image. In the present embodiment, the outer shape of the circular region is a quadrangle, but other shapes such as a circle may be used.

In addition, another method may be adopted as a method of extracting a circle area from the acquired reduced image data. For example, an extraction method utilizing the fact that the outer shape of the medal is circular may be adopted. In this extraction method, first, edge detection is performed on the acquired reduced image data to generate an edge image. As a method for generating an edge image, for example, the Sobel method, the Laplacian method, the Canny method, or the like is used. Next, a circular region is extracted from the generated edge image. As a method for extracting a circular region, for example, a Hough transform is used. Then, the circular region in the acquired reduced image data existing at the same position as the position of the circular region in the edge image is defined as the circular region.

Further, an extraction method of extracting a circular region from the reduced image data acquired by using the background subtraction method and labeling may be adopted. In this extraction method, first, a background subtraction image showing the difference between the acquired reduced image data and the reduced background grayscale image data is generated, and the generated background subtraction image is binarized. Then, labeling such as 4-linking is performed on the binary background subtraction image. Then, in the binary background subtraction image, a partial area of the acquired reduced image data existing at the same position as the position of the connected area (independent area) obtained as a result of labeling is defined as a circular area.

(2) Filter processing The image recognition DSP circuit 242 performs filter processing after the circular region detection processing. The filtering process includes a 3σ correction process and a non-linear diffusion filter process.
First, in the 3σ correction process, the image recognition DSP circuit 242 cuts out the image data of the circular region in the acquired reduced image data based on the circular region detected by the circular region detection process. Hereinafter, the cut out image data may be referred to as a circular region image data.

Next, the image recognition DSP circuit 242 creates a normal distribution (see FIG. 30) centered on the average value of the data in a certain range with respect to the luminance value in the cut out circular region image data. Here, 3σ is three times the standard deviation, and almost all data belong within the range of the mean value ± 3σ (when the variation is a normal distribution, 99.7% of the data is within this range. It belongs to).
Then, the brightness of the pixel whose brightness value is smaller than -3σ, for example, the brightness of the pixel of -4σ is replaced with the brightness value of -3σ. Further, the brightness of a pixel whose brightness value is larger than 3σ, for example, the brightness of a pixel having a brightness value of 4σ is replaced with the brightness value of 3σ. By doing so, it is possible that pixels with extremely large brightness values (pixels that are too bright) and pixels with extremely small brightness values (pixels that are too dark), which are irregular data, affect the subsequent processing. It can be suppressed.

Next, the image recognition DSP circuit 242 performs nonlinear diffusion filter processing on the circular region image data after 3σ correction processing to create an edge image X in the X (vertical) direction and an edge image Y in the Y (horizontal) direction. To do.

FIG. 31A schematically shows the circular region image data after the 3σ correction process. In FIG. 31A, one square of the grid represents a pixel. Further, FIG. 31B shows the coefficient for edge image X. Here, when the brightness values of the pixels A1 to A8 and P of FIG. 31A are a1 to a8 and p, respectively, the brightness value of the pixel of interest P in the edge image X is described below using the coefficient for the edge image X. It is calculated by the formula 4 of.
Luminance of P (PX) = a1 × (-3) + a2 × 0 + a3 × 3 + a4 × (-10) + p × 0 + a5 × 10 + a6 × (-3) + a7 × 0 + a8 × 3 ... Equation (4)

The image recognition DSP circuit 242 creates an edge image X by calculating the brightness of all the pixels of the circular region image data after the 3σ correction process using the above equation 4.

FIG. 31C shows the coefficient for edge image Y. Here, when the brightness values of the pixels A1 to A8 and P of FIG. 31A are a1 to a8 and p, respectively, the brightness value of the pixel of interest P in the edge image Y is as follows using the coefficient for the edge image Y. It is calculated by the formula 5 of.
Luminance of P (PY) = a1 × (-3) + a2 × (-10) + a3 × (-3) + a4 × 0 + P × 0 + a5 × 0 + a6 × 3 + a7 × 10 + a8 × 3 ... Equation (5)

The image recognition DSP circuit 242 creates an edge image Y by calculating the brightness of all the pixels of the circular region image data after the 3σ correction process using the above equation 5.

After creating the edge image X and the edge image Y, the image recognition DSP circuit 242 creates the edge image XY from both images. The brightness PXY of each pixel in the edge image XY is calculated by the following equation 6 when the value of the brightness of the pixel in the edge image X is PX and the value of the brightness of the pixel in the edge image Y at the same position is PY. be able to.

The image recognition DSP circuit 242 creates an edge image XY by calculating the brightness PXY using the above equation 6 for all the pixels of the edge image X and the edge image Y, and stores the created edge image XY in the SRAM 243. Let me.
The various determination processes performed by the image recognition DSP circuit 242 will be described later.

<Image recognition accelerator circuit>
The image recognition accelerator circuit 249 performs a process related to the gradient average image data and a process related to the edge gradient image.

[Processing related to gradient average image data]
The processing related to the gradient average image data includes a rotation image generation process, a gradient average image data generation process, and a gradient average image template generation process.

(1) Rotation image generation processing In the rotation image generation processing, the image recognition accelerator circuit 249 acquires an edge image XY from SRAM 243 and rotates the acquired edge image XY in 1 degree units to obtain a 360 degree rotation image. Generate.

(2) Gradient average image data generation processing In the gradient average image data generation processing, the image recognition accelerator circuit 249 cumulatively adds (superimposes) 360-degree rotated images generated by the rotating image generation processing, and gradient averaging. Generate image data. As an example of the gradient average image data, the gradient average image data of the regular medal shown in FIG. 32A is shown in FIG. 32B. Then, the image recognition accelerator circuit 249 stores the generated gradient average image data in the SRAM 243.

(3) Gradient Average Image Template Generation Process The gradient average image template generation process is a process of generating a gradient average image template which is image data used in the determination process of the image recognition DSP circuit 242 described later.

In the gradient averaging image template generation process, the image recognition accelerator circuit 249 compares the gradient averaging image data of 50 (that is, related to 50 medals) stored in the SRAM 243 with each other and matches or is similar to a certain degree. Gradient Average image data to be grouped. Next, the image recognition accelerator circuit 249 selects the top four groups in descending order of the number of gradient average image data to which the image recognition accelerator circuit 249 belongs. Then, for each of the top four selected groups, any one gradient average image data is selected, and the four gradient average image data are used as the gradient average image template in the storage area for storing the gradient average image template of SRAM 243. Remember. For each of the top four selected groups, instead of selecting any one gradient average image template, the average value of the gradient average image data belonging to the same group (average value of the brightness of each pixel). May generate a gradient mean image template by calculating. Further, the gradient average image template stored in the SRAM 243 may be deleted by an initialization process (not shown) of the host controller 241 when the power of the game machine is turned on.

By generating the gradient average image template as described above, for example, when two types of medals with different markings (patterns) on the front and back are used as regular medals, 50 of these regular medals are inserted after the power is turned on. By doing so, it is possible to generate up to four types of gradient average image templates related to the front and back of these two types of medals. If the 50 regular medals inserted after the power is turned on are one type, two types of gradient average image templates related to the front and back of the regular medals are generated, and the gradient average image template comparison process described later is performed. In, two types of gradient average image templates generated are used.

Here, in the gradient average image template generation process, when the gradient average image template is not stored in the storage area of the SRAM 243, the number of medals inserted after the power is turned on reaches the specified initial number of inserted medals, 50 in the present embodiment. It is performed using the gradient average image data of. The image recognition accelerator circuit 249 stores the generated gradient average image data in the gradient average image template generation data storage area of SRAM 243 until the number of gradient average image data generated in the gradient average image data generation process reaches 50. Further, the image recognition accelerator circuit 249 performs a gradient averaging image template generation process when 50 gradient averaging image data are stored in the gradient averaging image template generation data storage area of SRAM 243. The image recognition accelerator circuit 249 stores the gradient average image data generated by the gradient average image data generation process in the determination target gradient average image data storage area of the SRAM 243 after the gradient average image template generation process is executed. In this embodiment, when 50 gradient average image data are stored in SRAM 243, a mode in which gradient average image data that match or are similar to a certain degree is grouped to generate a gradient average image template has been described. However, not limited to this, each time the gradient average image data is generated, the gradient average image data stored earlier is compared, and the gradient average image data that matches or is similar to a certain degree is grouped and the gradient average is obtained. You may generate an image template.

[Processing related to edge gradient image]
The processing related to the edge gradient image includes a polar coordinate conversion processing, a Scharr conversion processing, a HOG conversion processing, and a HOG template generation processing.

(1) Polar Coordinate Conversion Process In the polar coordinate conversion process, the image recognition accelerator circuit 249 acquires an edge image XY from SRAM 243, converts the orthogonal coordinates of the acquired edge image XY into polar coordinates, and creates polar coordinate image data. Specifically, the image recognition accelerator circuit 249 expresses the Cartesian coordinates (x, y) of each pixel of the edge image XY by the length r of the moving diameter and the angle φ from the reference position (r, φ). ). The relationship between polar coordinates (r, φ) and Cartesian coordinates (x, y) is expressed by the following equations 7 and 8.
x ＝ r cos (φ) ・ ・ ・ Equation (7)
y ＝ r sin (φ) ・ ・ ・ Equation (8)

Then, the image recognition accelerator circuit 249 stores the created polar coordinate image data in the SRAM 243.

(2) Scharr conversion process In the Scharr conversion process, the image recognition accelerator circuit 249 acquires polar coordinate image data from SRAM 243 and creates an edge polar coordinate image X in the X (vertical) direction and an edge polar coordinate image Y in the Y (horizontal) direction. To do. Therefore, the image recognition accelerator circuit 249 that performs the Scharr conversion process constitutes a directional image separating means that separates the polar coordinate image into a vertical image and a horizontal image.
Since the mode of creating the edge polar coordinate image X and the edge polar coordinate image Y in the Scharr conversion process is the same as the mode of creating the edge image X and the edge image Y in the above-described nonlinear diffusion filter process, the coefficients used are the same. The description is omitted here.

(3) HOG conversion processing In the HOG conversion processing, the image recognition accelerator circuit 249 creates an edge gradient image and performs HOG conversion on the created edge gradient image. Here, the HOG (Histograms of Oriented Gradients) transformation is to make a histogram of the gradient direction of the brightness of a local region (cell) in the image data, and for image matching accompanied by the HOG transformation, a local shape change (local shape change (cell)). It is strong against geometric transformation) and is not easily affected by fluctuations in lighting.

Specifically, an edge gradient image is created from the edge polar coordinate image X and the edge polar coordinate image Y created by the Scharr conversion process. The brightness of each pixel in the edge gradient image, that is, the gradient intensity, is calculated by the following equation 9 when the brightness value of the pixel in the edge pole coordinate image X is QX and the brightness value of the pixel in the edge pole coordinate image Y at the same position is QY. Can be calculated by.

Further, the gradient angle of each pixel in the edge gradient image can be calculated by the following equation 10.
Gradient angle = tan ^-1 (QY / QX) ... Equation (10)

FIG. 33 schematically shows the created edge gradient image G4. The image recognition accelerator circuit 249 creates a histogram of the brightness gradient direction in the local region for each local region, using the rectangular frame S indicated by the alternate long and short dash line in the created edge gradient image G4 as a local region (cell). .. Then, the created histogram set is stored in SRAM 243.

[HOG template generation process]
The HOG template generation process is a process for generating a HOG template used in the determination process of the image recognition DSP circuit 242 described later.

In the HOG template generation process, the image recognition accelerator circuit 249 compares 50 sets of histogram sets (that is, related to 50 medals) stored in SRAM 243 with each other, and sets of histograms that match or are similar to a certain degree. To group. Next, the image recognition accelerator circuit 249 selects the top four groups in descending order of the number of histogram sets to which they belong. Then, for each of the top four selected groups, an arbitrary set of histograms is stored as a HOG template in the storage area for storing the HOG template of SRAM 243. For each of the top four selected groups, instead of selecting any one set of histograms, the average value of the set of histograms belonging to the same group (the average value of the gradient intensity in the same local region) is calculated. By doing so, a HOG template may be generated. Further, in the present embodiment, when 50 sets of histogram sets are stored in SRAM 243, the stored histogram sets are compared with each other, and a set of histograms that match or are similar to a certain degree are grouped to generate a HOG template. Aspects have been described. However, the present invention is not limited to this, and each time a set of histograms is generated, a set of histograms stored in advance may be compared, and a set of histograms that match or are similar to a certain degree may be grouped to generate a HOG template. ..

By generating the HOG template as described above, for example, when two types of medals having different markings (patterns) on the front and back are used as regular medals, and the HOG template is stored in the storage area of SRAM 243. If not, by inserting 50 of these regular medals after turning on the power, it is possible to generate four types of HOG templates related to the front and back of these two types of medals. If the HOG template is not stored in the storage area of SRAM 243 and there is only one type of 50 regular medals inserted after the power is turned on, two types of HOG related to the front and back of the regular medals. A template is generated, and in the HOG template comparison process described later, the two types of generated HOG templates are used.

The match or similarity of the histogram set is determined by comparing the histograms for the same position (local regions at the same position in the edge gradient image) in the histogram set. In addition, the criteria for judgment can be set as appropriate. For example, it may be determined that both histogram sets match, provided that all histograms match perfectly. Further, it may be determined that both histogram sets are similar on condition that there is no histogram in which the degree of agreement is less than a predetermined degree, for example, 80% or less.

Here, the HOG template generation process is performed using a set of histograms related to the edge gradient image until the number of medals inserted after the power is turned on reaches the specified initial number of inserted medals, or 50 medals in the present embodiment. The image recognition accelerator circuit 249 stores the created histogram set in the HOG template generation data storage area of the SRAM 243 until the histogram set created in the HOG conversion process reaches 50 sets. Further, the image recognition accelerator circuit 249 performs the HOG template generation process when 50 sets of histogram sets are stored in the HOG template generation data storage area of the SRAM 243. After executing the HOG template generation process, the image recognition accelerator circuit 249 stores a set of histograms created by the HOG conversion process in the determination target histogram storage area of the SRAM 243.

<Judgment processing by image recognition DSP circuit>
Next, the determination process executed by the image recognition DSP circuit 242 will be described. The determination process includes a gradient average image template comparison process and a HOG template comparison process.

(1) Gradient Average Image Template Comparison Process In the gradient average image template comparison process, the image recognition DSP circuit 242 acquires the gradient average image data generated by the image recognition accelerator circuit 249 from the determination target gradient average image data storage area of the SRAM 243. ..

Next, the image recognition DSP circuit 242 calculates the difference between the acquired gradient average image data and the gradient average image template stored in the SRAM 243. Then, the image recognition DSP circuit 242 determines whether or not the gradient average image data and the gradient average image template match or are similar to a predetermined degree based on the calculated difference value and the threshold value for marking determination. , "Yes" or "No" is stored in SRAM 243 as the determination result. In this embodiment, since a maximum of four gradient average image templates are used, a maximum of four determination results are stored in the SRAM 243. Further, in the gradient average image template comparison process, the gradient average determination result is stored in the SRAM 243. Here, when at least one "OK" is stored as the judgment result for up to four templates, "OK" is stored in the SRAM 243 as the gradient average judgment result, and "No" is stored in all. Is stored in the SRAM 243 as a gradient average determination result. Therefore, in one gradient average image template comparison process, a maximum of four determination results for a maximum of four gradient average image templates and one gradient average determination result based on these determination results are stored.

For example, the image recognition DSP circuit 242 compares the brightness of each pixel of the acquired gradient average image data and the gradient average image template (calculates the difference), and determines whether or not the brightness of these pixels matches from the difference value. Alternatively, it is determined whether the difference is within a predetermined range, and if there are a certain number of pixels that match or the difference is within a predetermined range, it is determined that the gradient average image data and the gradient average image template match or are similar to a predetermined degree. .. On the other hand, when the number of matching pixels is less than a certain number, it is determined that the gradient average image data and the gradient average image template match or are not similar to a predetermined degree.

(2) HOG template comparison processing In the HOG template comparison processing, the image recognition DSP circuit 242 acquires a set of judgment target histograms from the judgment target histogram storage area. Next, it is determined whether or not the acquired histogram set and the HOG template stored in the SRAM 243 match or are similar to a predetermined degree, and "OK" or "NO" is stored in the SRAM 243 as the determination result. In this embodiment, since a maximum of four HOG templates are used, a maximum of four determination results are stored in the SRAM 243. Further, in the HOG template comparison process, the HOG determination result is stored in the SRAM 243. Here, when at least one "OK" is stored as the judgment result for up to four templates, "OK" is stored in the SRAM 243 as the HOG judgment result, and "No" is stored in all of them. Is stored in the SRAM 243 as a HOG determination result. Therefore, in one HOG template comparison process, a maximum of four determination results for a maximum of four HOG templates and one HOG determination result based on these determination results are stored.

Since the determination of the match or similarity between the acquired histogram set and the HOG template is the same as the determination of the match or similarity between the histogram sets in the above-mentioned HOG template generation process, the description thereof will be omitted here.

As described above, the image recognition DSP circuit 242 that performs the gradient average image template comparison processing and the HOG template comparison processing constitutes a game medium determination means for determining whether or not the object passing on the medal rail 210 is a regular medal. To do.

<GPIO>
The GPIO 250 (see FIG. 18) is a device for input / output of each device connected to the medal selector 201 and the control LSI 234. Further, it is a device for input / output of the control LSI 234 and various devices constituting the medal selector 201.
For example, the medal count output PORT and the medal determination output PORT of the GPIO250 are connected to the main control circuit 91 via the door relay terminal plate 68 (the door relay terminal plate 68 is not shown in FIG. 18). .. Further, the LED control output PORT of the GPIO 250 is connected to the LED 233, and the control LSI 234 can control the lighting and extinguishing of the LED 233. Further, the notification LED control output PORT of the GPIO250 is connected to the notification LED 206c, and the control LSI 234 can control the lighting and extinguishing of the notification LED 206c. Further, the AE setting port of the GPIO 250 is connected to the CMOS image sensor 233, and the control LSI 234 can control the exposure time setting mechanism of the CMOS image sensor 233 (exposure time setting).

<Host controller>
The host controller 241 controls each device constituting the control LSI 234, for example, a medal count circuit 246, a color recognition circuit 247, a fisheye correction scaler circuit 248, an image recognition DSP circuit 242, an image recognition accelerator circuit 249, and a GPIO250.

When the host controller 241 receives the determination result of the AE determination process from the ISP circuit 245, the host controller 241 first refers to an area in the SRAM 243 that stores the value of the exposure time stage. Next, when the exposure time step is set to "25", that is, the exposure time is not set to the upper limit of 175 μsec, the exposure time setting mechanism of the CMOS image sensor 232 is set via the AE setting PORT of the GPIO250. A signal is output to instruct the exposure time to be increased by one step. Then, 1 is added to the value of the region in which the value of the exposure time stage is stored in the SRAM 243. In the present embodiment, since the initial value of the exposure time is set to 70 μsec, the initial value stored in the area where the value of the stage of the exposure time is stored is set to 10. That is, in the present embodiment, the host controller 241 of the control LSI 234 constitutes an exposure time setting means for setting the exposure time of the CMOS image sensor 232.

On the other hand, when the exposure time stage is set to "25", that is, the exposure time is set to the upper limit of 175 μsec, the host controller 241 instructs the notification LED 206c to light via the notification LED control output PORT of the GPIO250. Output the signal to Further, the host controller 241 outputs a medal abnormality signal to the main control board 71 via the medal determination output PORT of the GPIO250.
Further, the host controller 241 is pressed by an initialization switch (not shown) arranged on a switch board (not shown) provided at an arbitrary location of the medal selector 201 (for example, in the vicinity of the first board 231). Then, the step of the exposure time is set to the initial value "10", that is, the exposure time is set to 70 μsec. As a result, for example, an employee of the game hall can reset the appropriate exposure time of the CMOS image sensor 232 by pressing the initialization switch after maintaining (cleaning, etc.) the lens of the camera unit 209. Become.

Further, the host controller 241 outputs a signal related to a lighting instruction or an extinguishing instruction to the LED 233 via the GPIO 250. Further, the host controller 241 receives the determination result related to the counting process stored in the SRAM 243 via the GPIO 250, that is, "the medal has passed", "the medal has been guided to the medal shoot 202", and "abnormality". Has occurred ”, and one of the judgment results is output. Specifically, when the judgment result is "the medal has passed", the medal count signal is output from the medal count output PORT, and when "an abnormality has occurred", the medal abnormality signal is output from the medal judgment output PORT. Is output. In addition, the determination result related to the color determination process is output. Specifically, when "threshold value judgment impossible" is stored in SRAM 243 as the judgment result of the threshold value judgment processing, or when "no" is stored as the color judgment result, the medal judgment output assigned to GPIO250. A medal abnormality signal is output from PORT when a predetermined output condition is satisfied. In addition, the determination result related to the determination process by the image recognition DSP circuit 242 is output. Specifically, when the slope average determination result or the HOG determination result “No” is stored in the SRAM 243, a medal abnormality signal is output from the medal determination output PORT assigned to the GPIO250, and a predetermined output condition is set. Output when it is established.

The predetermined output conditions of each determination result can be appropriately set. For example, the determination result related to the counting process may be set as when "an abnormality has occurred" is stored in the SRAM 243 as the determination result of the counting process, or continuously or most recently. It may be set when the cumulative number of predetermined determinations (for example, 50 times) in the counting process is stored as "an abnormality has occurred" for a specified number (for example, 10 times) or more. Further, the determination result of the threshold value determination process may be set as when "threshold value determination impossible" is stored in the SRAM 243 as the determination result, or continuously or in the latest threshold value determination process. It may be set when the cumulative number of predetermined determinations (for example, 50 times) is more than the specified number (for example, 10 times) and "threshold value determination impossible" is stored. Further, the color determination result of the color determination process may be set as when "No" is stored in the SRAM 243, or may be continuously or a predetermined number of determinations of the latest color determination process ( For example, it may be set when "No" is stored for a specified number (for example, 10 times) or more in the cumulative total of 50 times). Further, the gradient average determination result of the marking determination process or the HOG determination result may be set as when "No" is stored in the SRAM 243, or continuously or most recently. It may be set when the cumulative number of predetermined determinations (for example, 50 times) of the marking determination process is the specified number (for example, 10 times) or more and "No" is stored.

A backup power supply (not shown) is connected to the SRAM 243, and the contents stored in the SRAM 243 are retained for a certain period (for example, about one week) even when the power supply of the pachislot machine 1 is turned off. Further, the host controller 241 can erase various templates stored in the SRAM 243, such as a color template, a gradient average image template, and a HOG template, by an initialization switch (not shown) provided in the medal selector 201. .. Specifically, by turning on the power of the pachi-slot machine 1 while pressing the initialization switch, the area in which various templates of the SRAM 243 are stored is initialized (value of 0) during the initialization process of the host controller 241. Write), that is, delete various templates.

<Flash memory>
The flash memory 244 is required for parameters and various processes used by various devices constituting the control LSI 234, for example, a host controller 241, an image recognition DSP circuit 242, a fisheye correction scaler circuit 248, and an image recognition accelerator circuit 249. The data is stored. Further, the flash memory 244 is provided with an area for storing the value of the above-mentioned exposure time stage.

<Processing flow of control LSI>
Next, the processing performed by the control LSI 234 will be described with reference to FIG. 34. FIG. 34 is a processing flow diagram for explaining the processing performed by the control LSI 234.
As shown in FIG. 34, the control LSI 234 is roughly divided into input processing, conversion processing, color determination processing, counting processing, and marking determination processing.

<Input processing>
The input process is performed by the ISI circuit 251. In the input process, as described above, the ISI circuit 251 converts the image data transmitted from the CMOS image sensor 232 in the LVDS method into an RGB Bayer image and outputs the image data to the ISP circuit 245.

<AE correction processing>
The AE correction process is performed by the ISP circuit 245 and the host controller 241 when the power of the pachislot machine 1 is turned on. Further, the AE correction process is performed in parallel with the conversion process, the color determination process, and the count process, which will be described later.

In the AE correction process, the ISP circuit 245 determines whether or not the RGB bayer image output from the ISI circuit 251 includes an image of the ridge portion 210a (see FIG. 8) formed on the surface of the medal rail 210. Performs AE determination processing. Further, when the ISP circuit 245 determines that the output image does not include the image of the ridge portion 210a, the ISP circuit 245 outputs the determination result of this AE determination process to the host controller 241.

Further, in the AE correction process, when the determination result of the AE determination process is output from the ISP circuit 245, the host controller 241 first refers to the area in which the value of the exposure time stage is stored in the SRAM 243. Next, when the exposure time step is set to "25", that is, the exposure time is not set to the upper limit of 175 μsec, the exposure time setting mechanism of the CMOS image sensor 232 is set via the AE setting PORT of the GPIO250. A control signal is output to instruct to increase the exposure time by one step (extend by 7 μs). Then, 1 is added to the value of the region in which the value of the exposure time stage is stored in the SRAM 243.

By doing so, the image to which the ISP circuit 245 performs the AE determination process is an RGB Bayer image based on the image acquired by the CMOS image sensor 232 whose exposure time is increased by one step. The AE correction process is repeated until the IPS circuit 245 determines in the AE determination process that the image includes the image of the ridge portion 210a, or until the exposure time is set to the upper limit of 175 μsec.

When the ISP circuit 245 determines in the AE determination process that the image output from the ISI circuit 251 includes the image of the ridge portion 210a, the determination result of the AE determination process is not output to the host controller. Further, thereafter, the AE determination process is not performed on the image output from the ISI circuit 251. That is, the exposure time of the COMS image sensor 232 is set to the exposure time when the ISP circuit 245 determines that the image of the ridge portion 210a is included in the image output from the ISI circuit 251. When the ISP circuit 245 determines that the image of the ridge portion 210a is included in the image first output from the ISI circuit 251 after the power is turned on, the exposure time of the CMOS image sensor 232 is the initial value. It takes 70 μsec (step 10).

In the AE correction process, when the determination result of the AE determination process is output from the ISP circuit 245, the host controller 241 sets the exposure time stage to "25", that is, when the exposure time is set to the upper limit of 175 μsec. The host controller 241 outputs a control signal instructing the notification LED 206c to turn on via the notification LED control output PORT of the GPIO250. Further, the host controller 241 outputs a medal abnormality signal to the main control board 71 via the medal determination output PORT of the GPIO250.

In this way, when the host controller 241 outputs a control signal instructing lighting to the notification LED 206c and outputs a medal abnormality signal to the main control board 71, the exposure time is set to the upper limit value of 175 μsec. Even so, the ridge portion 210a of the medal rail 210 could not be imaged. In such a case, it is conceivable that some kind of obstacle (for example, dirt such as dust is attached to the lens) has occurred in the camera unit 209. Therefore, in this state, it is not possible to effectively detect the insertion of the game medal and the detection of fraudulent activity using the camera unit 209. Therefore, the main control circuit 91 is similar to various processes when there is fraudulent activity. Perform processing. For example, the main control circuit 91 forcibly interrupts the game, displays an error code on the 7-segment display 24, sends an error command to the sub control circuit 101, and causes an error via the sub control circuit 101. Notify (for example, display a predetermined error screen on the liquid crystal display device 11).

<Conversion process>
The conversion process is performed by the ISP circuit 245. In the conversion process, the ISP circuit 245 performs an image correction process of performing a lens distortion correction process and a projective conversion (homography) process on the RGB bayer image output from the ISI circuit 251. Next, the ISP circuit 245 performs a color conversion process of converting the corrected RGB bayer image into YUV image data and outputting the grayscale image data to the medal count circuit 246. Further, a color conversion process is performed in which the RGB bayer image is converted into HSV image data and the HSV image data is output to the color recognition circuit 247.

After the conversion process, the control LSI 234 performs a color determination process, a count process, and a stamp determination process. Since the circuits that execute each process are configured as separate circuits, these processes are executed in parallel at each feasible timing.

<Color judgment processing>
The color determination process is performed by the color recognition circuit 247. The color determination process includes a medal detection process, a threshold value determination process, a saturation / hue multiplication process, a color template generation process, and a color template comparison process.

First, the color recognition circuit 247 performs a medal detection process for determining whether or not the HSV image data output from the ISP circuit 245 includes a medal image. When it is determined that the HSV image data includes the image of the medal, the color recognition circuit 247 performs the threshold value determination process based on the HSV image data. In the threshold value determination process, if the position on the threshold graph (see FIG. 21) based on the average saturation value and the average hue value is within the allowable region, the color determination process is continued. On the other hand, in the case of the non-allowable area, "threshold value determination impossible" is stored in SRAM 243 as a determination result, and the color determination process is terminated.

After the threshold value determination process, the color recognition circuit 247 performs a saturation / hue multiplication process to create color determination data. Then, the created color determination data is compared with the color template, it is determined whether or not they match or are similar to a predetermined degree, and the determination result is stored in the SRAM 243.

Since the color template is not generated until the number of medals inserted after the power is turned on reaches the specified initial number of medals, 50 in the present embodiment, the color template comparison process is not executed.

Further, in the color recognition circuit 247, when the number of medals inserted after the power is turned on reaches 50, which is the specified initial number of inserted medals, and the number of color determination data stored in the color determination data storage area reaches 50, that is, 50 medals. When the color determination data related to the medal is created, the color template generation process is executed.

<Count processing>
The counting process is performed by the medal counting circuit 246. The counting process includes a medal detection process and an order determination process. The medal image detection process and the medal position detection process described above correspond to the medal detection process. In the medal detection process, the medal counting circuit 246 determines whether or not the grayscale image data output from the ISP circuit 245 includes a medal image. Further, it is determined whether or not the medal image exists in the predetermined determination area in the grayscale image data output from the ISP circuit 245, and the determination results (“IN”, “OUT”, “ON”, “OFF”) are determined. Data) is stored in SRAM 243.

In the order determination process, the medal count circuit 246 transitions “IN”, “OUT”, “ON”, and “OFF” data for each determination area in a predetermined number of grayscale image data arranged in time series. It is determined whether or not the aspect of is consistent with the aspect of the predetermined transition. Then, as the determination result, either "the medal has passed", "the medal has been guided by the medal shoot 202", or "an abnormality has occurred" is stored in the SRAM 243. Further, when the SRAM 243 stores that "the medal has passed", the host controller 241 outputs a medal count signal from the medal count output PORT assigned to the GPIO 250. Based on this medal count signal, the main control circuit 91 detects that medals have been inserted and counts the number of inserted medals or the number of credits. That is, in the present embodiment, the medal counting circuit 246 that performs the order determination process constitutes a passage determination means that determines whether or not an object has passed through the passage based on the image data obtained via the image pickup means.

<Engraving judgment processing>
The marking determination processing includes fisheye correction processing and equalization processing performed by the fisheye correction scaler circuit 248, and circular area detection processing, filter processing, gradient average image template comparison processing, and HOG template comparison performed by the image recognition DSP circuit 242. Processing is included. Further, the rotation image generation process, the gradient average image data generation process, the gradient average image template generation process, the polar coordinate conversion process, the Scharr conversion process, the HOG conversion process, and the HOG template generation process performed by the image recognition accelerator circuit 249 are included.

In the fisheye correction process, the fisheye correction scaler circuit 248 acquires grayscale image data from SRAM 243 and performs fisheye correction processing for correcting the acquired grayscale image data. Next, in the equalization process, the fisheye correction scaler circuit 248 performs the equalization process on the grayscale image data that has undergone the fisheye correction process, creates reduced image data, and stores it in the SRAM 243.

When it is determined in the counting process that the medal has passed on the medal rail 210, the host controller 241 instructs the image recognition DSP circuit 242 and the image recognition accelerator circuit 249 to execute the processing after the circular area detection processing in the marking determination processing. To do.

In the circle area detection process, the image recognition DSP circuit 242 acquires the reduced image data from the SRAM 243 and detects the circle area from the reduced image data. Further, in the filter processing, the image recognition DSP circuit 242 performs a non-linear diffusion filter processing on the detected circular region to create an edge image XY, which is stored in the SRAM 243.

Next, in the rotation image generation process, the image recognition accelerator circuit 249 acquires the edge image XY from the SRAM 243 and generates a rotation image for 360 degrees from the edge image XY. Further, in the gradient average image data generation process, the image recognition accelerator circuit 249 cumulatively adds (superimposes) 360-degree rotation images to generate gradient average image data, and stores the gradient average image data in SRAM 243. Let me. The image recognition accelerator circuit 249 stores the gradient average image data in the data storage area for generating the gradient average image template before generating the gradient average image template, and after generating the gradient average image template, the determination target. Stored in the gradient average image data storage area.

Next, in the gradient average image template comparison process, the image recognition DSP circuit 242 determines whether or not the gradient average image data to be determined and the gradient average image template match or are similar to each other to a predetermined degree, and the determination result is transmitted to SRAM 243. Remember. Here, if the gradient average image template is not generated when the gradient average image template comparison process is executed (in the present embodiment, the number of medals inserted after the power is turned on is less than 50), the gradient average image template No comparison process is performed.

As described above, at the timing when the number of medals inserted after the power is turned on reaches the specified initial number of inserted 50 medals and 50 gradient average image data are stored in the gradient average image data generation data storage area of SRAM 243. , The image recognition accelerator circuit 249 performs the gradient average image template generation process.

Further, in parallel with the rotation image generation process, the image recognition accelerator circuit 249 performs a polar coordinate conversion process. In the polar coordinate conversion process, the edge image XY is acquired from the SRAM 243, the orthogonal coordinates of the acquired edge image XY are converted into polar coordinates, the polar coordinate image data is created, and the polar coordinate image data is stored in the SRAM 243.

Next, in the Scharr conversion process, the image recognition accelerator circuit 249 acquires polar coordinate image data from SRAM 243 and performs nonlinear diffusion filter processing to create an edge polar coordinate image X and an edge polar coordinate image Y.

Next, in the HOG conversion process, the image recognition accelerator circuit 249 creates an edge gradient image based on the edge polar coordinate image X and the edge polar coordinate image Y, performs HOG conversion on the created edge gradient image, and performs HOG conversion for each local region. Create a histogram of the gradient direction of the brightness inside. Then, the created histogram set is stored in SRAM 243. The image recognition accelerator circuit 249 stores the histogram set in the data storage area for HOG template generation before the HOG template is generated, and stores it in the determination target histogram storage area after the HOG template is generated.

Next, in the HOG template comparison process, the image recognition DSP circuit 242 determines whether or not the set of histograms to be determined and the HOG template stored in the SRAM 243 match or are similar to a certain degree. Then, the determination result is stored in the SRAM 243. If the HOG template is not generated (in the present embodiment, the number of medals inserted after the power is turned on is less than 50), the HOG template comparison process is not executed.

As described above, when the number of medals inserted after the power is turned on reaches 50 and 50 sets of histogram sets are stored in the HOG template generation data storage area of SRAM 243, the image recognition accelerator circuit 249 sets the HOG. Perform template generation processing.

<Timing of control LSI processing>
Next, with reference to FIG. 35, the timing of various processes performed by the control LSI 234 will be described.
FIG. 35 shows the relationship of processing in the host controller 241, the ISP circuit 245, the medal counting circuit 246, and the color recognition circuit 247, which are the devices constituting the control LSI 234, in chronological order. The relatively thick line portion in the line extending below each device name indicates that the device is in the state of performing the various processes described above.

Also, the dashed arrows between the lines corresponding to each device indicate the signals input and output between each device. Further, the broken line arrow between the line extending below "IN" and the line extending below "OUT" in the host controller indicates the signal detected by the host controller 241 and the signal output from the host controller 241. It shows the correspondence with.
The AE correction process performed by the host controller 241 and the ISP circuit 245 is not shown.

First, when the CMOS image sensor 232 (see FIG. 17) outputs the image data to the control LSI 234, the ISP circuit 245 acquires the image data via the ISI circuit 251 and VSYNC (Vertical Synchronization) interrupt signal # 0 (1IH). ) Is output to the host controller 241. Further, the ISP circuit 245 performs a conversion process for converting the RGB bayer image into various formats. Then, the grayscale image data and the HSV image data are output to the SRAM 243, the medal count circuit 246, and the color recognition circuit 247. The detailed description of the conversion process will be omitted because it has been described above.

When the VSYNC interrupt signal # 0 is input, the host controller 241 outputs a start request signal (1HC, 1HM) to the color recognition circuit 247 and the medal count circuit 246 after a lapse of a predetermined time. It should be noted that this predetermined time is set longer than the time required for the conversion process in the ISP circuit 245 based on experiments and simulations.

When the start request signal is input, the color recognition circuit 247 also performs color determination processing on the HSV image data output from the ISP circuit 245, stores the determination result in the SRAM 243, and makes the color determination in the host controller 241. Outputs an interrupt signal (1CH). The detailed description of the color determination process will be omitted because it has been described above.

When the start request signal is input, the medal count circuit 246 performs a count process based on the data output from the ISP circuit 245, stores the determination result in the SRAM 243, and stores the medal count in the host controller 241. An input signal (1 MH) is output. The detailed description of the counting process will be omitted because it has been described above.

When the host controller 241 detects the color determination interrupt signal and the count interrupt signal, the host controller 241 acquires the determination result of the count process from the SRAM 243. Then, as a determination result, it is determined whether or not any one of "the medal has passed", "the medal has been guided by the medal shoot 202", and "an abnormality has occurred" is stored. If none of these are stored, the host controller 241 omits the process of outputting the determination result to the main control board 71 (main control circuit 91) via the GPIO 250. Here, in the present embodiment, as described above, in the order determination process of the count process, it is necessary to store the mode of data transition in each determination area of the plurality of grayscale image data on the SRAM 243. The process of outputting the determination result to the main control board 71 is omitted until at least the number of grayscale image data received by the medal count circuit 246 reaches a predetermined number (14 or 4 when the medal cannot be inserted). In some cases.

Regarding the processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signals # 1 to 4 (2IH to 5IH) shown in FIG. 35, the above-mentioned input of the VSYNC interrupt signal # 0 (1IH) ) Is the same as the processing timing and signal input / output of each device, so the description will be omitted here.

Next, the processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signal #n (nIH), which is the nth VSYNC interrupt signal after the power is turned on, will be described with reference to FIG. 35. .. The processing and signal input / output from the time when the ISP circuit 245 outputs the VSYNC interrupt signal #n to the host controller 241 (nIH) until the host controller 241 acquires the determination result of the count processing from the SRAM 243. The description of the above description will be omitted here because it is the same as the processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signal # 0 (1IH) described above.

When the host controller 241 stores any one of "the medal has passed", "the medal has been guided to the medal shoot 202", and "an abnormality has occurred" as the determination result of the counting process, The determination result and the determination result of the color determination process are acquired from the SRAM 243, and these determination results are output to the allocation PORT of the GPIO250 (nHG). That is, the host controller 241 outputs the determination result of the count determination process and the determination result of the color determination process to the main control board 71 (main control circuit 91) via the GPIO 250. In addition, there may be a plurality of determination results of the color determination process output here.

Further, when the determination result of the count process is "passed medals", the host controller 241 relates to each medal up to the specified initial number of medals inserted into the game machine, or 50 medals in the present embodiment. In order to generate the color determination data, the color recognition circuit 247 is instructed to generate the color determination data using the HSV image data before a predetermined time. Further, the host controller 241 instructs the image recognition DSP circuit to perform preprocessing using the reduced image data before a predetermined time.

Further, the host controller 241 deletes the determination result output to the main control board 71 from the SRAM 243.

When the determination result of the count process is "medals have passed", the main CPU 93 of the main control circuit 91 detects the medal count signal output from the medal count output PORT of the GPIO250 and determines the number of inserted medals. 1 is added to the value of the input number counter, which is a counter provided for the main CPU 93 to count. When the value of the inserted number counter is the maximum value (for example, 3), 1 is added to the value of the credit counter, which is a counter provided for the main CPU 93 to count the number of credited medals. When the credit counter has a maximum value (for example, 50), the main control circuit 91 sets the medal solenoid 208 of the medal selector 201 to the OFF state. As a result, the select plate 207 is positioned at the "discharging position", medals cannot be inserted, and the medals inserted after the credit counter reaches the maximum value are guided to the medal shoot 202 and the medal tray is inserted from the medal payout exit 32. Discharge to unit 34. In the present embodiment, when the start lever is operated when the value of the input number counter is a specified value (for example, 2 or 3), the main CPU 93 performs the above-mentioned internal lottery process.

Further, when the judgment result of the color judgment process is "threshold judgment impossible", when the color judgment result is "no", or when the count judgment result is "abnormality has occurred", the medal judgment output of GPIO250 The medal abnormality signal (Judgment in FIG. 35) output from the PORT when a predetermined output condition is satisfied causes the main control circuit 91 to misunderstand that a regular game medium is used in the game machine and perform the game. Detect that there was cheating. Then, various processes are performed when there is a fraudulent act. Here, various processes when there is a fraudulent act include, for example, the main control circuit 91 forcibly interrupting the game, displaying an error code on the 7-segment display 24, and making an error on the sub control circuit 101. This is a process of transmitting a command and notifying the fact that a fraudulent activity has occurred (for example, displaying the fact that the fraudulent activity has occurred on the liquid crystal display device 11) via the sub-control circuit 101.

Next, with reference to FIG. 36, the timing of other processing performed by the control LSI 234 will be described.
FIG. 36 shows the relationship of processing in the host controller 241, the ISP circuit 245, the fisheye correction scaler circuit 248, the image recognition DSP circuit 242, and the image recognition accelerator circuit 249, which are the devices constituting the control LSI 234, in chronological order. .. Since the meanings of the various notations in FIG. 36 are the same as those in FIG. 35, description thereof will be omitted here. Further, FIG. 36 shows the timing of processing after the VSYNC interrupt signal #m, which is the mth VSYNC interrupt signal after the power is turned on, is output from the ISP circuit 245.

First, when the CMOS image sensor 232 (see FIG. 17) outputs the image data to the control LSI 234, the ISP circuit 245 acquires the image data via the ISI circuit 251 and VSYNC (Vertical Synchronization) interrupt signal #m (1IH). ) Is output to the host controller 241. Further, the ISP circuit 245 performs a conversion process for converting the RGB bayer image into various formats. Then, the grayscale image data is stored in the SRAM 243. The detailed description of the conversion process will be omitted because it has been described above.

When the VSYNC interrupt signal #m is input, the host controller 241 detects the end of the conversion process of the ISP circuit 245, and at the timing when the conversion process is completed, the fisheye correction scaler circuit 248 receives a start request signal (1HG). Is output. It should be noted that this predetermined time is set longer than the time required for the conversion process in the ISP circuit 245 based on experiments and simulations.

When the start request signal is input, the fisheye correction scaler circuit 248 acquires grayscale image data from SRAM 243, performs fisheye correction processing and equalization processing, stores the created reduced image data in SRAM 243, and also stores the created reduced image data in SRAM 243. The reduction end interrupt signal (1GH) is output to the host controller 241. The detailed description of the fisheye correction process and the equalization process will be omitted because they have been described above.

The host controller 241 outputs the determination result of the count process that "the medal has passed" to the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interruption signal. Is input to the image recognition DSP circuit 242 as a signal (1HD) instructing the start of preprocessing. It should be noted that, as a condition for instructing the start of the preprocessing, the determination result of the color determination process output to the main control circuit 91 is "threshold determination impossible" or does not match or resemble any of the four color templates to a predetermined degree. It may be added to the condition that it is not included, that is, it includes a determination result that it matches or is similar to any color template to a certain extent.

The image recognition DSP circuit 242 performs preprocessing when the above signal is input from the host controller 241. As described above, the pre-processing comprises a circular area detection process and a filter process, the edge image XY created in the pre-process is stored in the SRAM 243, and the pre-process end interrupt signal (1DH1) is output to the host controller 241. The detailed description of the preprocessing will be omitted because it has been described above.

When the preprocessing completion interrupt signal is input, the host controller 241 outputs a signal (1HA) instructing the start of the correction process to the image recognition accelerator circuit 249. Here, the correction processing is the rotation image generation processing, the gradient average image data generation processing, the polar coordinate conversion processing, the Scharr conversion processing, and the HOG conversion processing described above. The detailed description of these processes will be omitted because they have been described above.

The image recognition accelerator circuit 249 performs correction processing when the above signal is input from the host controller 241. Then, when the generated gradient average image data has already been generated, the gradient average image template is stored in the determination target gradient average image data storage area of the SRAM 243, while the gradient average image template has not been generated yet. Is stored in the data storage area for generating the gradient average image template. Further, the generated histogram set is stored in the determination target histogram storage area of SRAM 243 when the HOG template has already been generated, while in the data storage area for HOG template generation when the HOG template has not been generated yet. Remember.

Next, the image recognition accelerator circuit 249 outputs a correction processing end interrupt signal (1AD) to the image recognition DSP circuit 242 when the gradient average image template and the HOG template have already been generated. On the other hand, when the gradient average image template and the HOG template have not been generated yet, the process of outputting the correction process end interrupt signal to the image recognition DSP circuit 242 is omitted. When 50 gradient average image data are stored in the gradient average image data generation data storage area of SRAM 243, the image recognition accelerator circuit 249 performs the gradient average image template generation process. Further, the image recognition accelerator circuit 249 performs the HOG template generation process when 50 sets of histogram sets are stored in the HOG template generation data storage area of the SRAM 243.

When the correction processing end interrupt signal is input, the image recognition DSP circuit 242 performs the marking determination processing. The marking determination process here includes a gradient average image template comparison process and a HOG template comparison process. Specifically, the image recognition DSP circuit 242 acquires the gradient average image data from the determination target gradient average image data storage area of the SRAM 243 and performs a gradient average image template comparison process for comparison with the gradient average image template. Then, the determination result of the gradient average image template comparison process is stored in the SRAM 243. In addition, a set of histograms is acquired from the determination target histogram storage area of SRAM 243, and a HOG template comparison process for comparison with the HOG template is performed. Then, the determination result of the HOG template comparison process is stored in the SRAM 243. After that, the image recognition DSP circuit 242 outputs the marking determination end interrupt signal (1DH2) to the host controller 241.

When the marking determination end interrupt signal is input, the host controller 241 acquires the gradient averaging determination result and the HOG determination result as the determination results of the marking determination process stored in the SRAM 243. Further, when the host controller 241 stores "No" as the acquired gradient average determination result, or when "No" is stored as the HOG determination result, when the above-mentioned predetermined output condition is satisfied. In addition, a medal abnormality signal (Judient in FIG. 36) is output from the medal determination output PORT of the GPIO250 to the main controller 91 (1HG). That is, the host controller 241 outputs the determination result of the marking determination process to the main control board 71 (main control circuit 91) via the GPIO 250. Further, the host controller 241 deletes the determination result of the marking determination process output to the main control board 71 from the SRAM 243. In the present embodiment, the output of the determination result of the color determination process to the main control circuit 91 and the output of the determination result of the marking determination process to the main control circuit 91 are assigned to the same output PORT of the GPIO250. Not limited to this, it may be assigned to different output PORTs. In this case, the main control circuit 91 can determine whether the medal abnormality signal is based on the determination result of the color determination process or the medal abnormality signal based on the determination result of the marking determination process.

The main control circuit 91 misidentifies that a regular game medium is used for the game machine when either the input judgment result of the marking judgment process, that is, the gradient average judgment result or the HOG judgment result is "No". Detect that there was a fraudulent act of playing a game. Then, various processes are performed when there is a fraudulent act. Here, various processes when there is a fraudulent act include, for example, the main control circuit 91 forcibly interrupting the game, displaying an error code on the 7-segment display 24, and making an error on the sub control circuit 101. This is a process of transmitting a command and notifying the fact that a fraudulent activity has occurred (for example, displaying the fact that the fraudulent activity has occurred on the liquid crystal display device 11) via the sub-control circuit 101.

In FIG. 36, the above-mentioned VSHYC # m is used as an opportunity for various processes triggered by VSYNC # m + 1, VSYNC # m + 2, VSYNC # m + 3, VSYNC # m + 4, VSYNC # m + 5, VSYNC # m + 6, following VSYNC # m. For the same processing as the various processing, the various signals output according to the processing are designated by a reference numeral for changing only the first digit, and detailed description thereof will be omitted.

Here, after the process of outputting the reduction end interrupt signal (2GH, 3GH, 4GH, 6GH) from the fisheye correction scaler circuit 248 to the host controller 241, the preprocessing is started from the host controller 241 to the image recognition DSP circuit 242. The process of outputting the signal instructing is not performed.

This is because the host controller 241 determines the determination result of the count process that "the medal has passed" in the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interrupt signal. This is because it is not output. In this example, the host controller 241 "passes the medal" in the main control circuit 91 between the time when the reduction end interrupt signal related to 4GH is input and the time when the reduction end interrupt signal related to 5GH is input. The judgment result of the count process is output. Therefore, after the reduction end interrupt signal related to 5GH is input, the host controller 241 outputs a signal (2HD) instructing the image recognition DSP circuit 242 to start the preprocessing.

Further, in the present embodiment, it is preferable that the engraving determination process is performed on all the inserted medals. However, when the host controller 241 outputs a signal instructing the start of preprocessing to the image recognition DSP circuit 242, the host controller 241 confirms whether or not the image recognition DSP circuit 242 or the image recognition accelerator circuit 249 is processing (busy state). However, if any of them is being processed, the signal may not be output, and if none of them are being processed, the signal may be output. In this case, the engraving determination process is performed intermittently for the medals that are continuously inserted. For example, when three medals are inserted in succession, the stamp determination process is performed on the first and third medals.

The processing timing of each device in the control LSI 234 shown in FIGS. 35 and 36 is merely an example. Regular medal discrimination processing can be performed at various processing timings according to the processing capacity, processing content, and processing procedure of each device.

<First action>
In the pachislot machine 1 of the present embodiment, the result of the color determination process based on the image data output from the CMOS image sensor 232 performed by the color recognition circuit 247 is "threshold value determination impossible" or matches any of the four color templates. Or, if the color of the inserted medal does not match the color of the regular medal, the main control circuit 91 indicates that the game machine uses a regular game medium. Detects that there was a fraudulent act of misidentifying and playing a game.

Further, when the result of the counting process based on the image data output from the CMOS image sensor 232 is "an abnormality has occurred", the main control circuit 91 causes the gaming machine to misidentify that a regular gaming medium is used. Detects that there was a fraudulent act of playing a game.

Further, the result of the marking determination process (in this embodiment, the gradient average determination result or the HOG determination result) based on the image data output from the CMOS image sensor 232 performed by the image recognition DSP circuit 242 is "No". In that case, that is, when the engraving of the inserted medal and the engraving of the regular medal are different, the main control circuit 91 misleads the gaming machine to misunderstand that a regular game medium is used, and indicates that there was a fraudulent act of playing the game. Detect.

Therefore, the main control circuit 91 performs fraudulent acts performed by inserting a special instrument into the medal slot, and fraudulent acts performed using medals having the same diameter as the regular medals but different in color and engraving (pattern). It can be detected with high accuracy.

Then, when it is detected that there has been a fraudulent activity, the main control circuit 91 forcibly interrupts the game and notifies that there has been a fraudulent activity via the sub control circuit 101. Therefore, it is possible to suppress the spread of damage caused by the above fraudulent acts.

<Second action>
Further, in the pachi-slot machine 1 of the present embodiment, the control LSI 234 of the medal selector 201 passes on the medal rail 210 until the number of inserted medals reaches the specified initial number of inserted medals after the power is turned on, and 50 in the present embodiment. A color template used for the color determination process is generated based on the image including. Similarly, a gradient average image template and a HOG template used for the marking determination process are generated.

Therefore, when there is a change in the medal used as a regular medal at a game store, after turning on the power, 50 consecutive regular medals after the change can be inserted to obtain a color template for the changed regular medal. Gradient average image templates and HOG templates can be easily created. In addition, even if a regular medal deteriorates due to, for example, being put into a game machine, being paid out, or washed at a game store, and the engraving becomes less noticeable than it was originally, a color template corresponding to the current state of the regular medal, Since the gradient average image template and the HOG template can be generated, the accuracy of the results of various determinations can be maintained.

<Third action>
Further, in the pachi-slot machine 1 of the present embodiment, the medal counting circuit 246 of the control LSI 234 performs counting processing based on the grayscale image data output from the ISP circuit 245. In the order determination process in the count process, the medal count circuit 246 uses "IN" based on changes in brightness for a plurality of (16 in this embodiment) determination areas for a predetermined number of grayscale image data arranged in time series. , "OUT", "ON", and "OFF", it is determined whether or not the transition mode of the data matches the transition mode of the medal count determination table (see FIG. 27). Then, if they match, it is determined that "the medal has passed" or "the medal has been guided by the medal shoot 202" on the medal rail 210. If any of "IN", "OUT", and "ON" data is stored in the determination area E, it is determined that an abnormality has occurred.

As described above, since the passing of the medal is determined based on the change in the brightness in the plurality of determination areas, the accuracy of the determination can be improved.

Further, the number of determination areas to be set on the grayscale image data can be appropriately set according to the allowable determination time required and the accuracy of the determination to be obtained. Therefore, for example, even when the number of determination areas is increased in order to further improve the accuracy of determination, it is not necessary to newly install parts such as a photo sensor for medal counting. Therefore, an increase in manufacturing cost can be suppressed.

In addition, when the determination result of the counting process is "an abnormality has occurred", the main control circuit 91 misidentifies that the game machine is using a legitimate game medium, and there is a fraudulent act of playing the game. Is detected. That is, fraudulent activity can be detected based on the determination result of the counting process.

<Fourth action>
Further, in the pachi-slot machine 1 of the present embodiment, the ISP circuit 245 of the control LSI 234 performs an image correction process of performing a lens distortion correction process and a projective conversion (homography) process on the RGB bayer image output from the ISI circuit 251.

Therefore, the RGB bayer image can be complemented so that the characteristics of the lens of the camera unit 209 and the deviation of the mounting position of the camera unit 209 do not affect the various determination / determination processes, and the accuracy of the various determination processes can be improved.

<Fifth action>
Further, in the pachi-slot machine 1 of the present embodiment, the color recognition circuit 247 of the control LSI 234 performs the threshold value determination process. As a result, it is possible to prevent a medal whose hue or saturation value is clearly different from that of the regular medal from being erroneously determined to match the color template or to be similar to a certain degree. That is, in addition to the determination based on the degree of agreement with the color template, it is possible to determine whether or not the color to be determined is an effective color, so that the accuracy of the determination result of the color determination process can be improved.

<Sixth action>
Further, in the pachi-slot machine 1 of the present embodiment, the fisheye correction scaler circuit 248 of the control LSI 234 performs bilateral conversion processing on each of the created reduced image data in the equalization processing.
As a result, the noise of the grayscale image data can be reduced and the edges in the grayscale image data can be emphasized. Therefore, the accuracy of the determination result in the marking determination process can be improved.

<Seventh action>
Further, in the pachi-slot machine 1 of the present embodiment, the image recognition accelerator circuit 249 of the control LSI 234 performs the HOG conversion process. Further, the image recognition DSP circuit 242 determines in the marking determination process whether or not the histogram set of the determination target created by the HOG conversion process and the HOG template match or are similar to a predetermined degree.

Therefore, the engraving determination process is performed by performing image matching with the HOG conversion process, which has the advantage of local shape change (geometric transformation), on the imaged data of the medal passing on the medal rail 210 while rotating. It is possible to improve the accuracy of the judgment result of.

<Eighth action>
In the pachi-slot machine 1 of the present embodiment, the image recognition accelerator circuit 249 of the control LSI 234 performs the polar coordinate conversion process before the HOG conversion process.
As a result, the characteristics of the outer peripheral region of the regular medal can be easily reflected in the histogram set created by the HOG conversion process. Therefore, it is possible to improve the accuracy of the determination result of the subsequent engraving determination process for the medal having the characteristic engraving (pattern) on the outer peripheral region.

<Ninth action>
In a conventional game machine, the number of inserted medals and the detection of medal clogging in the selector of inserted medals are detected by the main CPU in the main control circuit executing a program stored in the main ROM. It was done. However, in the pachi-slot machine 1 of the present embodiment, the control LSI 234 of the medal selector 201 performs these detections with higher accuracy than before. Therefore, since it is not necessary to store the programs for these detections in the main ROM 94, the storage capacity of the main ROM 94 is reduced.

<10th action>
In the pachi-slot machine 1 of the present embodiment, the AE correction process is performed by the ISP circuit 245 of the control LSI 234 and the host controller 241. Therefore, the exposure time of the CMOS image sensor 232 can be set to the exposure time at which the ridge portion 210a of the medal rail 210 can take an image. As a result, an appropriate exposure time can be set, so that the accuracy of the color determination process, the marking determination process, and the count process based on the image captured by the camera unit 209 provided with the CMOS image sensor 232 can be ensured.

Further, even if some dust or the like adheres to the lens of the camera unit 209 and becomes dirty, the color determination process is performed while suppressing the shortening of the life of the LED 233 by extending the exposure time instead of increasing the brightness of the LED 233. It is possible to ensure the accuracy of the marking determination process and the count process. In addition, since the frequency of removing stains on the lens can be reduced, the workload of employees in the game hall can be reduced.

<11th action>
In the pachi-slot machine 1 of the present embodiment, when the determination result of the AE determination process is output from the ISP circuit 245 in the AE correction process, the host controller 241 notifies if the exposure time is set to the upper limit of 175 μsec. A signal instructing lighting is output to the LED 206c for notification, and the LED 206c for notification is lit. As a result, the person who sees the notification LED 206c, for example, the manager of the game hall, can grasp that some kind of obstacle (for example, dirt such as dust is attached to the lens) has occurred in the camera unit 209. ..

Further, in the AE correction process, when the determination result of the AE determination process is output from the ISP circuit 245, the host controller 241 receives a medal on the main control board 71 when the exposure time is set to the upper limit of 175 μsec. Output an abnormal signal. Then, when the medal abnormality signal is output, the main control board 71 (main control circuit 91) forcibly interrupts the game, displays an error code on the 7-segment display 24, and causes an error on the sub control circuit 101. A command is transmitted to notify an error (for example, a predetermined error screen is displayed on the liquid crystal display device 11). As a result, it is possible to prevent the game from being played in a state where the accuracy of the color determination process, the engraving determination process, and the count process cannot be ensured, that is, the fraudulent activity cannot be effectively detected.

In the present embodiment, the mode in which the AE correction process is performed when the power of the pachi-slot machine 1 is turned on has been described, but the execution timing of the AT correction process can be appropriately set. For example, when the front door 2b is opened and the main control circuit 91 detects the security signal output from the door open / close monitoring switch 67, the AE correction process may be executed. Further, the AE correction process may be executed when a predetermined time has elapsed since the operation on the pachi-slot machine 1 is no longer detected. Further, the AE correction process may be executed every time a predetermined time, for example, one hour elapses.

Further, when the host controller 241 outputs a signal instructing lighting to the notification LED 206c and outputs a medal abnormality signal to the main control board 71, the output PORT for this medal abnormality signal is determined as a medal. It may be provided separately from the output PORT. By doing so, the main control board 71 can distinguish between the medal abnormality signal output from the medal determination output PORT and the medal abnormality signal output from the separately provided output PORT.

As a result, when a medal abnormality signal is input from an output PORT provided separately from the medal determination output PORT, the main control board 71 can display the image data acquired by the CMOS image sensor 232 even if the exposure time is adjusted. It is possible to grasp that a predetermined image is not included. Therefore, for example, the main control board 71 sends an error command to the sub control circuit 101 to notify the message prompting the removal of the dirt on the lens via the sub control circuit 101 (for example, the liquid crystal display device 11). To that effect) can be displayed. This can encourage employees in the game hall to remove dirt from the lens.

<Modification example>
The gaming machine according to the embodiment of the present invention has been described above, including its action and effect. However, the gaming machine of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described in the claims.

<Modification example 1>
For example, the medal selector 301 having a hole may be used at a position corresponding to the determination region shown in FIGS. 22 to 24.
The configuration of the medal selector 301 according to the first modification will be described with reference to FIG. 37. FIG. 37 is a diagram for explaining the medal selector in the first modification. Note that in FIG. 37, the cancel shooter 206 of the medal selector 301 and the camera unit 209 (see FIG. 7) are not shown.

A medal rail 310 is formed on the base plate portion 304 of the medal selector 301 so as to be recessed in front of the pachislot machine 1 and in a substantially L shape. A plurality of ridges 310a are formed on the surface of the medal rail 310.

Further, on the medal rail 310, a determination region AB hole 310b having the same shape as the combined shape of these determination regions is formed at positions corresponding to the determination regions A1 to A4 and the determination regions B1 to B4 shown in FIGS. 22 to 24. Has been done. Similarly, a determination region C hole 310c having the same shape is formed at a position corresponding to the determination regions C1 and C2, and a determination region D310d hole having the same shape is formed at a position corresponding to the determination regions D1 to D4. .. Although not shown, the base plate portion 304 is formed with a determination region F hole 310e at a position corresponding to the determination region F shown in FIGS. 22 to 24.

Further, as shown in FIG. 37, a determination region F hole 305a is formed in the sub-plate 305 of the medal selector 301 at a position corresponding to the determination region F shown in FIGS. 22 to 24. The determination region F hole 305a formed in the sub plate 305 and the determination region F hole 310e formed in the base plate portion 304 communicate with each other in the front-rear direction.
Since the other points of the medal selector 301 are the same as those of the medal selector 201, the description thereof will be omitted.

In this modification, the holes (judgment area AB hole 310b, judgment area C hole 310c, judgment area D310d) are located at the corresponding positions of the determination areas A1 to A4, B1 to B4, C1, C2, D1 to D4, and F. Holes and determination areas F holes 310e, 305a) were provided. Therefore, the brightness value of the position corresponding to each determination area of the background grayscale image data (grayscale image data not including the medal image) used in the medal position detection process performed by the medal count circuit 246 is these values. The value is lower than that in the case where the hole is not provided (because the light of the LED 233 for the light source is not reflected by the CMOS image sensor 232 by passing through the hole). Therefore, even if a medal having a brightness close to the surface of the medal rail 310 is used, the difference between the brightness in each determination area of the background grayscale image data and the brightness of the medal image in the grayscale image data to be processed. (For example, when the brightness value of the surface of the medal rail 310 is 50, and the brightness value of the hole portion is 22, a value of 28 is calculated as the difference). Therefore, in the medal position detection process, medals with a brightness close to the surface of the medal rail 310 (medals whose surface is processed into black, gray, or brown colors, or medals whose surface is deteriorated or dirty and does not reflect light sufficiently. Etc.) can be accurately detected for various medals. Similarly, the accuracy of the medal edge detection process performed by the medal count circuit 246 can be improved. That is, in the present embodiment, the medal count circuit 246 that performs the medal position detection process constitutes an object presence / absence detecting means.

A hole having the same shape may be provided at a position on the medal rail 310 corresponding to the determination region E shown in FIGS. 22 to 24. Further, since the other points of this modification are the same as those in the above embodiment, the description thereof will be omitted.

<Modification 2>
Next, the configuration of the medal selector 401 according to the second modification will be described with reference to FIGS. 38 and 39.
FIG. 38 is a block diagram showing a circuit configuration example of the medal selector of the game machine of the second modification. Further, FIG. 39 is a block diagram showing a circuit configuration example of the control LSI in the gaming machine of the second modification.

As shown in FIGS. 38 and 39, the control LSI 234 and the medal solenoid 208 in the medal selector 401 of the second modification are electrically connected. Therefore, the control LSI 234 can set the medal solenoid 208 to the ON state or the OFF state. Specifically, the control LSI 234 outputs a control signal for setting the medal solenoid 208 to the ON state or the OFF state from the output PORT assigned to the GPIO 250 via the GPIO 250 to the medal solenoid 208.

In the above embodiment, in the marking determination process, the host controller 241 of the control LSI 234 determines that the medal count circuit 246 has "passed the medal" on the medal rail 210, and a predetermined time before the determination. The mode of instructing the image recognition DSP circuit to perform preprocessing using the reduced image data (that is, before a predetermined frame) has been described. That is, the mode in which the control LSI 234 performs the stamp determination process on the already passed medals after the fact has been described. However, although the control LSI 234 in this modification performs the same marking determination processing, it differs from the above embodiment in that the marking determination processing is performed on the object moving on the medal rail 210 in real time.

Specifically, in the host controller 241 of the medal selector 401 in this modification, when the fisheye correction scaler circuit 248 creates the reduced image data and stores it in the SRAM 243, the stored reduced image data is obtained. The image recognition DSP circuit 242 and the image recognition accelerator circuit 249 are instructed to execute the processing after the circular area detection processing in the marking determination processing. If the circle area cannot be extracted in the circle area detection process, the subsequent processes in the stamp determination process are omitted.

By doing so, in the present embodiment, the image recognition DSP circuit 242 before the object moving on the medal rail 210 reaches the upper exposed hole 219 or the lower exposed hole 220 (see FIG. 8) of the medal rail 210. Can store the gradient averaging determination result and the HOG determination result in the SRAM 243 as the determination result of the marking determination process for this object. Further, the host controller 241 acquires the gradient average determination result and the HOG determination result as the determination results of the marking determination process stored in the SRAM 243 in response to the marking determination end interrupt signal from the image recognition DSP circuit 242. Can be done.

The host controller 241 that has acquired the gradient average determination result and the HOG determination result is a medal when "No" is stored as the acquired gradient average determination result or when "No" is stored as the HOG determination result. A control signal for setting the solenoid 208 to the OFF state is output to the medal solenoid 208. In this case, the object to be determined can be pushed out to the after-medal pressure 218 protruding from the exposed hole 219 or the medal stopper portion 227 protruding from the lower exposed hole 220, and discharged toward the cancel shooter 206.

Further, the host controller 241 of the medal selector 401 in this modification acquires the latest determination result of the color determination process stored in the SRAM 243 each time a color determination interrupt signal is input, and determines the color determination process. Depending on the result, a control signal for setting the medal solenoid 208 to the ON state or the OFF state is output to the medal solenoid 208.

Therefore, in the present embodiment, the determination result of the color determination process for the object before the object moving on the medal rail 210 reaches the upper exposed hole 219 or the lower exposed hole 220 (see FIG. 8) of the medal rail 210. The medal solenoid 208 can be set to the ON state or the OFF state according to the above.

Specifically, the host controller 241 stores the "threshold value determination impossible" as the determination result of the acquired threshold value determination process, or the medal solenoid 208 when "no" is stored as the color determination result. Is output to the medal solenoid 208 to set the control signal to the OFF state. In this case, the object to be determined can be pushed out to the after-medal pressure 218 protruding from the exposed hole 219 or the medal stopper portion 227 protruding from the lower exposed hole 220, and discharged toward the cancel shooter 206.

On the other hand, when "threshold value judgment impossible" is not stored as the judgment result of the threshold value judgment processing and "possible" is stored as the color judgment result, and as the acquired gradient average judgment result and HOG judgment result, " When "OK" is stored, the host controller 241 keeps the state of the medal solenoid 208 in the ON state. In this case, the object to be determined is guided by the hopper device 51.

The host controller 241 of the medal selector 401 in the modified example is a control signal that sets the medal solenoid 208 to the ON state when the circular area cannot be detected in the circular area detection process performed on the reduced image data stored in the SRAM 243. Is output to the medal solenoid 208. By doing so, when the next inserted object is a regular medal, this medal can be appropriately guided to the hopper device 51. That is, the medal solenoid 208 constitutes a drive means for arranging the select plate 207 at a guide position for guiding the regular medal to the hopper device 51 or a discharge position for discharging the medal toward the cancel shooter 206, and the control LSI 234 is a medal solenoid. A drive control means for controlling the drive of the 208 is configured.

Further, when a predetermined condition is satisfied, the host controller 241 of the medal selector 401 in the present modification sends a medal abnormality signal related to the engraving determination process and the color determination process from the medal determination output PORT of the GPIO 250 to the door relay terminal plate 68. It is output to the main control board 71 via. The above-mentioned predetermined output conditions can be appropriately set. For example, the SRAM 243 is provided with an area for storing the value of the number of times the medal solenoid 208 is set from the ON state to the OFF state based on the results of the marking determination processing and the color determination processing of this modification. Further, the host controller 241 adds "1" to the value in this region each time the medal solenoid 208 is set from the ON state to the OFF state. Then, the host controller 241 outputs a medal abnormality signal to the main control board 71 when the stored value reaches a predetermined value, for example, “10”. That is, the host controller 241 of the control LSI 234 constitutes an error notification means.

The value of the number of times stored in the area is cleared when the power is turned on or when the initialization switch (not shown) is pressed after the power is turned on. In addition, it is cleared every time a predetermined time, for example, one hour elapses. The clearing conditions can be set as appropriate.

In this modification, the main control circuit 91 (main control board 71) outputs a medal insertion signal to the medal selector at a predetermined cycle. Specifically, the main control circuit 91 has a medal insertion signal that cannot be inserted when the pachislot 1 is not in the medal insertion permission state where medals can be inserted, or when a medal abnormality signal is output from the medal selector 401. Is output to the medal selector 401. For the medal abnormality signal output from the medal selector 401, the value of the number of times the medal solenoid 208 is set from the ON state to the OFF state is set to a predetermined value based on the results of the above-mentioned marking determination processing and color determination processing. In addition to the medal abnormality signal output when the signal is reached, the medal abnormality signal based on the determination result related to the counting process being "an abnormality has occurred" is also included.

Here, when the pachislot machine 1 is not in the medal insertion permission state where medals can be inserted, for example, when a so-called replay role is won and the replay is activated, or when the start lever 23 is set by the player in the unit game. After being manipulated, and when the credit counter is at its maximum (eg, 50).

When a medal insertion signal having a content that cannot be inserted is output from the main control circuit 91, the host controller 241 of the medal selector 401 sets the medal solenoid 208 to the OFF state. That is, in this modification, the host controller 241 determines when the determination result of the color determination process is "threshold determination impossible" or "no", when the determination result of the marking determination process is "no", and the main control. The medal solenoid 208 is set to the OFF state when a medal insertion signal having a content that cannot be inserted is output from the circuit 91.

Further, the main control circuit 91 outputs a medal insertion signal having a content that allows insertion when the pachislot 1 is in a medal insertion permission state in which medals can be inserted and when a medal abnormality signal is not output from the medal selector 401. Output to the medal selector 401. The host controller 241 sets the medal solenoid 208 to the ON state when a medal insertion signal having a content that allows insertion is output from the main control circuit 91.

In this modification, when the medal abnormality signal is output, the main control circuit 91 has some abnormality (medal clogging, etc.) in the medal selector 401, or a regular game medium is used for the game machine. It is detected that there was a fraudulent act of playing a game by misidentifying it as. Then, various processes are performed when there is a fraudulent act. As various processes when there is a fraudulent act, the main control circuit 91 forcibly interrupts the game, displays an error code on the 7-segment display 24, and sends an error command to the sub control circuit 101. , Notifies that some abnormality has occurred in the medal selector 401 or that there has been a fraudulent act (for example, the liquid crystal display device 11 indicates that an abnormality or fraudulent act has occurred) via the sub-control circuit 101. To do).

Further, the main control circuit 91 maintains a state in which the game is interrupted, that is, a state in which the game cannot be played, until the initialization switch (not shown) provided in the medal selector 401 is pressed. In addition, the medal insertion signal of the content that cannot be inserted is continuously output to the medal selector 401. When the initialization switch is pressed and the state changes from the OFF state to the ON state, the host controller 231 ends to output the medal abnormality signal to the main control circuit 91. When the output of the medal abnormality signal is completed, the main control circuit 91 ends various processes in the case of the above-mentioned fraudulent activity, and restarts the game from the place where the game was interrupted.
Since the other points of this modification are the same as those in the above embodiment, the description thereof will be omitted.

In the pachi-slot machine 1 of the present modification, the engraving determination process and the color determination process are performed in real time on the object passing on the medal rail 210, and the medal solenoid 208 is operated based on the result. Therefore, the object to be determined can be appropriately guided to the cancel shooter 206 or the hopper device 51 based on the determination result.

Further, the host controller 241 mainly controls the medal abnormality signal when the value of the number of times the medal solenoid 208 is set from the ON state to the OFF state reaches "10" based on the results of the color determination process and the marking determination process. Output to the board 71. Then, when the medal abnormality signal is output, the main control circuit 91 (main control board 71) detects that there has been a fraudulent act of playing a game by mistaking the game machine to use a legitimate game medium. Then, various processes are performed when there is a fraudulent act including forcibly interrupting the game. As a result, when an illegal medal that is not a regular medal is frequently used for a short period of time (in this modified example, the value of the number of times set from the ON state to the OFF state is cleared every hour as described above), The main control circuit 91 can detect that there has been a fraudulent act, disable the game, and prevent the continuation of the game accompanied by the fraudulent act.

Further, when the value of the number of times the medal solenoid 208 is set from the ON state to the OFF state based on the result of the color determination process and the engraving determination process does not reach "10", the host controller 241 mainly outputs a medal abnormality signal. No output to the control board 71. Therefore, if the fraudulent medal is not frequently used in a short period of time, for example, when the player intentionally inserts the fraudulent medal into the pachislot machine 1, the game becomes impossible. It can be prevented from being lost.

<Other variants>
Further, in the above embodiment, the mode of generating the four color templates, the gradient average image template, and the HOG template has been described, but the number of these templates can be appropriately set according to the allowable determination time required and the accuracy of the desired determination. Is.

Further, in the above embodiment, the mode in which the color determination process and the engraving determination process are executed for all the inserted medals has been described. However, the present invention is not limited to this, and a switch board is provided at an arbitrary location of the medal selector 201 (for example, in the vicinity of the first board 231), and a color determination ON / OFF switch and a marking determination ON / OFF switch are provided on the switch board. May be provided so that the host controller 241 can select whether or not to execute the color determination process and the marking determination process by reading the state of the switch.

Further, in the above embodiment, when "No" is input to the main control circuit 91 as the gradient average determination result, or when "No" is input as the HOG determination result, the main control circuit 91 is The mode of detecting that there was cheating was explained. However, instead of this, when "No" is input to the main control circuit 91 as the gradient average determination result and "No" is input as the HOG determination result, the main control circuit 91 is cheated. It may be detected that there was.

Further, in the above embodiment, the mode in which the color template, the gradient average image template, and the HOG template stored in the SRAM 243 are deleted when the initialization switch is pressed when the power of the game machine is turned on has been described. However, instead of this, an arbitrary operation may be set to erase various templates stored in SRAM 243. For example, various templates of SRAM 243 may be deleted in conjunction with the change of the setting of the game machine.

Further, in the order determination process when medals cannot be inserted, the mode of data transition in each determination area of the latest four grayscale image data stored in SRAM 243 and the medal count determination table are defined. If the modes of data transitions corresponding to E1 to E4 do not match, it may be determined that "an abnormality has occurred" and the determination result may be stored in SRAM 243.

Further, in the above embodiment, the host controller 241 counts that "the medal has passed" in the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interrupt signal. The mode of instructing the image recognition DSP circuit 242 to start the preprocessing has been described on condition that the determination result of the above is output. That is, when it is determined in the counting process that the medal has passed on the medal rail 210, the host controller 241 executes the processing after the circular region detection processing in the marking determination processing in the image recognition DSP circuit 242 and the image recognition accelerator circuit 249. The mode of instructing is described. However, instead of this, the determination result of some count processing (that is, "medal shoots medal") in the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interruption signal. The image recognition DSP circuit 242 may be instructed to start the preprocessing on the condition that "guided to 202" or "an abnormality has occurred" is output.

Further, the threshold value determination process in the color determination process may be omitted.
Further, the present invention may be adopted for other gaming machines that use a gaming medium, such as pachinko.

1 ... Pachislot, 3L ... Left reel, 3C ... Middle reel, 3R ... Right reel, 4 ... Reel display window, 21 ... Medal slot, 23 ... Start lever, 32 ... Medal payout exit, 51 ... Hopper device, 71 ... Main Control board, 72 ... Sub control board, 79 ... Start switch, 80 ... Stop switch board, 91 ... Main control circuit, 101 ... Sub control circuit, 140 ... Cancel shooter, 201 ... Medal selector, 202 ... Medal shoot,
203 ... Slope, 204 ... Base plate, 205 ... Sub plate, 206 ... Cancel shooter, 207 ... Select plate, 208 ... Medal solenoid, 209 ... Camera unit, 210 ... Medal rail, 211 ... Medal entrance, 212 ... Central hole , 213 ... Medal pressure, 217 ... Magnet, 218 ... After medal pressure, 227 ... Medal stopper, 230 ... First substrate, 231 ... Second substrate, 232 ... CMOS image sensor, 233 ... LED, 234 ... Control LSI , 235 ... legs, 241 ... host controller, 242 ... image recognition DSP circuit, 243 ... SRAM, 244 ... flash memory, 245 ... ISP circuit, 246 ... medal count circuit, 247 ... color recognition circuit, 248 ... fisheye correction scaler Circuit, 249 ... Image recognition accelerator circuit, 250 ... GPIO, 251 ... ISI circuit

Claims (2)

A slot for inserting game media and
A game machine including a game medium detecting means for detecting a game medium input from the slot.
The game medium detecting means is
A passage forming portion that forms a passage through which the game medium passes,
An imaging means for imaging the passage and
Passage determination means for determining whether or not an object has passed through the passage based on image data obtained via the image pickup means.
Based on the image data, a game medium determination means for determining whether or not the object passing through the passage is the regular game medium, and
Each of the plurality of determination areas arranged on the image data has a reference image storage means for storing the reference image data value when the object does not pass in advance.
The passage determination means is
The presence or absence of an object in each of the plurality of determination regions is detected by comparing the image data values of the plurality of determination regions in the plurality of image data captured within a predetermined period with the corresponding reference image data values. Object presence / absence detection means and
The change mode information indicating the mode of change in the presence or absence of the object in each of the plurality of determination regions in the plurality of image data and the mode of the change when the object passes through the passage are stored in advance. It has a passage order determining means for determining that an object has passed through the passage by comparing with the reference change mode information and, if they match.
In the plurality of determination areas, when the game medium passing through the passage is the regular game medium, a plurality of non-passage determination areas provided at positions not overlapping with the game medium and the game medium A game machine characterized in that it is provided at a position overlapping with and includes a plurality of passage determination regions capable of detecting a transition mode of the game medium according to the progress of the game medium . The brightness of the plurality of determination regions is at least lower than the brightness of the area of the passage forming portion other than the plurality of determination regions.
The gaming machine according to claim 1, wherein the object presence / absence detecting means can detect a difference in brightness between the gaming medium and the plurality of determination regions.

Images