JP6679140B2 - Amusement machine - Google Patents

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called a pachi-slot, which is provided with a plurality of reels on each surface of which a plurality of symbols are arranged, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter, also referred to as “start operation”) after a game medium such as a medal has been inserted into the game machine, and starts the rotation of all reels. Output the requested signal. The stop switch detects that the stop button provided corresponding to each reel is pressed by the player (hereinafter, also referred to as "stop operation"), and outputs a signal requesting stop of rotation of the corresponding reel. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

  In such a gaming machine, when a start operation is detected, a lottery process using random numbers on the program (hereinafter, referred to as “internal lottery process”) is performed, and a result of the lottery (hereinafter, “internal winning combination”). That is) and the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all reels is stopped and the symbol combination relating to the establishment of the winning is displayed, the privilege corresponding to the symbol combination is given to the player.

  In addition, such a gaming machine is provided with a medal selector for detecting a medal inserted at the tip of the medal insertion slot. In addition, for this medal selector, a medal (illegal medal) that is not a proper medal (regular medal) is inserted into the medal insertion slot, or a device is inserted into the medal insertion slot, and the regular medal is inserted into the game machine. Measures have been taken against fraudulent acts of playing games by misidentifying that they have been thrown.

  For example, in Patent Document 1, two medal detection proximity sensors are provided in the medal passage, and it is determined whether or not a gaming medal has passed through the medal passage based on the output of each proximity sensor. A slot machine for detecting fraudulent activity using a tool such as a shape is described.

JP, 2002-342814, A

  However, the slot machine described in Patent Document 1 cannot detect an illegal act performed using an illegal medal without using an instrument such as a plate-shaped body. For example, if a medal with a unit price of 20 yen and a medal with a 5 yen price are the same diameter and are different only in color and stamp (pattern), the slot machine will be Cannot be determined. For this reason, in a gaming machine that handles a medal with a loan unit price of 20 yen as a regular medal, it is not possible to detect an illegal act of playing a game using a medal with a loan unit price of 5 yen (illegal medal). .

  In addition, in the slot machine described in Patent Document 1, a medal lent in a hall in which a gaming machine is installed, a medal lent in another hall, and a gaming machine purchased at a used machine store are attached. When a medal that is present or a counterfeit medal (including a device that looks like a medal) has the same diameter but only the color and the marking (pattern), these cannot be distinguished. Therefore, it is difficult to detect (detect) an illegal act of playing a game using a medal (illegal medal) other than the regular medal.

  The present invention has been made to solve the above problems, and an object of the present invention is to make it possible to detect a fraudulent act of playing a game by misidentifying that a legitimate game medium is used in a gaming machine. Providing a gaming machine.

  In order to achieve the above object, the present invention provides a gaming machine having the following configuration.

A slot for inserting a game medium (for example, a medal slot 21 described later),
A game machine comprising: a game medium detecting unit (for example, a medal selector 201 described later) for detecting a game medium inserted from the slot.
The game medium detecting means,
A passage forming portion (for example, a medal rail 210 described later) that forms a passage through which the game medium passes,
An image pickup means (for example, a camera unit 209 described later) for picking up an image of the passage,
Passage determining means (for example, a medal counting circuit 246 described later) for determining whether or not an object has passed through the passage based on image data obtained via the image capturing means,
Image conversion means for converting the image data (for example, an ISP circuit 245 and an image recognition DSP circuit 242 described later);
Based on the image data converted by the image conversion means, a game medium determination means (for example, an image recognition DSP circuit 242 described later) for determining whether or not the object passing through the passage is the regular game medium. Has,
Wherein the image conversion means, for the image data, using a predetermined image processing kernel, emphasizing processing process and the edge component to remove noise components (e.g., a bilateral filter to be described later) applies, after the process A game machine, wherein a region including the outer shape of the regular game medium is extracted from the image data.

  According to the present invention, it is possible to misidentify that a regular game medium is used in a gaming machine and detect fraudulent activity in playing a game.

It is explanatory drawing explaining the function flow in the game machine of one Embodiment of this invention. It is a perspective view showing an example of appearance composition in a game machine of one embodiment of the present invention. 1 is a perspective view showing an internal structure of a gaming machine according to an embodiment of the present invention and showing a state in which a middle door is closed. It is a perspective view showing an internal structure in a game machine of one embodiment of the present invention, and showing a state in which a middle door is opened. It is an explanatory view showing the inside of the cabinet in the game machine of one embodiment of the present invention. It is explanatory drawing which shows the back surface side of the front door in the game machine of one Embodiment of this invention. It is the perspective view which looked at the medal selector in the game machine of one embodiment of the present invention from diagonally back of the game machine. It is an exploded view of the medal selector in the gaming machine of one embodiment of the present invention. It is the perspective view which looked at the medal selector in the game machine of one embodiment of the present invention from the slanting front of the game machine. It is a rear view of the base plate portion of the medal selector in the gaming machine of one embodiment of the present invention. It is a perspective view of the select plate of the medal selector in the gaming machine of the embodiment of the present invention. It is a figure which shows the path of the medal when the medal selector in the gaming machine of one embodiment of the invention guides the medal to the hopper device. It is a figure showing a course of a medal when a medal selector in a game machine of one embodiment of the invention guides a medal to a medal shoot. It is a block diagram showing a control system in a game machine of one embodiment of the present invention. It is a block diagram showing an example of composition of a main control circuit in a game machine of one embodiment of the present invention. It is a block diagram showing an example of composition of a sub control circuit in a game machine of one embodiment of the present invention. It is a block diagram showing an example of circuit composition of a medal selector in a game machine of one embodiment of the present invention. It is a block diagram showing an example of circuit composition of control LSI in a game machine of one embodiment of the present invention. It is a figure for explaining distortion of a lens in a game machine of one embodiment of the present invention. FIG. 6 is a diagram for explaining the projective transformation process in the gaming machine according to the embodiment of the present invention, where A shows an RGB Bayer image before projective transformation and B shows an RGB Bayer image after projective transformation. It is a figure for explaining a threshold graph in the game machine of one embodiment of the present invention. It is a figure (the 1) for explaining the judgment field in the game machine of one embodiment of the present invention. It is a figure (the 2) for explaining the judgment field in the game machine of one embodiment of the present invention. It is a figure (the 3) for explaining the judgment field in the game machine of one embodiment of the present invention. It is a figure (the 4) for explaining the judgment field in the game machine of one embodiment of the present invention. It is a figure showing an example of judgment area judgment result data memorized by SRAM in a game machine of one embodiment of the present invention. It is a figure for explaining the medal count determination table in the gaming machine of one embodiment of the present invention. It is a figure for explaining the Gaussian filter in the game machine of one embodiment of the present invention. It is a figure for explaining circle area detection processing in a game machine of one embodiment of the present invention. It is a figure for explaining 3σ correction processing in the game machine of one embodiment of the present invention. It is a figure for explaining filter processing in a game machine of one embodiment of the present invention, A shows typically circle field image data after 3σ correction processing, B shows a coefficient for edge image X, C indicates the coefficient for the edge image Y. It is a figure showing an example of a regular medal used for a game machine of one embodiment of the present invention, A shows one side of a regular medal, and B shows gradient average image data of a regular medal. It is a figure for explaining HOG conversion processing in the game machine of one embodiment of the present invention. It is a flow chart of processing which control LSI in a game machine of one embodiment of the present invention performs. It is a timing chart (the 1) of the processing which the control LSI in the game machine of one embodiment of the present invention performs. It is a timing chart (the 2) of the processing which the control LSI in the game machine of one embodiment of the present invention performs.

  Hereinafter, a pachi-slot which is a gaming machine showing an embodiment of the present invention will be described with reference to FIGS. 1 to 36.

<Function flow>
First, the functional flow of the pachi-slot will be described with reference to FIG.
In the pachi-slot of the present embodiment, medals are used as a game medium for playing a game. As a game medium, coins, game balls, game point data, tokens, etc. can be applied in addition to medals.

  When a player inserts a medal and operates the start lever, one value (hereinafter, a random number value) is extracted from random numbers in a predetermined numerical value range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. The internal lottery means is handled by the main control circuit described later. By the determination of the internal winning combination, the combination of symbols that is allowed to be displayed along the winning determination line described later is determined. The types of symbol combinations include those related to "winning", in which benefits such as payout of medals, operation of re-play, operation of bonus, etc. are given to the player, and those related to other so-called "miss". Is provided.

  Further, when the start lever is operated, the plurality of reels are rotated. After that, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means controls the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. To do. This reel stop control means is carried out by a main control circuit described later.

  In the pachi-slot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec or 75 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the “number of sliding pieces”. When the prescribed period is 190 msec, the maximum number of sliding pieces is set to 4 symbols, and when the prescribed period is 75 msec, the maximum number of sliding pieces is set to 1 symbol.

  The reel stop control means, when the internal winning combination permitting the combination display of the symbols relating to the winning is determined, normally, the combination of the symbols is the winning determination line within the prescribed time of 190 msec (for four symbols of the symbol). Stop the rotation of the reel so that it is displayed along with. Further, the reel stop control means defines, for example, one or more reels at the time of the operation of the challenge bonus (CB) and the middle bonus (MB) of continuously operating the second type special accessory. Within a time of 75 msec (one frame of the symbol), the rotation of the reel is stopped so that the symbol combination is displayed along the winning determination line as much as possible. Further, the reel stop control means uses various prescribed times corresponding to the gaming state to rotate the reels so that a combination of symbols not allowed to be displayed by the internal winning combination is not displayed along the winning determination line. Stop.

  In this way, when the rotations of the plurality of reels are all stopped, the winning determination means determines whether or not the symbol combination displayed along the winning determination line is related to winning. This winning determination means is carried out by the main control circuit described later. When it is determined by the prize determination means that the prize is related to the prize, a bonus such as payout of medals is given to the player. In the pachi-slot, a series of flows as described above is performed as one game.

  In addition, in the pachi-slot, in the above-described series of flow, display of images performed by a display device such as a liquid crystal display device, light output performed by various lamps, sound output performed by a speaker, or a combination thereof is used. Various performances are performed.

  When the start lever is operated, a random number value for production (hereinafter, a random number value for production) is extracted in addition to the random number value used for determining the internal winning combination described above. When the random number value for effect is extracted, the effect content determination means randomly determines, from among a plurality of types of effect content associated with the internal winning combination, the effect content to be executed this time. The sub-control circuit described later plays a role of this effect content determination means.

  When the content of the effect is determined, the effect executing means executes the corresponding effect in association with each trigger such as the start of the rotation of the reel, the stop of the rotation of each reel, the determination of the presence or absence of the winning. In this way, in the pachi-slot, the player has an opportunity to know or anticipate the determined internal winning combination (in other words, the combination of symbols to be aimed) by executing the effect contents associated with the internal winning combination. It is provided, and the interest of the player can be improved.

<Structure of pachi-slot>
Next, the structure of the pachi-slot 1 according to the embodiment will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi-slot 1.

As shown in FIG. 2, the pachi-slot 1 includes an exterior body 2. The exterior body 2 has a cabinet 2a that accommodates a hopper device 51, a medal auxiliary storage 52, and the like (see FIG. 5) described later, and a front door 2b that is openably and closably attached to the cabinet 2a.
Handles 7 are provided on both sides of the cabinet 2a (only one handle 7 is shown in FIG. 2). The handle 7 is a recess for holding the pachi-slot 1 when carrying it.

  Inside the exterior body 2, three reels 3L, 3C, 3R are provided side by side. Hereinafter, the reels 3L, 3C, 3R are referred to as the left reel 3L, the middle reel 3C, and the right reel 3R, respectively. Each of the reels 3L, 3C, 3R has a reel body formed in a cylindrical shape, and a translucent sheet material mounted on the peripheral surface of the reel body. On the surface of the sheet material, a plurality of (for example, 20) patterns are drawn at predetermined intervals along the circumferential direction.

  The front door 2b includes a door body 9, a front panel 10, and a liquid crystal display device 11 showing a specific example of a display device.

  The door body 9 is attached to the cabinet 2a using a hinge (not shown), and opens and closes the opening of the cabinet 2a. The hinge is provided at the left end of the door body 9 when the door body 9 is viewed from the front of the pachi-slot 1. The liquid crystal display device 11 is attached to the upper part of the door body 9. The liquid crystal display device 11 includes a display unit (display screen) 11 a, and the liquid crystal display device 11 is used to perform an effect by displaying an image.

  The front panel 10 is arranged so as to overlap the display portion 11a side of the liquid crystal display device 11 and is formed in a frame shape having a panel opening 10a exposing the display portion 11a of the liquid crystal display device 11. A lamp group 18 is provided on the front panel 10. The lamp group 18 includes LEDs (Light Emitting Diodes) and the like, and turns on and off the light in a pattern corresponding to the effect contents.

  A pedestal portion 12 is formed at the center of the front door 2b. The pedestal portion 12 is provided with the symbol display area 4 and various devices to be operated by the player.

  The symbol display area 4 is arranged on the front side overlapping with the three reels 3L, 3C, 3R when viewed from the front, and is provided corresponding to the three reels 3L, 3C, 3R. The symbol display area 4 functions as a display window and is configured to allow the reels 3L, 3C, 3R provided behind it to pass through. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  When the reels 3L, 3C, 3R provided behind the reel display window 4 are stopped from rotating, the reel display window 4 has a plurality of types of symbols on the reels 3L, 3C, 3R in the upper, middle and lower stages of the frame. One symbol is displayed in each area (3 in total). In the present embodiment, a pseudo line formed by combining any one of predetermined three regions including the upper stage, the middle stage, and the lower stage of the reel display window 4 is an object for determining whether or not to win. Is defined as a line (winning determination line).

  The reel display window 4 is formed by a frame member 13 provided on the pedestal portion 12. The frame member 13 has a reel display window 4, an information display window 14, and a stop button mounting portion 15.

  The information display window 14 is continuously provided below the reel display window 4 and opens upward. That is, the reel display window 4 and the information display window 14 are formed as one continuous opening. The information display window 14 and the reel display window 4 are covered with a transparent window cover 16.

  The window cover 16 is arranged on the inner surface side of the frame member 13 and cannot be removed from the front surface side of the front door 2b. Further, the frame member 13 has a sheet placing portion 17 which faces the opening of the information display window 14 with the window cover 16 interposed therebetween. Then, a sheet member (information sheet) in which information regarding a game is described is arranged between the sheet placing portion 17 and the window cover 16. Therefore, the information sheet is covered with the window cover 16 having a smooth surface without irregularities or gaps.

  Since the window cover 16 constituting the mounting portion of the information sheet is not removable from the front side of the front door 2b and has a smooth surface without unevenness or gap, the pachi-slot 1 can be used by using the mounting portion of the information sheet. You can prevent fraudulent activities that access the inside of the.

  The stop button attachment portion 15 is provided below the information display window 14 and is formed in a plane facing the front. The stop button mounting portion 15 is provided with a through hole through which the stop buttons 19L, 19C, 19R penetrate. The stop buttons 19L, 19C, 19R are associated with each of the three reels 3L, 3C, 3R, and are provided to stop the rotation of the corresponding reels. Hereinafter, the stop buttons 19L, 19C, and 19R are referred to as the left stop button 19L, the middle stop button 19C, and the right stop button 19R, respectively.

  The stop buttons 19L, 19C, and 19R represent examples of various devices that are targets of operation by the player. In addition, the pedestal portion 12 is provided with a medal insertion slot 21, a BET button 22, and a start lever 23, which are various devices to be operated by the player.

  The medal slot 21 is provided to receive medals that are dropped from the outside by the player. The medals received in the medal insertion slot 21 will be inserted into one game with a predetermined specified number (for example, 3) as an upper limit, and the amount exceeding the specified number will be deposited inside the pachi-slot 1. It becomes possible (a so-called credit function).

  The BET button 22 is provided to determine the number of medals deposited in the pachi-slot 1 for one game. The start lever 23 is provided to start rotation of all reels (3L, 3C, 3R).

  A 7-segment display 24 including a 7-segment LED (Light Emitting Diode) is provided on the left side of the reel display window 4 when the front door 2b is viewed from the front. The 7-segment display 24 digitally displays information such as the number of medals to be paid out to the player as a privilege (hereinafter, the number of payouts) and the number of medals stored in the pachi-slot (hereinafter, the number of credits). .

  A settlement button 27 is provided on the left side of the pedestal portion 12 when the front door 2b is viewed from the front. The settlement button 27 is provided for pulling out (discharging) to the outside stored in the pachi-slot 1. A waist panel unit 31 is provided below the pedestal portion 12. The waist panel unit 31 includes a decorative panel on which an arbitrary image is drawn and a light source that emits light for illuminating the decorative panel from the back side.

  Below the waist panel unit 31, a medal payout opening 32, speaker holes 33L and 33R, and a medal tray unit 34 are provided. The medal payout port 32 guides the medals discharged from the medal selector 201 described later and the medals discharged by driving the hopper device 51 described later to the outside. The medals discharged from the medal payout opening 32 are stored in the medal tray unit 34. The speaker holes 33L and 33R are provided to output sound effects and music such as music according to the contents of the effect.

[Internal structure]
3 and 4 are perspective views showing the internal structure of the pachi-slot 1. In FIG. 3, the front door 2b is opened, and the middle door 41 provided on the back surface side of the front door 2b is closed with respect to the front door 2b. Further, FIG. 4 shows a state in which the front door 2b is opened and the middle door 41 is opened with respect to the front door 2b.
Further, FIG. 5 is an explanatory diagram showing the inside of the cabinet 2a. FIG. 6 is an explanatory view showing the back surface side of the front door 2b.

  The cabinet 2a has a top plate 20a, a bottom plate 20b, left and right side plates 20c and 20d, and a back plate 20e (see FIG. 5). A cabinet-side speaker 42 is provided on the upper side inside the cabinet 2a. The cabinet-side speaker 42 is attached to the back plate 20e of the cabinet 2a via mounting brackets 43L and 43R. The cabinet side speaker 42 is, for example, a speaker for outputting a sound effect.

  A cabinet-side relay board 44 is disposed on the left side of the cabinet-side speaker 42 when the inside of the cabinet 2a is viewed from the front. The cabinet side relay board 44 is attached to the left side plate 20c of the cabinet 2a. The cabinet side relay board 44 includes a main control board 71 (see FIG. 14), which will be described later, attached to the middle door 41 (see FIGS. 3 and 4), a hopper device 51, a medal auxiliary storage switch (not shown), and a medal payout. The wiring for connecting with a count switch (not shown) is relayed.

  An amplifier board 45 for controlling the output of sound from the cabinet-side speaker 42 is arranged in the center of the cabinet 2a. The amplifier board 45 is attached to a mounting shelf 46 fixed to the left and right side plates 20c and 20d.

  Further, when the inside of the cabinet 2a is viewed from the front, an external concentrated terminal board 47 is arranged on the right side of the amplifier board 45 (see FIG. 5). The external centralized terminal board 47 is attached to the right side surface board 20d of the cabinet 2a. The external centralized terminal board 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachi-slot 1.

  A sub power supply device 48 is disposed on the left side of the amplifier board 45 when the inside of the cabinet 2a is viewed from the front. The sub power supply device 48 is attached to the left side plate 20c of the cabinet 2a. The sub power supply device 48 supplies electric power with an AC voltage of 100 V to the power supply device 53 described later. Further, the AC voltage of 100 V is converted into the DC voltage and supplied to the amplifier board 45.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged below the inside of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 20b of the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large amount of medals and discharging them one by one. For example, when the settlement button 27 (see FIG. 2) is pressed and the medals stored in the pachi-slot are settled, the hopper device 51 discharges the stored medals by the number of credits. The medals paid out by the hopper device 51 are discharged from the medal payout opening 32 (see FIG. 2).

  The medal auxiliary storage 52 stores the medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is engaged with the bottom plate 20b of the cabinet 2a and is configured to be attachable to and detachable from the bottom plate 20b.

  The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side face plate 20c. The power supply device 53 has a power switch 53a and a power board 53b (see FIG. 14). The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device 48 into the power of the DC voltage required by each unit, and supplies the converted power to each unit.

  As shown in FIGS. 3, 4 and 6, the middle door 41 is arranged at the center of the back surface of the front door 2b, and is configured to open and close the reel display window 4 (see FIG. 4) from the back side. Door stoppers 41a, 41b, 41c are provided on the upper and lower portions of the middle door 41. The door stoppers 41a, 41b, 41c fix (prohibit) the opening operation of the middle door 41 with the reel display window 4 closed from the back side. That is, in order to open the middle door 41, it is necessary to rotate the door stoppers 41a, 41b, 41c to release the fixation of the middle door 41.

  A main control board case 55 accommodating a main control board 71 (see FIG. 14) and three reels 3L, 3C, 3R are attached to the middle door 41. A stepping motor is connected to the three reels 3L, 3C, 3R via a gear having a predetermined reduction ratio.

As shown in FIG. 6, the main control board case 55 is provided with a setting key type switch 56. The setting key type switch 56 is used when the setting of the pachi-slot 1 is changed or the setting of the pachi-slot 1 is confirmed.
In the present embodiment, the main control board case 55 and the main control board 71 housed in the main control board case 55 constitute a main control board unit.

  The main control board 71 housed in the main control board case 55 constitutes a main control circuit 91 (see FIG. 15) described later. The main control circuit 91 is a circuit for controlling the main flow of the game in the pachi-slot 1, such as determination of internal winning combination, rotation and stop of the reels 3L, 3C, 3R, and determination of winning or not. The specific configuration of the main control circuit 91 will be described later.

  A sub control board case 57 that accommodates the sub control board 72 (see FIG. 14) is provided above the middle door 41, and a center speaker 58 is provided above the sub control board case 57. The sub control board 72 housed in the sub control board case 57 constitutes a sub control circuit 101 (see FIG. 16). The sub-control circuit 101 is a circuit that controls execution of effects such as display of images. The specific configuration of the sub control circuit 101 will be described later.

  A sub relay board 61 is disposed on the right side of the sub control board case 57 when the front door 2b is viewed from the back side. The sub relay board 61 relays the wiring connecting the sub control board 72 and the main control board 71. The sub-control board 72 is a board that relays a wiring that connects the sub-control board 72 and a board arranged around the sub-control board 72. It should be noted that LED boards 62A, 62B, and 62C, which will be described later, can be cited as the boards arranged around the sub-control board 72.

  The LED boards 62A, 62B, and 62C are arranged on both sides of the sub control board case 57 when viewed from the back surface side of the front door 2b. These LED boards 62A, 62B, and 62C are a plurality of LEDs (Light Emitting Diodes) 85 (see FIG. 14) showing a specific example of a light source according to the effect executed by the control of the sub control circuit 101 (see FIG. 16). ) Is lit to display the blinking pattern. The pachi-slot 1 of the present embodiment includes a plurality of LED boards in addition to the LED boards 62A, 62B, 62C.

  Below the sub relay board 61, a 24h door opening / closing monitoring unit 63 is arranged. The 24h door opening / closing monitoring unit 63 stores a history of opening / closing of the middle door 41. Further, when the middle door 41 is opened, a signal for displaying an error on the liquid crystal display device 11 is output to the sub control board 72 (sub control circuit 101).

  A board speaker 64 and lower speakers 65L and 65R are arranged below the middle door 41. The board speaker 64 faces the waist panel unit 31 (see FIG. 2), and the lower speakers 65L and 65R face the speaker holes 33L and 33R (see FIG. 2), respectively.

  A medal selector 201, a medal chute 202, and a door opening / closing monitoring switch 67 are arranged above the lower speaker 65L. The medal selector 201 is a device for determining whether or not the material, shape, etc. of the medal are appropriate, and guides the medal inserted into the medal insertion slot 21 to the hopper device 51 via the slope 203, or Guide to the chute 202. The specific configuration of the medal selector 201 will be described later.

  The medal chute 202 is a substantially Y-shaped tubular member, and guides the medals guided by the medal selector 201 and the medals discharged from the hopper device 51 to the medal payout outlet 32 (see FIG. 2).

  The door opening / closing monitoring switch 67 is arranged on the left side of the medal selector 201 when the front door 2b is viewed from the back side. The door opening / closing monitoring switch 67 outputs a security signal for informing the opening / closing of the front door 2b to the outside of the pachi-slot 1.

  Further, a door relay terminal plate 68 is arranged in a region below the reel display window 4 and opened / closed by the middle door 41 (see FIG. 4). The door relay terminal board 68 includes a main control board 71 (see FIG. 14) in the main control board case 55, various buttons and switches, a sub control board 72 (see FIG. 14), a medal selector 201, and a game operation display board. 81 is a substrate that relays the wiring with 81 (see FIG. 14). The various buttons and switches include, for example, the BET button 22, the settlement button 27, the door opening / closing monitoring switch 67, the BET switch 77, the start switch 79, and the like described later.

<Medal selector configuration>
Next, a specific configuration of the medal selector 201 will be described with reference to FIGS. 7 to 13. FIG. 7 is a perspective view of the medal selector 201 seen from diagonally behind the pachi-slot 1. FIG. 8 is an exploded view of the medal selector 201. FIG. 9 is a perspective view of the medal selector 201 as seen obliquely from the front of the pachi-slot 1. FIG. 10 is a rear view of a base plate portion 204, which will be described later, of the medal selector 201. FIG. 11 is a perspective view of a later-described select plate 207 of the medal selector 201. FIG. 12 is a diagram showing a route of medals when the medal selector 201 guides the medals to the hopper device 51. FIG. 13 is a diagram showing a route of medals when the medal selector 201 guides the medals to the medal shoot 202. In addition, the arrow X shown in FIGS. 7 to 13 indicates the horizontal direction of the pachi-slot 1, the arrow Y indicates the front-back direction of the pachi-slot 1, and the arrow Z indicates the vertical direction.

  As shown in FIGS. 7 to 9, the medal selector 201 includes a base plate portion 204, a sub plate 205, a cancel shooter 206, a select plate 207, a medal solenoid 208 (see FIG. 9), a camera unit 209, Is equipped with.

  The base plate portion 204 is a substantially plate-shaped member that forms the outer frame housing of the medal selector 201, and is formed such that both left and right ends of the pachi-slot 1 are bent rearward of the pachi-slot 1. The base plate portion 204 has a rear surface 204b, which is one plane orthogonal to the front-back direction of the pachi-slot 1, and a front surface 204a (see FIG. 9) which is the other plane. A medal rail 210 is formed on the rear surface 204b so as to be recessed forward of the pachi-slot 1 and in a substantially L-shape. A plurality of ridges are formed on the surface of the medal rail 210.

  A medal entrance 211 for receiving medals inserted from the medal insertion slot 21 (see FIG. 2) is provided at the upper end of the base plate portion 204. The medals inserted into the medal selector 201 from the medal entrance portion 211 move from the upper side to the lower side along the medal rails 210. A medal exit portion 204c (see FIG. 8) is provided below the base plate portion 204. The medals that have moved inside the medal selector 201 are discharged from the medal exit portion 204c and are stored in the hopper device 51 via the slope 203 (see FIG. 4).

  A center hole 212 penetrating in the front-rear direction is formed at a substantially middle position of the medal rail 210, and an end portion of the medal pressure 213 (see FIG. 8) is exposed from the center hole 212. As shown in FIG. 9, the medal pressure 213 is rotatably supported by a shaft portion 214 provided on the front surface 204 a of the base plate portion 204. A coil spring 215 is attached to the shaft portion 214, and the medal pressure 213 is biased by the coil spring 215 so that the medal pressure 213 projects from the central hole 212.

  As shown in FIG. 9, a magnet 217 is provided on the front surface 204 a of the base plate portion 204. The magnet 217 attracts (magnetizes) illegal medals that are not made of a proper material among the medals moving on the medal rail 210.

  Further, as shown in FIG. 8, an upper exposure hole 219 is formed in a substantially central portion of a downstream region of the medal rail 210, the upper exposure hole 219 penetrating in the front-rear direction and exposing a rear end portion of an after medal pressure 218 described later. . Further, a lower exposure hole 220 that penetrates in the front-rear direction and exposes a medal stopper portion 227, which will be described later, of the select plate 207 is formed in a lower portion of the downstream region of the medal rail 210.

  Further, as shown in FIG. 10, six reference markers 260 are formed on the medal rail 210. The reference marker 260 is arranged in an imaging area A1 (indicated by a chain line in FIG. 10) which is an area on the medal rail 210 captured by the camera unit 209.

  The reference marker 260 is composed of an upper reference marker 261 and a lower reference marker 262, and the upper reference marker 261 is arranged above the medal rail 210 so as to be inclined and arranged side by side in three rows. Further, three lower reference markers 262 are arranged below the medal rail 210 so as to be aligned in the left-right direction while being inclined.

  In the reference marker 260, in the image data of the imaging region imaged by the camera unit 209, the luminance of the pixel where the reference marker 260 is formed and the luminance of the pixel where the reference marker 260 is not formed, Are formed to differ by a predetermined value or more. In the present embodiment, each reference marker 260 is formed by forming a triangular hole in the medal rail 210. The form of the reference marker 260 is not limited to this, and the shape of the hole can be appropriately selected. Further, for example, the reference marker 260 may be formed on the medal rail 210 by printing a graphic having a color different from the background color of the medal rail 210.

  As shown in FIG. 9, the after medal pressure 218 is rotatably supported by the front surface 204 a of the base plate portion 204. When the front end of the after medal pressure 218 is pressed to the rear of the pachi-slot 1 by the medal solenoid 208, the after medal pressure 218 rotates and the rear end of the after medal pressure 218 comes out from the upper exposure hole 219 (see FIG. 8). Exposed.

  As shown in FIGS. 7 and 8, the cancel shooter 206 is a substantially plate-shaped member, and is formed such that the left and right ends of the pachi-slot 1 are bent forward of the pachi-slot 1. The cancel shooter 206 is detachably fixed to the base plate portion 204 and covers the lower portion of the base plate portion 204 from the rear side. The cancel shooter 206 guides the medals discharged without passing through the medal exit portion 204c to the medal chute 202 (see FIG. 4). A notch portion 206a, which is cut out in a substantially rectangular shape downward, is formed at an upper portion of a substantially central portion in the left-right direction of the cancel shooter 206.

  As shown in FIGS. 7 and 8, the sub plate 205 is a plate-shaped member that covers the medal rail 210 from the rear side. The sub-plate 205 has a flat plate-shaped main body portion 221 and a shaft portion 222 provided on the upper portion of the main body portion 221. A through hole 221a penetrating in the front-rear direction is provided at a substantially central portion of the main body portion 221, and a downstream region is exposed from the substantially central portion of the medal rail 210 through the through hole 221a.

  The shaft part 222 is supported by the base plate part 204, and the sub-plate 205 is attached to the base plate part 204 so as to be rotatable around the shaft part 222. A coil spring 223 is attached to the shaft portion 222. Normally, the sub-plate 205 is pressed against the base plate portion 204 side by the biasing force of the coil spring 223. At this time, a space through which medals can pass is formed between the sub plate 205 and the upper portion of the medal rail 210 covered by the sub plate 205. That is, the sub plate 205 functions as a guide plate that allows medals to pass through.

Here, for example, when a medal jam occurs in the medal selector 201, the sub plate 205 can be rotated against the biasing force of the coil spring 223 to eliminate the medal jam.

  As shown in FIG. 7, the select plate 207 is a member that guides medals that move in a substantially central portion of the medal rail 210 that is not covered by the sub-plate 205. As shown in FIG. 11, the select plate 207 includes a plate body 224 having a substantially trapezoidal plate shape, and a pair of bearing portions formed by bending the left and right ends of the plate body 224 toward the front of the pachi-slot 1. 225 and. Further, a flange portion 226 formed by bending the pachi-slot 1 forward and bending the rear end upward is formed on the upper portion of the plate body 224. Further, a medal stopper portion 227 extending downward is formed on one bearing portion 225.

  As shown in FIG. 7, the plate body 224 faces the substantially central portion of the medal rail 210 not covered by the sub-plate 205 in the front-back direction of the pachi-slot 1.

  As shown in FIG. 9, the select plate 207 is rotatably supported by a shaft portion 228 provided on the front surface 204 a of the base plate portion 204. The shaft portion 228 is provided with a coil spring 229 and biases the flange portion 226 toward the front of the pachi-slot 1. The flange portion 226 is in contact with one end of the medal solenoid 208. When the medal solenoid 208 is in the ON state, the flange portion 226 is pressed by one end of the medal solenoid 208 and moves rearward of the pachi-slot 1 against the biasing force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “guide position”. The distance between the plate body 224 of the select plate 207 at the guide position and the medal rail 210 is set to a predetermined distance that allows the medal rail 210 to be guided to the hopper device 51 without discharging the medal to the cancel shooter 206 side. Further, at this time, the medal stopper portion 227 does not protrude from the lower exposed hole 220 (see FIG. 8).

  Further, when the medal solenoid 208 is in the OFF state, the flange portion 226 is released from the pressure of the medal solenoid 208 and moves to the front of the pachi-slot 1 by the biasing force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “discharge position”. The distance between the plate body 224 of the select plate 207 at the ejection position and the medal rail 210 is set to be longer than a predetermined distance. At this time, the flange portion 226 moving to the front of the pachi-slot 1 is pressed, and one end of the medal solenoid 208 moves to the front of the pachi-slot 1. Along with this, the other end of the medal solenoid 208 moves to the rear of the pachi-slot 1 and presses the front end of the after medal pressure 218. As a result, the after medal pressure 218 is rotated, and the rear end portion of the after medal pressure 218 is exposed from the upper exposure hole 219 (see FIG. 8).

  The medal stopper portion 227 does not protrude from the lower exposure hole 220 (see FIG. 8) when the select plate 207 is in the guide position, and protrudes from the lower exposure hole 220 when it is in the ejection position.

  As shown in FIG. 12, when the medal moving on the medal rail 210 satisfies the standard size, the select plate 207 in the guide position contacts the upper part of the moving medal and moves the medal to the medal exit portion 204c (see FIG. 8). ) To. The medal presses the medal pressure 213 toward the front of the pachi-slot 1 when being guided by the select plate 207. Note that, in FIG. 12, the sub-plate 205 and the cancel shooter 206 of the medal selector 201 are omitted.

  On the other hand, as shown in FIG. 13, the select plate 207 at the ejection position has a distance between the plate body 224 and the medal rail 210 even if the medal moving on the medal rail 210 satisfies the standard size. Therefore, the medal cannot be guided to the medal exit portion 204c (see FIG. 8). Further, the medal is pushed out to the medal pressure 213, the after medal pressure 218 protruding from the upper exposure hole 219, or the medal stopper portion 227 protruding from the lower exposure hole 220, and is ejected toward the cancel shooter 206. Note that, in FIG. 13, as with FIG. 12, the sub-plate 205 and the cancel shooter 206 of the medal selector 201 are omitted.

  Further, in the present embodiment, the select plate 207 is normally positioned at the guide position, but under a predetermined condition (for example, when a specified number of medals are inserted, when an error occurs, when a game is started, etc.), the select plate 207 is at the discharge position. It is positioned.

  Further, when the medal moving on the medal rail 210 has a diameter smaller than the standard size, even if the select plate 207 is in the guide position, the medal is not guided to the select plate 207 but pushed out to the medal pressure 213, and the cancel shooter 206. Is discharged toward.

  As shown in FIGS. 7 and 8, the camera unit 209 includes a first substrate 230, a second substrate 231, and a lens (not shown). Whether the object moving on the medal rail 210 is a regular medal or not. Is a unit that outputs the determination result to the main control circuit 91. A CMOS image sensor 232 (see FIG. 17) and an LED 233 (see FIG. 17) are provided on the first substrate 230. A control LSI 234 (see FIG. 17) communicably and controllably connected to the CMOS image sensor 232 and the LED 233 is provided on the second substrate 231.

  The first substrate 230 and the second substrate 231 are connected by a BtoB (Board-to-Board) type connector (not shown), and by the leg portions 235 provided at the corners of the respective substrates 230 and 231. It is fixed. The specific configuration of the circuit of the camera unit 209 will be described later. Further, in the present embodiment, the mode in which the camera unit 209 is configured with the two substrates 230 and 231 and the lens has been described, but instead of this, one substrate provided with the CMOS image sensor 232, the LED 233, and the control LSI 234 is used. A camera unit may be configured. Further, a diaphragm mechanism may be added.

  The camera unit 209 is fixed by screwing the first substrate 230 into a screw hole 206b provided around the notch 206a in the upper portion of the cancel shooter 206.

  The CMOS image sensor 232 (see FIG. 17) is provided in a substantially central portion of the first substrate 230. The CMOS image sensor 232 captures an image of the image capturing area A1 (see FIG. 10) on the medal rail 210 via the cutout portion 206a (see FIG. 8) of the cancel shooter 206, and captures the captured image data to the control LSI 234 (see FIG. 17). Output).

  The LED 233 (see FIG. 17) emits surface light around the CMOS image sensor 232 and illuminates an object moving on the medal rail 210 with light. The control LSI 234 (see FIG. 17) determines whether the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232, and outputs the determination result to the main control circuit 91. To do. In the present embodiment, the mode in which the camera unit 209 is fixed to the cancel shooter 206 by screwing in the screw hole 206b formed around the notch 206a has been described, but the fixing mode of the camera unit is not limited to this. Not done. For example, a mounting rail is provided between the first substrate 230 and the second substrate 231, a recess is provided in the upper portion of the cancel shooter 206, and the mounting rail is fitted in this recess, and then the mounting rail and the cancel shooter 206 are provided. May be fixed with screws or an adhesive.

<Circuit configuration of pachi-slot>
Next, the configuration of the circuit included in the pachi-slot 1 will be described with reference to FIGS.
First, with reference to FIG. 14, an outline of the entire circuit included in the pachi-slot 1 will be described. FIG. 14 is a block configuration diagram of the entire circuit included in the pachi-slot 1.

The pachi-slot 1 has a main control board 71 arranged on the middle door 41 and a sub-control board 72 arranged on the front door 2b.
The reel control terminal board 74, the setting key type switch 56, the external centralized terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, and the power supply board 53b of the power supply device 53 are provided on the main control board 71. It is connected. The setting key type switch 56, the external centralized terminal board 47, the hopper device 51, and the medal auxiliary storage box switch 75 are connected to the main control board 71 via the cabinet side relay board 44. Since the external centralized terminal board 47 and the hopper device 51 have been described above, the description thereof will be omitted.

  The reel relay terminal plate 74 is arranged inside the reel body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R and relays a signal output from the main control board 71 to the stepping motor.

  The medal auxiliary storage case switch 75 penetrates a switch through hole (not shown) of the medal auxiliary storage case 52. The medal auxiliary storage switch 75 detects whether or not the medal auxiliary storage 52 is full of medals.

  A power switch 53a is connected to the power board 53b of the power supply device 53. The power switch 53a is turned on when the pachi-slot 1 is supplied with necessary power.

  Further, on the main control board 71, via the door relay terminal board 68, a medal selector 201, a door opening / closing monitor switch 67, a BET switch 77, a settlement switch 78, a start switch 79, a stop switch board 80, a game operation display board 81. And the sub relay board 61 is connected. The door open / close monitor switch 67 and the sub relay board 61 have been described above, and thus their description is omitted. The circuit configuration of the medal selector 201 will be described later.

  The BET switch 77 detects that the BET button 22 has been pressed by the player. The settlement switch 78 detects that the settlement button 27 has been pressed by the player. The start switch 79 detects that the start lever 23 has been operated by the player (start operation).

  The stop switch board 80 is a board that constitutes a circuit for stopping a rotating reel and a circuit for displaying a stoppable reel by an LED or the like. The stop switch board 80 is provided with a stop switch. The stop switch detects that the stop buttons 19L, 19C, 19R have been pressed by the player (stop operation).

  The game operation display board 81 displays the number of inserted medals on the 7-segment display 24 when accepting the insertion of medals, when the three reels 3L, 3C, 3R are rotatable and when replaying. It is a substrate for making. The 7-segment display 24 and the LED 82 are connected to the game operation display board 81. The LED 82 lights, for example, a mark indicating the start of a game, a mark for performing a replay, or the like.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. A sound I / O board 84, LED boards 62A, 62B, 62C, and a 24h door opening / closing monitoring unit 63 are connected to the sub control board 72 via a sub relay board 61. Since the LED boards 62A, 62B, 62C and the 24h door opening / closing monitoring unit 63 have been described above, the description thereof will be omitted.

  The sound I / O board 84 outputs sound to a center speaker 58, a board speaker 64, lower speakers 65L and 65R, and speakers (not shown) provided on the front door 2b.

A ROM cartridge substrate 86 and a liquid crystal relay substrate 87 are connected to the sub control substrate 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub control board case 57 together with the sub control board 72.
The ROM cartridge board 86 is a board for managing images for production (video), sound, LED boards 62A and 62B, other LED boards (not shown), and communication data. The liquid crystal relay board 87 is a board that relays the wiring that connects the sub-control board 72 and the liquid crystal display device 11.

<Main control circuit>
Next, the main control circuit 91 configured by the main control board 71 will be described with reference to FIG.
FIG. 15 is a block diagram showing a configuration example of the main control circuit 91 of the pachi-slot 1.

  The main control circuit 91 has a microcomputer 92 installed on the main control board 71 as a main component. The microcomputer 92 includes a main CPU 93, a main ROM 94 and a main RAM 95. The main CPU 93 and the hopper device 51 described above constitute the game medium payout device of the present invention.

  In the main ROM 94, a control program executed by the main CPU 93 (for example, a program for executing the above-mentioned internal lottery process), a data table, and various control commands (commands) to the sub-control circuit 101 are transmitted. Data and the like are stored. The main RAM 95 is provided with a storage area for storing various data such as an internal winning combination determined by executing the control program.

  A clock pulse generation circuit 96, a frequency divider 97, a random number generator 98, and a sampling circuit 99 are connected to the main CPU 93. The clock pulse generation circuit 96 and the frequency divider 97 generate clock pulses. The main CPU 93 executes the control program based on the generated clock pulse. The random number generator 98 generates a random number in a predetermined range (for example, 0 to 65535). The sampling circuit 99 extracts one value from the generated random numbers.

The main CPU 93 counts the number of times the pulse is output to the stepping motor of each reel 3L, 3C, 3R after detecting the reel index. Thereby, the main CPU 93 manages the rotation angle of each reel 3L, 3C, 3R (mainly, how many symbols the reel has rotated).
The reel index is information indicating that the reel has rotated once. This reel index is provided, for example, with an optical sensor having a light emitting portion and a light receiving portion, and is provided at a predetermined position of each reel 3L, 3C, 3R. It is detected by a reel position detection unit (not shown) having a detection piece interposed therebetween.

  Here, the management of the rotation angles of the reels 3L, 3C, 3R will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 95. Then, each time the pulse counter counts the output of a predetermined number of times (for example, 16 times) required for rotating one symbol, the symbol counter provided in the main RAM 95 is incremented by one. The symbol counter is provided for each reel 3L, 3C, 3R. The value of the symbol counter is cleared when the reel index is detected by the reel position detector (not shown).

  In other words, in the present embodiment, by managing the symbol counter, the number of symbols rotated after the reel index is detected is managed. Therefore, the position of each symbol on each reel 3L, 3C, 3R is detected with reference to the position where the reel index is detected.

  As described above, when the maximum number of sliding pieces is set to 4 symbols, the symbol of the left reel 3L in the middle of the reel display window 4 when the left stop button 19L is pressed, and its 4 symbols Each symbol within the range up to the previous symbol is a symbol that can be stopped in the middle of the reel display window 4.

  Further, when the determination result is input from the control LSI 234 of the medal selector 201 as described later, the main CPU 93 causes the gaming machine to mistakenly recognize that the regular game medium is used based on the input determination result. Detect fraudulent acts of playing games.

<Sub control circuit>
Next, the sub control circuit 101 configured by the sub control board 72 will be described with reference to FIG.
FIG. 16 is a block diagram showing a configuration example of the sub control circuit 101 of the pachi-slot 1.

  The sub control circuit 101 is electrically connected to the main control circuit 91, and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 91. The sub control circuit 101 basically includes a sub CPU 102, a sub RAM 103, a rendering processor 104, a drawing RAM 105, and a driver 106.

  The sub CPU 102 controls the output of video, sound, and light according to the control program stored in the ROM cartridge board 86 in response to the command transmitted from the main control circuit 91. The ROM cartridge board 86 is basically composed of a program storage area and a data storage area.

  A control program executed by the sub CPU 102 is stored in the program storage area. For example, in the control program, a main board communication task for controlling the communication with the main control circuit 91, and a performance registration task for extracting a random number value for performance and determining and registering the performance content (performance data). Is included. In addition, a drawing control task for controlling display of an image by the liquid crystal display device 11 (see FIG. 2) based on the decided effect contents, a lamp control task for controlling light output by a light source such as the LED 85, and speakers 58, 64, 65L. , 65R, and the like, including a voice control task for controlling the output of sound by a speaker.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data forming each effect content, and a storage area for storing animation data related to image creation. Further, a storage area for storing sound data regarding BGM and sound effects, a storage area for storing lamp data regarding a pattern of turning on / off light, and the like are included.

  The sub RAM 103 is provided with a storage area for registering the decided effect contents and effect data, and a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 91.

  The sub CPU 102, the rendering processor 104, the drawing RAM (including a frame buffer) 105, and the driver 106 create a video according to the animation data specified by the effect contents, and display the created video on the liquid crystal display device 11.

  In addition, the sub CPU 102 causes the speakers 58, 64, 65L, 65R and the like to output sounds such as BGM according to the sound data specified by the effect contents. Further, the sub CPU 102 controls turning on and off of the light source such as the LED 85 according to the lamp data specified by the effect contents.

<Circuit configuration of medal selector>
Next, the circuit configuration of the medal selector 201 will be described with reference to FIG.
FIG. 17 is a block diagram showing a circuit configuration example of the medal selector 201.

As shown in FIG. 17, the medal selector 201 includes a camera unit 209 and a medal solenoid 208.
Further, the medal selector 201 is connected to the main control board 71 via the door relay terminal plate 68. That is, the medal selector 201 is electrically connected to the main control circuit 91. Therefore, the main control circuit 91 can set the medal solenoid 208 of the medal selector 201 to the ON state or the OFF state.

  The camera unit 209 includes a control LSI 234, a CMOS image sensor 232, and an LED 233. The control LSI 234 of the camera unit 209 is composed of an ASIC (Application Specific Integrated Circuit) and is electrically connected to the CMOS image sensor 232 and the LED 233. The control LSI 234 controls the light emission of the LED 233. In addition, the control LSI 234 determines whether the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232, and the determination result is output from the output PORT assigned to the GPIO 250. When a predetermined output condition, which will be described later, is satisfied, the signal is output to the main control board 71 via the door relay terminal board 68. The CMOS image sensor 232 used in the present embodiment is a CMOS image sensor having a resolution of 648 × 488 pixels and a frame rate of 240 fps (Frames Per Second).

<Circuit configuration of control LSI>
Next, the circuit configuration of the control LSI 234 will be described with reference to FIG.
FIG. 18 is a block diagram showing a circuit configuration example of the control LSI 234.

  The control LSI 234 includes a host controller 241, an image recognition DSP (digital signal processor) circuit 242, an SRAM (Static Random Access Memory) 243 to which a backup power supply (not shown) is connected, a flash memory 244, and an ISP (Image Signal Processing) circuit 245. And a medal counting circuit 246. The control LSI 234 also includes a color recognition circuit 247, a fisheye correction scaler circuit 248, an image recognition accelerator circuit 249, and a GPIO (General Purpose Input / Output) 250. The devices constituting these control LSIs 234 are connected to each other via a bus, and in the control LSI 234 of this embodiment, AXI (Advanced eXtensible Interface) is adopted as a bus protocol.

  The control LSI 234 also includes an ISI (Image Sensor Interface) circuit 251. The ISI circuit 251 is electrically connected to the CMOS image sensor 232 and the ISP circuit. The ISI circuit 251 converts the image data output from the CMOS image sensor 232 by the LVDS (Low voltage differential signaling) method into an RGB Bayer image and outputs the RGB Bayer image to the ISP circuit 245.

<ISP circuit>
When receiving the RGB Bayer image from the ISI circuit 251 (inputting the RGB Bayer image), the ISP circuit 245 outputs a VSYNC (Vertical Synchronization) interrupt signal to the host controller 241.
Further, the ISP circuit 245 performs an image correction process of performing a lens distortion correction process and a projective transformation (homography) process on the RGB Bayer image output from the ISI circuit 251.

  The lens distortion correction process is a process for correcting the distortion caused by the characteristics of the lens in the camera unit 209 on the image data captured by the CMOS image sensor 232 in order to improve the accuracy of various determination / determination processes described later. is there.

  For example, when a convex lens is used as the lens of the camera unit 209, the thickness at the end of the lens is smaller than the thickness at the center of the lens, so that distortion as shown in FIG. 19 occurs. In FIG. 19, the image pickup area A1 of the CMOS image sensor 232 and the image data G1 of the image pickup area A1 picked up by the CMOS image sensor 232 are schematically shown. The black dots in the image data G1 represent the locations corresponding to the vertices of each lattice in the imaging area A1.

  As shown in FIG. 19, in the image data G1, a relatively large amount of distortion is generated at the end portion as compared with the central portion. The ISP circuit 245 processes the image data G1 (received RGB Bayer image) by performing lens distortion correction processing based on various correction parameters set in advance. Specifically, the image data G1 is complemented so that the positions of the black dots of the image data G1 are at the same positions as the vertices of the grid of the corresponding imaging region A1. This suppresses the influence of this distortion on various determination processes described later.

  It should be noted that various correction parameters are preliminarily defined in a program on the basis of prior characteristic evaluation of the lens adopted in the camera unit 209. The various correction parameters may be stored in the flash memory 244 and referred to by the ISP circuit 245 during the lens distortion correction processing.

The projective transformation process is a process of correcting the image data so that the displacement of the mounting position of the camera unit 209 does not affect the accuracy of various determination / determination processes described later.
For example, when the camera unit 209 is attached to the cancel shooter 206 at an angle that is not a suitable angle, as shown in FIG. 20A, an image region A2 necessary for various determination / determination processes described later is distorted and imaged. There is a case. In the projective transformation process, this distortion is corrected, and the image data is complemented in a mode suitable for various discrimination / determination processes described later.

  Specifically, in the projective transformation process, the ISP circuit 245 analyzes the RGB Bayer image after the lens distortion correction process and detects the position (coordinates: x, y) of at least four reference markers 260 in this RGB Bayer image. To do.

Next, at the position (coordinates: u, v) of the reference marker 260 in the image data suitable for improving the accuracy of various determination processes, which will be described later and are defined in advance on the program, corresponding to the detected four reference markers. Based on the above, the conversion coefficients a, b, c, d, e, f, g, and h in the following equations 1 and 2 are calculated.
u = (x × a + y × b + c) / (x × g + y × h + 1) Equation (1)
v = (x × d + y × e + f) / (x × g + y × h + 1) Equation (2)

  Then, the calculated conversion coefficients a, b, c, d, e, f, g, h and the coordinate value of each pixel in the RGB Bayer image after the lens distortion correction processing are substituted into the above equations 1 and 2. , The converted coordinates for each pixel are calculated, and this RGB Bayer image is processed so that each pixel is positioned at the calculated converted coordinates. FIG. 20B schematically shows the image area A2 shown in FIG. 20A in the RGB Bayer image after the projective transformation process.

  In the present embodiment, a mode has been described in which the position (coordinates: u, v) of the reference marker 260 in the image data suitable for improving the accuracy of various determination processes is defined on the program. However, instead of this, for example, the position of the reference marker 260 may be stored in the flash memory 244 and referred to by the ISP circuit 245 during the projective conversion process.

  Next, the ISP circuit 245 performs color conversion processing for converting the RGB Bayer image after lens distortion correction processing and projective conversion processing into various formats. In the color conversion processing, the ISP circuit 245 converts the RGB Bayer image into image data (YUV image data) corresponding to the YUV color space, and data relating to the luminance in this YUV image data (hereinafter, “grayscale image data”). May be called) is output to the medal count circuit 246. Further, the grayscale image data is stored in the SRAM 243. The SRAM 243 is provided with a storage area capable of storing a predetermined number of grayscale image data. When the number of grayscale image data stored in the SRAM 243 reaches the upper limit number, the stored order is overwritten from the oldest grayscale image data.

  In the color conversion process, the ISP circuit 245 converts the RGB Bayer image into image data (HSV color space) corresponding to a color space (HSV color space) composed of three components (H: hue, S: saturation, V: lightness). Image data) and outputs the HSV image data to the color recognition circuit 247.

<Color recognition circuit>
The color recognition circuit 247 performs color determination processing based on the hue and saturation in the HSV image data output from the ISP circuit 245. The color determination processing includes medal detection processing, threshold determination processing, saturation / hue multiplication processing, color template generation processing, and color template comparison processing.

(1) Medal Detection Processing In the color determination processing, the color recognition circuit 247 causes the SRAM 243 to store the HSV image data received (input) from the ISP circuit 245. The SRAM 243 is provided with a storage area capable of storing a predetermined number of HSV image data. When the number of HSV image data stored in the SRAM 243 reaches the upper limit number, the stored order is overwritten with the oldest HSV image data.

  Further, the color recognition circuit 247 performs medal detection processing for determining whether or not the HSV image data received from the ISP circuit 245 includes a medal image. Specifically, this time, the difference between the HSV image data received from the ISP circuit 245 and the background HSV image data stored in the SRAM 243 is detected, and if the difference portion matches the shape of the medal, It is determined that the image is included. The background HSV image data is HSV image data that does not include the image of the medal, and when the medal is not moving on the medal rail 210, for example, the image captured by the CMOS image sensor 232 immediately after the power is turned on. It is obtained by converting the data into HSV image data by the ISP circuit 245. In the present embodiment, the ISP circuit 245 stores the obtained background HSV image data in the SRAM 243. Whether or not the detected difference portion matches the medal shape is determined by comparing with the HSV image data of the medal shape stored in advance in the flash memory 244.

(2) Threshold value determination processing When it is determined that the HSV image data includes a medal image, the color recognition circuit 247 performs the threshold value determination processing based on the HSV image data. In the threshold determination process, the color recognition circuit 247 determines whether a predetermined area of the medal image in the HSV image data, for example, a substantially square area including the center of the medal in the present embodiment (hereinafter, may be referred to as “medal area”). The values of saturation of all the pixels are integrated, and the values of hue are integrated. Then, the integrated value is divided by the number of pixels in the medal area to calculate the average saturation value and the average hue value, and the position on the threshold graph shown in FIG. 21 is specified based on the calculated values.

  Here, the threshold graph of FIG. 21 is a graph in which the vertical axis represents the saturation value and the horizontal axis represents the hue value. In the threshold graph, the graph is divided into a permissible region and a non-permissible region based on a predetermined formula. In FIG. 21, the background of the permissible area is represented by a white background, and the background of the non-permissible area is represented by shading.

  When the position on the threshold graph based on the average saturation value and the average hue value is within the allowable region, the color determination process is continued. On the other hand, if it is within the non-permissible area, “threshold judgment impossible” is stored in the color judgment area storage area of the SRAM 243 as the judgment result of the color judgment processing, and the color judgment processing ends.

  Instead of the above, for each pixel in the medal area, the color recognition circuit 247 specifies the position on the threshold graph shown in FIG. 21 based on the saturation value and the hue value of the pixel. Good. In this case, it is determined whether or not the number of pixels positioned in the non-allowable area exceeds a predetermined number, for example, 20% of the number of pixels in the medal area. If not, the color determination process is continued and exceeded. In this case, “threshold value determination not possible” may be stored in the SRAM 243 as the determination result of the color determination process, and the color determination process may be ended.

  Further, the allowable area and the non-allowable area in the threshold graph can be set appropriately. For example, in addition to the non-permissible area in FIG. 21, when the saturation value is a predetermined value or more, for example, 90 or more, a non-permissible area may be provided so as to be located in the non-permissible area.

(3) Saturation / Hue Multiplication Processing After the threshold determination processing, the color recognition circuit 247 performs saturation / hue multiplication processing in the threshold determination processing. In the saturation / hue multiplication processing, the saturation value and the hue value of each pixel in the medal area are multiplied, and the value calculated by the multiplication is stored in the SRAM 243 in association with the position of the pixel. In the following description, a group of data stored by associating the multiplication value of the saturation value and the hue value of each pixel in the medal area with the position of that pixel is referred to as “color determination data”. There is.

(4) Color Template Generation Process The color template generation process is a process of generating a color template used in the color template comparison process described later. In the color template generation process, the color recognition circuit 247 compares the color determination data for each medal until the number of medals thrown after the power is turned on reaches the specified initial number of medals, which is 50 in the present embodiment, and matches them. Yes, or color determination data that is similar to a predetermined degree is grouped.

  For example, the color recognition circuit 247 compares, with respect to the color determination data for 50 medals, the multiplication value of the saturation value and the hue value for each corresponding pixel position. Then, when the number of multiplication values that match or are within a predetermined error range (for example, ± 5) is a predetermined number or more (for example, 80% or more of all multiplication values), these color determination data are grouped. .

  Next, the color recognition circuit 247 selects the upper four groups in descending order of the number of pieces of color determination data to which they belong. Then, one arbitrary color determination data is selected for each of the selected upper four groups, and the four color determination data are stored as a color template in the storage area of the SRAM 243 storing the color template. Note that instead of selecting one arbitrary color determination data for each of the selected upper four groups, the average value of the color determination data belonging to the same group (the average value of the multiplication values of each pixel) is selected. ) May be calculated to generate the color template. Further, the color template stored in the SRAM 243 may be erased by initialization processing (not shown) of the host controller 241 when the power of the game machine is turned on.

  As described above, by generating a color template, for example, when two types of medals having different markings (patterns) and colors on the front and back are used as regular medals, and the color template is stored in the storage area of the SRAM 243. If not stored, by inserting 50 regular medals after the power is turned on, it is possible to generate four types of color templates for the front and back of these two types of medals. If the color template is not stored in the storage area of the SRAM 243, and one type of 50 regular medals has been thrown in after the power is turned on, two types of colors for the front and back of this regular medal are provided. A template is generated, and two types of generated color templates are used in the color template comparison process described below.

  When the color template is not stored in the storage area of the SRAM 243, the color determination data for each medal until the number of medals thrown after the power is turned on reaches the specified initial number of medals, 50 in this embodiment, is It is generated according to an instruction from the host controller 241. When the medal counting circuit 246, which will be described later, determines that “a medal has passed” on the medal rail 210, the host controller 241 has triggered the HSV image data a predetermined time before (that is, a predetermined frame before) the judgment. Is used to instruct the color recognition circuit 247 to generate the color determination data. The predetermined time is set in advance based on experiments and simulations so that the HSV image data before the predetermined time always includes the image of the medal.

  The color determination data is generated through the medal detection process, the threshold determination process, and the saturation / hue multiplication process described above, and is stored in the color determination data storage area of the SRAM 243. The color recognition circuit 247 executes a color template generation process when the number of color determination data stored in the color determination data storage area reaches 50, that is, when the color determination data for 50 medals is created. To do.

(5) Color Template Comparison Processing If it is determined that the medal image is included in the medal detection processing after the color template generation processing, the color recognition circuit 247 performs the color template comparison processing.

  In the color template comparison process, the HSV image data that is determined to include the image of the medal is compared with the color determination data created through the threshold determination process and the saturation / hue multiplication process and the color template. Whether or not they match or are similar to each other by a predetermined degree is determined, and “OK” or “NO” is stored in the color determination storage area of the SRAM 243 as a determination result. In this embodiment, since a maximum of four color templates are used, the determination results for the maximum of four templates are stored in the SRAM 243. In the color template comparison process, the color determination result is stored in the color determination storage area of the SRAM 243. Here, as the color determination result, "Yes" is stored when at least one "Yes" is stored as the determination result for up to four templates, and when all "No" is stored. “No” is stored. Therefore, in one color template comparison process, a maximum of four determination results for a maximum of four color templates and one color determination result based on these determination results are stored. Note that a predetermined number of determination results can be stored in the color determination storage area of the SRAM 243, and when the stored determination results reach the upper limit number, the stored results are overwritten from the earlier determination result.

  For example, the color recognition circuit 247 compares the product of the color determination data, the saturation value in the color template, and the hue value for each associated pixel position. Then, when the number of multiplication values that match or are within a predetermined error range (for example, ± 5) is a predetermined number or more (for example, 80% or more of all multiplication values), it is determined that they match or are similar to a predetermined degree. It should be noted that in this processing, the criterion for determining whether they match or are similar to a predetermined degree can be set as appropriate.

  As described above, in the color determination process, the threshold determination process is performed, the color template comparison process is performed, the color determination data is compared with the color template, and it is determined whether they match or are similar to a predetermined degree. The color recognition circuit 247 constitutes a game medium determination means for determining whether or not the object passing on the medal rail 210 is a regular medal.

<Medal counting circuit>
The medal counting circuit 246 performs counting processing based on the grayscale image data output from the ISP circuit 245. The counting process includes a medal image determination process, a medal position detection process, and an order determination process.

(1) Medal Image Discrimination Processing In the counting processing, the medal count circuit 246 first performs medal image discrimination processing. In the medal image discrimination process, the medal count circuit 246 discriminates whether or not the inputted grayscale image data includes a medal image. Specifically, this time, the difference between the grayscale image data input from the ISP circuit 245 and each pixel of the background grayscale image data stored in the SRAM 243 is detected, and the difference is detected. When the formed shape matches the template data of the medal shape stored in the flash memory 244, it is determined that the image of the medal is included. The background grayscale image data is grayscale image data that does not include a medal image, and when the medal is not moving on the medal rail 210, for example, the CMOS image sensor 232 captures an image immediately after the power is turned on. It is obtained by converting the processed image data into gray scale image data by the ISP circuit 245. In the present embodiment, the ISP circuit 245 stores the obtained background grayscale image data in the SRAM 243. In the present embodiment, the medal counting circuit 246 detects the difference between the background grayscale image data and the input grayscale image data, and the medal image is included depending on whether the detected difference matches the medal shape. It was determined whether or not there is. However, the present invention is not limited to this, and it may be determined that a medal image is included when the number of detected difference pixels is equal to or greater than a certain number.

(2) Medal Position Detection Processing Next, the medal count circuit 246 performs medal position detection processing on the received grayscale image data. In the medal position detection process, the medal counting circuit 246 determines whether or not a medal image is present in a predetermined determination area in the received grayscale image data, and stores the determination result in the SRAM 243.

  The predetermined determination area is a plurality of rectangular areas in the grayscale image data G2, and in this embodiment, as shown in FIGS. 22 to 24, the determination areas A1 to A4, B1 to B4, C1 and C2. , D1 to D4, E and F, a total of 16 determination areas are set. 22A to 22C, 23D to F, and 24G are diagrams for explaining the relationship between the determination area and the medals M that pass through the medal rail 210 and are discharged from the medal exit portion 204c. Further, FIG. 24H is a diagram for explaining the relationship between the medal guided by the medal shoot 202 and the determination area.

  Each determination region is defined in advance by a program by defining the coordinate values (X, Y) of the corners of each determination region in the grayscale image data G2 so that a plurality of pixels are included in the determination region. ing. For example, as shown in FIG. 25, the determination region of C1 includes eight pixels in the region, and the coordinate values of four corners (450,95), (454,95), (450,96), (450 454, 96), the position is defined. In addition, in FIG. 25, one cell of the lattice represents one pixel.

  As shown in FIGS. 22A to 22C, 23D to F, and 24G, the determination areas A1 to A4 and B1 to B4 are below the image of the medal M passing through the medal rail 210 and discharged from the medal exit portion 204c. Are placed so that they overlap. Further, the determination areas C1 and C2 are arranged so as to overlap with the upper portion of the image of the medal M which passes through the medal rail 210 and is ejected from the medal exit portion 204c. The determination areas E and F are arranged so as not to overlap the image of the medal M that passes through the medal rail 210 and is ejected from the medal exit portion 204c.

  Further, as shown in FIG. 24H, the determination area F is arranged below the grayscale image data G2 so as to overlap the image of the medal M when the medal is guided by the medal shoot 202. The determination area E is located above the path of the medal M, and is arranged above the grayscale image data G2 so as to overlap the images of various instruments used for cheating.

  The medal count circuit 246 calculates the difference value of the brightness of each pixel in each determination region of the grayscale image data to be processed and the background grayscale image data, and the calculated difference value is the number of pixels having a threshold value or more, Count for each judgment area. Then, the medal counting circuit 246 determines, for each determination area, whether or not the number of counted pixels is a predetermined number or more. If it is determined that the number of pixels is a predetermined number or more, the medal image is displayed in the determination area. Is present (there is a medal). On the other hand, when it is determined that the number of counted pixels is less than the predetermined number, it is determined that the image of the medal does not exist in the determination area (there is no medal). In the present embodiment, the mode in which the grayscale image data is used in this process has been described, but the present invention is not limited to this. For example, for the color determination that is generated by multiplying the saturation and the hue used in the color determination process described above. Data may be used.

  Further, the medal count circuit 246 performs the medal edge detection process on the determination area determined to have the image of the medal (there is a medal) in the medal position detection process.

  The medal edge detection process is a process of detecting the outer edge of the medal based on the arrangement of pixels whose luminance difference value does not reach the threshold value in the determination area in which it is determined that a medal image exists. In the present embodiment, the moving direction of the medal is from left to right in FIGS. Therefore, if there is at least one pixel on the right side of which the brightness difference value does not reach the threshold value in the determined region where the medal image is present, the medal counting circuit 246 causes the medal counting circuit 246 to determine the outer edge of the front side in the moving direction of the medal. It is determined that there is a medal edge).

  On the other hand, if there is at least one pixel on the left side whose brightness difference value does not reach the threshold value in the determination area in which the medal image is present, the medal counting circuit 246 causes the medal counting circuit 246 to determine the outer edge of the rear side in the moving direction of the medal. Direction medal edge) is present. If there is no pixel whose brightness difference value does not reach the threshold value, the medal counting circuit 246 determines that there is no outer edge of the medal in the determination area.

  For example, in the determination area C1 shown in FIG. 25, if any one of the pixels 5C to 8C located on the right side has a brightness difference value less than the threshold value, the moving direction token Judge that there is an edge. On the other hand, if any one of the pixels 1C to 4C located on the left side has a brightness difference value less than the threshold value, it is determined that there is a post-movement direction medal edge.

  In addition, regarding the determination areas E and F, it is considered that the moving direction of the medal or various appliances is from the top to the bottom in FIGS. When there is even one pixel whose difference value is less than the threshold value, the medal counting circuit 246 determines that there is a lower outer edge (movement destination direction medal edge) in the moving direction of the medal. On the other hand, when there is at least one pixel having a brightness difference value less than the threshold value above the pixel having a brightness difference value greater than or equal to the threshold value, the medal counting circuit 246 causes the medal counting circuit 246 to move the outer edge of the upper side in the moving direction of the medal (after movement). Direction medal edge) is present. In addition, if there is no pixel whose luminance difference value is lower than or equal to the threshold value with respect to pixels whose luminance difference value is greater than or equal to the threshold value, the medal count circuit 246 causes the medal count circuit 246 to determine whether or not there is a medal in the determination area. It is determined that the image exists, but the outer edge of the medal does not exist.

  Then, the medal counting circuit 246, for each judgment area of the input grayscale image data, the above judgment result, that is, the judgment result of whether or not a medal image exists in the judgment area, and the destination medal edge. Alternatively, the determination result as to whether or not the post-movement direction medal edge exists is stored in the SRAM 243 in the order of input. For example, the medal counting circuit 246 stores the data “OFF” in the determination area in which it is determined that the image of the medal does not exist. Further, data “IN” is applied to the determination area determined to have the destination-direction medal edge, data “OUT” is applied to the determination area determined to have the post-movement-direction medal edge, and the medal image. However, the data “ON” is stored in the determination area determined to have no outer edge of the medal. When it is determined in the medal image determination process that the image of the medal is not included, the medal count circuit 246 omits the medal position detection process and stores the data “OFF” in all the determination regions. May be.

  Further, the medal counting circuit 246 omits the judgment of the judgment areas A1 to A4, B1 to B4, C1, C2, D1 to D4 when the medal cannot be inserted, for example, when the credit counter has the maximum value as described later. To do. Further, in this case, the medal counting circuit 246 indicates in the SRAM that the above determination is omitted for the determination areas A1 to A4, B1 to B4, C1, C2, and D1 to D4, that is, it is undetermined. * "Data (specifically, hexadecimal number" FF ") is stored.

  Therefore, the determination area determination result data as shown in FIG. 26 is stored in the SRAM 243 for the eight grayscale image data G2 shown in FIGS. 22A to 22C, 23D to F, 24G, and 24H. For example, with respect to the grayscale image data G2 of FIG. 22A, since it is determined that the destination direction medal edge exists in the determination areas A1 and A2, the data “IN” (specifically, a hexadecimal number) “01”) is stored, and it is determined that no medal image exists in the other determination areas. Therefore, the data “OFF” (specifically, “00” in hexadecimal) is stored. Remembered.

  Further, regarding the grayscale image data of FIG. 23E, since it is determined that the medal image does not exist in the determination areas A1 to A4, E, and F, the data “OFF” is stored. Further, for the determination areas B1, B2, C1 and C2, since it is determined that there is a post-movement direction medal edge, the data “OUT” (specifically, the hexadecimal number “02”) is stored. To be done. In addition, the determination areas B3, B4, D1 to D4 have a medal image, but it is determined that there is no outer edge of the medal, so the data "ON" (specifically, a hexadecimal number " 03 ”) is stored.

  Further, regarding the grayscale image data G2 shown in FIG. 24H, since it is determined that the medal image exists in the determination area F but the outer edge of the medal does not exist, the data “ON” is stored. Further, for the judgment areas A1 to A4, B1 to B4, C1, C2, D1 to D4, data “*” indicating that the judgment is not made is stored.

  Note that the grayscale image data G2 of FIGS. 22A to 22C, 23D to F, and 24G shows the medal counting circuit from the ISP circuit 245 when a medal passes on the medal rail 210 and is ejected from the medal exit portion 204c. For the convenience of explanation, seven grayscale image data G2 are extracted from the grayscale image data G2 received by the H.246. That is, in the same case, the grayscale image data received by the medal counting circuit 246 exists in addition to the grayscale image data G2 shown in FIGS. 22A to 22C, 23D to F, and 24G.

  In addition, the SRAM 243 is provided with a storage area for storing the above-described determination result for a predetermined number of grayscale image data as the determination area determination result data. When the determination result stored in the SRAM 243 reaches the upper limit number, the stored order is overwritten with the determination result relating to the old grayscale image data.

(3) Order Determination Process After the medal image detection process and the medal position detection process, the medal count circuit 246 performs the order determination process. In the order determination process, in a predetermined number of grayscale image data arranged in time series, the transition mode of the data of “IN”, “OUT”, “ON”, “OFF” for each determination region is a predetermined transition. It is determined whether the medals have passed through the medal rail 210.

  Here, as a mode of the predetermined transition, in the present embodiment, the medal count determination table shown in FIG. 27 is converted into a numerical value and stored in the flash memory 244. In the medal count determination table, “IN” and “IN” in each determination region on the 14 grayscale image data arranged in time series when the medal passes on the medal rail 210 and is ejected from the medal exit portion 204c. The mode of transition of data of “OUT”, “ON”, and “OFF” is defined. The mode of transition of these data is defined in advance by simulation, experiment, or the like.

  In the order determination process, the medal count circuit 246 determines the data transition mode in each determination area of the latest 14 grayscale image data stored in the SRAM 243, and the time series 1 defined in the medal count determination table. The transition states of the data corresponding to -14 are compared with each other, and when they completely match, it is determined that the medal has passed. If they do not match, it is determined that “an abnormality has occurred”. When they do not match, for example, the first half of the data transition mode in each determination region of the latest 14 grayscale image data (hereinafter, may be referred to as “comparison target data transition mode”) Corresponds to the transition mode of the data corresponding to the time series 1 to 8 defined in the medal count determination table, but the following part is the data corresponding to the time series 8 to 4 defined in the medal count determination table. There is a case where it matches the transition mode (hereinafter, this case may be referred to as “time-series backward movement”). If they do not match, for example, the first half of the transition mode of the comparison target data matches the transition mode of the data corresponding to the time series 1 to 7 defined in the medal count determination table, When the following part matches the transition mode of the data corresponding to the time series 10 to 14 specified in the medal count judgment table, that is, the data corresponding to the time series 8 and 9 specified in the medal count judgment table May be missing. When they do not match, for example, the first half of the transition mode of the comparison target data matches the transition mode of the data corresponding to the time series 1 to 8 defined in the medal count determination table, There are cases where the following portions all match the transition mode of the data corresponding to the time series 9 defined in the medal count determination table, that is, the same transition mode overlaps. The above-described time-series backward movement corresponds to an existing medal backward error, and when the same transition mode overlaps, it corresponds to an existing medal jamming error. Further, if the above data is missing, it is an error that cannot be detected by the existing medal selector, and the medal selector 201 that can detect the error is superior in error detection performance to the existing medal selector. Can be said.

  In addition, the medal count circuit 246 defines the mode of data transition in each judgment area of the latest four grayscale image data stored in the SRAM 243 and the medal count judgment table when a medal cannot be inserted. The transition states of the data corresponding to the time series E1 to E4 that are present are compared, and if they completely match, it is determined that “the medal was guided by the medal shoot 202”.

  If the number of grayscale image data stored in the SRAM 243 is less than a predetermined number, for example, less than 4 or 14, the transition modes do not match due to the insufficient number of data. In the comparison process, it is not determined that “the medal has passed” or “the medal has been guided to the medal shoot 202”. In this case, the comparison process may be omitted.

  Further, the medal counting circuit 246 stores the data “IN”, “OUT”, or “ON” in the determination area E of the most recent grayscale image data stored in the SRAM 243. , It is determined that an abnormality has occurred.

  Further, in the order determination process, the medal count circuit 246 stores the above determination result in the order determination process in the SRAM 243 as the determination result of the counting process. That is, in the SRAM 243, as the determination result of the counting process, “a medal has passed” (a hexadecimal number is “01” as a concrete numerical value) and “a medal has been guided to the medal shoot 202” (a concrete numerical value). Is stored in hexadecimal number "02") and "abnormality has occurred" (specifically, hexadecimal number "10") is stored. Note that, here, the case where it is determined that the medal has passed is, for example, the case where the main control circuit 91 inserts a medal while the medal can be inserted. Further, when it is determined that the medal has been guided to the medal chute 202, the main control circuit 91 is in a state where the medal can be inserted, and an illegal medal having an outer diameter smaller than the prescribed medal is inserted, or This is a case where a medal is inserted in a state where the control circuit 91 cannot insert the medal. In addition, when it is determined that "an abnormality has occurred", it is compared with the case where some foreign matter is detected outside the range through which the medal passes or the mode of data transition defined in the above medal counter determination table. This is a case where the transition mode of the target data does not match.

  As a result of the comparison, instead of determining that the medal has passed or that the medal was guided by the medal shoot 202 in the case of a perfect match, a predetermined degree, for example, a degree of match of 80% or more In this case, it may be determined in consideration of a predetermined determination margin that the "medal has passed" or "guided by the medal shoot 202".

  Further, in the medal position detection process, the medal edge detection process may be omitted. In this case, the medal counting circuit 246 causes the SRAM 243 to store the data “OFF” for the determination area determined to have no medal image and the “ON” for the determination area determined to have the medal image. Data is stored. Then, in the medal count determination table shown in FIG. 27, the manner of transition of the “ON” and “OFF” data in each determination region is defined.

  Further, in the order determination processing, instead of the comparison using the medal count determination table shown in FIG. 27, the order of the determination areas in which the data of “ON” is stored is defined in advance, and the predetermined order and the actual The passage of the medal may be determined by comparing with the order of the determination areas in which the data of “ON” is stored. In this case, the order defined in advance is determined by grouping the determination areas A1 to A4 into the A area, the determination areas B1 to B4 into the B area, the determination areas C1 and C2 into the C area, and the determination areas D1 to D4 into the D area. May be specified in. For example, in the order defined in advance, all of the areas A to D are “OFF”, then only the area A is “ON”, then the areas A, B and C are “ON”, then the areas B, C and D. May be "ON", then only the D area may be "ON", and finally all of the A to D areas may be "OFF". In this case, the area A being “ON” means that “ON” data is stored in any of the determination areas A1 to A4.

  Further, the number, shape, and arrangement location of the determination areas set on the grayscale image data can be appropriately set according to the allowable determination required time and the required determination accuracy. For example, in FIGS. 22A to 22C, FIGS. 23D to 23F, and FIGS. 24G and 24H, the determination region may be set to extend vertically from the upper end to the lower end of the grayscale image data G2.

<Fish-eye correction scaler circuit>
The fisheye correction scaler circuit 248 acquires grayscale image data from the SRAM 243 and performs fisheye correction processing for correcting the acquired grayscale image data.

  Further, the fisheye correction scaler circuit 248 performs equalization processing on the grayscale image data that has undergone fisheye correction processing. In the equalization process, the fisheye correction scaler circuit 248 creates reduced image data reduced to 1/2, 1/4, and 1/8.

  Further, the fisheye correction scaler circuit 248 performs bilateral conversion processing on each of the reduced image data created in the equalization processing. In the present embodiment, in order to remove noise from the reduced image data, a Gaussian filter having a 3 × 3 kernel (a kernel in image processing, not a kernel indicating an OS function) shown in FIG. 28 is used. However, the Gaussian filter has a drawback that edges in the image data are inconspicuous (blurred). Therefore, in order to eliminate this drawback, a bilateral filter represented by the following Expression 3 is adopted as a processing algorithm of the bilateral conversion processing. That is, the bilateral filter is a filter that removes noise in image data by using a kernel of a Gaussian filter and performs edge correction and enhancement.

  In Equation 1, the array of image data before bilateral conversion processing is f (i, j), and the array of image data after processing is g (i, j). Further, w represents a kernel size, σ represents a standard deviation, and d represents a difference in brightness value.

  Then, the fish-eye correction scaler circuit 248 causes the SRAM 243 to store the reduced image data subjected to the equalization processing. The SRAM 243 is provided with a storage area capable of storing a predetermined number of reduced image data. When the number of reduced image data stored in the SRAM 243 reaches the upper limit number, the stored order is overwritten from the oldest reduced image data.

<Image recognition DSP circuit>
The host controller 241 uses the reduced image data a predetermined time before the determination (that is, a predetermined frame before) when the medal counting circuit 246 determines that the medal has passed on the medal rail 210. Then, the image recognition DSP circuit is instructed to perform preprocessing. The predetermined time is set in advance based on experiments and simulations so that the reduced image before the predetermined time always includes the image of the medal.

  The image recognition DSP circuit 242 acquires reduced image data (reduced image data reduced to ¼ in this embodiment) from the SRAM 243 in the preprocessing, and detects a circular region from the acquired reduced image data. The filter processing is performed by performing the processing and the nonlinear diffusion filter processing to create the edge image and storing it in the SRAM 243. The image recognition DSP circuit 242 also performs various determination processes described later. In the present embodiment, the image data reduced to 1/4 is used, but the present invention is not limited to this, and the flash memory 244 stores the setting for selecting the reduced image data to be used, and the setting is performed according to the setting. The image data reduced to ½ or the image data reduced to ⅛ may be selected.

(1) Circle Area Detection Processing In the circle area detection processing, the image recognition DSP circuit 242 generates a background difference image indicating a difference between the acquired reduced image data and the reduced background grayscale image data corresponding to the reduced image data. To do. Here, the reduced background grayscale image data is image data obtained by subjecting the background grayscale image data stored in the SRAM 243 to fisheye correction processing and equalization processing by the fisheye correction scaler circuit 248, and to the circle area detection processing. Previously stored in SRAM 243.

  Next, the image recognition DSP circuit 242 binarizes the generated background difference image. Then, as shown in FIG. 29, template matching is performed on the binary background difference image G3 using the binary outline template T1 indicating the outline of the medal. That is, the image recognition DSP circuit 242 specifies where in the background difference image G3, a region similar to the outer shape template T1 exists. In other words, the image recognition DSP circuit 242 specifies where, in the background difference image G3, an area that matches the outer shape of the medal indicated by the outer shape template T1 exists. The outer shape template T1 is stored in the flash memory 244 in advance.

  In template matching, the outer shape template T1 is gradually moved (for example, one pixel (pixel) at a time) in the raster scan direction on the background difference image G3. In other words, the image recognition DSP circuit 242 raster-scans the outline template T1 on the background difference image G3. At this time, the image recognition DSP circuit 242 generates an AND image of the outline template T1 and the partial region of the background difference image G3 that overlaps with the outline template T1 at each position of the outline template T1. As a result, a plurality of binary AND images are generated. Then, the image recognition DSP circuit 242 causes the background difference of the outer shape template T1 used in the generation of the AND image having the largest number of pixels (high-luminance pixels) having the pixel value of “1” among the plurality of generated AND images. The position on the image G3 is specified. This position is a position where a region similar to the outer shape template T1 exists in the background difference image G3.

  Then, the image recognition DSP circuit 242 detects a partial area in the acquired reduced image data existing at the same position as the specified position as a circular area. In other words, the image recognition DSP circuit 242 detects, as a circular area, a partial area in the reduced image data that overlaps with the outer shape template T1 when the outer shape template T1 is arranged in the reduced image data at the same position as the specified position. . At this time, in the partial area, the one in which the pixel value of each pixel outside the circle indicated by the outer shape template T1 on the partial area is zero may be set as the circular area. The circular area extracted by the image recognition DSP circuit 242 is a grayscale image. In the present embodiment, the outer shape of the circular region is a quadrangle, but it may be another shape such as a circle.

  It should be noted that another method may be adopted as a method for extracting the circular area from the acquired reduced image data. For example, an extraction method that uses the outer shape of the medal may be adopted. In this extraction method, first, edge detection is performed on the acquired reduced image data to generate an edge image. As a method of generating an edge image, for example, the Sobel method, Laplacian method, Canny method or the like is used. Next, a circular area is extracted from the generated edge image. As a method for extracting the circular area, for example, Hough transform is used. Then, the circular area in the acquired reduced image data that exists at the same position as the position of the circular area in the edge image is set as the circular area.

  Further, an extraction method of extracting a circular area from the reduced image data acquired by using the background subtraction method and labeling may be adopted. In this extraction method, first, a background difference image indicating the difference between the acquired reduced image data and the reduced background grayscale image data is generated, and the generated background difference image is binarized. Then, labeling such as 4-connection is performed on the binary background difference image. Then, the partial area of the acquired reduced image data existing at the same position as the position of the connected area (independent area) obtained as a result of labeling in the binary background difference image is set as the circular area.

(2) Filter processing The image recognition DSP circuit 242 performs filter processing after the circular area detection processing. The filter process includes a 3σ correction process and a non-linear diffusion filter process.
First, in the 3σ correction process, the image recognition DSP circuit 242 cuts out the image data of the circular area in the acquired reduced image data based on the circular area detected by the circular area detection processing. Hereinafter, the cut-out image data may be referred to as circle area image data.

Next, the image recognition DSP circuit 242 creates a normal distribution (see FIG. 30) with respect to the luminance value in the cut out circular area image data centered on the average value of the data in a certain range. Here, 3σ is three times the standard deviation, and almost all the data belong to the range of the average value ± 3σ (when the variation is a normal distribution, 99.7% of the data are within this range). Belong to).
Then, the luminance of a pixel whose luminance value is smaller than −3σ, for example, the luminance of a pixel of −4σ is replaced with the luminance value of −3σ. Further, the brightness of a pixel whose brightness value is larger than 3σ, for example, the brightness of a pixel of 4σ is replaced with the brightness value of 3σ. By doing so, it is possible that pixels with extremely large brightness values (pixels that are too bright) and pixels with extremely small brightness values (pixels that are too dark), which are irregular data, affect subsequent processing. Can be suppressed.

  Next, the image recognition DSP circuit 242 performs non-linear diffusion filter processing on the circular region image data after the 3σ correction processing to create an edge image X in the X (vertical) direction and an edge image Y in the Y (horizontal) direction. To do.

FIG. 31A schematically shows the circular area image data after the 3σ correction processing. In FIG. 31A, each square in the grid represents a pixel. Further, FIG. 31B shows the coefficients for the edge image X. Here, assuming that the brightness values of the pixels A1 to A8 and P in FIG. 31A are a1 to a8 and p, respectively, the brightness value of the target pixel P in the edge image X is calculated by using the coefficient for the edge image X It is calculated by the following equation 4.
P luminance (PX) = a1 * (-3) + a2 * 0 + a3 * 3 + a4 * (-10) + p * 0 + a5 * 10 + a6 * (-3) + a7 * 0 + a8 * 3 ... Equation (4)

  The image recognition DSP circuit 242 creates the edge image X by calculating the brightness using Expression 4 for all the pixels of the circular area image data after the 3σ correction processing.

FIG. 31C shows the coefficients for the edge image Y. Here, assuming that the brightness values of the pixels A1 to A8 and P in FIG. 31A are a1 to a8 and p, respectively, the brightness value of the pixel of interest P in the edge image Y is calculated as follows using the coefficient for the edge image Y. It is calculated by the following equation 5.
P luminance (PY) = a1 * (-3) + a2 * (-10) + a3 * (-3) + a4 * 0 + P * 0 + a5 * 0 + a6 * 3 + a7 * 10 + a8 * 3 ... Equation (5)

  The image recognition DSP circuit 242 creates the edge image Y by calculating the brightness using Expression 5 for all the pixels of the circular area image data after the 3σ correction processing.

  After creating the edge image X and the edge image Y, the image recognition DSP circuit 242 creates the edge image XY from both images. The brightness PXY of each pixel in the edge image XY is calculated by the following equation 6 when the brightness value of the pixel in the edge image X is PX and the brightness value of the pixel in the edge image Y at the same position is PY. be able to.

The image recognition DSP circuit 242 creates the edge image XY by calculating the brightness PXY using the above equation 6 for all the pixels of the edge image X and the edge image Y, and stores the created edge image XY in the SRAM 243. Let
The various determination processes performed by the image recognition DSP circuit 242 will be described later.

<Image recognition accelerator circuit>
The image recognition accelerator circuit 249 performs processing related to the gradient average image data and processing related to the edge gradient image.

[Processing relating to gradient average image data]
The process related to the gradient average image data includes a rotation image generation process, a gradient average image data generation process, and a gradient average image template generation process.

(1) Rotated Image Generation Process In the rotated image generation process, the image recognition accelerator circuit 249 acquires the edge image XY from the SRAM 243, rotates the acquired edge image XY in 1 degree units, and outputs a 360 degree rotated image. To generate.

(2) Gradient Average Image Data Generation Process In the gradient average image data generation process, the image recognition accelerator circuit 249 cumulatively adds (overlaps) the rotated images for 360 degrees generated in the rotated image generation process to obtain the gradient average. Generate image data. As an example of the gradient average image data, FIG. 32B shows the gradient average image data of the regular medal shown in FIG. 32A. Then, the image recognition accelerator circuit 249 causes the SRAM 243 to store the generated gradient average image data.

(3) Gradient Average Image Template Generation Process The gradient average image template generation process is a process of generating a gradient average image template which is image data used in the determination process of the image recognition DSP circuit 242 described later.

  In the gradient average image template generation processing, the image recognition accelerator circuit 249 compares the 50 gradient average image data stored in the SRAM 243 (that is, relating to 50 medals) with each other and agrees or is similar to a predetermined degree. The gradient average image data to be grouped. Next, the image recognition accelerator circuit 249 selects the upper four groups in descending order of the number of gradient average image data to which they belong. Then, arbitrary one gradient average image data is selected for each of the selected upper four groups, and the four gradient average image data are used as the gradient average image template in the storage area of the SRAM 243 for storing the gradient average image template. Remember. It should be noted that instead of selecting any one gradient average image template for each of the selected upper four groups, the average value of the gradient average image data belonging to the same group (the average value of the luminance of each pixel) The gradient average image template may be generated by calculating Further, the gradient average image template stored in the SRAM 243 may be erased by initialization processing (not shown) of the host controller 241 when the power of the gaming machine is turned on.

  As described above, by generating the gradient average image template, for example, when two types of medals having different markings (patterns) on the front and the back are used as regular medals, 50 regular medals are thrown after the power is turned on. By doing so, a maximum of four types of gradient average image templates for the front and back of these two types of medals can be generated. In addition, when 50 regular medals are thrown in after the power is turned on, two types of gradient average image templates for the front and back of the regular medals are generated, and the gradient average image template comparison process described later is performed. Then, two types of generated gradient average image templates are used.

  Here, when the gradient average image template is not stored in the storage area of the SRAM 243, the gradient average image template generation process is performed until the number of medals thrown after the power is turned on reaches the prescribed initial number, 50 in this embodiment. Of the gradient average image data. The image recognition accelerator circuit 249 stores the generated gradient average image data in the gradient average image template generation data storage area of the SRAM 243 until the number of the gradient average image data generated in the gradient average image data generation process reaches 50 pieces. Further, the image recognition accelerator circuit 249 performs a gradient average image template generation process when 50 pieces of gradient average image data are stored in the gradient average image template generation data storage area of the SRAM 243. The image recognition accelerator circuit 249 stores the gradient average image data generated by the gradient average image data generation process in the determination target gradient average image data storage area of the SRAM 243 after executing the gradient average image template generation process. Note that, in the present embodiment, a mode has been described in which, when 50 pieces of gradient average image data are stored in the SRAM 243, the gradient average image data that match or are similar to a predetermined degree are grouped to generate a gradient average image template. However, not limited to this, each time the gradient average image data is generated, it is compared with the previously stored gradient average image data, and the gradient average image data that match or are similar to each other by a predetermined degree are grouped to obtain the gradient average image data. Image templates may be generated.

[Processing related to edge gradient image]
The processing related to the edge gradient image includes polar coordinate conversion processing, Scharr conversion processing, HOG conversion processing, and HOG template generation processing.

(1) Polar Coordinate Conversion Processing In the polar coordinate conversion processing, the image recognition accelerator circuit 249 acquires the edge image XY from the SRAM 243, converts the acquired edge image XY from orthogonal coordinates to polar coordinates, and creates polar coordinate image data. Specifically, the image recognition accelerator circuit 249 polar coordinates (r, φ) that represents the orthogonal coordinates (x, y) of each pixel of the edge image XY by the radius r and the angle φ from the reference position. ). The relationship between polar coordinates (r, φ) and Cartesian coordinates (x, y) is expressed by the following equations 7 and 8.
x ＝ r cos (φ) ・ ・ ・ Equation (7)
y ＝ r sin (φ) ・ ・ ・ Equation (8)

  Then, the image recognition accelerator circuit 249 stores the created polar coordinate image data in the SRAM 243.

(2) Scharr conversion processing In the Scharr conversion processing, the image recognition accelerator circuit 249 acquires polar coordinate image data from the SRAM 243 and creates an edge polar coordinate image X in the X (vertical) direction and an edge polar coordinate image Y in the Y (horizontal) direction. To do. Therefore, the image recognition accelerator circuit 249 that performs the Scharr conversion process constitutes a directional image separation unit that separates the polar coordinate image into a vertical image and a horizontal image.
Note that the manner in which the edge polar coordinate image X and the edge polar coordinate image Y are created in the Scharr conversion processing is the same as the manner in which the edge image X and the edge image Y are created in the above-described nonlinear diffusion filter processing, including the coefficients used. The description is omitted here.

(3) HOG conversion processing In the HOG conversion processing, the image recognition accelerator circuit 249 creates an edge gradient image and performs HOG conversion on the created edge gradient image. Here, the HOG (Histograms of Oriented Gradients) conversion is to histogram the direction of the gradient of the brightness of the local area (cell) in the image data, and for image matching involving HOG conversion, a local shape change ( It has the characteristics that it is strong against geometrical transformation) and is not easily affected by changes in lighting.

  Specifically, an edge gradient image is created from the edge polar coordinate image X and the edge polar coordinate image Y created by the Scharr conversion process. If the luminance value of the pixel in the edge polar coordinate image X is QX and the luminance value of the pixel in the edge polar coordinate image Y at the same position is QY, the luminance of each pixel in the edge gradient image is represented by the following equation 9: Can be calculated by

Further, the gradient angle of each pixel in the edge gradient image can be calculated by the following Expression 10.
Gradient angle = tan ⁻¹ (QY / QX) ... Equation (10)

  In FIG. 33, the created edge gradient image G4 is schematically shown. The image recognition accelerator circuit 249 creates a histogram in the direction of the brightness gradient in each local area, using the rectangular frame S indicated by the two-dot chain line in the created edge gradient image G4 as a local area (cell). . Then, the set of created histograms is stored in the SRAM 243.

[HOG template generation process]
The HOG template generation process is a process of generating a HOG template used in the determination process of the image recognition DSP circuit 242 described later.

  In the HOG template generation process, the image recognition accelerator circuit 249 compares the 50 sets of histograms (that is, relating to 50 medals) stored in the SRAM 243 with each other, and sets the histograms that match or are similar to each other to a predetermined degree. To group. Next, the image recognition accelerator circuit 249 selects the upper four groups in descending order of the number of histogram sets to which they belong. Then, for each of the selected upper four groups, any one set of histograms is stored as a HOG template in the storage area of the SRAM 243 storing the HOG template. It should be noted that instead of selecting any one set of histograms for each of the selected top four groups, the average value of the set of histograms belonging to the same group (the average value of the gradient strength in the same local region) is calculated. By doing so, a HOG template may be generated. Further, in the present embodiment, when 50 sets of histogram sets are stored in the SRAM 243, the stored histogram sets are compared with each other and the set of matching or similar histograms are grouped to generate a HOG template. Aspects have been described. However, the present invention is not limited to this, and each time a set of histograms is generated, the set of histograms stored in advance is compared, and a set of histograms that match or are similar to a predetermined degree are grouped to generate a HOG template. .

  By generating the HOG template as described above, for example, when two kinds of medals having different markings (patterns) on the front and the back are used as regular medals, and the HOG template is stored in the storage area of the SRAM 243. If not, by inserting 50 regular medals after the power is turned on, four kinds of HOG templates for the front and back of these two kinds of medals can be generated. Further, when the HOG template is not stored in the storage area of the SRAM 243 and the number of the 50 regular medals thrown after the power is turned on is one, the two types of HOG for the front and back of the regular medals are used. A template is generated, and two types of generated HOG templates are used in the HOG template comparison process described below.

  The matching of the set of histograms or the determination of the degree of similarity is performed by comparing histograms at the same position (local regions at the same position in the edge gradient image) in the set of histograms. Further, the criteria for determination can be set as appropriate. For example, it is possible to determine that both histogram sets match each other on the condition that all histograms are completely matched. Alternatively, it may be determined that the two histogram sets are similar to each other, provided that there is no histogram having a degree of coincidence equal to or less than a predetermined degree, for example, 80% or less.

  Here, the HOG template generation process is performed using a set of histograms related to the edge gradient image until the number of medals thrown after the power is turned on reaches a prescribed initial number, 50 in this embodiment. The image recognition accelerator circuit 249 stores the created histogram set in the HOG template generation data storage area of the SRAM 243 until the set of histograms created in the HOG conversion process reaches 50 sets. Further, the image recognition accelerator circuit 249 performs the HOG template generation process when a set of 50 sets of histograms is stored in the HOG template generation data storage area of the SRAM 243. Note that the image recognition accelerator circuit 249 stores the set of histograms created by the HOG conversion process in the determination target histogram storage area of the SRAM 243 after the HOG template creation process is executed.

<Judgment process by image recognition DSP circuit>
Next, the determination process executed by the image recognition DSP circuit 242 will be described. The determination process includes a gradient average image template comparison process and a HOG template comparison process.

(1) Gradient Average Image Template Comparison Processing In the gradient average image template comparison processing, the image recognition DSP circuit 242 acquires the gradient average image data generated by the image recognition accelerator circuit 249 from the determination target gradient average image data storage area of the SRAM 243. .

  Next, the image recognition DSP circuit 242 calculates the difference between the acquired gradient average image data and the gradient average image template stored in the SRAM 243. Then, the image recognition DSP circuit 242 determines whether or not the gradient average image data and the gradient average image template match or are similar to each other to a predetermined degree, based on the calculated difference value and the threshold value for marking determination. , “Yes” or “No” is stored in the SRAM 243 as the determination result. In the present embodiment, since maximum four gradient average image templates are used, maximum four determination results are stored in the SRAM 243. Further, in the gradient average image template comparison processing, the gradient average determination result is stored in the SRAM 243. Here, in the case where even one “OK” is stored as the determination result for the maximum four templates, “OK” is stored in the SRAM 243 as the gradient average determination result, and all “NO” is stored. “No” is stored in the SRAM 243 as the gradient average determination result. Therefore, in a single gradient average image template comparison process, a maximum of four determination results for a maximum of four gradient average image templates and one gradient average determination result based on these determination results are stored.

  For example, the image recognition DSP circuit 242 compares the brightness of each pixel of the acquired gradient average image data and the gradient average image template (calculates the difference), and determines whether the brightness of these pixels matches from the difference value. Alternatively, it is determined whether or not the difference is within a predetermined range, and if there is a certain number of pixels that match or the difference is within a predetermined range, it is determined that the gradient average image data and the gradient average image template match or are similar to a predetermined degree. . On the other hand, when the number of matching pixels is less than a certain number, it is determined that the gradient average image data and the gradient average image template match or are not similar to a predetermined degree.

(2) HOG Template Comparison Processing In the HOG template comparison processing, the image recognition DSP circuit 242 acquires a set of histograms to be determined from the determination target histogram storage area. Next, it is determined whether or not the acquired set of histograms and the HOG template stored in the SRAM 243 match or are similar to each other by a predetermined degree, and the SRAM 243 stores “OK” or “NO” as the determination result. In the present embodiment, since a maximum of 4 HOG templates are used, a maximum of 4 determination results are stored in the SRAM 243. Further, in the HOG template comparison process, the HOG determination result is stored in the SRAM 243. Here, in the case where even one “OK” is stored as the determination result for the maximum four templates, “OK” is stored in the SRAM 243 as the HOG determination result, and all “NO” is stored. “No” is stored in the SRAM 243 as the HOG determination result. Therefore, in one HOG template comparison process, maximum four determination results for maximum four HOG templates and one HOG determination result based on these determination results are stored.

  Note that the determination of the match or similarity between the acquired set of histograms and the HOG template is the same as the determination of the match or similarity between the set of histograms in the above-described HOG template generation processing, and therefore the description thereof is omitted here.

  As described above, the image recognition DSP circuit 242 that performs the gradient average image template comparison process and the HOG template comparison process constitutes a game medium determination unit that determines whether the object passing on the medal rail 210 is a regular medal. To do.

<GPIO>
The GPIO 250 (see FIG. 18) is a device for inputting / outputting with each device connected to the medal selector 201. For example, the medal count output PORT and the medal determination output PORT of the GPIO 250 are connected to the main control circuit 91 via the door relay terminal board 68. The LED control output PORT of the GPIO 250 is connected to the LED 233 so that the medal selector 201 can control the turning on and off of the LED 233.

<Host controller>
The host controller 241 controls each device forming the control LSI 234, for example, the medal count circuit 246, the color recognition circuit 247, the fisheye correction scaler circuit 248, the image recognition DSP circuit 242, the image recognition accelerator circuit 249, and the GPIO 250.

  Further, the host controller 241 outputs a signal related to a lighting instruction or a light extinguishing instruction to the LED 233 via the GPIO 250. In addition, the host controller 241 determines, via the GPIO 250, the determination result relating to the count processing stored in the SRAM 243, that is, “the medal has passed”, “the medal has been guided to the medal shoot 202”, and “the abnormality. Has occurred "is output. Specifically, when the determination result is "a medal has passed", a medal count signal is output from the medal count output PORT, and when it is "an abnormality has occurred", a medal abnormality signal is output from the medal determination output PORT. Is output. Also, the determination result related to the color determination processing is output. Specifically, when “threshold judgment is not possible” is stored in the SRAM 243 as the judgment result of the threshold judgment process, or when “no” is stored as the color judgment result, the medal judgment output assigned to the GPIO 250 is output. The medal abnormality signal is output from the PORT when a predetermined output condition is satisfied. Further, it outputs the determination result related to the determination processing by the image recognition DSP circuit 242. Specifically, when the SRAM 243 stores the gradient average determination result or “NO” as the HOG determination result, a medal abnormality signal is output from the medal determination output PORT assigned to the GPIO 250 as a predetermined output condition. Output when established.

  The predetermined output condition can be set as appropriate. For example, the predetermined output condition may be set such that “abnormality has occurred” is stored in the SRAM 243 as the determination result of the count process. Further, it may be set that the “threshold judgment impossible” is continuously or cumulatively stored in the SRAM 243 as a judgment result of the threshold judgment process, for a predetermined number (for example, 10 times) or more. In addition, even if the slope average determination result or “NO” as the HOG determination result is continuously or cumulatively stored in the SRAM 243 a prescribed number of times (for example, 10 times) or more, the setting may be made. Good.

  A backup power supply (not shown) is connected to the SRAM 243, and the contents stored in the SRAM 243 are retained for a certain period (for example, about one week) even when the power of the pachi-slot 1 is cut off. In addition, the host controller 241 has an initialization switch (not shown) disposed on a switch substrate (not shown) provided at an arbitrary location of the medal selector 201 (eg, near the first substrate 231) via the GPIO 250. Various templates, such as a color template, a gradient average image template, and a HOG template, stored in the SRAM 243 can be erased (not shown). Specifically, by turning on the power of the pachi-slot 1 with the initialization switch pressed, the area in the SRAM 243 in which various templates are stored is initialized (value of 0 is set during initialization processing of the host controller 241). Write), that is, erase various templates.

<Flash memory>
In the flash memory 244, various devices constituting the control LSI 234, for example, a host controller 241, an image recognition DSP circuit 242, a fisheye correction scaler circuit 248, an image recognition accelerator circuit 249, and parameters necessary for various processes and necessary for various processes. The data is stored.

<Processing flow of control LSI>
Next, the processing performed by the control LSI 234 will be described with reference to FIG. FIG. 34 is a process flow diagram for explaining the process performed by the control LSI 234.
As shown in FIG. 34, the control LSI 234 roughly performs an input process, a conversion process, a color determination process, a count process, and a marking determination process.

<Input processing>
The input processing is performed by the ISI circuit 251. In the input processing, as described above, the ISI circuit 251 converts the image data transmitted from the CMOS image sensor 232 by the LVDS method into an RGB Bayer image, and outputs the RGB Bayer image to the ISP circuit 245.

<Conversion process>
The conversion process is performed by the ISP circuit 245. In the conversion process, the ISP circuit 245 performs an image correction process of performing lens distortion correction process and projective conversion (homography) process on the RGB Bayer image output from the ISI circuit 251. Next, the ISP circuit 245 performs the color conversion process of converting the corrected RGB Bayer image into YUV image data and outputting the grayscale image data to the medal count circuit 246. Further, the RGB Bayer image is converted into HSV image data, and color conversion processing is performed to output this HSV image data to the color recognition circuit 247.

  After the conversion processing, the control LSI 234 performs color determination processing, count processing, and marking determination processing. It should be noted that these processes are executed in parallel at respective executable timings because the circuits that execute the respective processes are configured as separate circuits.

<Color determination processing>
The color determination processing is performed by the color recognition circuit 247. The color determination processing includes medal detection processing, threshold determination processing, saturation / hue multiplication processing, color template generation processing, and color template comparison processing.

  First, the color recognition circuit 247 performs a medal detection process for determining whether the HSV image data received from the ISP circuit 245 includes a medal image. When it is determined that the HSV image data includes a medal image, the color recognition circuit 247 performs a threshold determination process based on the HSV image data. In the threshold determination process, if the position on the threshold graph (see FIG. 21) based on the average saturation value and the average hue value is within the allowable region, the color determination process is continued. On the other hand, if it is within the non-permissible area, “threshold determination not possible” is stored in the SRAM 243 as the determination result, and the color determination processing ends.

  After the threshold value determination processing, the color recognition circuit 247 performs saturation / hue multiplication processing to create color determination data. Then, the created color determination data is compared with the color template to determine whether they match or are similar to each other to a predetermined degree, and the determination result is stored in the SRAM 243.

  The color template comparison process is not executed until the number of medals thrown after the power is turned on reaches the prescribed initial number of medals, which is 50 in this embodiment, because the color template is not generated.

  Further, the color recognition circuit 247, when the number of medals thrown after the power is turned on reaches the prescribed initial number of medals of 50 and the number of color determination data stored in the color determination data storage area reaches 50, that is, 50 medals. When the color determination data for the medals is created, the color template generation process is executed.

<Count processing>
The counting process is performed by the medal counting circuit 246. Count processing includes medal detection processing and order determination processing. The medal image determination process and the medal position detection process described above correspond to the medal detection process. In the medal detection process, the medal count circuit 246 determines whether or not the received grayscale image data includes a medal image. Further, it is determined whether or not a medal image is present in a predetermined determination area in the received grayscale image data, and the determination result (“IN”, “OUT”, “ON”, “OFF” data) is stored in the SRAM 243. Remember.

  In the order determination process, the medal count circuit 246 causes the transition of the data of “IN”, “OUT”, “ON”, “OFF” for each determination region in the predetermined number of grayscale image data arranged in time series. It is determined whether or not the mode of 1 corresponds to the mode of the predetermined transition. Then, as the determination result, any one of “a medal has passed”, “a medal was guided to the medal shoot 202”, or “an abnormality has occurred” is stored in the SRAM 243. Further, when it is stored in the SRAM 243 that “a medal has passed”, the host controller 241 outputs a medal count signal from the medal count output PORT allocated to the GPIO 250. Based on this medal count signal, the main control circuit 91 detects that a medal has been inserted, and counts the number of inserted medals or the number of credits.

<Engraving judgment processing>
The marking determination processing includes fisheye correction processing and equalization processing performed by the fisheye correction scaler circuit 248, and circle area detection processing, filter processing, gradient average image template comparison processing, and HOG template comparison performed by the image recognition DSP circuit 242. Processing is included. Further, it includes a rotation image generation process, a gradient average image data generation process, a gradient average image template generation process, a polar coordinate conversion process, a Scharr conversion process, a HOG conversion process, and a HOG template generation process performed by the image recognition accelerator circuit 249.

  In the fisheye correction processing, the fisheye correction scaler circuit 248 acquires grayscale image data from the SRAM 243 and performs fisheye correction processing of correcting the acquired grayscale image data. Next, in the equalizing process, the fisheye correction scaler circuit 248 performs the equalizing process on the grayscale image data subjected to the fisheye correcting process, creates reduced image data, and stores it in the SRAM 243.

  When it is determined in the counting process that the medal has passed on the medal rail 210, the host controller 241 instructs the image recognition DSP circuit 242 and the image recognition accelerator circuit 249 to execute the processes after the circle area detection process in the marking determination process. To do.

  In the circle area detection process, the image recognition DSP circuit 242 acquires the reduced image data from the SRAM 243 and detects the circle area from the reduced image data. Further, in the filter processing, the image recognition DSP circuit 242 performs nonlinear diffusion filter processing on the detected circular area to create an edge image XY, and stores it in the SRAM 243.

  Next, in the rotation image generation process, the image recognition accelerator circuit 249 acquires the edge image XY from the SRAM 243 and generates a rotation image for 360 degrees from the edge image XY. Further, in the gradient average image data generation processing, the image recognition accelerator circuit 249 cumulatively adds (overlaps) the rotated images for 360 degrees to generate gradient average image data, and stores the gradient average image data in the SRAM 243. Let The image recognition accelerator circuit 249 stores the gradient average image data in the gradient average image template generation data storage area before generating the gradient average image template, and after the gradient average image template is generated, the determination target It is stored in the gradient average image data storage area.

  Next, in the gradient average image template comparison processing, the image recognition DSP circuit 242 determines whether the gradient average image data to be determined and the gradient average image template match or are similar to each other by a predetermined degree, and the determination result is stored in the SRAM 243. Remember. Here, if the gradient average image template is not generated at the time of executing the gradient average image template comparison process (in the present embodiment, less than 50 medals have been thrown after the power is turned on), the gradient average image template is generated. The comparison process is not executed.

  As described above, at the timing when the number of medals thrown after the power is turned on reaches the prescribed initial number of medals of 50, and the gradient average image data generation data storage area of the SRAM 243 stores 50 gradient average image data. The image recognition accelerator circuit 249 performs gradient average image template generation processing.

  Further, the image recognition accelerator circuit 249 performs polar coordinate conversion processing in parallel with the rotation image generation processing. In the polar coordinate conversion processing, the edge image XY is acquired from the SRAM 243, the orthogonal coordinates of the acquired edge image XY are converted into polar coordinates, polar coordinate image data is created, and the polar coordinate image data is stored in the SRAM 243.

  Next, in the Scharr conversion process, the image recognition accelerator circuit 249 acquires the polar coordinate image data from the SRAM 243 and performs the nonlinear diffusion filter process to create the edge polar coordinate image X and the edge polar coordinate image Y.

  Next, in the HOG conversion processing, the image recognition accelerator circuit 249 creates an edge gradient image based on the edge polar coordinate image X and the edge polar coordinate image Y, performs HOG conversion on the created edge gradient image, and performs local area for each local area. A histogram in the gradient direction of the luminance in is created. Then, the set of created histograms is stored in the SRAM 243. The image recognition accelerator circuit 249 stores the set of histograms in the HOG template generation data storage area before generating the HOG template and in the determination target histogram storage area after generating the HOG template.

  Next, in the HOG template comparison process, the image recognition DSP circuit 242 determines whether the set of histograms to be determined and the HOG template stored in the SRAM 243 match or are similar to each other by a predetermined degree. Then, the determination result is stored in the SRAM 243. When the HOG template is not generated (in the present embodiment, less than 50 medals have been thrown after the power is turned on), the HOG template comparison process is not executed.

  Note that, as described above, the image recognition accelerator circuit 249 causes the image recognition accelerator circuit 249 to perform the HOG at the timing when the number of medals thrown after the power is turned on reaches 50 and the set of 50 sets of histograms is stored in the HOG template generation data storage area of the SRAM 243. Perform template generation processing.

<Timing of control LSI processing>
Next, the timing of various processes performed by the control LSI 234 will be described with reference to FIG.
FIG. 35 shows a time-series relationship of processes in the host controller 241, the ISP circuit 245, the medal count circuit 246, and the color recognition circuit 247, which are the devices constituting the control LSI 234. The relatively thick line portion of the line extending below each device name indicates that the device is in a state of performing the above-described various processes.

  In addition, broken line arrows between the lines corresponding to the respective devices indicate signals input / output between the respective devices. In addition, a dashed arrow between a line extending below “IN” and a line extending below “OUT” in the host controller indicates a signal detected by the host controller 241 and a signal output from the host controller 241. Shows the correspondence with.

  First, when the CMOS image sensor 232 (see FIG. 17) outputs the image data to the control LSI 234, the ISP circuit 245 acquires (receives) the image data via the ISI circuit 251, and the VSYNC (Vertical Synchronization) interrupt signal #. 0 (1IH) is output to the host controller 241. The ISP circuit 245 also performs conversion processing for converting the RGB Bayer image into various formats. Then, the grayscale image data and the HSV image data are output to the SRAM 243, the medal count circuit 246, and the color recognition circuit 247. The detailed description of the conversion process is omitted because it has been described above.

  When the VSYNC interrupt signal # 0 is input, the host controller 241 outputs a start request signal (1HC, 1HM) to the color recognition circuit 247 and the medal count circuit 246 after a lapse of a predetermined time. The predetermined time is set longer than the time required for the conversion processing in the ISP circuit 245, based on experiments and simulations.

  The color recognition circuit 247 performs color determination processing when an activation request signal is input and when HSV image data is input from the ISP circuit 245, stores the determination result in the SRAM 243, and causes the host controller 241 to perform color determination. Outputs a judgment interrupt signal (1CH). The detailed description of the color determination process has been described above, and will be omitted.

  The medal count circuit 246 performs a count process when the activation request signal is input and when data is input from the ISP circuit 245, stores the determination result in the SRAM 243, and also causes the host controller 241 to interrupt the medal count interrupt. The signal (1MH) is output. The detailed description of the counting process is omitted because it has been described above.

  Upon detecting the color determination interrupt signal and the count interrupt signal, the host controller 241 acquires the determination result of the count process from the SRAM 243. Then, it is determined whether or not any one of "a medal has passed", "a medal was guided to the medal shoot 202", and "an abnormality has occurred" is stored as the determination result. If neither is stored, the host controller 241 omits the process of outputting the determination result to the main control board 71 (main control circuit 91) via the GPIO 250. Here, in the present embodiment, as described above, in the order determination process of the count process, it is necessary that the mode of data transition in each determination region of a plurality of grayscale image data is stored in the SRAM 243. The process of outputting the determination result to the main control board 71 is omitted at least until the number of grayscale image data received by the medal count circuit 246 reaches a predetermined number (14 or 4 when medals cannot be inserted). There are cases.

  Regarding the timing of the processing of each device triggered by the input of the VSYNC interrupt signals # 1 to 4 (2IH to 5IH) and the signal input / output shown in FIG. 35, the input of the VSYNC interrupt signal # 0 (1IH Since the processing timing and signal input / output of each device triggered by) are the same, the description thereof is omitted here.

  Next, the processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signal #n (nIH), which is the nth VSYNC interrupt signal after the power is turned on, shown in FIG. 35 will be described. . It should be noted that the ISP circuit 245 outputs the VSYNC interrupt signal #n to the host controller 241 (nIH), and then the host controller 241 acquires the count determination result from the SRAM 243 and outputs signals. With respect to the above, since the processing timing and signal input / output of each device triggered by the input of the VSYNC interrupt signal # 0 (1IH) described above are the same, description thereof will be omitted here.

  The host controller 241 stores, as the determination result of the counting process, any of “a medal has passed”, “a medal has been guided to the medal shoot 202”, and “an abnormality has occurred”, The determination result and the determination result of the color determination process are acquired from the SRAM 243, and these determination results are output to the allocation PORT of the GPIO 250 (nHG). That is, the host controller 241 outputs the determination result of the count determination process and the determination result of the color determination process to the main control board 71 (main control circuit 91) via the GPIO 250. There may be a plurality of judgment results of the color judgment processing output here.

  Further, when the determination result of the counting process is “the medal has passed”, the host controller 241 relates to each medal until the number of medals inserted into the gaming machine reaches the specified initial insertion number, 50 in this embodiment. In order to generate the color determination data, the color recognition circuit 247 is instructed to generate the color determination data by using the HSV image data before the predetermined time. Further, the host controller 241 instructs the image recognition DSP circuit to perform preprocessing using the reduced image data of a predetermined time.

  Further, the host controller 241 deletes the determination result output to the main control board 71 from the SRAM 243.

  When the determination result of the counting process is “a medal has passed”, the main CPU 93 of the main control circuit 91 detects the medal count signal output from the medal count output PORT of the GPIO 250 and determines the number of inserted medals. The main CPU 93 adds 1 to the value of the inserted number counter, which is a counter provided for counting. When the value of the inserted number counter is the maximum value (for example, 3), 1 is added to the value of the credit counter which is a counter provided for the main CPU 93 to count the number of credited medals. When the credit counter has the maximum value (for example, 50), the main control circuit 91 sets the medal solenoid 208 of the medal selector 201 to the OFF state. As a result, the select plate 207 is positioned at the “discharging position”, the medals cannot be inserted, and the inserted medals are guided to the medal chute 202 through the medal tray 32 from the medal payout opening 32. Discharge to unit 34. In the present embodiment, when the start lever is operated when the value of the thrown-in number counter is a specified value (for example, 2 or 3), the main CPU 93 performs the above-mentioned internal lottery process.

  In addition, when the determination result of the color determination process is “threshold determination not possible”, the color determination result is “no”, and the count determination result is “abnormal”, the medal determination output of the GPIO 250 is output. With a medal abnormality signal (Judgment in FIG. 35) output when a predetermined output condition is satisfied from the PORT, the main control circuit 91 causes the gaming machine to mistakenly recognize that a regular game medium is used and plays the game. Detects fraudulent activity. Then, various processes are carried out when there is an illegal act. Here, various processes in the case of an illegal act include, for example, the main control circuit 91 forcibly interrupting the game, displaying an error code on the 7-segment display 24, and an error on the sub control circuit 101. This is a process of transmitting a command and notifying that there has been an illegal act via the sub control circuit 101 (for example, displaying that the illegal act has occurred on the liquid crystal display device 11).

Next, the timing of other processing performed by the control LSI 234 will be described with reference to FIG.
FIG. 36 shows a time-series relationship of processing in the host controller 241, the ISP circuit 245, the fisheye correction scaler circuit 248, the image recognition DSP circuit 242, and the image recognition accelerator circuit 249, which are the devices constituting the control LSI 234. . Note that the meanings of various notations in FIG. 36 are the same as those in FIG. 35, and therefore description thereof will be omitted here. FIG. 36 shows the timing of processing after the VSYNC interrupt signal #m, which is the mth VSYNC interrupt signal after power-on, is output from the ISP circuit 245.

  First, when the CMOS image sensor 232 (see FIG. 17) outputs the image data to the control LSI 234, the ISP circuit 245 acquires (receives) the image data via the ISI circuit 251, and the VSYNC (Vertical Synchronization) interrupt signal #. m (1IH) is output to the host controller 241. The ISP circuit 245 also performs conversion processing for converting the RGB Bayer image into various formats. Then, the grayscale image data is stored in the SRAM 243. The detailed description of the conversion process is omitted because it has been described above.

  When the VSYNC interrupt signal #m is input, the host controller 241 detects the end of the conversion process of the ISP circuit 245, and at the timing when the conversion process ends, the start request signal (1HG) to the fisheye correction scaler circuit 248. Is output. The predetermined time is set longer than the time required for the conversion processing in the ISP circuit 245, based on experiments and simulations.

  When the activation request signal is input, the fisheye correction scaler circuit 248 acquires the grayscale image data from the SRAM 243, performs the fisheye correction process and the equalization process, and stores the created reduced image data in the SRAM 243. A reduction end interrupt signal (1GH) is output to the host controller 241. The detailed description of the fisheye correction process and the equalization process is omitted because it has been described above.

  The host controller 241 has output the determination result of the count process that "the medal has passed" to the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interrupt signal. Under the condition, the signal (1HD) instructing the start of the preprocessing is input to the image recognition DSP circuit 242. Note that the condition for instructing the start of the pre-processing is that the determination result of the color determination process output to the main control circuit 91 is “threshold determination is not possible”, or does not match or is similar to any of the four color templates to a predetermined degree. It may be added to the condition that it is not included, that is, that the determination result that it matches or is similar to a certain degree to any of the color templates is included.

  The image recognition DSP circuit 242 performs preprocessing when the above signal is input from the host controller 241. As described above, the preprocessing includes the circular area detection processing and the filter processing. The edge image XY created in the preprocessing is stored in the SRAM 243, and the preprocessing end interrupt signal (1DH1) is output to the host controller 241. The detailed description of the preprocessing is omitted because it has been described above.

  When the preprocessing completion interrupt signal is input, the host controller 241 outputs a signal (1HA) instructing the image recognition accelerator circuit 249 to start the correction processing. Here, the correction processing is the above-described rotation image generation processing, gradient average image data generation processing, polar coordinate conversion processing, Scharr conversion processing, and HOG conversion processing. The detailed description of these processes is omitted because it has been described above.

  The image recognition accelerator circuit 249 performs a correction process when the signal is input from the host controller 241. If the generated gradient average image data has already generated the gradient average image template, it is stored in the determination target gradient average image data storage area of the SRAM 243, while the gradient average image template has not been generated yet. Is stored in the gradient average image template generation data storage area. The set of generated histograms is stored in the determination target histogram storage area of the SRAM 243 when the HOG template has already been generated, while it is stored in the HOG template generation data storage area when the HOG template has not been generated yet. Remember.

  Next, the image recognition accelerator circuit 249 outputs a correction processing end interrupt signal (1AD) to the image recognition DSP circuit 242 when the gradient average image template and the HOG template have already been generated. On the other hand, when the gradient average image template and the HOG template have not been generated yet, the processing of outputting the correction processing end interrupt signal to the image recognition DSP circuit 242 is omitted. The image recognition accelerator circuit 249 performs the gradient average image template generation process when 50 pieces of the gradient average image data are stored in the gradient average image data generation data storage area of the SRAM 243. Further, the image recognition accelerator circuit 249 performs the HOG template generation process when a set of 50 sets of histograms is stored in the HOG template generation data storage area of the SRAM 243.

  The image recognition DSP circuit 242 performs the marking determination process when the correction process end interrupt signal is input. The marking determination process here includes a gradient average image template comparison process and a HOG template comparison process. Specifically, the image recognition DSP circuit 242 acquires the gradient average image data from the determination target gradient average image data storage area of the SRAM 243, and performs the gradient average image template comparison process of comparing with the gradient average image template. Then, the determination result of the gradient average image template comparison processing is stored in the SRAM 243. In addition, a set of histograms is acquired from the determination target histogram storage area of the SRAM 243, and a HOG template comparison process for comparing with the HOG template is performed. Then, the determination result of the HOG template comparison processing is stored in the SRAM 243. Then, the image recognition DSP circuit 242 outputs a marking determination end interrupt signal (1DH2) to the host controller 241.

  When the marking determination end interrupt signal is input, the host controller 241 acquires the slope average determination result and the HOG determination result as the determination result of the marking determination processing stored in the SRAM 243. In addition, when the host controller 241 stores “NO” as the acquired gradient average determination result or “NO” as the HOG determination result, when the above-described predetermined output condition is satisfied. Then, the medal determination output PORT of the GPIO 250 outputs a medal abnormality signal (Judgment in FIG. 36) to the main control circuit 91 (1HG). That is, the host controller 241 outputs the determination result of the marking determination process to the main control board 71 (main control circuit 91) via the GPIO 250. Further, the host controller 241 deletes the determination result of the marking determination processing output to the main control board 71 from the SRAM 243. In the present embodiment, the same output PORT of the GPIO 250 is assigned to the output of the determination result of the color determination processing to the main control circuit 91 and the output of the determination result of the marking determination processing to the main control circuit 91. Not limited to this, it may be assigned to different output PORTs. In this case, the main control circuit 91 can determine whether the medal abnormality signal is based on the determination result of the color determination process or the medal abnormality signal is based on the determination result of the marking determination process.

  When the judgment result of the inputted marking judgment processing, that is, either the gradient average judgment result or the HOG judgment result is “NO”, the main control circuit 91 erroneously recognizes that a regular game medium is used in the gaming machine. Then, it is detected that there is an illegal act of playing a game. Then, various processes are carried out when there is an illegal act. Here, various processes in the case of an illegal act include, for example, the main control circuit 91 forcibly interrupting the game, displaying an error code on the 7-segment display 24, and an error on the sub control circuit 101. This is a process of transmitting a command and notifying that there has been an illegal act via the sub control circuit 101 (for example, displaying that the illegal act has occurred on the liquid crystal display device 11).

  Note that, in FIG. 36, various processes following VSYNC # m, triggered by VSYNC # m + 1, VSYNC # m + 2, VSYNC # m + 3, VSYNC # m + 4, VSYNC # m + 5, VSYNC # m + 6, are triggered by the above-mentioned VSHYC # m. With respect to the same processes as those described above, various signals output in accordance with the processes are denoted by reference numerals for changing only the leading numeral, and detailed description thereof will be omitted.

  Here, after the processing of outputting the reduction end interrupt signal (2GH, 3GH, 4GH, 6GH) from the fisheye correction scaler circuit 248 to the host controller 241, the host controller 241 starts the preprocessing to the image recognition DSP circuit 242. The process of outputting the signal instructing is not performed.

  This is because the host controller 241 displays the determination result of the count process that the medal has passed in the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interrupt signal. This is because it has not been output. In this example, the host controller 241 “passes the medal” to the main control circuit 91 between the input of the reduction end interrupt signal for 4GH and the input of the reduction end interrupt signal for 5GH. The determination result of the counting process is output. Therefore, after the reduction end interrupt signal related to 5GH is input, the host controller 241 outputs a signal (2HD) instructing the image recognition DSP circuit 242 to start the preprocessing.

  Further, in the present embodiment, it is preferable that the marking determination process be performed on all the medals to be inserted. However, the host controller 241 confirms whether the image recognition DSP circuit 242 or the image recognition accelerator circuit 249 is in processing (busy state) when outputting a signal instructing the image recognition DSP circuit 242 to start preprocessing. However, the signal may not be output when any one is being processed, and the signal may be output when no one is being processed. In this case, the marking determination process is performed intermittently for medals that have been continuously inserted. For example, when three medals are continuously inserted, the marking determination process is performed on the first and third medals.

  The processing timing of each device in the control LSI 234 shown in FIGS. 35 and 36 is merely an example. The regular medal determination process may be performed at various processing timings according to the processing capability of each device, the processing content, and the processing procedure.

<First action>
In the pachi-slot 1 according to the present embodiment, the result of the color determination processing performed by the color recognition circuit 247 based on the image data output from the CMOS image sensor 232 is “threshold determination not possible” or matches with any of the four color templates. Alternatively, if the color of the inserted medal does not match the color of the regular medal, the main control circuit 91 determines that the regular game medium is used for the gaming machine. It is detected that there is a fraudulent act of playing by misidentifying.

  Further, when the result of the count process based on the image data output from the CMOS image sensor 232 is “abnormality has occurred”, the main control circuit 91 causes the gaming machine to erroneously recognize that a regular game medium is used. It detects that there is an illegal act of playing a game.

  In addition, the result of the marking determination processing (in the present embodiment, the gradient average determination result or the HOG determination result) performed by the image recognition DSP circuit 242 based on the image data output from the CMOS image sensor 232 is “NO”. In this case, that is, when the stamp of the inserted medal and the stamp of the regular medal are different, the main control circuit 91 misidentifies that the regular game medium is used in the gaming machine, and detects that there is an illegal act of playing the game. Detect.

  Therefore, the main control circuit 91 performs a fraudulent act performed by inserting a special device into the medal insertion slot, or a fraudulent act performed using a medal having the same diameter as the regular medal but different in color and marking (pattern). It can be detected accurately.

  Then, when detecting that there has been a cheating, the main control circuit 91 forcibly interrupts the game, and notifies that there has been a cheating through the sub control circuit 101. Therefore, it is possible to suppress the spread of damage caused by the above-mentioned fraudulent acts.

<Second action>
Further, in the pachi-slot 1 of the present embodiment, the control LSI 234 of the medal selector 201 passes through the medal rail 210 until the number of medals inserted after the power is turned on reaches the specified initial number, 50 in the present embodiment. A color template used in the color determination process is generated based on the image including. Further, similarly, the gradient average image template and the HOG template used for the marking determination process are generated.

  Therefore, when the medals to be used as the regular medals are changed at the amusement store, the color template relating to the changed regular medals can be obtained by continuously supplying 50 changed regular medals after the power is turned on. Gradient average image templates and HOG templates can be easily created. In addition, even if the regular medal is, for example, inserted into a game machine, paid out, or deteriorated due to cleaning at a game store, and the marking is less noticeable than originally, a color template corresponding to the current state of the regular medal, Since the gradient average image template and the HOG template can be generated, the accuracy of the results of various determinations can be maintained.

<Third action>
Further, in the pachi-slot 1 of the present embodiment, the medal counting circuit 246 of the control LSI 234 performs counting processing based on the grayscale image data output from the ISP circuit 245. The medal counting circuit 246, in the order determination process in the counting process, determines “IN” based on a change in luminance of a plurality (16 in this embodiment) of determination regions for a predetermined number of grayscale image data arranged in time series. ], “OUT”, “ON”, and “OFF” data transition modes are determined to match the transition modes of the medal count determination table (see FIG. 27). If they match, it is determined that “the medal has passed” or “the medal has been guided by the medal shoot 202” on the medal rail 210. If any of the data “IN”, “OUT”, and “ON” is stored in the determination area E, it is determined that an abnormality has occurred.

  As described above, since the passage of a medal or the like is determined based on the change in the brightness in the plurality of determination areas, the determination accuracy can be improved.

  Further, the number of determination areas set on the grayscale image data can be set appropriately according to the allowable determination required time and the required determination accuracy. Therefore, for example, even if the number of determination regions is increased in order to further improve the determination accuracy, it is not necessary to newly install a component such as a photo sensor for counting medals. Therefore, an increase in manufacturing cost can be suppressed.

  Further, when the determination result of the count process is “abnormality has occurred”, the main control circuit 91 causes the gaming machine to misidentify that a legitimate game medium is used, and there is an illegal act of playing a game. To detect. That is, it is possible to detect an illegal act based on the determination result of the counting process.

<Fourth action>
Further, in the pachi-slot 1 of the present embodiment, the ISP circuit 245 of the control LSI 234 performs an image correction process of performing a lens distortion correction process and a projective transformation (homography) process on the RGB Bayer image output from the ISI circuit 251.

  Therefore, the RGB Bayer image can be complemented so that the characteristics of the lens of the camera unit 209 and the displacement of the mounting position of the camera unit 209 do not affect various determination / determination processes, and the accuracy of various determination processes can be improved.

<Fifth action>
Further, in the pachi-slot 1 of the present embodiment, the color recognition circuit 247 of the control LSI 234 performs the threshold value judgment processing. As a result, it is possible to prevent an erroneous determination that a hue or saturation value that is different from that of the regular medal is coincident with or similar to the color template to a predetermined extent. That is, in addition to the determination based on the degree of coincidence with the color template, it is possible to determine whether or not the color to be determined itself is a valid color, so the accuracy of the determination result of the color determination processing can be improved.

<Sixth action>
Further, in the pachi-slot 1 of the present embodiment, the fisheye correction scaler circuit 248 of the control LSI 234 performs bilateral conversion processing on each of the reduced image data created in the equalization processing.
This makes it possible to reduce noise in the grayscale image data and enhance edges in the grayscale image data. Therefore, the accuracy of the determination result in the marking determination process can be improved.

<Seventh action>
Further, in the pachi-slot 1 of the present embodiment, the image recognition accelerator circuit 249 of the control LSI 234 performs the HOG conversion process. Further, the image recognition DSP circuit 242 determines whether or not the set of determination target histograms created by the HOG conversion process and the HOG template match or are similar to each other in a predetermined degree in the marking determination process.

  Therefore, the marking determination process is performed by performing image matching with the HOG conversion process, which has an advantage in the local shape change (geometric conversion), on the imaged data of the medal passing on the medal rail 210 while rotating. The accuracy of the determination result of can be improved.

<Eighth action>
In the pachi-slot 1 of the present embodiment, the image recognition accelerator circuit 249 of the control LSI 234 performs polar coordinate conversion processing before the HOG conversion processing.
As a result, the characteristics of the outer peripheral area of the regular medal are easily reflected in the set of histograms created by the HOG conversion process. Therefore, it is possible to improve the accuracy of the determination result of the subsequent engraving determination process for the medals having the characteristic engraving (pattern) on the outer peripheral area.

<Ninth action>
In a conventional game machine, the count of inserted medals, the detection of clogging of medals in the selector of inserted medals, etc., the main CPU in the main control circuit, by executing the program stored in the main ROM, It was done. However, in the pachi-slot 1 of the present embodiment, the control LSI 234 of the medal selector 201 performs these detections with higher accuracy than conventional. Therefore, it is not necessary to store the programs for these detections in the main ROM 94, and the storage capacity of the main ROM 94 is reduced.

<Modification>
The gaming machine according to the embodiment of the present invention has been described above, including its function and effect. However, the game machine of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described in the claims.

  For example, in the present embodiment, the mode in which four color templates, the gradient average image template, and the HOG template are generated has been described, but the number of these templates can be set as appropriate according to the allowable determination required time and the required determination accuracy. Is.

  Further, in the present embodiment, the mode has been described in which the color determination process and the marking determination process are executed for all the inserted medals. However, the present invention is not limited to this, and a switch substrate is provided at an arbitrary location of the medal selector 201 (for example, near the first substrate 231), and the color determination ON / OFF switch and the marking determination ON / OFF switch are provided on the switch substrate. May be provided so that the host controller 241 can read the state of the switch to select whether to execute the color determination process and the marking determination process.

  Further, in the present embodiment, when “NO” is input to the main control circuit 91 as the gradient average determination result, or “NO” is input as the HOG determination result, the main control circuit 91 The aspect of detecting that there has been cheating has been described. However, instead of this, if “NO” is input to the main control circuit 91 as the gradient average determination result and “NO” is input as the HOG determination result, the main control circuit 91 determines that the fraudulent activity has occurred. You may detect that there was.

  Further, in the present embodiment, a mode has been described in which the color template, the gradient average image template, and the HOG template stored in the SRAM 243 are erased when the initialization switch is pressed when the game machine is powered on. However, instead of this, an arbitrary operation may be set in order to delete the various templates stored in the SRAM 243. For example, various templates of the SRAM 243 may be erased in association with changes in the settings of the gaming machine.

  In addition, in the order determination process in the case where medals cannot be inserted, the mode of data transition in each determination region of the latest four grayscale image data stored in the SRAM 243 and the medal count determination table are defined. When the transition states of the data corresponding to E1 to E4 do not match, it may be determined that “an abnormality has occurred” and the determination result may be stored in the SRAM 243.

  In addition, in the present embodiment, the host controller 241 performs a count process of "medals have passed" in the main control circuit 91 from the input of the previous reduction end interrupt signal to the input of the current reduction interrupt signal. The mode in which the image recognition DSP circuit 242 is instructed to start the preprocessing on condition that the determination result of (1) is output has been described. That is, when it is determined that the medal has passed on the medal rail 210 in the counting process, the host controller 241 executes the processes after the circle area detection process in the marking determination process to the image recognition DSP circuit 242 and the image recognition accelerator circuit 249. Has been described. However, instead of this, the determination result of some counting process (that is, "medal is a medal shot) from the input of the previous reduction end interrupt signal to the input of this reduction interrupt signal is performed. Alternatively, the image recognition DSP circuit 242 may be instructed to start the preprocessing on the condition that "the information is guided by 202" or "the abnormality has occurred" is output.

Further, the threshold value determination process in the color determination process may be omitted.
Further, the present invention may be adopted in other game machines using a game medium, for example, a pachinko machine.

  1 ... Pachi-slot, 3L ... Left reel, 3C ... Middle reel, 3R ... Right reel, 4 ... Reel display window, 21 ... Medal slot, 23 ... Start lever, 32 ... Medal payout port, 51 ... Hopper device, 71 ... Main Control board, 72 ... Sub control board, 79 ... Start switch, 80 ... Stop switch board, 91 ... Main control circuit, 101 ... Sub control circuit, 140 ... Cancel shooter, 201 ... Medal selector, 202 ... Medal shoot, 203 ... Slope , 204 ... Base plate part, 205 ... Sub plate, 206 ... Cancel shooter, 207 ... Select plate, 208 ... Medal solenoid, 209 ... Camera unit, 210 ... Medal rail, 211 ... Medal entrance part, 212 ... Central hole, 213 ... Medal pressure, 217 ... Magnet, 218 ... After medal pressure, 227 ... Medal stopper portion, 230 ... First substrate, 231 ... Second substrate, 232 ... CMOS image sensor, 233 ... LED, 234 ... Control LSI, 235 ... Leg portion, 241 ... Host controller , 242 ... Image recognition DSP circuit, 243 ... SRAM, 244 ... Flash memory, 245 ... ISP circuit, 246 ... Medal counting circuit, 247 ... Color recognition circuit, 248 ... Fisheye correction scaler circuit, 249 ... Image recognition accelerator circuit, 250 … GPIO, 251… ISI circuit

Claims (1)

An input port for inputting game media,
A game machine comprising: a game medium detecting means for detecting a game medium inserted through the slot.
The game medium detecting means,
A passage forming portion forming a passage through which the game medium passes,
Imaging means for imaging the passage,
Passage determining means for determining whether or not an object has passed through the passage based on image data obtained via the image capturing means,
Image conversion means for converting the image data,
Based on the image data converted by the image converting means, a game medium determining means for determining whether or not the object passing through the passage is the regular game medium,
Wherein the image conversion means, for the image data, using a predetermined image processing kernels performs processing for emphasizing processing and edge component for removing noise components, the game of the normal from the image data after the process A game machine characterized by extracting a region including a contour of a medium.

Images