JP2017093632A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of securing a large number of moving images and still images to enable realization of image presentations rich in variety, without expanding a memory.SOLUTION: Compression data stored in CGROM 55 includes unevenly reduced data in which a crosswise direction and a lengthwise direction are unevenly reduced by W (W<1) time and H (H≤1) time respectively (W≠H) to degrade the original resolution before a compression. When a drawing circuit 76 generates an image frame by expanding the unevenly reduced data, a display circuit 74 performs an output after enlarging 1/W times in the crosswise direction and 1/H times in the lengthwise direction on the basis of an instruction from an image control CPU 63.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a gaming machine that performs a lottery process resulting from a gaming operation and executes an image effect corresponding to the lottery result, and more particularly to a gaming machine that can stably execute a powerful image effect.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

  In this type of gaming machine, it is desired to make various productions complicated and rich, especially for image production. For this reason, the display device is increasing in size and it is desired to increase the resolution as much as possible, including moving images that change at high speed.

  However, since the amount of data of a high-resolution moving image is increased by the amount corresponding to the resolution, there is a problem in securing a large amount of various types of moving images and still images in a memory (CGROM). That is, when the size of the CGROM is increased, the manufacturing cost is increased, and there is a problem in the arrangement space.

  The present invention has been made in view of the above-described problems, and is a gaming machine that can secure a large amount of moving images and still images without enlarging a memory and can realize a variety of image effects. The purpose is to provide.

  In order to achieve the above object, the present invention is a sub-process for executing an image effect corresponding to a lottery result of a lottery process executed based on a predetermined switch signal based on a control command received from another control means. A gaming machine provided with a control means, wherein the sub-control means is an image effect control means for centrally controlling an image effect, and compressed data that is a constituent element of a still image and / or a moving image constituting the image effect. Data storage means for storing the image data, and image generation means for realizing the image effect by outputting the image data generated from the compressed data based on the instruction of the image effect control means to the display device, The image production control means is provided with a list generation means for generating a drawing list for specifying image display for one frame of the display device, while the image generation means includes the list generation means. A drawing unit that generates image data for one frame corresponding to the drawing list generated by the image forming unit, and an output unit that receives the image data generated by the drawing unit and outputs the image data to a display device. Comprises a display circuit for outputting the image data for one frame generated based on one drawing list to a predetermined display device, and the compressed data stored in the data storage means includes a horizontal direction Includes W (W <1) times and the vertical direction H (H ≦ 1) times non-uniformly (W ≠ H), and includes non-uniformly reduced data that has been compressed after degrading the original resolution. For the image frame generated by the drawing means by expanding the unequal reduction data, the display circuit is 1 / W times in the horizontal direction and 1 / H times in the vertical direction based on an instruction from the image effect control means. To be expanded and output It has been made.

  The non-uniformly reduced data is preferably stored in the data storage means as moving image compressed data constituting a moving image. Further, it is preferable that the non-uniform reduction process is performed on a rectangular image and W <H ≦ 1 is set.

  The list generation unit and the drawing unit operate intermittently with a predetermined operation cycle, and the drawing list generated by the list generation unit draws at a timing delayed by N times the predetermined operation cycle. It is preferable that the image data specified by the drawing list is generated by being interpreted by the means. Preferably, the output unit operates intermittently with the same operation cycle as the list generation unit and the drawing unit, and the image data generated by the drawing unit is delayed by one operation cycle by the display circuit. It is configured to output.

  The drawing means and the output means operate intermittently with a predetermined operation cycle, and the drawing means switches between the first area and the second area and uses any one of the two areas. Preferably, the image data for one frame is stored while the output means reads the image data stored by the drawing means with a delay of one operation cycle.

  The display circuit is configured to be able to output standard moving image data updated at a normal cycle and low-speed moving image data updated at an operation cycle longer than the normal cycle at the same or different timing, It is preferable that the image frame of the low-speed moving image is generated by expanding the non-uniformly reduced data. In this case, at the timing one operation cycle before the display circuit outputs the image data of the low-speed moving image, the drawing means generates image data for one frame using the same image data as before for the low-speed moving image. Typically, the rendering means may not generate image data for low speed moving images.

  The low-speed video is configured so that each frame of a plurality of consecutive frames can be encoded independently without depending on other frames. In addition to the operation of reproducing in the forward direction, the operation of reproducing in the reverse direction, from the middle It is preferable that all or a part of the operation to be reproduced and the operation to resume the reproduction after being stopped halfway be executed.

  According to the gaming machine of the present invention described above, a large amount of moving images and still images can be secured without increasing the size of the memory, and a variety of image effects can be realized.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of an Example. FIG. 4 is a block diagram illustrating a circuit configuration of an effect control unit and an image control unit. 2 is a diagram illustrating a configuration of a timepiece IC. It is a block diagram which shows the internal structure of the composite chip in charge of image production. 6 is a diagram illustrating an operation of a display circuit. It is drawing explaining the operation | movement procedure which implement | achieves the structure of a memory, and image production. It is a flowchart explaining the operation | movement content of 1st Example which does not use a preloader. It is drawing explaining operation | movement in the sub-display device when an auxiliary moving image is reproduced at low speed. It is a figure explaining operation | movement in a main display apparatus when carrying out normal reproduction | regeneration of a normal moving image, and reproducing an auxiliary | assistant moving image at low speed. It is a flowchart explaining the operation | movement content of 2nd Example using a preloader. It is drawing explaining operation | movement of 2nd Example.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  A main display device DS1 composed of a large liquid crystal color display (LCD) is disposed in the central opening HO, and a movable sub display device composed of a small liquid crystal color display is disposed on the right side of the main display device DS1. DS2 is arranged. The main display device DS1 is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. The display device DS1 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, a reach effect that expects a big hit state may be executed, and in the special symbol display portions Da to Dc and the surroundings, a notice effect such as an appropriate video is executed. The

  The sub display device DS2 normally displays the image information in a stationary state in which the display screen is inclined at an angle that is easy for the player to see. However, at the time of the predetermined notice effect, the predetermined moving image (auxiliary moving picture) is displayed while moving to the left side of the figure while changing the tilt angle to an angle that is easy for the player to see. That is, the sub display device DS2 of the embodiment functions not only as a display device but also as a movable effect body that executes a notice effect. Here, the announcement effect by the sub display device DS2 is set with high reliability, and the player pays attention to the moving operation of the sub display device DS2 with a great sense of expectation.

  In this embodiment, the moving image effect is executed not only on the main display device DS1 but also on the sub display device DS2. However, the sub display device DS2 and / or the sub display device DS2 and / or the CGROM can be reproduced without increasing the size of the CGROM. The main display device DS1 reproduces an auxiliary moving image that is not high in production value at a low speed. Although details of this point will be described later, a normal moving image mainly reproduced on the main display device DS1 is about 30 fps (frame per second), whereas an auxiliary moving image mainly reproduced on the sub display device DS2 is 15 fps. It is a degree, and it realizes the animation production with abundant variations while suppressing the total amount of video data.

  By the way, in the game area where the game ball falls and moves, the first symbol starting port 15a, the second symbol starting port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17, and the gate 18 are used. Is arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  In other words, when a game ball wins the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of the special game (hit state) varies according to the jackpot symbols to be arranged, etc., which game value is given based on the lottery result according to the winning timing of the game ball in advance It is determined.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIG. 4 shows a part of it in detail. As shown in FIG. 3, the pachinko machine GM receives 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. A main control board 21 that centrally handles the sound, an effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the main control board 21, and a control command CMD received from the effect control board 22 The image control board 23 that drives the two display devices DS1 and DS2 based on 'and the payout control board 24 that controls the payout motor M based on the control command CMD "received from the main control board 21 to pay out the game ball. And a launch control board 25 that launches a game ball in response to the player's operation.

  As illustrated, the control command CMD output from the main control board 21 is transmitted to the effect control board 22. The control command CMD ″ output from the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

  The control commands CMD, CMD ′, and CMD ”are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel every two 8 bits. On the other hand, the control command CMD ′ transmitted from the effect control board 22 to the image control board 23 is transmitted in parallel with a 16-bit length. Even when such control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  As shown in the figure, in this embodiment, a liquid crystal interface board 28 accessible from the image control board 23 and the effect control board 22 is provided. The liquid crystal interface board 28 is equipped with a clock circuit (real time clock) RTC capable of measuring the current time and a memory element (Static Random Access Memory) SRAM for storing game performance information.

  In this embodiment, the image control board 23 drives the main display device DS1 and the sub display device DS2 via the liquid crystal interface board 28 on which an LVDS receiving circuit and the like are mounted. Here, the liquid crystal interface board 28 and the image control board 23 are directly connected to the male connector and the female connector without going through a wiring cable. Similarly, for the effect control board 23 and the liquid crystal interface board 28, the male connector and the female connector are directly connected without going through the wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  A computer circuit such as a one-chip microcomputer is mounted on each of the main control board 21, the effect control board 22, the image control board 23, and the payout control board 24. Therefore, the control board 21 to 24 and the circuit mounted on the liquid crystal interface board 28 and the operations realized by the circuit are collectively referred to as a function. 22, image control unit 23, and payout control unit 24. Note that, with respect to the main control unit 21, all or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 become sub-control units.

  This pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35. Each is fixed in place on the front frame 3. On the other hand, a main control board 21, an effect control board 22, and an image control board 23 are fixed to the back of the game board 5 together with the display devices DS1 and DS2 and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect control unit 22 as they are. Then, the effect control unit 22 outputs the received system reset signal SYS to the image control unit 23 as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputer 40 and the image control section of the effect control unit 22 by this power supply reset signal. The built-in CPU circuit 23 is reset with a power supply together with other circuit elements and internal circuits including VDP.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the output from the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS is used.

  The reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and each CPU is provided unless a regular clear pulse is received from the CPU of each control unit 21, 24. Is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22, the image control board 23, and the liquid crystal interface board 28 are integrated by connector connection, and the effect control unit 22 is connected to the power supply board 20 via the power relay board 33. The DC voltage (5V, 12V, 32V) of each level and the system reset signal SYS are received (see FIGS. 3 and 4A).

  The effect control unit 22 receives a control command CMD and a strobe signal STB from the main control unit 21. Then, the effect control unit 22 serially transmits the lamp drive signal SDATA to the driver ICs mounted on the lamp drive board 36, the lamp drive board 29, and the motor lamp drive board 30 in synchronization with the clock signal CK. A lamp group composed of a large number of LED lamps and electric lamps is driven to realize a lamp effect based on the control command CMD.

  In the case of this embodiment, the lamp effect is executed by the three lamp groups CH0 to CH2, and the lamp driving board 36 receives the CH0 lamp driving signal SDATA0 via the frame relay boards 34 and 35 as a clock. It is received in synchronization with the signal CK0 (clock synchronous serial communication). Note that a series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, so that the lighting state is updated all at once.

  The same applies to the lamp drive board 29. The driver IC of the lamp drive board 29 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. The lighting state of the lamp group CH1 is updated all at the same time.

  On the other hand, the driver IC mounted on the motor lamp driving board 30 receives the lamp driving signal transmitted in a clock synchronous manner to drive the lamp group CH2, and receives the motor driving signal transmitted in a clock synchronous manner, The effect motor groups M1 to Mn composed of a plurality of stepping motors are driven. The lamp driving signal and the motor driving signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives the signals transmits the timing at which the operation control signal ENABLE2 changes to the active level. Thus, the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

  In addition, the effect control unit 22 sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23, a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). Is output. The image control unit 23 drives the display devices DS1 and DS2 based on the control command CMD 'to execute various image effects. As shown in FIGS. 3 and 4A, the image control unit 23 includes a built-in CPU circuit (image production control device) 51 having an internal configuration equivalent to that of a general-purpose one-chip microcomputer, a VDP (Video Display Processor) 52, It is comprised centering on the composite chip | tip 50 which incorporated. In addition, a control memory (PROM) 53 that stores a control program for the built-in CPU, a DRAM (Dynamic Random Access Memory) 54 that can access a large amount of data at high speed, and a CGROM 55 that stores a large amount of CG data necessary for image control. And are installed.

  Then, the image data generated by the VDP 52 based on the CG data read from the CGROM 55 is passed through the liquid crystal interface board 28 as first and second LVDS (low voltage differential signaling) signals. The data is transmitted to the main display device DS1 and the sub display device DS2. The display device DS1 has a built-in LVDS receiver that converts LVDS signals into RGB signals. The display device DS1 includes five pairs of LVDS signals from the liquid crystal interface substrate 28 and a direct current including an LED backlight power source. It is driven by receiving power supply voltage. On the other hand, the sub display device DS1 is driven by receiving the digital RGB signal converted by the LVDS receiver of the liquid crystal interface board 28 and the DC power supply voltage including the LED backlight power supply.

  Next, the configuration of the effect control unit 22 will be described in more detail based on FIG. As shown in FIG. 4A, the effect control unit 22 includes a one-chip microcomputer 40 (effect control CPU 40) that executes processing such as voice effect, lamp effect, notice effect by effect movable body, and data transfer, and effect control CPU 40. A control memory (flash memory) 41 for storing the control program and various effect data EN, and a sound processor 42 for reproducing and outputting a sound signal based on the instructions of the effect control CPU 40 set in the built-in registers RG0 to RGn The audio memory 43 stores compressed audio data that is the original data of the audio signal to be reproduced, and the digital amplifier 46 receives the audio signal output from the audio processor 42.

  In the case of the present embodiment, the effect data EN stored in the control memory 41 includes scenario data for managing the effect progress of the lamp effect and the sound effect, lamp drive data for determining the blinking mode of the LED, and motor rotation. Motor drive data for determining the mode. The lamp driving data and the motor driving data are sequentially output bit by bit to become a lamp driving serial signal and a motor driving serial signal.

  The one-chip microcomputer 40 includes a plurality of serial input / output ports SIO and a plurality of parallel input / output ports PIO. The serial input / output port SIO includes a serial output port Soi that outputs a lamp driving signal of CHi or a motor driving signal SDATAi in synchronization with the clock signal CKi, and origin sensor signals (serial signals) of the motor groups M1 to Mn. And a serial port Si that receives the signal in synchronization with the clock signal CK3. Note that i = 0 to 2, and corresponds to the three groups of lamp groups CH0 to CH2 and the motor groups M1 to Mn driven together with the lamp groups of CH2.

  On the other hand, the parallel input / output port PIO is divided into output ports Po and Po 'and an input port Pi. A control command CMD and a strobe signal STB from the main control unit 21 are input to the input port Pi. On the other hand, operation control signals ENABLE0 to ENABLE2 are output from the output port Po ', and a control command CMD' and a strobe signal STB 'are output from the output port Po. Specifically, after the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are stepped down to a logic level corresponding to the power supply voltage 3.3 V of the one-chip microcomputer 40 in the buffer 44, It is supplied to the input port Pi in two in 8 bit units. The interrupt signal STB is supplied to the interrupt terminal of the effect control CPU 40, and the effect control unit 22 is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 includes (1) an abnormality notification and other notification control commands, and (2) a control command for specifying an outline of various effect operations resulting from winning at the symbol start opening. (Variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ relating to the performed image effect is output.

  In order to realize an image effect synchronized with such an effect operation, the effect control unit 22 sends a 16-bit control command CMD ′ along with a strobe signal (interrupt signal) STB ′ to the image control unit 23 through the output port Po. Output. In addition, when receiving the symbol designation command, the abnormality notification control command, and other control commands, the effect control unit 22 collects the 8-bit unit control commands in a 16-bit length, It is output to the image control unit 23 together with STB ′.

As described above, the audio processor 42 according to the present embodiment accesses the audio memory 43 based on an instruction (set value by the audio command SND) received from the effect control CPU 40 to the built-in registers (audio control registers) RG0 to RGn. The necessary audio signal is played back and output. As shown in the figure, the audio processor 42 and the audio memory 43 are connected to each other by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, data of 1 Gbit (= 226 * 16) can be stored in the audio memory 43. In the case of the present embodiment, the compressed audio data stored in the audio memory 43 is phrase compressed data specified by a phrase number (000H to 1FFFH) having a 13-bit length, and is a sequence of background music. (BGM), a group of effect sounds (notice sounds), and the like are stored in a maximum of 8192 types (= 2 ¹³ ), each corresponding to a phrase number. The phrase number is specified by the set value of the voice command SND transmitted from the effect control CPU 40 to the voice control registers RG0 to RGn of the voice processor 42.

  The voice command SND is a plurality (2 or 3) bytes long, and is used for a write purpose of transmitting a predetermined set value to any one of the many voice control registers RG0 to RGn built in the voice processor 42. The However, the voice command SND of the present embodiment is used not only for a write application for writing a set value such as a phrase number, but also for a read application for reading status information (error information) STS from a predetermined voice control register RGi. The predetermined audio control register RGi to be accessed is specified by a 1-byte register address.

  The setting (Write) of the set value to the sound control register RGi is not necessarily executed individually for each sound control register, and a group of sound control is performed by designating the SAC data stored in the sound memory 43. A series of setting operations for the registers RGi to RGj can be completed. Here, the SAC data is an aggregate of a maximum of 512 pieces (up to 1024 bytes) in which the register address (1 byte) of the voice control register RGi is associated with the set value (multiple bytes) in the voice control register RGi. Means. In the present embodiment, only a necessary set of such SAC data is stored in the audio memory 43 in advance, and a set of SAC data is specified by a SAC number of about 13 bits that is a single ID information. It is like that.

  Therefore, in the case of the present embodiment, the voice command SND for write use specifies a SAC number and specifies a set of SAC data, or specifies a set value and a register address individually.

  As shown in FIG. 4 (b), the connection control main part describes the effect control CPU 40 and the audio processor 42 with parallel signal lines (data buses) CD0 to CD7 capable of transmitting and receiving 1-byte data, and operation management data. Chip that selects 2-bit operation control data lines (address bus) A0 to A1 that can be transmitted, 2-bit control signal lines WR and RD that can control read / write operations, and a voice processor 42 It is connected to a select signal line CS.

  The parallel signal lines CD0 to CD7 are realized by the data bus of the effect control CPU 40, and the operation management data lines A0 to A1 are realized by the address bus of the effect control CPU 40, and are connected to the effect control CPU 40, respectively. Yes. Then, when the production control CPU 40 executes, for example, an IOREAD operation or an IOWRITE operation by program processing, the control signals WR and RD and the chip select signal CS are appropriately changed, and the audio specified by the parallel signal lines CD0 to CD7. A read / write (R / W) operation with the control register RGi is realized.

  Specifically, as shown in the time chart of FIG. 4B ', the register address of the audio control register RGi and the write data to the audio control register RGi are transmitted in parallel through the parallel signal lines CD0 to CD7, respectively. Is done. Whether the 1 byte transmitted in parallel is a register address or write data (write data) is specified by the operation management data A0 to A1.

  Accordingly, as shown in FIG. 4B, the operation management data (address data A0 to A1) is changed from [00] to [01], while 1-byte data on the data bus is changed to [voice control register RGi. A predetermined voice command SND is transmitted by transiting from “register address” → [write data to voice control register RGi]. When the write data is a plurality of bytes long as in the case of transmitting the SAC number (13 bits), the operation management data A0 to A1 of [01] are changed from [00] → [01] → [01]. → Send the data of multiple bytes while repeating [01].

  The voice command transmitted in this way is subsequently validated as long as there is no communication abnormality. However, if a communication error is recognized, such as data having a plurality of bytes inconsistent with each other, the voice command SND is not activated. Then, the error flag of the voice control register RGn is set. This error flag (status information STS) is produced by changing the operation management data A0 to A1 of the address bus from [01] to [10]. The control CPU 40 can receive it by the Read operation.

  As described above, in this embodiment, error information (abnormality of a plurality of bits) is obtained in the final cycle in which the operation management data A0 to A1 are changed from [00] → [01] →... [01] → [10]. FFH) can be obtained. Then, by retransmitting the voice command SND that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to reliably eliminate the unnaturalness that the sound effect suddenly stops.

  In the configuration of FIG. 4B, the effect control CPU 40 receives the status information STS including error information in parallel from the audio processor 42, but the configuration is not limited to this configuration. That is, it is also preferable to adopt a configuration in which an interrupt signal is output to the effect control CPU 40 when the sound processor 42 recognizes a communication error. In this case, the sound in which the communication error has occurred in the interrupt processing program of the effect control CPU 40. You can resend the command. If such a configuration is adopted, an error flag (status information STS) acquisition process that is a useless process in most cases, that is, a process of transitioning the operation management data A0 to A1 to [10] may be omitted. it can.

  As shown in FIGS. 3 and 4A, in this embodiment, the left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, it is necessary for the audio processor 42 to generate a 3-channel audio signal. If this is transmitted in parallel, the wiring between the audio processor 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the sound processor 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. Are suppressed to a total of 4-bit signal lines including the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit length serial signals SD1 and SD2.

  Here, SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SD2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The audio processor 42 transmits the audio signal L of the left channel while maintaining the channel control signal LRCLK at the L level, and outputs the audio signal R of the right channel while maintaining the channel control signal LRCLK at the H level. Transmit (see FIG. 4C). Since there is one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is overwhelmingly smaller than parallel transmission.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  4A, a buffer circuit 47 that transfers serial data SDATAi output from the serial output port Soi of the serial input / output port SIO of the one-chip microcomputer 40 and the clock signal CKi to the effect control board 22. -49 are provided (i = 0-2).

  Here, the output buffer 47 transfers the lamp drive signal SDATA0 and the clock signal CK0 output from the serial output port So0 to the shift register circuit (driver IC) of the lamp drive substrate 36. The output buffer 48 transfers the lamp drive signal SDATA1 and the clock signal CK1 output from the serial output port So1 to the driver IC of the lamp drive substrate 29. As described above, the driver ICs mounted on the lamp driving substrates 29 and 36 drive and drive the lamp groups CH0 and CH1.

  On the other hand, the buffer circuit 49 functions as an input / output buffer, and transfers the serial signal SDATA2 output from the serial output port So2 to the motor lamp driving substrate 30 together with the clock signal CK2. Further, an origin sensor signal (serial signal) indicating the origin position of the group of effect motors M1 to Mn is transferred to the serial input port Si of the one-chip microcomputer 40 in synchronization with the clock signal CK3.

  In this embodiment, the serial signal SDATA2 transferred by the buffer circuit 49 includes a lamp drive signal (serial signal) for lighting the lamp group CH2 and a motor drive signal (serial signal) for rotating the effect motors M1 to Mn. ) Are continuous. The motor lamp drive board 30 divides the series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, a series of lamp effects is executed as the effect operation determined by lottery in response to the control command CMD, and when a motor drive signal is received, the effect motors M1 to Mn are rotated to appropriately A movable notice effect is being executed.

  Next, as shown on the left side of FIG. 4A, in this embodiment, the data bus and the address bus of the effect control CPU 40 extend to the liquid crystal interface board 28. For convenience of explanation, this relationship is illustrated on the left side of FIG. 4A, but the clock circuit RTC is connected to the CPU by the lower 4 bits of the address bus of the effect control CPU 40 and the lower 4 bits of the data bus. It is configured to be arbitrarily accessible. In addition, the memory element SRAM for storing game performance information enables the effect control CPU 40 to randomly access the 16 bits of the address bus of the effect control CPU 40 and the lower 16 bits of the data bus.

  The clock circuit RTC is a clock IC (real-time clock) that measures the current date and time, and operates permanently with the secondary battery BT charged with the power supply voltage received from the effect control board 22 together with the memory element SRAM. doing. That is, while the gaming machine is powered on, the secondary battery BT (FIG. 5) is charged, and after the gaming machine is powered off, based on the charged secondary battery BT, The timekeeping operation of the clock circuit RTC is continued, and the effect data is also permanently stored (backup operation).

  As shown in FIG. 5, the clock circuit RTC of the embodiment is connected to the effect control CPU 40 through a 4-bit data bus, a 4-bit data bus, and a control bus RD + WR for Read / Write operation. Then, the effect control CPU 40 adds important game information and abnormality information related to the game operation to the memory element SRAM by adding the year / month / day information, day information and time information acquired from the clock circuit RTC. .

  This clock circuit RTC has two types of chip select terminals, CS1 and CS0 bars, and permits access from the effect control CPU 40 on condition that the input voltage to each terminal is at a normal level. It has become. Here, the CS0 bar terminal is a normal chip select terminal that receives the output of the address decoder. On the other hand, the CS1 terminal receives the output (voltage drop signal) Vo of the power supply abnormality detecting unit ER, and when the CS1 terminal receives the abnormal level output Vo, the abnormality detection flag Fos of the clock circuit RTC is automatically set. To be set.

  In the case of the present embodiment, this abnormality detection flag Fos is determined by the effect control CPU 40 together with other abnormality detection flags TEMP when the power is turned on. If the abnormality detection flag Fos is set, the date and time at that time and The time is reported. Therefore, if an abnormality in the clock function is recognized, it can be dealt with quickly.

  Even if the voltage of the secondary battery BT drops when the power is shut down, the voltage level of the secondary battery BT is quickly recovered by power recovery and the CS1 terminal returns to the normal level, so access from the effect control CPU 40 is permitted. Will be. Therefore, if the configuration of the present embodiment in which the determination process for the abnormality detection flag Fos is not employed, the abnormality of the clock circuit RTC may not be detected permanently.

  Further, the clock circuit RTC of the embodiment is configured to output the interrupt signal IRQ once a week, for example, every Friday at 21:50. In the effect control CPU 40 that receives the interrupt signal IRQ, The game information and abnormality information accumulated in the memory element SRAM so far are appropriately tabulated.

  The game information to be aggregated is a summary of history information related to the big hit state. For example, (1) the number of winnings to the symbol start opening required to become the big hit state, (2) the symbol of the big hit state, Total value and statistical value of jackpot state whether or not it is probable, (3) type of notice effect or reach effect that reached the big hit state, (4) number of consecutive chants, (5) number of balls thrown out by consecutive chans Increasing trends are included. And these total information and statistical information are alert | reported suitably according to a player's request | requirement. The player's instruction is specified, for example, by pressing the chance button 11 during the demonstration effect, and the notification content is displayed on the display device DS1.

  On the other hand, the abnormal information to be tabulated includes, for example, (1) the number of times the door is opened, (2) the detection type, the number of detection times and the detection time of the detection sensor for detecting illegal activities, This includes the number of detections, detection frequency, detection time, etc. of an act of forcibly opening the winning opening 16 with a wire or the like. The total information is displayed on the display device DS1 in response to a special operation by an attendant.

  As shown in FIG. 5A, the clock circuit RTC according to the embodiment is configured by incorporating three internal register tables Bank0 to Bank2. However, since the bank 2 register table relates to time setting and date setting, only the bank 0 and bank 1 register tables are shown in FIGS. 5 (b) and 5 (c). In any case, each register table is composed of 4 bytes × 16 registers, and the current date and time measured by the internal circuit are written in the Bank0 register table (FIG. 5B). It is configured to be.

  As shown in FIG. 5B, in the bank 0 register table, bit 3 of the first register is an abnormality detection flag Fos, and bit 2 of the 14th register indicates that the built-in temperature sensor has detected an abnormal temperature. This is a temperature abnormality flag TEMP shown. In this embodiment, when the CPU of the effect control unit 22 is reset, the value of the abnormality detection flag Fos is determined, thereby preventing the abnormal timekeeping operation from continuing. In addition, the clock circuit RTC is disposed close to the effect control CPU 40, and the temperature abnormality of the effect control CPU 40 is quickly detected by repeatedly determining the value of the temperature abnormality flag TEMP at appropriate time intervals.

  In the register table of Bank0, bit 0 of the 15th register is a Busy flag indicating that the register table is being updated. In this embodiment, the current date and time are acquired from the register table of Bank 0 on the condition that the Busy flag is in a non-Busy state (update completion). For this reason, in this embodiment, there is no possibility of acquiring halfway during the updating operation or irrational clock information, and the validity of the clock information stored in the memory element SRAM is ensured. For example, if clock information that is being updated from 1:59:59 to 2: 00: 00: 00 is acquired, there is a possibility that the clock information of 1: 0: 0 is acquired.

  Further, the register table of Bank 1 is configured so that the generation time of the interrupt signal IRQ can be set. Therefore, in this embodiment, an interrupt generation is instructed by setting 1 to bit 0 of the register No. 1 of Bank 1 (Interrupt Enable), and the day of the week of Friday is designated in the registers 0 to 8 of Bank 1. Time information of 30:30 hours is set.

  Next, the image control unit 23 will be described in detail with reference to FIGS. First, FIG. 6A is a circuit block diagram illustrating the composite chip 50 constituting the image control unit 23 including related circuit elements. As illustrated, the composite chip 50 of the embodiment includes a built-in CPU circuit 51 and a VDP circuit 52. The built-in CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays mutual transmission / reception data, and a V blank interrupt signal (VBLANK) is supplied from the VDP circuit 52 to the built-in CPU circuit 51. It has come to be.

  Here, the V blank interrupt signal corresponds to the vertical synchronization signal of the display device DS1, and defines the timing at which the output of image data for one frame of the display device DS1 is completed every 1/60 seconds. In this embodiment, of the two display circuits 74A / 74B, the display circuit 74A is configured to function constantly, while the display circuit 74B functions when necessary and operates in synchronization with the display circuit 74A. Therefore, in the end, the vertical synchronization signal (V blank interrupt signal) means that the output operation of the display circuit 74A is finished.

  The sequence operation based on the V blank interrupt will be described later. As shown in FIG. 6, the CPU IF circuit 56 has a control memory (PROGRAM_ROM) 53 for storing a control program and necessary control data in a nonvolatile manner, and about 2 Mbytes. Are connected to a work memory (RAM) 57 having the above storage capacity, and can be accessed from the built-in CPU circuit 51.

  The built-in CPU circuit 51 is a circuit having a performance equivalent to that of a general-purpose one-chip microcomputer. A watchdog timer (WDT) 58 forcibly resetting, a RAM 59 having a storage capacity of about 16 kbytes and used as a work area of the CPU, and a DMAC (Direct Memory Access Controller) for realizing data transfer without going through the CPU 60, a serial input / output port (SIO) 61 having a plurality of input ports Si and output ports So, and a parallel input / output port (PIO) 62 having a plurality of input ports Pi and output ports Po. Has been.

  For convenience, the expression “input / output port” is used. In the image control unit 23, the input / output port includes an input port and an output port that operate independently. This also applies to the input / output circuit 64p and the input / output circuit 64s described below.

  The parallel input / output port 62 is connected to an external device (the effect control board 22) through the input / output circuit 64p, and the image control CPU 63 outputs the output from the effect control unit 22 via the input circuit 64p and the parallel input port Pi. The control command CMD ′ and the interrupt signal STB ′ to be received are received. On the other hand, in this embodiment, the serial input / output port 61 and the DMAC 60 are not used.

  Next, the VDP circuit 52 will be described. The VDP circuit 52 includes a CGROM 55 that stores compressed data that is a constituent element of a still image and a moving image that constitute an image effect, and an external DRAM (Dynamic DRAM having a storage capacity of about 4 Gbits). Random Access Memory) 54, main display device DS1, and sub display device DS2 are connected.

  Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of NAND flash memory having a storage capacity of about 62 Gbit, and compression required by serial transmission. Configured to retrieve data. Therefore, the problem of skew (difference in transmission speed for each bit data) inevitably generated in parallel transmission is solved, and an extremely high-speed transmission operation becomes possible.

  A NAND flash memory is mechanically more stable than a hard disk and can be accessed at a high speed, but is a sequential access memory, and therefore has an access speed higher than that of a DRAM or SRAM (Static Random Access Memory). Inferior, the access speed decreases in the order of built-in VRAM 71> external DRAM 54> CGROM 55. However, by executing a preload operation in which a group of compressed data (CG data) is read to the DRAM 54 prior to the drawing operation, smooth random access of the CG data during the drawing operation can be realized.

  Specifically, the VDP circuit 52 has a register group 70 in which various operation parameters that define the operation of the VDP are set, and about 48 Mbytes used when generating image data to be displayed on the display devices DS1 and DS2. A VRAM (video RAM) 71, a data transfer circuit 72 that controls data transmission / reception between each part inside the chip and data transmission / reception outside the chip, a preloader 73 that executes a preload operation, and image data in the VRAM 71 are read out as appropriate. 3 (A / B / C) display circuits 74 that execute parallel image processing, a graphics decoder 75 that decodes compressed data read from the CGROM 55, and still image data and moving image data after decoding as appropriate A drawing circuit 76 for generating image data for one frame of each display device DS1, DS2 in combination with As part of the operation of the drawing circuit 76, a geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion, an SMC unit 78 capable of transmitting and receiving serial data, and a three-line (A / B / C) display circuit 74 From the CGROM 55, an output selection unit 79 that appropriately selects and outputs the output, an LVDS unit 80 that converts image data output from the output selection unit 79 into an LVDS signal, a CPUIF unit 81 that relays data transmission and reception with the CPUIF circuit 56, and CG bus IF unit 82 for relaying data reception, DRAMIF unit 83 for relaying data transmission / reception with external DRAM 54, and VRAMIF unit 84 for relaying data transmission / reception with VRAM 71.

  6B illustrates the relationship among the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, and the VRAMIF unit 84, and the register group 70, CGROM 55, DRAM 54, and VRAM 71. Part of 70 is specifically described. As shown in the figure, the CGROM 55 and the CG bus IF unit 82 are connected by a serial line, and the CGROM 55 is sequentially accessed in response to transmission of the address information Tx, and a group of CG data (compressed data) Rx is sequentially read out. It is supposed to be.

  In the first embodiment, the CG data read from the CGROM 55 is stored in the VRAM 71 via the CG bus IF unit 82 → VRAMIF unit 84. The arrow at timing T1 + δ in FIG. Show. As shown in FIG. 8, in the VRAM 71, a still picture decoding area and a moving picture decoding area are secured as work areas of the graphics decoder 75, and the CG data is compressed at a position corresponding to the type of CG data. Stored as is. Further, as shown in FIGS. 7 and 8, the VRAM 71 also has a frame buffer FB area for arranging image data for one frame after decoding.

  On the other hand, in the second embodiment in which the preloader 73 functions, the CG data is stored in the preload area of the DRAM 54 via the CG bus IF unit 82 → the DRAM IF unit 83 prior to the timing necessary for the decoding process. After that, it is randomly accessed at a necessary timing and transferred to the VRAM 71. However, in any of the embodiments, the CG data stored in the still picture decoding area or the moving picture decoding area of the VRAM 71 is decoded by the graphics decoder 75 and then placed in a proper position in the frame buffer FB area of the VRAM 71 by the drawing circuit 76. Be expanded. The arrow at timing T1 + δ ′ in FIG. 8 indicates this operation.

  Returning to FIG. 6A, the description will be continued. The data transfer circuit 72 uses a resource (storage medium) in the VDP circuit and an external storage medium as a transfer source port or a transfer destination port, and performs a data transfer operation between them. Is a circuit for executing In addition to the VRAM 71, the transfer source port includes a storage medium (resource) connected to the CPU bus, CG bus, and external DRAM bus. Similarly, the transfer destination port includes a storage medium connected to the CPU bus, CG bus, and external DRAM bus in addition to the VRAM 71. The data transfer circuit 72 is also in charge of the operation of transmitting the display list DL for specifying the display image for one frame to the drawing circuit 76 (preloader 73 when necessary) by a group of drawing commands.

  The preloader 73 is a circuit that interprets the display list DL transmitted by the data transfer circuit 72 and transfers the CG data on the CGROM 55 referred to in the display list DL to a preload area of the DRAM 54 designated in advance. At this time, the preloader 73 outputs the display list DL in which the reference destination of the CG data is rewritten to the address after transfer. The rewritten display list DL is transmitted to the drawing circuit 76 by the data transfer circuit 72.

  However, the preloader 73 is not used in the first embodiment. On the other hand, in the second embodiment, a sufficient preload area of the storage area is set in the external DRAM 54 based on the set value in the preloader register (see FIG. 6B). In the second embodiment, unless the storage area set as the preload area is used up, the preloaded compressed data is maintained without being overwritten and erased by the subsequent compressed data. Therefore, in the second embodiment using the preload process, the CGROM 55 is accessed only when necessary compressed data does not exist in the preload area. Since a sufficient storage area is secured in the preload area, no problem occurs even if CG data for a plurality of frames is preloaded at once.

  The drawing circuit 76 sequentially analyzes the drawing commands of the display list DL transmitted by the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, etc., and the frame buffer FB formed in the VRAM 71. And a circuit for drawing an image for one frame of the display device DS1 or the display device DS2.

  Here, the display list DL is composed of a group of drawing commands described in the drawing order. The drawing command includes a command that defines what image is to be drawn at which position in one frame, and the storage position (source address) of the image to be drawn, such as CGROM, is also specified. The drawing circuit 76 interprets the display list DL and generates image data for each frame of the display devices DS1 and DS2 in the frame buffer FB secured in the built-in VRAM 71 (FIG. 7). reference).

  As shown in FIG. 7, the frame buffer FB of this embodiment is divided into three sections (FBa, FBb, FBc) corresponding to the display circuits 74A / 74B / 74C, but each frame buffer FB (FBa, FBb, The drawing position of FBc) is specified by a predetermined drawing command described in the display list DL.

  Each of the three divided frame buffers FB (FBa, FBb, FBc) is a double buffer functionally divided into a drawing area and a display area, and two areas (area 0 and area 1) are alternately arranged. The usage is switched. That is, when the drawing circuit 76 writes image data in one of the two areas, the display circuit 74 reads out the image data in the other area and outputs it to the display devices DS1 and DS2. ing. However, in this embodiment, since the display circuit 74C is not used, the frame buffer FBc is not used.

  Although not particularly limited, in this embodiment, one frame of the display devices DS1 and DS2 is composed of three or more types of images (moving images and still images) in the maximum state. In other words, the display devices DS1 and DS2 are configured such that, in the maximum state, one or a plurality of moving images are reproduced while a still image that changes over time is superimposed on the background image. . For this reason, the amount of CG data may be enormous, especially for moving image effects, but the amount of CG data is suppressed by adopting a later-described data reduction method or low-speed playback method.

  The basic shape of the still image is stored in advance in the CGROM 55 as a sprite image. The basic shape is appropriately enlarged / reduced / rotated / deformed and the temporal position is changed by changing the arrangement position. ing. On the other hand, a moving image is a so-called movie that changes smoothly for a predetermined time, and M frames are compressed by a moving image compression method such as an MPEG encoding method and stored in the CGROM 55.

  In this embodiment, the compressed data of moving images is divided into normal data compressed while maintaining the original resolution (number of pixels) and reduced data compressed after the resolution is degraded. The reduced data is reduced W times (W <1) in the horizontal direction as viewed from the player and H times (H <1) in the vertical direction, but greatly reduced in the horizontal direction (W <H <1). ), Compressed after being deformed vertically. Therefore, in this embodiment, the total amount of CG data can be greatly suppressed, and a large number of moving image data is stored to increase the variation of image effects without increasing the size of the CGROM.

  For example, a moving image composed of N frames is as shown in the lower part of FIG. 10, and all pixel data is compressed in a moving image after being vertically reduced in units of rectangular image frames. Then, such reduced data is decoded into a moving image, and then enlarged to the original vertical and horizontal dimensions in units of frames in the scalers (see FIG. 7) of the display circuits 74A and 74B. That is, it is restored to the original vertical and horizontal dimensions by being enlarged 1 / W times in the horizontal direction and 1 / H times in the vertical direction.

This vertical reduction method was experimentally detected by the present inventor. According to many experimental results, the image quality of the restored image in moving image reproduction is better when the vertical reduction is performed than when the same size reduction is performed. Have confirmed. The reduction ratio is appropriately selected in the range of 0.5 ≦ H ≦ 1 according to the effect value of the moving image. In any case, H / W is about 1.1 to 1.8. Is considered appropriate. In this case, since W = H / 1.1 to H / 1.8, the data amount is H * W = H ² /1.1 to H ² /1.8, and H = 0.9. In this case, the reduction effect is 0.74 times at least. Although the moving image has been described above, the sprite image constituting the still image may be set to be reduced to an appropriate vertically long (H / W> 1) according to the effect value. However, the data reduction effect is more remarkable for moving image data.

  Regardless of whether or not a vertical reduction method that exhibits such an effect is adopted, the moving image of the present embodiment is a normal moving image that is played back at a playback speed of about 30 fps (frame per second), and the production value. Is not so high, it is roughly classified into auxiliary moving images that are played back at a low speed of about 15 fps. This point is as described at the beginning, and the auxiliary moving image is to reproduce a movie generated at 2 times speed at 1/2 times speed, that is, to reproduce a moving image of N seconds with a reproduction time of 2 × N seconds. Thus, suppression of CG data (moving image data) is attempted.

  Although not particularly limited, the normal moving image of this embodiment is an IP stream moving image composed of I frames and P frames. On the other hand, the auxiliary moving image includes not only the same IP stream moving image as the normal moving image but also an I stream moving image composed of only I frames. Here, the P frame means a frame composed of a P picture (Predictive Picture) that encodes a difference from data predicted from a past frame, and although the compression rate is high, sequential reproduction is essential.

  On the other hand, an I frame means a frame composed of an I picture (Intra Picture) that can be encoded independently without depending on other frames. Therefore, although the I stream moving image has a lower compression rate than the IP stream moving image, reverse reproduction that reproduces in reverse time order and seek reproduction that reproduces from an arbitrary position are possible. Therefore, the sub display device DS2 enhances the effect by performing irregular reproduction of such an I stream moving image (auxiliary moving image) as necessary.

  Further, in this embodiment, the I-stream moving image whose compression rate is inferior to that of the IP stream moving image is played back at a low speed on the main display device DS1 and the sub display device DS2, thereby suppressing the amount of CG data. Note that I picture and P picture are terms of the MPEG encoding system, but the compression method of this embodiment is not necessarily limited to the MPEG system, and the IP stream moving picture and I stream moving picture have other compression methods. It can also be configured by a technique.

  Corresponding to such a configuration, the graphics decoder 75 is divided into a still picture decoder and a moving picture decoder, and decodes a still picture and a moving picture encoded (compressed) by a predetermined compression algorithm by a decompression algorithm corresponding to each. (Stretching). For example, a still image is compressed by a predetermined algorithm for each image data constituting one still image, and a P frame of an IP stream moving image includes a plurality of still image data for realizing a series of moving images. Compressed based on data difference value.

  Next, the display circuit 74 is a circuit that reads out the image data from the frame buffer FB, performs final image processing, and outputs the image data (see FIG. 7). As shown in FIG. 7, the image processing in the display circuit 74 includes scaling processing for scaling the frame image by functioning the scaler, subtle color correction processing, and dithering that minimizes the quantization error of the entire image. And ring processing. Note that scaling processing includes frame data enlargement processing (horizontal 1 / W times, vertical 1 / H times) after moving image decoding for vertically reduced moving image data (vertically reduced data).

  After these image processes, a digital RGB signal (24 bits in total) is output to the display devices DS1 and DS2 together with the horizontal synchronization signal and the vertical synchronization signal. As shown in FIG. 7, in this embodiment, there are provided three systems of display circuits 74A / 74B / 74C that execute the above operations in parallel, and each display circuit 74A / 74B / 74C corresponds to each. Image data in the frame buffer FBa / FBb / FBc is read out and the final image processing is executed. However, in this embodiment, as described above, the display circuit 74C and the frame buffer FBc are not used.

  As shown in FIG. 7, the output selection unit 79 transmits the output signal of the display circuit 74A to the LVDS unit 80a, and transmits the output signal of the display circuit 74B to the LVDS unit 80b. Then, the LVDS unit 80a and the LVDS unit 80b convert the image data (24-bit digital RGB signals in total) into LVDS signals, add a pair that transmits a clock signal, and display each of them as a total of five differential signals. Outputs to the devices DS1 and DS2. The display device DS1 has a built-in LVDS signal conversion receiver RV, which restores the RGB signal from the LVDS signal and, in the maximum state, duplicates three or more types of images (moving images and still images). it's shown. However, the image data to be output does not necessarily have to be an LVDS signal, and when the transmission distance is not long as in a gaming machine, the digital RGB signal is directly displayed on the display devices DS1, DS2 via the digital RGB unit 80c. It is also suitable to transmit to.

  Next, the SMC unit 78 (Serial Management Controller) is a composite controller that incorporates an LED controller and a Motor controller. Then, an LED / motor driver (driver IC with a built-in shift register) mounted on an external board outputs an LED drive signal and a motor drive signal in synchronization with the clock signal, while at the appropriate timing, a latch pulse is output. It is configured to allow output.

  Regarding the internal circuit of the VDP circuit 52 and its operation, the operation content to be executed by the internal circuit is defined by the operation parameter (setting value) set in the register group 70 by the image control CPU 63, and the execution state of the VDP circuit 52 Can be specified by reading the operation status value of the register group 70. The register group 70 means a large number of registers mapped in a memory space (0 to FFFFFH) of about 1 Mbytes on the memory map of the image control CPU 63. The image control CPU 63 passes operation parameters of the operation parameter via the CPUIF unit 81. The WRITE (setting) operation and the READ operation of the operation status value are executed (see FIG. 6B).

  In the register group 70, a “system control register” in which initial setting values related to system operations such as an interrupt operation are written, and settings related to data transfer processing by the data transfer circuit 72 between the image control CPU 63 and the internal circuit of the VDP circuit 52 are set. A “data transfer register” in which a value and the like are written, a “GDEC register” that can specify an execution status including an error occurrence of the graphics decoder 75, and a “drawing command” and a setting value related to the drawing circuit 76 are written A “register”, a “preloader register” in which setting values relating to the operation of the preloader 73 are written, a “display register” in which setting values relating to the operations of the three divided display circuits A / B / C are written, and LEDs “LED control register” in which setting values related to the controller (SMC unit 78) are written, and Moto Controller settings related (SMC unit 78) includes and a "motor control register" to be written is, these control registers is composed each of a plurality of bytes long.

  More specifically, in the “preloader register”, (1) the preload area is set in the DRAM 54 or the VRAM 84, (2) the start address of the preload area, (3) the preload data area, The number of frames used is set. (4) The data size per frame is set. Further, the data transfer source and data transfer destination are set in the “data transfer register”, and the start position of the frame buffer FBa / FBb / FBc corresponding to the display circuit A / B / C is set in the “display register”. In addition, in each frame buffer FBa / FBb / FBc, an instruction for switching between a drawing area and a display area that changes over time, a scaler vertical / horizontal enlargement ratio, and the like are set. In addition, the “drawing register”, “preloader register”, and “data transfer register” are instructed to start execution of the drawing operation, the preload operation, and the data transfer operation.

  In any case, the internal operation of the VDP circuit 52 is realized by the image control CPU 63 writing an appropriate set value in any of the register groups 70. Therefore, the image control CPU 63 realizes an image effect based on the display list DL based on the display list DL updated at an appropriate time interval and the set value in the register constituting the register group 70 described above. In this embodiment, the lamp effect and the motor effect are handled by the effect control CPU 40 of the effect control board 22, so that the setting value is written in the LED control register and the motor control register without using the SMC unit 78. It will never happen.

  Subsequently, the image production control operation executed using the display devices DS1 and DS2 will be described with reference to the flowcharts of FIGS. 9A to 9D and the operation explanatory diagrams of FIGS. explain. These image effects are realized by an image control CPU 63 that receives a control command CMD 'from the effect control CPU 40, and a VDP circuit 52 that functions as instructed by the image control CPU 63. An instruction from the image control CPU 63 to the VDP circuit 52 is specified by an operation parameter written in the register group 70.

  As shown in FIG. 9, the image effect operation includes display list DL update processing (FIG. 9A to FIG. 9B) executed every predetermined time by the image control CPU 63 and the display list received from the image control CPU 63. This is realized by each of the sequence operations (FIGS. 9C to 9D) of the drawing circuit 76 and the display circuit 74 that operate based on the DL. Note that the image control CPU 63 sets necessary operation parameters in the register group 70 at the time of resetting the power supply or at a necessary timing thereafter so that the drawing circuit 76 and the display circuit 74 realize the sequence operation described below. doing. For example, at the moving image playback timing in which the vertically reduced data is used, the frame data enlargement ratio (horizontal 1 / W times, vertical 1 / H times) is set in the display register.

  To explain the above, the image control CPU 63 starts a display list DL update process every predetermined time δ (for example, 1/30 seconds) defined by a V blank interrupt every 1/60 seconds (ST1). The sequence operation of the drawing circuit 76 and the display circuit 74 is started (ST2). As described with reference to FIG. 6, the V blank interrupt means that the output operation of the display circuit 74 </ b> A has ended, but the drawing circuit 76 and the display circuits 74 </ b> A / 74 </ b> B are intermittently based on the processing of step ST <b> 2. Performs its own operations in parallel (see FIG. 10).

  First, a sequence operation of the drawing circuit 76 and the display circuit 74 will be schematically described with reference to FIG. First, the display list DL generated by the CPU 63 in the execution cycle starting from T1 is interpreted by the drawing circuit 76 in the execution cycle starting from T1 + δ, and the image data generated by the drawing circuit 76 is created in the frame buffer FB. The image data is output by the display circuit 74 at an execution cycle starting from T1 + 2δ. Therefore, in this embodiment, one unit operation for the image effect is completed after three execution cycles.

  The above relationship is also described in FIG. 8, and based on the display list DL transferred to the DRAM 54 at the timing T1 ′, the CG data in the CGROM 55 is read to the VRAM 71 at the timing T1 + δ (however, when necessary) The image data is created in the frame buffer FB in the same execution cycle (timing T1 + δ ′). The image data is output to the display device DS1 and the display device DS2 at a timing of T1 + 2δ.

  Next, the operation of the display circuit 74 will be specifically described by limiting to moving image reproduction. As shown in FIG. 10, the display circuit 74A continuously outputs each frame (A1, A2,... A6) of the normal moving image that is updated every predetermined time δ. On the other hand, the display circuit 74B redundantly outputs each frame of the auxiliary moving image that is updated in two cycles 2δ twice (B1, B1, B2, B2, B3, B3...). . In addition, although moving image reproduction is described here, a background image and a still image that moves with time are displayed when necessary, overlapping with a normal moving image and an auxiliary moving image. Therefore, the term “one frame” does not necessarily mean the entire frame of the display devices DS1 and DS2. This point is the same in the following description.

  As described above, in the image production of the present embodiment, a normal moving image of 30 fps and an auxiliary moving image of 15 pfs are used. By repeating the operation of FIG. 9A every 1/30 seconds (ST1) It is possible to reproduce a normal movie at 30 fps at the maximum. However, if the execution cycle δ is set short (for example, 1/60 seconds), moving image reproduction exceeding 30 fps can be realized.

  As described above, the outline has been described, and then, the process of step ST2 will be specifically described based on FIG. 9B. First, the image control CPU 63 determines whether or not the effect timing is when the sub display device DS2 is reproducing the auxiliary moving image (ST10). If the auxiliary moving image is being reproduced, the toggle variable NUM is toggled between 0 and 1 (ST11), and it is determined whether or not the toggle variable NUM = 0 (ST12).

  This process is for switching the display operation of the display circuit 74B every 1/15 second in order to appropriately reproduce the 15 pfs auxiliary moving image at a low speed. That is, if the toggle variable NUM = 0, the display area of the frame buffer FBb of the display circuit 74B is switched by writing an appropriate set value to the display register that defines the operation of the display circuit 74B (ST13).

  As shown in FIG. 7, the frame buffer FB has a double buffer structure (0/1), one of which is a drawing area to be accessed by the drawing circuit 76 and the other is an access target of the display circuit 74. Display area. Then, the drawing area and the display area are switched by the process of step ST13, and the image data for one frame generated by the drawing circuit 76 in the frame buffer FBb until then is sub-processed by the display circuit 74B in this execution cycle. It is output to the display device DS2.

  As shown in FIG. 10, in this embodiment, the operation cycle of the display circuit A / B is set to 1/60 seconds, whereas the operation cycle of the image control CPU 63 is 1/30 seconds. The display circuit A actually outputs the same image data twice. That is, the main display device DS1 that displays a normal moving image also displays the same frame twice consecutively (reproduction operation of 30 fps).

  Next, the image control CPU 63 instructs the display circuit 74B to execute the display operation when the auxiliary moving image is being reproduced (ST14). For the convenience of explanation, the display operation of the display circuit 74B is permitted every time during the reproduction of the auxiliary moving image (ST14), but actually, it is permitted only once at the start of the auxiliary moving image (slow reproduction). It is only set. Similarly, when the reproduction of the auxiliary moving image ends, the display operation of the display circuit 74B is set to stop.

  As a result of the process in step ST13, the display circuit 74B repeats the output process every 1/30 seconds, but at the timing when the process in step ST13 is not performed, the previous image data is output again twice. . As a result, an auxiliary moving image with a playback time of M seconds in N frames is played back at a low speed taking 2 × M seconds.

  As described above, the display circuit 74B switches and outputs the image data every 1/15 seconds (ST13 to ST14), but the display circuit 74A displays the display area of the frame buffer FBa every 1/30 seconds. (ST15). Next, the drawing register that defines the operation of the drawing circuit 76 is instructed to start the drawing operation (ST16).

  As a result, the drawing circuit 76 also starts a predetermined operation every 1/30 seconds. It should be noted that the operation contents to be executed by the drawing circuit 76 and the display circuit 74 are set in the drawing register and the display register by the image control CPU 63 at the time of resetting the power supply or at a necessary timing thereafter, as described above. is there.

  Returning to FIG. 9A from FIG. 9B, the description is continued. The image control CPU 63 instructs the sequence operation of the drawing circuit 76 and the display circuit 74 in the process of step ST2, and then the image effect scenario. Based on the above, a display list DL for the next frame is created. Here, the image effect scenario embodies an image effect specified by the control command CMD ′ received from the effect control CPU 40.

  In other words, image production scenarios include (1) a series of videos that continue for a certain period of time, and still images (including background images and preview images) where the drawing position, layout orientation, and scaling ratio are appropriately defined. The start time and end time of the video production of (2) which still image is to be drawn, at what time, at what position, and so on are defined. Note that even if it is a video effect, the drawn image on the display device only changes quickly and smoothly, and the same or different next image data (frame image data) is drawn on the display device at regular intervals. This is the same as a still image.

  Then, the image control CPU 63 refers to the effect scenario having such a configuration, and at each timing (T1, T1 + δ, T1 + 2δ,...), Outputs a group of drawing commands for specifying the display images of the display devices DS1, DS2. The listed display list DL is generated. The display list DL specifies, for moving images, which part of the moving image that progresses in time by specifying the storage location of the CGROM, and where the still image such as a sprite image is stored in the CGROM. It defines how and where the displayed image is drawn on which position of the display device.

  In FIG. 10, the display list for generating the frame Ai and the frame Bj is also expressed as Ai and Bj for convenience. The display list Ai identifies one frame (A1, A2,... A6) of a normal moving image or still image, and the display list Bj represents one frame (B1, B2, B3) of an auxiliary moving image that is played back at a low speed. Has been identified. As described above, the update cycle of the display list Bj is twice that of the other update cycles.

  The display list DL (= Ai + Bj) created in this way is transferred from the internal RAM 59 to the external DRAM 54 by the data transfer circuit 72 instructed by the image control CPU 63 (ST4). The arrow at timing T1 'in FIG. 8 illustrates this operation. The image control CPU 63 does not need to generate one display list DL that specifies one frame of each display device for each operation cycle, and a plurality of display lists DL1, DL2,... That specify display contents at a plurality of timings. -May be generated together in one operation cycle.

  In FIG. 10, the process of step ST15 by the image control CPU 63 is indicated by a vertical arrow from the CPU 63 to the drawing circuit 76, and the process of steps ST13 to ST15 by the image control CPU 63 is performed from the CPU 63 to the display circuit A /. It is indicated by a vertical arrow pointing towards B.

  Subsequently, a drawing operation executed in cooperation by the drawing circuit 76, the graphics decoder 75, the geometry engine 77, and the like will be described with reference to FIGS. 9C to 9D and FIG. As shown in FIG. 10, this drawing operation is repeated every fixed time (δ). For convenience, in the following description, drawing after timing T1 + 2δ executed based on the display list DL (= A1 + B1) after rewriting is performed. The operation will be described.

  The drawing circuit 76 sequentially analyzes drawing commands described in the display list DL (= A1 + B1) which is an unprocessed and oldest display list among the display lists stored in the external DRAM 54 (FIG. 9 (c) SS20), the graphics decoder 75 and the geometry engine 77 are caused to function with respect to the still image or moving image specified by the drawing command.

  Then, the still image data and the moving image data decoded by the graphics decoder 75 are expanded and developed in the still image decoding area and the moving image decoding area secured in the built-in VRAM 71 (SS22 to SS23). Next, drawing processing is executed by writing the decoded still image data and moving image data in a predetermined position of the frame buffer FB (FBa, FBb) of the VRAM 71 in a drawing mode defined by the drawing command ( SS24). The drawing mode includes the drawing position in the frame buffer FB (FBa, FBb). However, in the case of a sprite image or the like, the drawing posture, the enlargement / reduction ratio, and the like may be further defined. 77 works.

  When there are two types of display lists DL (= Ai + Bj), the decoded data of still images and moving images is written at predetermined positions of the frame buffers FBa and FBb based on the display lists DL (= Ai + Bj). Thus, the drawing operation is realized (SS24). As described above, each of the frame buffers FBa / FBb has a double buffer structure divided into a drawing area and a display area. In the drawing operation (SS24), more accurately, the drawing area of the frame buffer FBa / FBb. Decode data is written at a predetermined position in FIG.

  In any case, after the processing in step SS22 or SS23, a necessary image is drawn at a predetermined position of a predetermined frame buffer FBa / FBb based on the decoded data (moving image / still image) (SS24). This process is executed from the top to the end of the display list DL in the order in which the drawing commands are written, so that the previously drawn image is overwritten by an image drawn in the same area thereafter. . Usually, a still image is drawn on a background image having an area for the entire frame of the display device, and a moving image is further drawn thereon.

  In this way, when drawing processing for all the drawing commands is completed, a standby state is entered until the next drawing operation started intermittently (SS25). In FIG. 8, an arrow indicates that a necessary image is drawn in the frame buffer FB (FBa + FBb) at the timing T1 + δ ′.

  Finally, the operation of the display circuit 74 will be described with reference to FIG. Although this display operation is also repeated at regular time intervals (δ), for the sake of convenience, the display operation after timing T1 + 2δ shown in FIG. 10 will be described. As described above, at this timing, image data based on the display list DL (= A1 + B1) is secured in the drawing area of the frame buffer FBa / FBb. The drawing area functions as a display area in display operations after timing T1 + 2δ.

  As shown in FIG. 9D, the display circuits 74A / 74B read the image data (A1, B1) stored in the display areas of the corresponding frame buffers FBa / FBb and output them to the output selection unit 79. (SS30).

  Thereafter, based on the operation of the output selection unit 79, the image data (A1) of the frame buffer FBa output from the display circuit 74A is transmitted to the main display device DS1 via the LVDS unit 80a and output from the display circuit 74B. Since the image data (B1) in the frame buffer FBb is transmitted to the sub display device DS2 via the LVDS unit 80b, one frame (A1) of a normal moving image or still image, and one frame (B1) of an auxiliary moving image Is displayed on each display device DS1, DS2.

  The above is the same not only for the display operation starting from the timing T1 + 2δ but also for the display operation starting from the timing T1 + 3δ. However, in the display operation starting from the timing T1 + 3δ, the display circuit 74B outputs unupdated image data, so that one frame (A2) of a normal moving image or still image and one frame (B1) of an auxiliary moving image are displayed on each display device. It is displayed on DS1 and DS2. Thereafter, since the same operation is repeated, the normal moving image is reproduced at 30 fps, and the auxiliary moving image is reproduced at a low speed of 15 fps.

  The embodiment has been described above in which the normal moving image of 30 fps is displayed on the main display device DS1, and the auxiliary moving image of 15 pfs is displayed on the sub display device DS2. However, the present invention is not particularly limited. It is also preferable to display an auxiliary moving image. FIG. 11 is a diagram illustrating such an embodiment, and shows an operation state in which a normal moving image and an auxiliary moving image are displayed on the same display device DS1 at the same time.

  In order to realize such an operation, the drawing circuit 76 of this embodiment is configured so that the previous decoded data can be used again. That is, one frame of a moving image or a still image is decoded and developed in the work area (temporary storage) and transferred to the frame buffer FB, but the work area data can be reused. Note that a drawing command for realizing such an operation is particularly referred to as a reuse command in this specification.

  When such a configuration is adopted, the previous decoded data can be used again by the reuse command written in the display lists B1 ', B2', B3 '. Therefore, at the timing when the drawing circuit 76 receives the display lists B1 ', B2', B3 ',..., The drawing circuit 76 writes the decoded data immediately before to the frame buffer FBa.

  Therefore, for example, in the operation cycle starting from T1 + δ and the operation cycle starting from T1 + 2δ, the same frame B1 of the auxiliary moving image is repeatedly stored in the drawing area of the frame buffer FBa. Note that switching between the display area and the drawing area in the frame buffer FBa is performed at every execution cycle δ, and therefore, in the operation cycle starting from T1 + 2δ, both image data of the same frame B1 are stored in the two regions of the double buffer. Will be stored.

  Therefore, the display circuit 47A repeatedly outputs the same frame B1 of the auxiliary moving image to the main display device DS1 in the operation cycle starting from T1 + 2δ and the operation cycle starting from T1 + 3δ. During the two execution cycles, the normal video frame A1 and the frame A2 are displayed on the display device DS1 together with the still image frame C1 and the frame C2, so that the normal video of 30 fps and the auxiliary video of 15 fps are eventually obtained. Are simultaneously reproduced on the same display device DS1.

  As described above, the first embodiment in which the preloader 73 does not function has been described. However, to cover the weak point of sequential access to the CGROM 55, it is preferable to use the preloader 73. FIGS. 12 and 13 use the preloader 73. A second embodiment is shown. Also in the second embodiment, a normal moving image and an auxiliary moving image are displayed on the main display device DS1, and when the auxiliary moving image is played back at a low speed, an appropriate frequency (for example, twice) is displayed in a series of display lists. The reuse command is written once.

  As shown in FIG. 12, the image effect operation of the second embodiment is based on the display list update process (FIG. 12A) executed every predetermined time by the image control CPU 63 and the display list received from the image control CPU 63. This is realized by each sequence operation (FIG. 12B to FIG. 12D) of the preloader 73, the drawing circuit 76, and the display circuit 74 that operate. As with the drawing circuit 76 and the display circuit 74, the image control CPU 63 also sets the necessary operation parameters for the preloader 73 at the time of resetting the power supply or at a necessary timing thereafter so as to realize the sequence operation described below. The register group 70 is set.

  The image control CPU 63 starts list update processing every predetermined time δ (ST1), and starts sequence operations of the preloader 73, the drawing circuit 76, and the display circuit 74 (ST2). As shown in FIG. 13A, the image control CPU 63, the preloader 73, the drawing circuit 76, and the display circuit 74 execute their operations in parallel intermittently at regular intervals (δ). Become. FIG. 13B schematically shows the contents of each memory of the built-in RAM 59 of the CPU circuit, the built-in VRAM 71 of the VDP circuit, the external DRAM 54, and the CGROM 55.

  Continuing the description of the operation of the image control CPU 63, following the processing of step ST2, the image control CPU 63 updates the display list DL based on the effect scenario (ST3). Then, the image control CPU 63 lists a group of drawing commands for specifying the display image of the display device DS1 at each timing (T1, T1 + δ, T1 + 2δ,...) With reference to the effect scenario having such a configuration. Display lists DL1, DL2,... Are generated.

  As described above, when the auxiliary moving image is played back at a low speed, a reuse command is written in the even-numbered display list (DL2, DL4...).

  Next, the display list DL configured in this way is transferred to the prescribed area of the external DRAM 54 and waits until the next list update timing is reached (ST4). FIGS. 13A and 13B show that the display list DL1 is generated as a result of the operation of the image control CPU 63 starting from the timing T1, and is transferred to the external DRAM 54 at the timing T1 ′. Has been.

  In the second embodiment, the display list DL1 is rewritten by the preloader 73 at a timing T1 + δ delayed by one timing, and further at a timing T1 + 2δ delayed by one timing by the drawing circuit 76 based on the display list DL1 after rewriting. Drawing processing is performed. At a timing T1 + 3δ that is further delayed by one timing, a display screen specified by the display list DL1 appears on the main display device DS1 based on the display operation of the display circuit 74.

  Thus, in the second embodiment, the preloader 73, the drawing circuit 76, and the display circuit 74 are configured to operate with a delay of one timing. Therefore, the preloader 73 started from the timing T1 processes the oldest display list that has not been processed by the external DRAM 54, and specifically processes the display list generated at the previous timing. become. In other words, the display list DL1 generated by the image control CPU 63 at the timing T1 is processed as follows based on the operation of the preloader 73 starting from the timing T1 + δ.

  Hereinafter, the timing after timing T1 + δ will be described. The preloader 73 analyzes the display list DL1, which is the unprocessed and oldest display list, stored in the specified area of the external DRAM 54. When a drawing command required for the CG data of the CGROM is detected in the display list DL1, necessary information is acquired in the CG bus IF unit in order to acquire the group of CG data in the CG data area of the external DRAM 54. Tell 82. In addition, the storage location of the CG data in the drawing command related to the prefetching (preload) processing is rewritten from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 (SS10).

  The above operation is repeatedly executed every time a drawing command that requires CG data of CGROM is detected, and all the CG data (compressed data) for constructing one frame of the display device DS1 is transferred from the CGROM 55 to the DRAM 54. It is secured in the CG data area. Since the CG data secured once in the CG data area of the DRAM 54 is managed so as to be usable thereafter, the preload process (SS11) is skipped when the CG data secured at the previous timing is used. Then (see the broken line in FIG. 12B), only the processing (SS10) of rewriting the storage location of the CG data from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 is executed.

  Then, with respect to the display list DL1 that identifies each frame of the display device DS1, for all drawing commands described therein, the necessary CG data transfer processing to the DRAM 54 and the display list rewriting processing are completed. It waits until the next preload operation that is started intermittently (SS12). In FIG. 13B, a state in which necessary CG data is transferred from the CGROM 55 to the external DRAM 54 at the timing T1 + δ is indicated by an arrow. Note that the transferred CG data remains in a compressed state.

  The drawing operation (SS20 to SS24) and the output operation (SS30) are the same as those in the first embodiment except that the operation timing is delayed. In FIG. 13B, an arrow indicates that a necessary image is drawn in the frame buffer FBa at the timing T1 + 2δ and is output at the timing T1 + 3δ. The display operation of the display circuit 74 is also repeated every predetermined time (δ), but the normal moving image is normally reproduced at a speed of 30 fps, and the auxiliary moving image is reproduced at a low speed of 15 fps.

  In this embodiment, the processes of steps SS10 to SS11 are not necessarily limited to a single display list DL, and can be executed in order for a plurality of n display lists DLi. In this case, the image control CPU 63 generates a plurality of display lists DLi and transfers them to the DRAM 54 in one operation cycle δ, and the preloader 73 interprets and executes the plurality of display lists DLi as early as possible. Become.

  As described above, in the second embodiment, since the preloader 73, the drawing circuit 76, and the display circuit 74 perform a series of operations in parallel with each other in parallel, the high-quality and high-speed operation is performed. It is possible to realize a large-screen image production that changes without any trouble.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention. For example, in each of the above-described embodiments, simple moving image reproduction has been described. In particular, for the I stream moving image, reverse reproduction and seek reproduction are performed in each of the display devices DS1 and DS2, as necessary. In such an operation, the display list (B1, B2,... Bn) that is normally updated in the forward direction is updated in the reverse direction (Bn, Bn-1,. This is realized by starting the update from (Bi, Bi + 1,... Bn).

  Further, in each of the above embodiments, the low speed reproduction of 1/2 times has been described. However, the operation of “no switching instruction + operation instruction” in FIG. 10 and the use of the reuse command in FIG. Thus, low-speed reproduction of 1 / (M + 1) times is also possible. Also, regular low-speed playback has been described. During normal playback, the operation of “no switching instruction + operation instruction” in FIG. 10 and the use of the reuse command in FIG. 11 can be continued as many times as necessary. In this case, it is possible to realize moving image playback that is paused at an appropriate place.

  As a mode of temporary stop, for example, an operation such as quickly moving and stopping for a while can be exemplified. In any case, by including 1 / (M + 1) times low-speed playback and pause operation corresponding to the contents of the effect, the effect of the effect can be enhanced while suppressing the data capacity of the moving image data. Of course, the present invention can be suitably used not only in the ball game machine but also in other game machines with image effects such as a spinning game machine.

GM gaming machine 23 Sub-control means DS1, DS2 Display device 51 Image effect control means (built-in CPU circuit)
55 Data storage means 52 Image generation means ST3 List generation means 76 Drawing means 74 Output means

Claims (10)

A gaming machine provided with sub-control means for executing an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal based on a control command received from another control means, Sub-control means
Image production control means for centrally controlling image production;
Data storage means for storing compressed data which is a constituent element of a still image and / or a moving image constituting an image effect;
Image generating means that realizes an image effect by outputting image data generated from compressed data based on an instruction of the image effect control means to a display device,
While the image effect control means is provided with a list generation means for generating a drawing list for specifying an image display for one frame of the display device,
The image generating means receives the image data for one frame corresponding to the drawing list generated by the list generating means, and receives the image data generated by the drawing means and outputs the image data to the display device. And an output means,
The output means includes a display circuit that outputs the image data for one frame generated based on one drawing list to a predetermined display device,
The compressed data stored in the data storage means is unequally reduced by W (W <1) times in the horizontal direction and H (H ≦ 1) times in the vertical direction (W ≠ H), thereby degrading the original resolution. Contains non-uniformly reduced data that has been compressed after
For the image frame generated by the drawing means by expanding the unequal reduction data,
The gaming machine is configured to output the display circuit after enlarging the horizontal direction to 1 / W times and the vertical direction to 1 / H times based on an instruction from the image effect control means.   The gaming machine according to claim 1, wherein the unequal reduction data is stored in a data storage unit as moving image compressed data constituting a moving image.   The gaming machine according to claim 1 or 2, wherein the non-uniform reduction processing is executed for a rectangular image and is set to W <H≤1. The list generation means and the drawing means operate intermittently with a predetermined operation cycle,
The image data specified by the drawing list is generated by interpreting the drawing list generated by the list generating unit by the drawing unit at a timing delayed by N times a predetermined operation cycle. The gaming machine according to any one of to 3. The output means operates intermittently with the same operation cycle as the list generation means and the drawing means,
The gaming machine according to claim 4, wherein the image data generated by the drawing means is configured to be output by the display circuit at a timing delayed by one operation cycle. The drawing means and the output means operate intermittently with a predetermined operation cycle,
The drawing means switches between the first area and the second area and stores the image data for one frame in either of the two areas,
The gaming machine according to claim 1, wherein the output unit is configured to read the image data stored by the drawing unit with a delay of one operation cycle. The display circuit is configured to be capable of outputting standard moving image data updated in a normal cycle and low-speed moving image data updated in an operation cycle longer than the normal cycle at the same or different timing,
The gaming machine according to any one of claims 1 to 6, wherein an image frame of a standard moving image and / or a low-speed moving image is generated by expanding the non-uniformly reduced data.   At the timing one operation cycle before the display circuit outputs the image data of the low-speed moving image, the drawing unit may generate image data for one frame using the same image data as before for the low-speed moving image. The gaming machine according to claim 7.   The gaming machine according to claim 7, wherein the drawing unit may not generate image data for a low-speed moving image at a timing before one operation cycle when the display circuit outputs low-speed moving image data. Slow video is configured so that each frame of multiple consecutive frames can be encoded independently without depending on other frames,
In addition to the operation that is played in the forward direction, all or part of the operation that is played in the reverse direction, the operation that is played back from the middle, and the operation that resumes playback after being stopped halfway is executed. Item 10. The gaming machine according to any one of Items 7 to 9.

Images