JP2017090873A5 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP2017090873A5 JP2017090873A5 JP2015240045A JP2015240045A JP2017090873A5 JP 2017090873 A5 JP2017090873 A5 JP 2017090873A5 JP 2015240045 A JP2015240045 A JP 2015240045A JP 2015240045 A JP2015240045 A JP 2015240045A JP 2017090873 A5 JP2017090873 A5 JP 2017090873A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring group
- voltages
- selector
- source lines
- analog signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
Claims (1)
前記表示部を駆動するデジタルアナログ変換回路と、を有し、
前記デジタルアナログ変換回路は、
入力されるデジタルデータに応じて複数の第1電圧を生成する第1の基準電圧生成回路と、
前記複数の第1電圧を供給する第1の配線群と、
前記第1の配線群より供給される複数の第1電圧の一を選択し、第1アナログ信号を出力する第1のセレクタと、
入力されるデジタルデータに応じて複数の第2電圧を生成する第2の基準電圧生成回路と、
前記複数の第2電圧を供給する第2の配線群と、
前記第2の配線群より供給される複数の第2電圧の一を選択し、第2アナログ信号を出力する第2のセレクタと、を有し、
前記第1のセレクタから出力された前記第1アナログ信号は、バッファアンプを介して、
前記表示部が有する複数のソース線の一に出力され、
前記第2のセレクタから出力された前記第2アナログ信号は、前記バッファアンプを介して、前記複数のソース線の一に出力され、
前記第1の配線群と前記第2の配線群とは、前記複数のソース線が延びる方向と交差する方向に延び、
前記第1の配線群と前記第2の配線群とは、それぞれ、前記複数のソース線が延びる方向に沿って重ならずに設けられる半導体装置。 A display unit;
A digital-analog conversion circuit for driving the display unit,
The digital-to-analog converter circuit is
A first reference voltage generation circuit that generates a plurality of first voltages according to input digital data ;
A first wiring group for supplying the plurality of first voltages;
A first selector for selecting one of a plurality of first voltages supplied from the first wiring group and outputting a first analog signal;
A second reference voltage generation circuit for generating a plurality of second voltages according to input digital data ;
A second wiring group for supplying the plurality of second voltages;
A second selector that selects one of a plurality of second voltages supplied from the second wiring group and outputs a second analog signal;
The first analog signal output from the first selector is passed through a buffer amplifier.
Output to one of a plurality of source lines of the display unit,
The second analog signal output from the second selector is output to one of the plurality of source lines via the buffer amplifier,
The first wiring group and the second wiring group extend in a direction intersecting with a direction in which the plurality of source lines extend,
Wherein the first wiring group and the second wiring group, respectively, the semiconductor device that is provided without overlapping along the direction in which the plurality of source lines extend.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015217893 | 2015-11-05 | ||
JP2015217893 | 2015-11-05 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2017090873A JP2017090873A (en) | 2017-05-25 |
JP2017090873A5 true JP2017090873A5 (en) | 2019-01-24 |
JP6739163B2 JP6739163B2 (en) | 2020-08-12 |
Family
ID=58768186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015240045A Active JP6739163B2 (en) | 2015-11-05 | 2015-12-09 | Semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JP6739163B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7446800B2 (en) * | 2019-12-06 | 2024-03-11 | ラピスセミコンダクタ株式会社 | Display driver and display device |
-
2015
- 2015-12-09 JP JP2015240045A patent/JP6739163B2/en active Active
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