JP2017090266A5 - - Google Patents
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- JP2017090266A5 JP2017090266A5 JP2015221160A JP2015221160A JP2017090266A5 JP 2017090266 A5 JP2017090266 A5 JP 2017090266A5 JP 2015221160 A JP2015221160 A JP 2015221160A JP 2015221160 A JP2015221160 A JP 2015221160A JP 2017090266 A5 JP2017090266 A5 JP 2017090266A5
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- semiconductor device
- test fixture
- impedance analyzer
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- 239000003990 capacitor Substances 0.000 claims 27
- 239000004065 semiconductor Substances 0.000 claims 21
- 230000003071 parasitic Effects 0.000 claims 16
- 238000005259 measurement Methods 0.000 claims 13
- 230000000875 corresponding Effects 0.000 claims 4
- 238000000691 measurement method Methods 0.000 claims 1
Claims (10)
各々が、前記インピーダンスアナライザの対応する端子と前記テストフィクスチャの対応する端子の間に接続され、前記インピーダンスアナライザによって前記半導体デバイスの寄生容量を測定する際に測定周波数で共振するように構成された直列に接続されたインダクタンスとコンデンサとからなる複数のＬＣ回路を備え、
前記コンデンサは、前記テストフィクスチャに接続される外部電源の印加電圧よりも高い耐圧のコンデンサである、半導体デバイスの寄生容量測定システムにおける共振装置。 A resonance device in a semiconductor device parasitic capacitance measurement system comprising an impedance analyzer and a test fixture connectable to a semiconductor device to be tested.
Each is connected between the corresponding terminals of the corresponding terminal of the impedance analyzer the test fixture configured to resonate at a determined frequency in measuring the parasitic capacitance of the semiconductor device by the impedance analyzer It has a plurality of LC circuits consisting of an inductance and a capacitor connected in series,
The resonance device in a semiconductor device parasitic capacitance measurement system, wherein the capacitor is a capacitor having a withstand voltage higher than an applied voltage of an external power source connected to the test fixture.
第２のモニタ端子と、
前記複数のＬＣ回路の一端のうちのいずれと前記第１のモニタ端子と接続するかを切替えることが可能な第１の切替器と、
前記複数のＬＣ回路の他端のうちのいずれと前記第２のモニタ端子と接続するかを切替えることが可能な第２の切替器とを備えた、請求項１に記載の半導体デバイスの寄生容量測定システムにおける共振装置。 A first monitor terminal;
A second monitor terminal;
A first switch capable of switching which one of one end of the plurality of LC circuits is connected to the first monitor terminal;
2. The parasitic capacitance of the semiconductor device according to claim 1, further comprising: a second switch capable of switching which one of the other ends of the plurality of LC circuits and the second monitor terminal are connected to. A resonant device in a measurement system.
前記インピーダンスアナライザの端子と前記テストフィクスチャの第１の端子との間に配置される直列に接続された第１のインダクタンスと第１のコンデンサからなる第１のＬＣ回路と、
前記インピーダンスアナライザの端子と前記テストフィクスチャの第２の端子との間に配置される直列に接続された第２のインダクタンスと第２のコンデンサからなる第２のＬＣ回路と、
前記インピーダンスアナライザの端子と前記テストフィクスチャの第３の端子との間に配置される第３のコンデンサと、
前記インピーダンスアナライザの端子と前記テストフィクスチャの第４の端子との間に配置される第４のコンデンサとを備え、
前記第１のＬＣ回路は、前記インピーダンスアナライザの第１の電流印加端子および第２の電流印加端子のうちの一方に接続され、前記第３のコンデンサは、前記インピーダンスアナライザの前記第１の電流印加端子および前記第２の電流印加端子のうちの他方に接続され、
前記第２のＬＣ回路は、前記インピーダンスアナライザの第１の電圧モニタ端子および第２の電圧モニタ端子のうちの一方に接続され、前記第４のコンデンサは、前記インピーダンスアナライザの前記第１の電圧モニタ端子および前記第２の電圧モニタ端子のうちの他方に接続され、
前記第１のコンデンサ、前記第２のコンデンサ、前記第３のコンデンサおよび前記第４のコンデンサは、前記テストフィクスチャに接続される外部電源の印加電圧よりも高い耐圧のコンデンサである、半導体デバイスの寄生容量測定システムにおける共振装置。 A resonance device in a semiconductor device parasitic capacitance measurement system comprising an impedance analyzer and a test fixture connectable to a semiconductor device to be tested.
A first LC circuit comprising a first inductance and a first capacitor connected in series disposed between a terminal of the impedance analyzer and a first terminal of the test fixture;
A second LC circuit comprising a second inductance and a second capacitor connected in series, arranged between the terminal of the impedance analyzer and the second terminal of the test fixture;
A third capacitor disposed between a terminal of the impedance analyzer and a third terminal of the test fixture;
A fourth capacitor disposed between a terminal of the impedance analyzer and a fourth terminal of the test fixture;
The first LC circuit is connected to one of a first current application terminal and a second current application terminal of the impedance analyzer, and the third capacitor is connected to the first current application terminal of the impedance analyzer. Connected to the other of the terminal and the second current application terminal,
The second LC circuit is connected to one of a first voltage monitor terminal and a second voltage monitor terminal of the impedance analyzer, and the fourth capacitor is connected to the first voltage monitor of the impedance analyzer. A terminal and the other of the second voltage monitor terminals;
Said first capacitor, said second capacitor, the third capacitor and the fourth capacitor is a high-voltage capacitors than the applied voltage of the external power supply connected to the test fixture, the semiconductor device A resonant device in a parasitic capacitance measurement system.
前記インピーダンスアナライザの第１の電流印加端子と前記テストフィクスチャの第１の端子との間に配置される直列に接続された第１のインダクタンスと第１のコンデンサからなる第１のＬＣ回路と、
前記インピーダンスアナライザの第１の電圧モニタ端子と前記テストフィクスチャの第２の端子との間に配置される直列に接続された第２のインダクタンスと第２のコンデンサからなる第２のＬＣ回路と、
前記インピーダンスアナライザの第２の電圧モニタ端子と前記テストフィクスチャの第３の端子との間に配置される第３のインダクタンスと第３のコンデンサからなる第３のＬＣ回路と、
前記インピーダンスアナライザの第２の電流印加端子と前記テストフィクスチャの第４の端子との間に配置される直列に接続された第４のインダクタンスと第４のコンデンサからなる第４のＬＣ回路と、
前記第２のＬＣ回路と前記テストフィクスチャの前記第２の端子との間の第１のノードと、前記第３のＬＣ回路と前記テストフィクスチャの前記第３の端子との間の第２のノードとの間に配置される直列に接続された第５のインダクタンスと第５のコンデンサからなる第５のＬＣ回路とを備え、
前記第１のコンデンサ、前記第２のコンデンサ、前記第３のコンデンサおよび前記第４のコンデンサは、前記テストフィクスチャに接続される外部電源の印加電圧よりも高い耐圧のコンデンサであり、前記第５のインダクタンスは、共振用の可変インダクタンスである、半導体デバイスの寄生容量測定システムにおける共振装置。 A resonance device in a semiconductor device parasitic capacitance measurement system comprising an impedance analyzer and a test fixture connectable to a semiconductor device to be tested.
A first LC circuit comprising a first inductance and a first capacitor connected in series, disposed between a first current application terminal of the impedance analyzer and a first terminal of the test fixture;
A second LC circuit comprising a second inductance and a second capacitor connected in series, disposed between a first voltage monitor terminal of the impedance analyzer and a second terminal of the test fixture;
Third inductance and the third LC circuit composed of a third capacitor which is arranged between the third terminal of the test fixture and the second voltage monitoring terminal of the impedance analyzer,
A fourth LC circuit comprising a fourth inductance and a fourth capacitor connected in series, disposed between the second current application terminal of the impedance analyzer and the fourth terminal of the test fixture;
Second between the first node and the third terminal of said third LC circuits the test fixture between the second terminal of the test fixture and the second LC circuit A fifth inductance circuit connected in series and a fifth LC circuit comprising a fifth capacitor,
Said first capacitor, said second capacitor, the third capacitor and the fourth capacitor is a high-voltage capacitors than the applied voltage of the external power supply connected to the test fixture, the fifth The resonance device in the semiconductor device parasitic capacitance measurement system is a variable inductance for resonance.
テスト対象の半導体デバイスに接続可能なテストフィクスチャと、
請求項１〜８のいずれか１項に記載の共振装置とを備えた半導体デバイスの寄生容量測定システム。 An impedance analyzer;
A test fixture that can be connected to the semiconductor device under test;
A system for measuring a parasitic capacitance of a semiconductor device, comprising the resonance apparatus according to claim 1.
前記共振装置は、
各々が、前記インピーダンスアナライザの対応する端子と前記テストフィクスチャの対応する端子の間に接続され、直列に接続された可変のインダクタンスとコンデンサからなる複数のＬＣ回路と、前記複数のＬＣ回路の各々の両端に接続された複数のモニタ端子を備え、前記コンデンサは、前記テストフィクスチャに接続される外部電源の印加電圧よりも高い耐圧のコンデンサであり、
前記モニタ端子の出力に基づいて、前記複数のＬＣ回路に含まれる可変のインダクタンスのインダクタンス値を調整するステップと、
前記インピーダンスアナライザによって前記半導体デバイスの寄生容量を測定する際に測定周波数で前記複数のＬＣ回路を共振させるステップとを備えた、半導体デバイスの寄生容量の測定方法。 A semiconductor device parasitic capacitance measurement method using a semiconductor device parasitic capacitance measurement system including an impedance analyzer, a test fixture connectable to a semiconductor device to be tested, and a resonance device,
The resonant device is:
Each, each of the corresponding terminal and being connected between the corresponding terminals of the test fixture, a plurality of LC circuit consisting of variable inductance and a capacitor connected in series, the plurality of LC circuits of said impedance analyzer comprising a plurality of monitor terminals connected to both ends of the capacitor is high withstand voltage capacitor than the applied voltage of the external power supply connected to the test fixture,
Adjusting an inductance value of a variable inductance included in the plurality of LC circuits based on an output of the monitor terminal;
A step of resonating the plurality of LC circuits at a measurement frequency when the parasitic capacitance of the semiconductor device is measured by the impedance analyzer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015221160A JP6422424B2 (en) | 2015-11-11 | 2015-11-11 | Resonance device in semiconductor device parasitic capacitance measurement system, semiconductor device parasitic capacitance measurement system, and method of measuring parasitic capacitance of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015221160A JP6422424B2 (en) | 2015-11-11 | 2015-11-11 | Resonance device in semiconductor device parasitic capacitance measurement system, semiconductor device parasitic capacitance measurement system, and method of measuring parasitic capacitance of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017090266A JP2017090266A (en) | 2017-05-25 |
| JP2017090266A5 true JP2017090266A5 (en) | 2018-01-18 |
| JP6422424B2 JP6422424B2 (en) | 2018-11-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7466502B2 (en) | 2021-06-25 | 2024-04-12 | 三菱電機株式会社 | measuring device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP4143591A1 (en) * | 2020-04-29 | 2023-03-08 | Microsoft Technology Licensing, LLC | Method and apparatus for determining gate capacitance |
| US11774476B2 (en) | 2021-08-03 | 2023-10-03 | Mitsubishi Electric Corporation | Input capacitance measurement circuit and method of manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5437582A (en) * | 1977-08-29 | 1979-03-20 | Mitsubishi Electric Corp | Measuring method for capacity of three-terminal semiconductor element |
| JP2945015B2 (en) * | 1988-07-06 | 1999-09-06 | 日本ヒューレット・パッカード株式会社 | DC bias applying device |
| JP2738828B2 (en) * | 1995-09-08 | 1998-04-08 | アデックス株式会社 | Method and apparatus for measuring capacitance |
| JP3902063B2 (en) * | 2002-04-30 | 2007-04-04 | 三菱重工業株式会社 | Resistance measurement device |
| JP6431687B2 (en) * | 2014-04-24 | 2018-11-28 | キーサイト テクノロジーズ， インク． | Method and apparatus for measuring capacitance between terminals of a three-terminal device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7466502B2 (en) | 2021-06-25 | 2024-04-12 | 三菱電機株式会社 | measuring device |
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