JP2017069363A - Manufacturing method for mps diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for reducing the number of steps when manufacturing a MPS diode.SOLUTION: A manufacturing method for MPS diode includes a semiconductor layer formation step of forming a semiconductor layer from a nitride semiconductor, a film formation step of forming a silicon-containing film having an opening and a thickness of 1-100 nm, on the N type semiconductor layer, and an ion injection step of injecting ions of a P type impurity into the N type semiconductor layer from above the silicon-containing film. In the ion injection step, a P type region is formed in a part of the N type semiconductor layer where ion injection was performed via the silicon-containing film, and an N type region is formed in a part of the N type semiconductor layer where ion injection was performed via the opening.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing an MPS diode.

  Conventionally, a semiconductor device using gallium nitride (GaN) as a semiconductor material is known. Also, as a semiconductor device, an MPS diode having an MPS (Merged PiN Schottky) structure in which a PN junction diode having a PN junction structure of a P-type semiconductor and an N-type semiconductor and a Schottky Barrier Diode (SBD) are combined. Is known (for example, Patent Documents 1 and 2).

As a method for manufacturing an MPS diode using gallium nitride (GaN), Patent Document 1 describes the following manufacturing method. That is, in the manufacturing method described in Patent Document 1, (i) a step of forming a P-type epitaxial layer on an N-type gallium nitride layer, and (ii) a mask made of silicon oxide (SiO ₂ ) or the like is patterned to form P And (iii) ion-implanting N-type impurities into the P-type epitaxial layer using the mask as an ion implantation mask.

JP 2014-110310 A JP2013-232564A

  However, the manufacturing method described in Patent Document 1 is complicated. For this reason, a technique for reducing the number of steps when manufacturing an MPS diode has been desired.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.

(1) According to one form of this invention, the manufacturing method of an MPS diode is provided. This MPS diode manufacturing method includes a semiconductor layer forming step of forming an N-type semiconductor layer from a nitride semiconductor, and a silicon-containing film having an opening on the N-type semiconductor layer and having a thickness of 1 nm to 100 nm. And an ion implantation step of ion-implanting P-type impurities into the N-type semiconductor layer from above the silicon-containing film, in the ion implantation step, the silicon-containing film through the silicon-containing film. A P-type region is formed in a part of the N-type semiconductor layer subjected to ion implantation, and an N-type semiconductor is formed in a part of the N-type semiconductor layer subjected to ion implantation through the opening. A region is formed. According to the MPS diode manufacturing method of this embodiment, the number of processes when manufacturing the MPS diode can be reduced.

(2) In the above manufacturing method, the P-type impurity may be magnesium or beryllium. According to the MPS diode manufacturing method of this embodiment, the number of processes when manufacturing the MPS diode can be reduced.

(3) In the above manufacturing method, the silicon-containing film may include at least one of silicon oxide and silicon nitride. According to the MPS diode manufacturing method of this embodiment, the number of processes when manufacturing the MPS diode can be reduced.

(4) In the manufacturing method described above, silicon and the P-type impurity are implanted into a part of the N-type semiconductor layer that has undergone the ion implantation through the silicon-containing film in the ion implantation step. May be. According to the MPS diode manufacturing method of this embodiment, the number of processes when manufacturing the MPS diode can be reduced.

(5) In the above manufacturing method, the nitride semiconductor may be gallium nitride. According to the MPS diode manufacturing method of this embodiment, the number of processes when manufacturing the MPS diode can be reduced.

(6) In the manufacturing method described above, an ion implantation mask having a film thickness larger than that of the silicon-containing film is formed on the silicon-containing film after the film formation step and before the ion implantation step. You may provide the process to do. According to the MPS diode manufacturing method of this embodiment, the number of processes when manufacturing the MPS diode can be reduced.

(7) In the above-described manufacturing method, the silicon-containing film removing step for removing the silicon-containing film after the ion implantation step, and the P-type region and the N-type region after the silicon-containing film removing step. And a Schottky electrode forming step of forming a Schottky electrode that is in contact with each other. According to the MPS diode manufacturing method of this embodiment, the number of processes when manufacturing the MPS diode can be reduced.

  The present invention can be realized in various forms other than the manufacturing method of the MPS diode. For example, it can be realized in the form of an MPS diode or an apparatus for manufacturing an MPS diode using the above-described manufacturing method.

  According to the MPS diode manufacturing method of the present invention, the number of steps when manufacturing an MPS diode can be reduced.

FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor device 10 according to the first embodiment. FIG. 5 is a process diagram illustrating a method for manufacturing the semiconductor device 10. The schematic diagram which shows the state in which the through film | membrane 130 was formed. The schematic diagram which shows the state in which the photoresist film 140 was formed. The schematic diagram which shows the state in which the opening part 135 of the through film 130 was formed. The schematic diagram which shows the state in which ion implantation is performed. The schematic diagram which shows the state from which the through film | membrane 130 was removed. The figure which shows the result of the evaluation test which supports a mechanism. The figure which shows the density | concentration regarding the carrier of the cross section of the semiconductor layer 120 containing the N type area | region 124. FIG. The figure which shows the density | concentration regarding the carrier of the cross section of the semiconductor layer 120 containing the P type area | region 122. FIG. The figure explaining the effect at the time of forward bias application. The schematic diagram explaining the effect at the time of forward direction bias application. The schematic diagram explaining the effect at the time of reverse direction bias application. Sectional drawing which shows typically the structure of 10 A of semiconductor devices in 2nd Embodiment. Sectional drawing which shows the structure of the semiconductor device 10B in 3rd Embodiment typically.

A. First embodiment A-1. Configuration of Semiconductor Device FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor device 10 in the first embodiment. FIG. 1 shows XYZ axes orthogonal to each other.

  Of the XYZ axes in FIG. 1, the X axis is an axis from the left side of FIG. 1 toward the right side of the page, the + X axis direction is a direction toward the right side of the page, and the −X axis direction is a direction toward the left side of the page. It is. Of the XYZ axes in FIG. 1, the Y axis is an axis from the front of the paper to the back of the paper in FIG. 1, the + Y axis direction is a direction toward the back of the paper, and the −Y axis direction is a direction toward the front of the paper. It is. Among the XYZ axes in FIG. 1, the Z axis is an axis that goes from the bottom of FIG. 1 to the top of the paper, the + Z axis direction is a direction that goes on the paper, and the −Z axis direction is a direction that goes down the paper. It is.

  In the present embodiment, the semiconductor device 10 is an MPS (Merged PiN Schottky) diode, and is a GaN-based semiconductor device formed using gallium nitride (GaN) which is a nitride semiconductor. The semiconductor device 10 includes a substrate 110, a semiconductor layer 120, a back electrode 170, and a Schottky electrode 190. As the nitride semiconductor, for example, indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN) may be used instead of gallium nitride (GaN).

  The substrate 110 of the semiconductor device 10 is a semiconductor layer extending along the X axis and the Y axis. The substrate 110 is formed of a nitride semiconductor. In the present embodiment, the substrate 110 is an N-type semiconductor layer that is mainly formed from gallium nitride (GaN) and contains silicon (Si) as a donor. In the present specification, “mainly formed” means containing 90% or more by mole fraction.

The semiconductor layer 120 of the semiconductor device 10 is an N-type semiconductor layer extending along the X axis and the Y axis. In the present embodiment, the semiconductor layer 120 is mainly formed of gallium nitride (GaN) and contains silicon (Si) as a donor. The semiconductor layer 120 is stacked on the + Z axis direction side of the substrate 110. The semiconductor layer 120 has a main surface 121. The main surface 121 is a surface along the XY plane in which the semiconductor layer 120 extends and facing the + Z-axis direction. In the present embodiment, the donor concentration of the semiconductor layer 120 is set to 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

A P-type region 122 and an N-type region 124 are formed in contact with each other in the vicinity of the main surface 121 that is the surface layer of the semiconductor layer 120. P-type region 122 contains magnesium (Mg) as an acceptor. The acceptor concentration of the P-type region 122 is set to 1 × 10 ¹⁸ cm ⁻³ to 2 × 10 ²⁰ cm ⁻³ . On the other hand, the N-type region 124 contains silicon (Si) as a donor. The donor concentration in the N-type region is set to 1 × 10 ¹⁴ cm ⁻³ to 5 × 10 ²⁰ cm ⁻³ .

  In the present embodiment, the donor concentration distribution in the N-type region 124 is set to be higher on the main surface 121 side (+ Z-axis direction side) of the semiconductor layer 120 than on the back electrode 170 side (−Z-axis direction side). Has been. More specifically, when the N-type region 124 is divided into the main surface 121 side (+ Z axis direction side) and the back electrode 170 side (−Z axis direction side), the main surface 121 side (+ Z axis direction side) The average donor concentration in the N-type region 124 is set to be higher than the average donor concentration in the N-type region 124 on the back electrode 170 side (−Z-axis direction side).

  The Schottky electrode 190 of the semiconductor device 10 is an electrode that has conductivity, is in contact with the main surface 121 of the semiconductor layer 120, and is in Schottky junction with the N-type region 124 of the semiconductor layer 120. The Schottky electrode 190 is formed across the P-type region 122 and the N-type region 124. The Schottky electrode 190 includes a nickel (Ni) layer, a palladium (Pd) layer, and a molybdenum layer (Mo) in order from the layer in contact with the semiconductor layer 120. In this embodiment, the thickness of the nickel layer is 100 nm, the thickness of the palladium layer is 100 nm, and the thickness of the molybdenum layer is 10 nm. Note that the Schottky electrode 190 is not limited to the above electrode material, and may be any electrode that can obtain a Schottky junction with the N-type region 124 of the semiconductor layer 120. Examples of the material of the Schottky electrode 190 include palladium (Pd), nickel (Ni), and tungsten (W). Further, a metal layer formed of another metal may be provided on the Schottky electrode 190.

  The back electrode 170 of the semiconductor device 10 is an electrode that is ohmic-bonded to the −Z-axis direction side of the substrate 110. The back electrode 170 includes, in order from the layer in contact with the substrate 110, (i) a first titanium layer containing titanium (Ti), (ii) an aluminum layer containing aluminum (Al), and (iii) titanium (Ti). A second titanium layer containing, (iv) a titanium nitride layer containing titanium nitride (TiN), (v) a third titanium layer containing titanium (Ti), and (vi) a silver layer containing silver (Ag) And comprising. In the present embodiment, in order from the layer in contact with the semiconductor layer 120, the thickness of the first titanium layer is 30 nm, the thickness of the aluminum layer is 300 nm, the thickness of the second titanium layer is 20 nm, and the titanium nitride layer The thickness of the third titanium layer is 200 nm, the thickness of the third titanium layer is 20 nm, and the thickness of the silver layer is 100 nm. The back electrode 170 may be any electrode that can obtain an N-type ohmic junction with respect to the substrate 110. The back electrode 170 may include, for example, (i) a titanium (Ti) layer, a nickel (Ni) layer, and gold (Au) in order from the substrate 110 side, and (ii) from the substrate 110 side. In order, a titanium (Ti) layer and an aluminum (Al) layer may be provided.

A-2. FIG. 2 is a process diagram showing a method for manufacturing the semiconductor device 10. When manufacturing the semiconductor device 10, first, the manufacturer forms the semiconductor layer 120 from the gallium nitride (GaN), which is a nitride semiconductor layer, on the substrate 110 in Step P <b> 110. In this embodiment, the manufacturer forms the semiconductor layer 120 on the substrate 110 by epitaxial growth using an MOCVD apparatus that realizes a metal organic chemical vapor deposition (MOCVD) method. Process P110 is also referred to as a semiconductor layer formation process. In the present embodiment, the semiconductor layer 120 is an N ⁻ type semiconductor layer having a donor concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The donor concentration of the semiconductor layer 120 is preferably 1 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁶ cm ⁻³ .

  After the semiconductor layer formation process (process P110), the manufacturer forms the through film 130 including the opening 135 in the process P120. Process P120 is also referred to as a film formation process. The process P120 includes a process of forming the through film 130 (process P122) and a process of forming the opening 135 in the through film 130 (process P124).

First, the manufacturer forms the through film 130 in the process P122. The through film 130 is a film containing silicon (Si) and is also referred to as a silicon-containing film. The through film 130 preferably includes at least one of silicon oxide (SiO ₂ ) and silicon nitride (SiN). In the present embodiment, silicon oxide (SiO ₂ ) is used as the material of the through film 130. In the present embodiment, the through film 130 is formed by a chemical vapor deposition (CVD) method. As a method for forming the through film 130, a sputtering method or an atomic layer deposition (ALD) method may be used.

  FIG. 3 is a schematic diagram showing a state in which the through film 130 is formed. The through film 130 is used for injecting an N-type impurity element contained in the through film 130 into the semiconductor layer 120 by a knock-on effect in ion implantation performed in a later step. For this reason, the thickness of the through film 130 is required to be 1 nm or more. Further, the through film 130 needs to have a thickness that allows the implanted ions to pass through when performing ion implantation. For this reason, the thickness of the through film 130 is 100 nm or less. In the present embodiment, the thickness of the through film 130 is 50 nm. Here, the through film 130 is different from an ion implantation mask used for preventing ion implantation into the semiconductor layer. In a commonly used ion implantation mask, the ion implantation species stays in the ion implantation mask and prevents the ion implantation species from being implanted into the semiconductor layer. On the other hand, the through film 130 is set to a thickness that allows ion implantation species to be implanted into the semiconductor layer 120.

  Next, the manufacturer forms the opening 135 in the through film 130 in the process P124. Specifically, first, the manufacturer applies a photoresist on the through film 130, and then performs exposure and development to form a photoresist film 140 patterned into a predetermined shape.

  FIG. 4 is a schematic view showing a state in which a patterned photoresist film 140 is formed. FIG. 4 shows a portion where the through film 130 is covered by the photoresist film 140 and a portion where the through film 130 is exposed.

Thereafter, the manufacturer performs etching on the surface in the + Z-axis direction of the photoresist film 140 and the surface in the + Z-axis direction where the through film 130 is exposed to form the opening 135 of the through film 130. As the etching, dry etching such as RIE (Reactive Ion Etching) may be performed, or wet etching such as BHF (Buffered Hydrogen Fluoride) or HF (Hydrofluoric acid) may be performed.

  FIG. 5 is a schematic view showing a state in which the opening 135 of the through film 130 is formed. The manufacturer strips the photoresist film 140 with a stripping solution, thereby completing the process of forming the opening 135 in the through film 130 (process P124) and completing the film forming process (process P120).

  If necessary, a patterned ion implantation mask may be formed on the through film 130 in order to prevent ion implantation from being performed in a region where ion implantation is unnecessary, such as an element isolation region. The ion implantation mask is formed with such a thickness that the ion implantation species cannot pass through the ion implantation mask. Therefore, by forming an ion implantation mask, a region where ions are not implanted into the semiconductor layer 120 can be formed. The film thickness of the ion implantation mask is larger than the film thickness of the through film 130. Generally, the film thickness of the ion implantation mask is set larger than the ion implantation depth. For example, when the ion implantation depth is 0.5 μm, the film thickness of the ion implantation mask can be 1 μm, which is twice the ion implantation depth.

  After the film formation process (process P120), the manufacturer ion-implants P-type impurities into the semiconductor layer 120 from above the through film 130 in process P130. Process P130 is also referred to as an ion implantation process.

  FIG. 6 is a schematic diagram showing a state in which ion implantation is performed. As the P-type impurity, magnesium (Mg), beryllium (Be), or zinc (Zn) can be used. In this embodiment, magnesium (Mg) is used as the P-type impurity.

  As shown in FIG. 6, in the region of the semiconductor layer 120 where ion implantation is performed through the opening 135 of the through film 130, only magnesium (Mg) that is a P-type impurity is implanted into the semiconductor layer 120. On the other hand, in the region of the semiconductor layer 120 in which ions are implanted through the through film 130, magnesium (Mg), which is a P-type impurity, is implanted into the semiconductor layer 120 and silicon (Si) in the through film 130 is used. Is injected into the semiconductor layer 120. The reason why silicon (Si) in the through film 130 is injected into the semiconductor layer 120 is that magnesium (Mg) collides with silicon (Si) in the through film 130, so that the collided silicon (Si) is knocked on. It is conceivable that the semiconductor layer 120 is implanted due to the effect. The rate at which silicon (Si) is injected into the semiconductor layer 120 is about 1/10 to 1/100 of the rate at which magnesium (Mg), which is a P-type impurity, is injected into the semiconductor layer 120.

  In the ion implantation process (process P130), a P-type region 122 is formed in a part of the semiconductor layer 120 in which the ion implantation is performed through the through film 130. On the other hand, an N-type region 124 is formed in a part of the semiconductor layer 120 into which ions have been implanted through the opening 135. That is, in the surface layer of the semiconductor layer 120, an N-type region 124 into which magnesium (Mg) and silicon (Si) are ion-implanted and a P-type region 122 into which only magnesium (Mg) is ion-implanted are formed. . Since silicon (Si) is ion-implanted from the through film 130 in the N-type region 124, the silicon (Si) concentration in the surface layer of the N-type region 124 is higher than the silicon (Si) concentration in the surface layer of the P-type region 122. Get higher.

  After the ion implantation process (process P130), the manufacturer removes the through film 130 in process P140. Process P140 is also referred to as a through film removal process.

  FIG. 7 is a schematic diagram showing a state in which the through film 130 has been removed. In the present embodiment, the through film 130 is removed by wet etching. As an etchant for wet etching, for example, BHF (Buffered Hydrogen Fluoride) or HF (Hydrofluoric acid) can be used.

  After the through film removal step (step P140), the manufacturer heats the semiconductor layer 120 including the N-type region 124 and the P-type region 122 in step P150. Process P150 is also referred to as a heat treatment process. By this heat treatment process (process P150), impurities implanted into the semiconductor layer 120 by ion implantation can be activated. That is, by the heat treatment process, the implanted impurity is moved to an appropriate lattice position in the semiconductor layer 120, and at the same time, the damage to the semiconductor layer 120 generated at the time of ion implantation is recovered, so that silicon (Si) becomes a donor. Magnesium (Mg) is an acceptor.

The heat treatment temperature is preferably 900 ° C. or higher from the viewpoint of activating impurities more reliably. In addition, from the viewpoint of suppressing nitrogen (N) from being released from the semiconductor layer 120, the heat treatment temperature is preferably 1200 ° C. or lower, and the heat treatment is preferably performed in an atmosphere containing ammonia (NH ₃ ). Note that a protective film is preferably formed on the main surface 121 of the semiconductor layer 120 in advance before the heat treatment step (step P150). By doing in this way, it can suppress that the main surface 121 of the semiconductor layer 120 becomes rough at the time of heat processing. As a material for the protective film, for example, aluminum nitride (AlN) can be used. When the protective film is formed, the manufacturer removes the protective film after the heat treatment. For example, when aluminum nitride (AlN) is used as the protective film, the manufacturer can remove the protective film by wet etching using tetramethylammonium hydroxide (TMAH) or the like.

  After the heat treatment process (process P150), in step P160, the manufacturer forms the N-type Schottky electrode 190 that contacts the N-type region 124 and the P-type region 122 on the main surface 121 of the semiconductor layer 120. . Process P160 is also called a Schottky electrode formation process.

  In this embodiment, the manufacturer (i) forms a nickel layer mainly on nickel (Ni) on the semiconductor layer 120, and (ii) a palladium layer mainly on palladium (Pd) on the nickel layer. (Iii) A molybdenum layer is mainly formed of molybdenum (Mo) on the palladium layer. In this embodiment, the Schottky electrode 190 is formed by using a vapor deposition method, but a sputtering method may be used.

  After the Schottky electrode formation process (process P160), the manufacturer forms the back electrode 170 on the surface on the −Z-axis direction side of the substrate 110 in process P170. Process P170 is also referred to as a back electrode forming process.

  In this embodiment, the manufacturer, in order from the −Z-axis direction side of the substrate 110, the first titanium layer, the aluminum layer, the second titanium layer, the titanium nitride layer, the third titanium layer, A silver layer is sequentially formed. In the present embodiment, the back electrode 170 is formed using a vapor deposition method, but a sputtering method may be used.

  Through these steps, the semiconductor device 10 is completed.

  In the method for manufacturing the semiconductor device 10 according to this embodiment, the P-type region 122 and the N-type region 124 can be formed in the semiconductor layer 120 by the ion implantation process (process P130). Hereinafter, the mechanism by which the P-type region 122 and the N-type region 124 can be formed in the semiconductor layer 120 by the ion implantation process (process P130) will be described in detail.

A-3. Mechanism Normally, in a semiconductor layer formed of silicon (Si) or silicon carbide (SiC), the activation rate of P-type impurities and the activation rate of N-type impurities are approximately the same. Moreover, all of these activation rates are a high ratio. For this reason, even if a part of the constituent elements of the through film 130 is an N-type impurity, the proportion of the N-type impurity implanted into the semiconductor layer is smaller than the proportion of the P-type impurity implanted into the semiconductor layer. Since it is about 1/10 to 1/100 and low, the constituent elements of the through film hardly affect the formation of the P-type semiconductor region.

  On the other hand, the activation rate of N-type impurities in the semiconductor layer formed of gallium nitride (GaN) is approximately the same as the activation rate of the semiconductor layer formed of silicon (Si) or silicon carbide (SiC) (activity This ratio is high. However, as described in Patent Document 1 (Japanese Patent Laid-Open No. 2014-110310), the activation rate of P-type impurities in a semiconductor layer formed of gallium nitride (GaN) is extremely low. Specifically, when ion implantation is used, the activation rate of the P-type impurity is about 1/100 to 1/200 of the activation rate of the N-type impurity. That is, when ion implantation is used, the influence of N-type impurities on a semiconductor layer formed of gallium nitride (GaN) is extremely large. That is, when an N-type impurity is included in the constituent element of the through film 130, even if the P-type impurity is ion-implanted, the N-type impurity is injected from the through film 130 into the semiconductor layer 120 by the knock-on effect. An N-type region may be formed unintentionally.

A-4. Test Results FIG. 8 is a diagram showing the results of an evaluation test that supports the mechanism. The following samples were used for the evaluation test. Specifically, the tester first formed a semiconductor layer 120 with a thickness of 3 μm on the substrate 110 by epitaxial growth. The donor concentration of the semiconductor layer 120 is 5 × 10 ¹⁵ cm ⁻³ or less. Next, the tester formed a silicon oxide (SiO ₂ ) film with a thickness of 30 nm as the through film 130 on the surface of the semiconductor layer 120. Then, the tester performed ion implantation into the semiconductor layer 120 through the through film 130. The conditions for ion implantation are shown below.

²⁴ Mg ⁺ was used as an ion species for ion implantation. The angle at which ions were implanted was an angle inclined by 7 ° from the perpendicular to the (0001) plane that is the surface of the semiconductor layer 120. Ion implantation was performed three times under the following conditions. The reason for performing it three times is that the concentration of magnesium (Mg) is uniform at about 5.0 × 10 ¹⁹ cm ^{−3 in} the region from the interface between the semiconductor layer 120 and the through film 130 to a depth of 0.2 μm. This is because of the adjustment.
Ion implantation first implantation energy: 200 keV, dose: 1.4 × 10 ¹⁵ cm ⁻²
Ion implantation second implantation energy: 80 keV, dose: 4.5 × 10 ¹⁴ cm ⁻²
Ion implantation third implantation energy: 20 keV, dose: 1.5 × 10 ¹⁵ cm ⁻²

FIG. 8 shows the result of measuring the impurity concentration in the semiconductor layer 120 of this sample by secondary ion mass spectrometry (SIMS). In FIG. 8, the horizontal axis indicates the depth (μm) of the semiconductor layer 120 in the −Z-axis direction, and the vertical axis indicates the concentration (cm ⁻³ ) of silicon (Si) and magnesium (Mg). The depth of 0 μm is the interface between the semiconductor layer 120 and the through film 130.

As shown in FIG. 8, the concentration of silicon (Si), which is an N-type impurity, is about 1 × 10 ²⁰ cm ⁻³ at a depth of 0 μm (the main surface 121 of the semiconductor layer 120), and at a depth of 0.2 μm. About 1.5 × 10 ¹⁷ cm ⁻³ . On the other hand, the concentration of magnesium (Mg), which is a P-type impurity, is about 4 × 10 ¹⁹ cm ⁻³ at a depth of 0 μm (the main surface 121 of the semiconductor layer 120) and about 3.times. At a depth of 0.2 μm. It is 0 * 10 < ¹⁹ > cm <^-3> .

The following can be understood from the result of FIG. That is, considering the activation rate (0.5%) during ion implantation of magnesium (Mg), the hole concentration is 2 × 10 ¹⁷ cm ^{−3 at} a depth of 0 μm and 1.5 × at a depth of 0.2 μm. 10 ¹⁷ cm ⁻³ . On the other hand, since the activation rate of silicon (Si) is 90% or more, the electron concentration is about 1 × 10 ²⁰ cm ^{−3 at} a depth of 0 μm and about 1.5 × 10 ¹⁷ cm at a depth of 0.2 μm. ^-3 . From the above, it can be seen that from the depth of 0 μm to about 0.2 μm, the electron concentration is higher than the hole concentration, and an N-type region is formed. That is, when magnesium (Mg) ions are implanted through the through film 130, an N-type region is formed in the surface layer up to a depth of 0.2 μm, not a P-type region.

  In the method for manufacturing the semiconductor device 10 according to this embodiment, in the ion implantation process (process P130), ions are implanted into the semiconductor layer 120 from the through film 130 including the opening 135. Therefore, a P-type region 122 made of magnesium (Mg) is formed in the region of the semiconductor layer 120 immediately below the opening 135 of the through film 130, and silicon (Mg) is formed in the region of the semiconductor layer 120 directly below the through film 130. It can be seen that an N-type region 124 of Si) is formed.

  FIG. 9 and FIG. 10 show the concentration distribution in the AA cross section and the BB cross section in the MPS diode shown in FIG. 1 manufactured by using this manufacturing method.

  FIG. 9 is a diagram showing the carrier concentration in the cross section of the semiconductor layer 120 including the N-type region 124 in the AA cross section of FIG. The horizontal axis in FIG. 9 indicates the depth (μm) of the semiconductor layer 120 in the −Z-axis direction. The depth of 0 μm is the interface between the semiconductor layer 120 and the Schottky electrode 190. The vertical axis in FIG. 9A is a logarithmic display and indicates impurity concentration, the vertical axis in FIG. 9B indicates electron concentration and hole concentration, and the vertical axis in FIG. 9C indicates carrier concentration. Show.

  In FIG. 9A, the concentration of magnesium (Mg) is indicated by a broken line, and the concentration of silicon (Si) is indicated by a solid line. As shown in FIG. 9A, the concentration of silicon (Si) in the semiconductor layer 120 is high at the interface with the Schottky electrode 190 (near depth 0), and decreases as the depth increases. It becomes almost constant. In other words, the concentration of silicon (Si) in the semiconductor layer 120 gradually decreases from the Schottky electrode side (+ Z-axis direction side) toward the back electrode side (−Z-axis direction side), and then becomes substantially constant. Become. Here, “concentration is substantially constant” indicates that the concentration is within ± 10 times.

  In the present embodiment, as shown in FIG. 9A, the concentration of silicon (Si) gradually decreases as the depth increases. However, instead of this, the concentration of silicon (Si) may be lowered step by step as the depth increases. In this embodiment, as shown in FIG. 9A, there is no region where the concentration of silicon (Si) as a donor increases as the depth increases.

  As shown in FIG. 9A, as the silicon (Si) concentration distribution in the N-type region 124 in this embodiment, the N-type region 124 is divided into the main surface 121 side (+ Z-axis direction side) and the back electrode 170 side (− When it is divided into two (Z-axis direction side), the average donor concentration on the interface side is higher than the average donor concentration on the back electrode 170 side. With such a concentration distribution, the depletion layer easily spreads in the N-type region 124 on the back electrode 170 side, and as a result, the Schottky junction between the semiconductor layer 120 and the Schottky electrode 190 is protected. Become.

  9C, the N-type carrier concentration in the N-type region 124 on the back electrode 170 side and the region of the semiconductor layer 120 in the direction of the back electrode 170 with respect to the N-type region 124 (hereinafter referred to as a semiconductor under the N-type region). This shows a case where the N-type carrier concentration in the region is substantially the same. However, when the electron concentration in the N-type region 124 in the vicinity of the back electrode 170 side approaches the hole concentration in the N-type region 124, the N-type region 124 in the vicinity of the back electrode 170 side has N in the semiconductor region under the N-type region. A region lower than the mold carrier concentration is partially formed. In this case, the depletion layer is selectively within the N-type region 124 in the vicinity of the back electrode 170, rather than spreading into the semiconductor layer 120 from the N-type region 124 on the back electrode 170 side toward the semiconductor region below the N-type region. Will spread. For this reason, the Schottky junction between the semiconductor layer 120 and the Schottky electrode 190 is further protected, which is preferable.

  FIG. 9A also shows the concentration distribution of magnesium (Mg). In the N-type region 124, magnesium (Mg) is present at a higher concentration than silicon (Si). However, the activation rate of magnesium (Mg) is about 0.5%, but the activation rate of silicon (Si) is 90% or more. For this reason, as shown in FIG. 9B, in the N-type region 124, the electron concentration shown by the solid line is higher than the hole concentration shown by the broken line. FIG. 9C shows a carrier concentration distribution obtained as a result of charge compensation between electrons and holes. As shown in FIG. 9C, the N-type region 124 and the semiconductor region under the N-type region are N-type carrier regions.

  FIG. 10 is a diagram showing the carrier concentration in the cross section of the semiconductor layer 120 including the P-type region 122 in the BB cross section of FIG. The horizontal axis in FIG. 10 indicates the depth (μm) of the semiconductor layer 120 in the −Z-axis direction. The depth of 0 μm is the interface between the semiconductor layer 120 and the Schottky electrode 190. The vertical axis in FIG. 10 is logarithmic display, the vertical axis in FIG. 10A indicates the impurity concentration, and the vertical axis in FIG. 10B indicates the electron concentration and the hole concentration.

  As described above, since the N-type region 124 is ion-implanted through the through film 130, magnesium (Mg) and silicon (Si) are implanted into the N-type region 124. On the other hand, since ions are implanted into the P-type region 122 through the opening 135, only magnesium (Mg) is implanted into the P-type region 122. For this reason, as shown in FIG. 10A, in the P-type region 122, the magnesium (Mg) concentration distribution illustrated by a broken line is present, and silicon (Si) hardly exists as illustrated by a solid line. When the electron concentration and hole concentration are calculated in consideration of the activation rate, FIG. 10B is obtained. As can be seen from FIG. 10B, the P-type region 122 has more holes than electrons, and a P-type carrier region is formed.

A-5. Effects in the present embodiment A manufacturing method described in Patent Document 1 (Japanese Patent Laid-Open No. 2014-110310), which is a conventional manufacturing method, includes (i) a step of forming a p-type epitaxial layer on an n-type gallium nitride layer, (Ii) a step of patterning a mask made of silicon oxide (SiO 2) or the like to form on the p-type epitaxial layer; and (iii) a step of ion-implanting n-type impurities into the p-type epitaxial layer using the mask as an ion implantation mask. And comprising.

  However, in the method for manufacturing the semiconductor device 10 of the present embodiment, the P-type region 122 and the N-type region 124 can be simultaneously formed in the semiconductor layer 120 by the ion implantation process (process P130). For this reason, in the manufacturing method of the semiconductor device 10 of this embodiment, compared with the manufacturing method described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2014-110310), the MPS diode is not used without the step (i). Can be manufactured. For this reason, according to the manufacturing method of the semiconductor device 10 of this embodiment, a process can be reduced rather than the conventional manufacturing method.

  Further, as the silicon (Si) concentration distribution in the N-type region 124 in this embodiment, the N-type region 124 is divided into two parts on the main surface 121 side (+ Z axis direction side) and the back electrode 170 side (−Z axis direction side). In this case, the average donor concentration on the interface side is higher than the average donor concentration on the back electrode 170 side. By using such a concentration distribution, the rising voltage can be reduced when a forward bias is applied, so that the efficiency of the power converter can be improved. On the other hand, the withstand voltage can be improved during reverse bias application. Hereinafter, this mechanism will be described.

  FIG. 11 and FIG. 12 are diagrams for explaining the effect at the time of forward bias application. Generally, in the MPS diode when forward bias is applied, the rising voltage of the Schottky junction is lower than that of the PN junction. For this reason, the effect of applying a forward bias will be described below with a focus on the Schottky junction.

FIG. 11 shows a profile of Ec (energy at the bottom of the conduction band) in the semiconductor layer 120 including the N-type region 124 and the Schottky electrode 190 in the AA cross section of FIG. When the N-type region 124 has a uniform donor concentration distribution, Ec becomes a broken line. On the other hand, in this embodiment, when the N-type region 124 is divided into the main surface 121 side (+ Z axis direction side) and the back electrode 170 side (−Z axis direction side), the average donor concentration on the main surface 121 side is It is higher than the average donor concentration on the back electrode 170 side. For this reason, in the case of this embodiment, Ec becomes like a dashed-dotted line. That is, the Schottky barrier width is reduced as compared with the case of the broken line, and in particular, the Schottky barrier width is significantly reduced above the Schottky barrier. Therefore, according to this embodiment, it is possible to reduce the Schottky barrier height phi _B on effective. As a result, the rising voltage during forward bias application can be reduced. If the N-type region 124 has a uniformly high donor concentration distribution, a conduction band (Ec) as shown by a solid line is formed, and the Schottky barrier width also decreases in this case. However, in this case, as will be described later, there arises a problem that the depletion layer does not spread at the time of reverse bias and the breakdown voltage is lowered.

  FIG. 12 is a diagram showing current-voltage characteristics. The horizontal axis indicates the voltage V, and the vertical axis indicates the current I. The + side of the horizontal axis indicates the forward bias. A broken line indicates a case where the P-type region 122 has a uniform donor concentration distribution (broken line in FIG. 11), and a solid line indicates a case of the present embodiment (dashed line in FIG. 11). From FIG. 12, it can be seen that the rising voltage at the time of forward bias application is lower in this embodiment than in the case where the P-type region 122 has a uniform donor concentration distribution. That is, when the diode of this embodiment is used for an inverter, power loss can be further reduced.

  FIG. 13 is a schematic diagram for explaining the effect when a reverse bias is applied. FIG. 13A is a schematic diagram of the semiconductor device 10 of this embodiment, and FIGS. 13B and 13C show the spread of the depletion layer in the region T shown in FIG. A solid line L in the figure indicates the spread of the depletion layer extending from the P-type semiconductor toward the N-type semiconductor. FIG. 13C shows the case where the N-type region 124 has a uniform donor concentration distribution, and FIG. 13B shows the case of this embodiment. In the case of this embodiment, when the N-type region 124 is divided into the main surface 121 side (+ Z-axis direction side) and the back electrode 170 side (−Z-axis direction side), the average donor concentration on the main surface 121 side is It is higher than the average donor concentration on the back electrode 170 side. For this reason, in the N-type region 124 on the back electrode 170 side, the donor concentration is low and the depletion layer spreads at a lower voltage. As a result, as shown in FIG. 13B, the Schottky junction formed between the N-type region 124 and the Schottky electrode 190 is covered with a depletion layer, and the Schottky junction is effectively formed by the depletion layer. Protected.

  In particular, in the present embodiment, in the N-type region 124, there is no region in which the concentration of silicon (Si) as a donor increases as it progresses toward the −Z axis direction side, so that the depletion layer spreads smoothly and uniformly when a bias is applied. Can do. The Schottky junction is effectively protected by the depletion layer. As a result, the Schottky junction is more effectively protected by the depletion layer. For this reason, the withstand voltage can be improved when the reverse bias is applied. In addition, when the donor concentration of the N-type region 124 is uniformly high compared to the donor concentration of the semiconductor layer 120, the depletion layer is difficult to spread when a reverse bias is applied, and the Schottky junction is protected by the depletion layer. It becomes impossible and a pressure | voltage resistance will fall. For this reason, when the N-type region 124 is divided into the main surface 121 side (+ Z-axis direction side) and the back electrode 170 side (−Z-axis direction side) as in the present embodiment, the average donor on the main surface 121 side. The concentration is preferably higher than the average donor concentration on the back electrode 170 side.

  On the other hand, as shown in FIG. 13C, when the N-type region 124 has a uniform donor concentration distribution, the depletion layer spreads with a constant width as a whole. As a result, a large reverse bias must be applied before the Schottky junction is protected by the depletion layer. Therefore, compared to the case where the P-type region 122 has a uniform donor concentration distribution, the Schottky junction is protected by the depletion layer in this embodiment, and the breakdown voltage can be improved. The current-voltage characteristic when the P-type region 122 has a uniform donor concentration distribution is as shown by the broken line in FIG. It can also be seen from FIG. 12 that the breakdown voltage can be improved in this embodiment compared to the case where the P-type region 122 has a uniform donor concentration distribution.

B. Second Embodiment FIG. 14 is a cross-sectional view schematically showing a configuration of a semiconductor device 10A in a second embodiment. In the semiconductor device 10 according to the first embodiment, the N-type region 124 is arranged at the end in the X-axis direction. However, in the semiconductor device 10A according to the second embodiment, the P-type region 122 is provided at the end in the X-axis direction. The points are different, but the rest is the same.

  In the present embodiment, the semiconductor device 10A has four P-type regions 122 and three N-type regions 124, but any number of these may be used.

  According to the present embodiment, since the P-type region 122 is arranged at the end portion in the X-axis direction, the N-type region 124 close to the end portion in the X-axis direction of the semiconductor device 10A is protected by the depletion layer. It will be. For this reason, it is possible to improve the breakdown voltage at the end of the semiconductor device 10A in the X-axis direction.

C. Third Embodiment FIG. 15 is a cross-sectional view schematically showing a configuration of a semiconductor device 10B in a third embodiment. The semiconductor device 10B in the third embodiment is different from the semiconductor device 10A in the second embodiment in that a field plate structure is adopted. Specifically, a field plate electrode 160 is formed at the end of the PN junction interface between the P-type region 122 and the semiconductor layer 120 at the end in the X-axis direction of the semiconductor device 10B via the insulating film 150. In the present embodiment, the insulating film 150 is made of silicon oxide (SiO ₂ ), and the field plate electrode 160 is made of aluminum (Al).

According to the present embodiment, since electric field concentration at the end of the PN junction interface can be suppressed, the breakdown voltage can also be improved at the end in the X-axis direction of the semiconductor device 10A. For example, silicon nitride (SiN) or aluminum oxide (Al ₂ O ₃ ) may be used as the material of the insulating film 150, and examples of the material of the field plate electrode 160 include aluminum silicon (AlSi) or aluminum. Silicon copper (AlSiCu) or copper (Cu) may be used.

D. Other Embodiments The present invention is not limited to the above-described embodiments, and can be realized with various configurations without departing from the spirit of the present invention. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above-described effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

  In the above-described embodiment, the Schottky electrode 190 includes a nickel (Ni) layer, a palladium (Pd) layer, and a molybdenum layer (Mo) in order from the layer in contact with the semiconductor layer 120. However, the present invention is not limited to this. The Schottky electrode 190 may include, for example, (i) a palladium (Pd) layer and a gold (Au) layer in order from a layer in contact with the semiconductor layer 120, (ii) a nickel (Ni) layer, A gold (Au) layer may be provided. Further, the Schottky electrode 190 may be only a palladium (Pd) layer, only a nickel (Ni) layer, or only a tungsten (W) layer.

  In the embodiment described above, the semiconductor device 10 includes the substrate 110 between the semiconductor layer 120 and the back electrode 170. However, the present invention is not limited to this. The semiconductor device 10 may not include the substrate 110, and the back electrode 170 may be formed on the surface of the semiconductor layer 120 on the −Z axis direction side.

  In the above embodiment, the back electrode 170 may be made of other materials. As other materials, other metals such as vanadium (V) and hafnium (Hf) may be used.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 10A ... Semiconductor device 10B ... Semiconductor device 110 ... Substrate 120 ... Semiconductor layer 121 ... Main surface 122 ... P-type area | region 124 ... N-type area | region 130 ... Through film 135 ... Opening part 140 ... Photoresist film 150 ... Insulating film 160 ... Field plate electrode 170 ... Back electrode 190 ... Schottky electrode T ... Region

Claims (7)

A semiconductor layer forming step of forming an N-type semiconductor layer from a nitride semiconductor;
Forming a silicon-containing film having an opening and a thickness of 1 nm to 100 nm on the N-type semiconductor layer; and
An ion implantation step of ion-implanting P-type impurities into the N-type semiconductor layer from above the silicon-containing film,
In the ion implantation step,
A P-type region is formed in a part of the N-type semiconductor layer subjected to the ion implantation through the silicon-containing film,
A method for manufacturing an MPS diode, wherein an N-type region is formed in a part of the N-type semiconductor layer into which the ion implantation has been performed through the opening. It is a manufacturing method of the MPS diode according to claim 1,
The method for manufacturing an MPS diode, wherein the P-type impurity is magnesium or beryllium. A method of manufacturing an MPS diode according to claim 1 or 2,
The method for manufacturing an MPS diode, wherein the silicon-containing film includes at least one of silicon oxide and silicon nitride. It is a manufacturing method of the MPS diode according to any one of claims 1 to 3,
In the ion implantation step,
A method of manufacturing an MPS diode, wherein silicon and the P-type impurity are implanted into a part of the N-type semiconductor layer that has undergone the ion implantation through the silicon-containing film. A method for manufacturing an MPS diode according to any one of claims 1 to 4,
The method for manufacturing an MPS diode, wherein the nitride semiconductor is gallium nitride. A method for producing an MPS diode according to any one of claims 1 to 5, further comprising:
After the film formation step and before the ion implantation step,
An MPS diode manufacturing method comprising a step of forming an ion implantation mask having a film thickness larger than that of the silicon-containing film on the silicon-containing film. The method of manufacturing an MPS diode according to any one of claims 1 to 6, further comprising:
After the ion implantation step, a silicon-containing film removal step of removing the silicon-containing film,
A method of manufacturing an MPS diode, comprising: a Schottky electrode forming step of forming a Schottky electrode in contact with the P-type region and the N-type region after the silicon-containing film removing step.

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