JP2017058738A - Information processing apparatus and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time to pre-load data stored in an external memory in an information processing apparatus comprising a plurality of cores.SOLUTION: An image forming apparatus comprises: a core 101 and a core 102; an L2 cache memory 121; and a main storage device 30 (external memory) that stores data. The core 101 includes request means that requests first partial data being part of data stored in the external memory, and the core 102 includes second request means that requests second partial data different from the first partial data.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an information processing apparatus and an image forming apparatus.

  In an information processing apparatus such as an image processing apparatus, processing using data read from an external memory is performed. However, since the core process stalls (waits) during memory access, frequent access to the external memory is a factor that hinders the speeding up of the process. For example, Patent Document 1 describes a technique in which data in an external memory is copied (preloaded) in advance into a cache memory inside the processor, and the core of the processor reads the data from the cache memory and performs processing.

JP 2011-223145 A

  In recent years, processor cores have become multi-core. The multi-core is intended to increase the speed by performing processing in parallel, but the time for preloading the data stored in the external memory cannot be shortened.

  The present invention provides a technique for shortening the time for preloading data stored in an external memory in an information processing apparatus having a plurality of cores.

  The present invention includes a first core, a second core that performs parallel processing with the first core, a cache memory that is shared by the first core and the second core, and an external memory that stores data. The first core includes first request means for requesting first partial data which is a part of the data, and the second core is a part of the data different from the first partial data. Second cache requesting means for requesting second partial data, the cache memory responding to a request from the first requesting means and a request from the second requesting means; Read means for reading out partial data from the external memory, and the first core and the second core respectively have a smaller amount of the first partial data and the second partial data stored in the cache memory. Also provides an information processing apparatus for performing processing using a part.

  The information processing apparatus equally divides the N cores including the first core and the second core, and the data into N partial data each including only a portion where addresses are continuous, And allocating means for allocating data to any of the N cores.

  The information processing apparatus equally divides the N cores including the first core and the second core and the data into N partial data each including a portion where addresses are discontinuous, And assigning means for assigning to any of the N cores.

  The external memory includes a DRAM, and each of the N partial data includes a portion where addresses are continuous, and the data size of the portion where the addresses are continuous is 1 when the reading means reads data from the DRAM. It may be less than the amount of data read per round.

  The processing in the first core and the second core may be processing for converting an index corresponding to a pixel into a pixel value, and the data may be a table for converting the index into the pixel value.

  The present invention also provides a first core, a second core that performs parallel processing with the first core, a first cache memory dedicated to the first core, a second cache memory dedicated to the second core, A cache memory shared by the first core and the second core; and an external memory storing data, wherein the first core requests a first partial data which is a part of the data. And the second core has second request means for requesting second partial data which is a part of the data different from the first partial data, and the first cache memory In response to a request from one requesting means, the first partial data is obtained from the external memory, and the second cache memory is configured to obtain the first partial data in response to a request from the second requesting means. 2nd partial data to the external Second acquisition means for acquiring from the memory, wherein the first core performs processing using the first partial data stored in the first cache memory, and the second core Provided is an information processing apparatus that performs processing using the second partial data stored in a memory.

  Furthermore, the present invention provides an image forming apparatus including any one of the information processing apparatuses described above and an image forming unit that forms an image according to a result processed by the first core and the second core.

According to the information processing apparatus of the first aspect, the data stored in the external memory is preloaded as compared with the case where each of the first core and the second core preloads the entire data stored in the external memory. Time can be shortened.
According to the information processing apparatus of the second aspect, the number of data requests from each core is reduced to 1 / compared to the case where each of the first core and the second core preloads the entire data stored in the external memory. N can be reduced.
According to the information processing apparatus of the third aspect, it is possible to shorten the time for reading data from the external memory as compared with the case where the data is simply divided into N equal parts.
According to the information processing apparatus of the fourth aspect, it is possible to reduce the number of accesses to the external memory as compared with the case where the data size of the portion where the addresses are continuous is small.
According to the information processing apparatus of the fifth aspect, it is possible to shorten the time for preloading a table used for image processing for converting an index into a pixel value.
According to the information processing apparatus of the sixth aspect, the data stored in the external memory is preloaded as compared with the case where each of the first core and the second core preloads the entire data stored in the external memory. Time can be shortened.
According to the image forming apparatus of the seventh aspect, the data stored in the external memory is preloaded as compared with the case where each of the first core and the second core preloads the entire data stored in the external memory. Time can be shortened.

The figure which illustrates the cache memory structure of CPU90 which concerns on related technology Sequence chart illustrating preload processing with a single core Sequence chart illustrating preload processing with multiple cores 1 is a diagram illustrating a configuration of an image forming apparatus 1 according to an embodiment. The figure which illustrates the function structure of the image forming apparatus 1 regarding the preload of data Flowchart illustrating image processing in image forming apparatus 1 Schematic diagram showing the outline of LUT division The figure which shows the specific example of the division | segmentation of LUT The figure which shows another specific example of the division | segmentation of LUT Sequence chart illustrating preload processing in image forming apparatus 1 The schematic diagram which shows the outline | summary of the division | segmentation of LUT which concerns on a modification

1. Outline First, consider the following image processing as an example. An index value is calculated from the pixel value of the input image. The entry value indicated by the index value is acquired from the lookup table. An output pixel value is calculated from the acquired entry value. One method for speeding up such image processing is to use a so-called multi-core CPU and process pixels in different regions (for example, odd rows and even rows) in parallel with different cores.

  Specifically, each core (1) reads an input pixel, (2) calculates an index value, (3) reads an entry value from a lookup table, (4) calculates an output pixel value, and (5) outputs A process of storing pixel values is performed. Of these, processes (1), (3), and (5) involve access to an external memory. The external memory is a memory formed on a chip different from the CPU, and corresponds to a main storage device (main memory) of a computer, for example. When accessing the external memory, the instruction execution of the core stalls (becomes a standby state). Since access to the external memory is relatively slow, frequent access to the external memory is a factor that hinders speeding up.

  In order to cope with this problem, a technique is known in which a lookup table stored in an external memory is copied, that is, preloaded to a cache memory prior to image processing. By preloading the LUT (Look Up Table) into the cache memory, access to the external memory in the process (3) can be eliminated.

  FIG. 1 is a diagram illustrating a cache memory configuration of a CPU 90 according to related technology. The CPU 90 has a plurality of cores, in this example, four cores 901 to 904. Here, the “core” of the processor refers to a portion of the processor that executes instructions and performs operations. The CPU 90 further includes cache memories 911 to 914 and a cache memory 921. The cache memories 911 to 914 are primary caches (so-called L1 caches) and are dedicated to the cores 901 to 904, respectively. The cache memory 921 is a secondary cache (so-called L2 cache). The cache memory 921 is shared by the cores 901 to 904. In general, the L1 cache may be included and referred to as “core”, but here the “core” does not include the L1 cache.

  The primary cache is a cache memory that is accessed with the highest priority from the core, and the secondary cache is a cache memory that is accessed with the next priority of the primary cache. The primary cache is faster and has a smaller capacity than the secondary cache. When an access request to the main memory (external memory) occurs, the core first checks whether the data at the access destination address is stored in the primary cache. When data at an access destination address (hereinafter simply referred to as “access destination data”) is stored in the primary cache, the core reads data from the primary cache. The fact that the access destination data is stored in the cache memory is called “hit”, and the rate at which hits occur is called “hit rate”. If the access destination data is not stored in the primary cache, the core checks whether the access destination data is stored in the secondary cache. When the access destination data is stored in the secondary cache, the core reads the data from the secondary cache. When the access destination data is not stored in the secondary cache, the core reads the data from the main memory 30 which is an external memory.

  When reading data from an address in the memory space, the core first makes a read request to the L1 cache dedicated to the core. The L1 cache checks whether the data at the designated address is stored in the L1 cache. When the data at the designated address is stored in the L1 cache, the L1 cache outputs the data at the designated address to the requesting core. If the data at the designated address is not stored in the L1 cache, the L1 cache issues a read request to the L2 cache. The L2 cache checks whether the data at the designated address is stored in the L2 cache. When the data at the designated address is stored in the L2 cache, the L2 cache outputs the data at the designated address to the L1 cache as the request source. When the data at the designated address is not stored in the L2 cache, the L2 cache issues a read request to the main storage device 30. Upon receiving a data read request, the main storage device 30 outputs the requested data to the L2 cache. The L2 cache stores the data read from the main storage device 30 by itself, and outputs it to the L1 cache that is the request source of the data.

  Next, LUT preloading using the CPU 90 of FIG. 1 will be described. Prior to description of LUT preloading by multi-core, first, LUT preloading by a single core will be described. Here, an example will be described in which the data size of the LUT is larger than the storage capacity of one L1 cache and smaller than the storage capacity of the L2 cache.

  FIG. 2 is a sequence chart illustrating a preload process according to a related technology of the LUT using a single core (core # 1, for example, the core 901 in FIG. 1). In the following, data (entry value) at address k out of LUT data is represented as P [k]. Further, the L1 cache corresponding to the core # 1 is represented as L1 cache # 1 (L1 # 1 in the drawing). In this example, LUT data is not stored in the L1 cache and the L2 cache before the start of the flow of FIG.

  First, the core # 1 requests the L1 cache # 1 to read P [0] (step S801). The L1 cache # 1 requests the L2 cache to read P [0] (step S802). The L2 cache requests the external memory (main storage device 30) to read P [0] (step S803). The external memory outputs P [0] of the stored data to the L2 cache (step S804). The L2 cache outputs P [0] to the L1 cache # 1 (step S805). The L1 cache # 1 outputs P [0] to the core # 1 (step S806).

  Next, the core # 1 requests the L1 cache # 1 to read P [1] (step S807). The L1 cache # 1 requests the L2 cache to read P [1] (step S808). The L2 cache requests the external memory to read P [1] (step S809). The external memory outputs P [1] of the stored data to the L2 cache (step S810). The L2 cache outputs P [1] to the L1 cache # 1 (step S811). The L1 cache # 1 outputs P [1] to the core # 1 (step S812).

  The same processing is performed for data after P [2]. Thus, the LUT data is stored in the L2 cache by sequentially preloading the LUT data.

  FIG. 3 is a sequence chart illustrating a preload process according to a related technology of LUT by a plurality of cores (core # 1 and core # 2, for example, core 901 and core 902 in FIG. 1). In this example, preloading is performed in parallel in each of the plurality of cores. The L1 cache corresponding to the core # 2 is represented as L1 cache # 2 (L1 # 2 in the drawing). In this example, LUT data is not stored in the L1 cache and the L2 cache before the start of the flow of FIG.

  First, the core # 1 requests the L1 cache # 1 to read P [0] (step S901). The L1 cache # 1 requests the L2 cache to read P [0] (step S902). The L2 cache requests the external memory (main storage device 30) to read P [0] (step S903). The external memory outputs P [0] of the stored data to the L2 cache (step S906).

  Core # 2 requests the L1 cache # 2 to read P [0] (step S904). The L1 cache # 2 requests the L2 cache to read P [0] (step S905). The processing of steps S904 to S905 by the core # 2 is performed in parallel with the processing of steps S901 to S902 by the core # 1, but here, for convenience, the processing of steps S904 to S905 is performed after the processing of steps S901 to S902. It is described as

  The L2 cache outputs P [0] to the L1 cache # 1 (step S907). The L1 cache # 1 outputs P [0] to the core # 1 (step S908). Further, the L2 cache outputs P [0] to the L1 cache # 2 (step S909). The L1 cache # 2 outputs P [0] to the core # 2 (step S910). The preloading of P [0] is thus completed.

  Next, the core # 1 requests the L1 cache # 1 to read P [1] (step S911). The L1 cache # 1 requests the L2 cache to read P [1] (step S912). The L2 cache requests the external memory (main storage device 30) to read P [1] (step S913). The external memory outputs P [1] of the stored data to the L2 cache (step S916).

  Core # 2 requests the L1 cache # 2 to read P [1] (step S914). The L1 cache # 2 requests the L2 cache to read P [1] (step S915). The processing of steps S914 to S915 by the core # 2 is performed in parallel with the processing of steps S911 to S912 by the core # 1, but for the sake of convenience, the processing of steps S914 to S915 is performed after the processing of steps S911 to S912. It is described as

  The L2 cache outputs P [1] to the L1 cache # 1 (step S917). The L1 cache # 1 outputs P [1] to the core # 1 (step S918). Further, the L2 cache outputs P [1] to the L1 cache # 2 (step S919). The L1 cache # 2 outputs P [1] to the core # 2 (step S920). Thus, the preloading of P [1] is completed.

  When the process of FIG. 3 is compared with the process of FIG. 2, the time required to preload P [0] and P [1] is the same as the process of FIG. This means that the processing of FIG. 3 does not exhibit multicore performance regarding data preloading. This embodiment provides a technique for reducing the time required for preloading.

2. Configuration FIG. 4 is a diagram illustrating a configuration of the image forming apparatus 1 according to an embodiment. The image forming apparatus 1 is an example of an information processing apparatus having a function of forming an image, and is a so-called multifunction machine, for example. The image forming apparatus 1 includes a CPU 10, a memory controller 20, a main storage device (main memory) 30, an IO controller 40, an auxiliary storage device 41, an image reading unit 42, an image forming unit 43, and a communication unit 44.

  The CPU 10 is a control device that controls each unit of the image forming apparatus 1 and is an example of a processing unit including N cores (N is a natural number of 2 or more) that executes different processes. In this example, N = 4. The CPU 10 includes cores 101 to 104, cache memories 111 to 114, and cache memories 121 to 122. The cache memories 111 to 114 are primary caches (L1 caches) and are dedicated to the cores 101 to 104, respectively. The cache memories 121 to 122 are secondary caches (L2 caches). The cache memory 121 is shared by the cores 101 and 102, and the cache memory 122 is shared by the cores 103 and 104.

  The memory controller 20 controls reading and writing of data with respect to the main storage device 30. The main storage device 30 is a main storage device, and includes, for example, a DRAM (Dynamic Random Access Memory). The main storage device 30 functions as a work area when the CPU 10 executes a program and is an example of a storage unit that stores various data.

  The IO controller 40 is a device that controls peripheral devices connected to the CPU 10. In this example, an auxiliary storage device 41, an image reading unit 42, an image forming unit 43, and a communication unit 44 are connected to the IO controller 40. The auxiliary storage device 41 is a non-volatile storage device that stores data and programs, and includes, for example, an HDD (Hard Disk Drive). The image reading unit 42 is a device that optically reads a document, and includes, for example, a so-called scanner. The image forming unit 43 is an apparatus that forms an image on a medium (for example, paper), and performs image formation by, for example, an electrophotographic technique or an ink jet technique. The communication unit 44 is an interface that communicates with other devices.

  FIG. 5 is a diagram illustrating a functional configuration of the image forming apparatus 1 relating to preloading of data from the external memory. The auxiliary storage device 41 stores a program for causing an OS (Operating System) of the image forming apparatus 1 to function (hereinafter referred to as “OS program”). When the CPU 10 executes the OS program, the OS 50 is mounted on the image forming apparatus 1.

  The OS 50 has an assigning unit 51. The allocating unit 51 divides data to be preloaded (LUT in this example) into N pieces of data. The divided data is called “partial data”. Furthermore, the assigning means 51 assigns each partial data to one of the N cores. Each of the cores 101 to 104 has a request unit. For example, the request unit (an example of the first request unit) of the core 101 requests the cache memory to read one of the N pieces of partial data (an example of the first partial data). Further, the request unit (an example of the second request unit) of the core 102 requests the cache memory to read another one of the N pieces of partial data (an example of the second partial data). In FIG. 5, the L1 cache is not shown.

  The cache memory 121 has a reading unit 1211. The reading unit 1211 reads data from the main storage device 30 in response to a request from the core. The read unit 1211 stores the partial data requested by the cores 101 to 104 in the cache memory 121. Note that the requesting means of the cores 101 to 104 are part of the functions of the OS. That is, each core executing the OS program is an example of a request unit. The cache memory 121 also has a controller (not shown) that controls reading of data. This controller is an example of a reading unit.

3. Operation FIG. 6 is a flowchart illustrating image processing in the image forming apparatus 1. The flow in FIG. 6 is started when an LUT preload is instructed by an application program, for example. In the following description, software such as the OS 50 may be described as the subject of processing, which means that the CPU 10 executing the software executes processing in cooperation with other hardware resources. .

  In step S100, the OS 50 generates a plurality of threads. Here, “thread” means processing in a program. These threads are a process of assigning partial data obtained by dividing the LUT to a plurality of cores, a process of requesting each core to read out partial data, a process of dividing an input image and assigning the divided image to each core, and The processing includes causing the core to convert the index value of the assigned partial image into an output pixel value.

  FIG. 7 is a schematic diagram showing an outline of LUT division. In the example of FIG. 4, since N = 4, the LUT is divided into four partial data. In this example, the LUT is divided into four equal parts. That is, the four partial data have the same data size and do not overlap with other partial data.

  FIG. 8 is a diagram illustrating a specific example of LUT division. In this example, the LUT includes k entry values P [0] to P [K-1]. The LUT is divided into four partial data (hereinafter referred to as “partial data # 1 to # 4”) each consisting of only a portion having consecutive addresses. For example, partial data # 1 includes K / 4 entry values P [0] to P [K / 4-1], and partial data # 2 includes P [K / 4] to P [2K / 4. -1] includes K / 4 entry values, and partial data # 3 includes P [2K / 4] to P [3K / 4-1] K / 4 entry values, Data # 4 includes K / 4 entry values P [3K / 4] to P [K-1].

  FIG. 9 is a diagram illustrating another specific example of LUT division. In this example, the LUT is divided into four partial data each including a portion where the addresses are discontinuous. For example, the partial data # 1 includes P [0] to P [15], P [64] to P [79], ..., P [K-64] to P [K-49], a total of K / 4 pieces. Contains the entry value. Partial data # 2 is a total of K / 4 entry values of P [16] to P [31], P [80] to P [95], ..., P [K-48] to P [K-33]. Is included. Partial data # 3 is a total of K / 4 entry values of P [32] to P [47], P [96] to P [111], ..., P [K-32] to P [K-17]. Is included. Partial data # 4 is a total of K / 4 entry values of P [48] to P [63], P [112] to P [127], ..., P [K-16] to P [K-1]. Is included.

  In this example, each partial data includes a plurality of sets of 16 entry values with consecutive addresses. The data size for 16 entry values is equal to the cache line size. The cache line size refers to the maximum data transfer amount (data read amount) per time between the L2 cache and the external memory. For example, in a DRAM, memory cells are divided into blocks called “banks”, and in order to access memory cells belonging to different banks, it is necessary to switch the bank to be accessed. When the external memory includes a DRAM and the consecutive K / 4 entry values illustrated in FIG. 8 are stored across a plurality of banks, the external memory (DRAM) is connected in parallel from a plurality of cores. For an access that occurs automatically, the entry value must be read while switching the bank.

  Consider an example in which a DRAM constituting an external memory includes four banks. In the example of FIG. 8, first, P [0] to P [15] are requested from the core 101, and P [K / 4] to P [K / 4 + 15] are requested from the core 103 according to the request from the core 102. P [2K / 4] to P [2K / 4 + 15] are read by the request, and P [3K / 4] to P [3K / 4 + 15] are read by the request from the core 104, respectively. However, since these entry values are stored in different banks, the DRAM must read data while switching the banks in parallel. In addition, it takes time to read data by the amount of bank switching.

  In contrast, in the example of FIG. 9, first, P [0] to P [15] are requested by the request from the core 101, and P [16] to P [31] are requested from the core 103 by the request from the core 102. Thus, P [32] to P [47] are read out, and P [48] to P [63] are read out according to the request from the core 104, respectively. Since these data are stored in the same bank, the DRAM can read the data at high speed without switching the bank.

  Refer to FIG. 6 again. In steps S101, S111, S121, and S141, the cores 101 to 104 preload partial data assigned to the cores 101 to 104, respectively. That is, the core 101 preloads partial data # 1, the core 102 preloads partial data # 2, the core 103 preloads partial data # 3, and the core 104 preloads partial data # 4. Preloading in each core is performed in parallel. As a result, the LUT is copied to the L2 cache.

  Hereinafter, processing is performed in parallel in the cores 101 to 104, but only the processing of the core 101 will be described here. The processing of the cores 102 to 104 (steps S111 to S116, S121 to S126, S141 to S146) is the same as the processing of the core 101, and thus the description thereof is omitted. In step S102, the core 101 reads the data of the target pixel from the external memory. In step S103, the core 101 calculates an index value from the data of the target pixel. In step S104, the core 101 acquires an entry value corresponding to the calculated index value using the LUT stored in the L2 cache. In step S105, the core 101 calculates an output pixel value from the entry value. In step S106, the core 101 writes the output pixel value in the external memory.

  In step S107, the OS 50 waits until all threads are completed. When all the threads assigned to the cores 101 to 104 are completed, the OS 50 ends the flow of FIG.

  FIG. 10 is a sequence chart illustrating the preload process in the image forming apparatus 1. Here, in order to simplify the description, only the processing of two cores, core # 1 and core # 2 (for example, core 101 and core 102) is illustrated.

  First, the core # 1 requests the L1 cache # 1 to read P [0] (step S201). The L1 cache # 1 requests the L2 cache to read P [0] (step S202). The L2 cache requests the external memory (main storage device 30) to read P [0] (step S203).

  The following processing is performed in parallel with the processing of steps S201 to S203. The core # 2 requests the L1 cache # 2 to read P [1] (step S204). The L1 cache # 2 requests the L2 cache to read P [1] (step S205). The L2 cache requests the external memory (main storage device 30) to read P [1] (step S206).

  The external memory outputs P [0] of the stored data to the L2 cache in response to a request from the core # 1 (step S207). The L2 cache outputs P [0] to the L1 cache # 1 (step S208). The L1 cache # 1 outputs P [0] to the core # 1 (step S209).

  The following processing is performed in parallel with the processing of steps S207 to S209. The external memory outputs P [1] of the stored data to the L2 cache in response to a request from the core # 2 (step S210). The L2 cache outputs P [1] to the L1 cache # 1 (step S211). The L1 cache # 1 outputs P [1] to the core # 1 (step S212). Thus, preloading of P [0] and P [1] is completed.

  In contrast to the flow of FIG. 3, it can be seen that the time until the preloading of P [0] and P [1] is completed is shortened in the flow of FIG.

4). Modifications The present invention is not limited to the above-described embodiments, and various modifications can be made. Hereinafter, some modifications will be described. Two or more of the following modifications may be used in combination.

4-1. Modification 1
FIG. 11 is a diagram showing an outline of the LUT dividing method according to the first modification. The LUT dividing method is not limited to the example described in the embodiment. In this example, the data sizes of the four divided data are not equal, and some of them overlap each other. Further, even if the four pieces of divided data are combined, the LUT stored in the main storage device 30 is not completely reproduced, and some entry values are missing. This is effective in the following cases. For example, a software component such as an application program specifies a portion of the LUT that is used when image processing is performed on the target image. The OS 50 divides the LUT so as to cover the part thus specified.

4-2. Modification 2
Further, in the first modification, in the software component such as an application program, a part used in image processing in the LUT may be specified for each core. In this case, the OS 50 divides the LUT so as to include a portion used for each core. In the example of FIG. 11, the partial data # 1 covers entry values used for image processing of an area handled by the core 101 in the target image. Similarly, partial data # 2 is an area of the target image that is handled by the core 102, partial data # 3 is an area of the target image that is handled by the core 103, and partial data # 4 is an area of the target image that is handled by the core 104. The entry value used for image processing of the area to be covered is covered. If the size of each partial data is smaller than the capacity of the L1 cache, each core can read the required entry value directly from the L1 cache, and the processing is further accelerated.

4-3. Modification 3
Data stored in the main storage device 30 and processing using the same are not limited to those exemplified in the embodiment. The data stored in the main storage device 30 may be, for example, a code (instruction) executed in each core. In this case, the core reads the code stored at the designated address and executes the read code. The code cache memory is preloaded.

4-4. Other Modifications The configuration of the CPU 10 is not limited to that illustrated in FIG. The number of cores and the hierarchical structure of the cache memory are merely examples. The CPU 10 may have at least two cores sharing the second cache memory. The CPU 10 may have an L3 cache below the L2 cache.

  Further, the CPU 10 is not limited to one in which a plurality of cores and a cache memory are physically mounted on one chip. The present invention may be applied to an information processing apparatus in which a plurality of CPU chips share one cache memory.

  Furthermore, the “plurality of cores” in the embodiments is not limited to a plurality of physically different cores. One physical core may be used as a plurality of cores in a logical (pseudo) manner in a time division manner.

  Further, the CPU 10 is not limited to one in which a plurality of cores and a cache memory are physically mounted on one chip. The present invention may be applied to an information processing apparatus in which a plurality of CPU chips share one cache memory.

  The information processing apparatus according to the present invention is not limited to the image forming apparatus 1 illustrated in FIG. As long as a plurality of processes are executed in parallel using the CPU 10, the information processing apparatus may be any apparatus. For example, the information processing apparatus may be a personal computer, a smartphone, or a tablet terminal.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... CPU, 20 ... Memory controller, 30 ... Main storage device, 40 ... IO controller, 41 ... Auxiliary storage device, 42 ... Image reading unit, 43 ... Image forming unit, 44 ... Communication unit, 50 ... OS, 51 ... Allocation means, 90 ... CPU, 101-104 ... Core, 111-114 ... Cache memory (L1), 121 ... Cache memory (L2), 901-904 ... Core, 911-914 ... Cache memory (L1) ), 921... Cache memory (L2)

Claims (7)

A first core;
A second core that performs parallel processing with the first core;
A cache memory shared by the first core and the second core;
And an external memory storing data,
The first core is
First request means for requesting first partial data which is a part of the data;
The second core is
Second request means for requesting second partial data that is a part of the data different from the first partial data;
The cache memory is
In response to a request from the first requesting unit and a request from the second requesting unit, the reading unit reads out the first partial data and the second partial data from the external memory,
Each of the first core and the second core performs processing using at least a part of the first partial data and the second partial data stored in the cache memory, respectively. N cores including the first core and the second core;
2. The allocation unit according to claim 1, further comprising: an assigning unit that equally divides the data into N pieces of partial data each consisting of only a portion having consecutive addresses, and assigns each piece of partial data to one of the N cores. Information processing device. N cores including the first core and the second core;
2. The information processing according to claim 1, further comprising: an assigning unit that equally divides the data into N pieces of partial data each including a portion in which addresses are discontinuous, and assigns each piece of partial data to one of the N cores. apparatus. The external memory includes a DRAM;
Each of the N partial data includes a portion where addresses are continuous,
4. The information processing apparatus according to claim 2, wherein a data size of a portion where the addresses are continuous is equal to or less than a data read amount per time when the reading unit reads data from the DRAM. The processing in the first core and the second core is processing for converting an index corresponding to a pixel into a pixel value,
The information processing apparatus according to any one of claims 1 to 4, wherein the data is a table for converting the index into the pixel value. A first core;
A second core that performs parallel processing with the first core;
A first cache memory dedicated to the first core;
A second cache memory dedicated to the second core;
A cache memory shared by the first core and the second core;
And an external memory storing data,
The first core is
First request means for requesting first partial data which is a part of the data;
The second core is
Second request means for requesting second partial data that is a part of the data different from the first partial data;
The first cache memory is
In response to a request from the first request means, the first acquisition means for acquiring the first partial data from the external memory;
The second cache memory is
In response to a request from the second request means, the second acquisition means for acquiring the second partial data from the external memory;
The first core performs processing using the first partial data stored in the first cache memory,
The second core performs processing using the second partial data stored in the second cache memory. An information processing apparatus according to any one of claims 1 to 6,
An image forming apparatus comprising: an image forming unit that forms an image according to a result processed by the first core and the second core.

Images