DE102021108857A1 - MULTIPROCESSOR SYSTEM - Google Patents

Abstract

In a multiprocessor system 16, at least one of sub-processing of parallel processing (n + 1) is provisionally executed by one or more processors in a standby state of processor elements 40a to 40n before the parallel processing (n + 1), so that at least a part of instructions and data used in the parallel processing (n + 1) is read out from a ROM 22 or RAM 24 and stored in an L2 cache 44.

Description

The present disclosure relates to a multiprocessor system having multiple processors.

For example, Patent Document 1 discloses an information processing apparatus having a CPU including a plurality of processor cores. Patent Document 1 discloses a method of shortening the time for preloading a look-up table stored in a main storage device into a cache, the look-up table being used in processing for forming an image on a medium such as paper. Specifically, the look-up table is divided into N (N is an integer) pieces of data (referred to as partial data), and the divided N partial data are each assigned to N processor cores. Each processor core provides a shared L2 cache memory with a data read request in order to read out the assigned partial data. The L2 cache memory has reading means, and the reading means reads out the corresponding partial data from a main storage device in response to the data read request from each processor core. As a result, all sub-data is preloaded from the main storage device into the L2 cache (i.e., the look-up table is copied to the L2 cache). Since preloading is performed in parallel by each processor core, the time required to copy the look-up table is reduced.

Patent Document 1: JP 2017 - 58 738 A

Since it takes a relatively long time to access the main storage device, it is common practice to provide a quick-access cache between a plurality of processor cores and the main storage device as in the information processing device of Patent Document 1.

However, in the system that periodically executes different processings such as those represented by an in-vehicle device control system, even if instructions and data used in specific processing are stored in the cache by the execution of the specific processing, the instructions can and data used in the specific processing is overwritten by performing some other processing before the same specific processing is performed again. In such a case, when the same specific processing is carried out again, the instructions and data used in the same specific processing may not stay in the cache. Thus, even if the cache is installed, the expected improvement in performance cannot be obtained.

The present disclosure has been made in view of the problems described above. It is an object of the present disclosure to provide a multiprocessor system that can increase the likelihood that instructions and data required to perform specific processing exist in a cache that is shared by multiple processors when performing the specific processing is performed.

• mehrere Prozessoren;
• einen Zeitplaner, der jeden der mehreren Prozessoren anweist, Ausführung einer zugewiesenen Aufgabe zu starten;
• einen Speicher zum Speichern von Anweisungen und Daten, die durch die mehreren Prozessoren verwendet werden, um die jeweiligen Aufgaben auszuführen; und
• einen Cache, der zwischen den mehreren Prozessoren und dem Speicher vorgesehen ist und durch die mehreren Prozessoren gemeinsam genutzt wird,
• wobei
• wenn Zuweisung paralleler Verarbeitung zu den mehreren Prozessoren geplant ist, wobei die parallele Verarbeitung eine Aufgabe ist, die synchron durch die mehreren Prozessoren auszuführen ist, der Zeitplaner konfiguriert ist, eine Cacheaktualisierungsverarbeitung, die mindestens einen Teil von Anweisungen und Daten, die in der parallelen Verarbeitung verwendet werden, von dem Speicher ausliest und die ausgelesenen Anweisungen und Daten in dem Cache speichert, einem Prozessor in einem Bereitschaftszustand zuzuweisen und einen Ausführungsstart der Cacheaktualisierungsverarbeitung vor Anweisen eines Ausführungsstarts der parallelen Verarbeitung anzuweisen.

To achieve the above object, an example of a multiprocessor system according to the present disclosure includes:

• multiple processors;
• a scheduler that instructs each of the plurality of processors to start executing an assigned task;
• a memory for storing instructions and data used by the plurality of processors to perform the respective tasks; and
• a cache that is provided between the plurality of processors and the memory and is shared by the plurality of processors,
• whereby
• when parallel processing is scheduled to be allocated to the multiple processors, the parallel processing being a task to be performed synchronously by the multiple processors, the scheduler is configured to perform cache update processing that includes at least a part of instructions and data included in the parallel processing is used, reads out from the memory and stores the read instructions and data in the cache, assigns to a processor in a standby state and instructs execution start of cache update processing before instructing execution start of parallel processing.

As described above, according to the multiprocessor system of the present disclosure, when the assignment of the parallel processing to the plurality of processors is scheduled, the cache update processing for reading out at least the part of instructions and data used in the parallel processing and storing the read out Instructions and data in the cache executed using the processor in the standby state. Accordingly, it is possible that if the several Processors start executing parallel processing, at least the portion of instructions and data used in the parallel processing are in the cache as the stored instruction (s) and / or data in the cache. Accordingly, the multiprocessor system of the present disclosure can increase the likelihood that at least the part of the instructions and data required for parallel processing exists in the cache when the parallel processing is performed.

For a better understanding of the present disclosure, the reference symbols in brackets are added in the claims merely as examples of correspondence relationships with concrete structures in the embodiments which are described below, so that no restriction of the scope of the claims can be derived therefrom.

• 1 ein Konfigurationsdiagramm, das ein Beispiel einer Konfiguration einer elektronischen Steuereinheit für ein Fahrzeug zeigt, auf das ein Multiprozessorsystem angewendet wird;
• 2 ein Konfigurationsdiagramm, das ein Beispiel einer Konfiguration des Multiprozessorsystems zeigt;
• 3 ein Ablaufdiagramm, das ein Beispiel einer Verarbeitung, die durch einen Zeitplaner ausgeführt wird, einschließlich einer Cacheaktualisierungsverarbeitung, gemäß einer ersten Ausführungsform zeigt;
• 4 ein Ablaufdiagramm, das ein Beispiel einer Verarbeitung zeigt, die durch den Zeitplaner ausgeführt wird, um eine Einstellung einer Speicherschutzeinheit aufzuheben;
• 5 ein Operationsdiagramm, das ein Beispiel eines Operationszustands jedes Prozessorelements zeigt, wenn der Zeitplaner ein Prozessorelement in einem Bereitschaftszustand vor Ausführen geplanter paralleler Verarbeitung (n + 1) veranlasst, vorläufig einen Teil der parallelen Verarbeitung (n + 1) durch die Verarbeitung, die in dem Ablaufdiagramm von 3 gezeigt ist, auszuführen;
• 6 ein Ablaufdiagramm, das ein Beispiel einer Verarbeitung, die durch den Zeitplaner ausgeführt wird, einschließlich einer Cacheaktualisierungsverarbeitung, gemäß einer zweiten Ausführungsform zeigt;
• 7 ein Operationsdiagramm, das ein Beispiel eines Operationszustands jedes Prozessorelements zeigt, wenn der Zeitplaner ein Prozessorelement in einem Bereitschaftszustand vor Ausführen geplanter paralleler Verarbeitung (n + 1) zum Ausführen von Verarbeitungen zum Lesen von Anweisungen und Daten, die in der parallelen Verarbeitung (n + 1) verwendet werden, von einem Speicher und Schreiben der ausgelesenen Anweisungen und Daten in einen Cache durch die Verarbeitung veranlasst, die in dem Ablaufdiagramm von 6 gezeigt ist;
• 8 ein Ablaufdiagramm, das ein Beispiel einer Verarbeitung, die durch den Zeitplaner ausgeführt wird, einschließlich einer Cacheaktualisierungsverarbeitung, gemäß einer dritten Ausführungsform zeigt;
• 9 ein Operationsdiagramm, das ein Beispiel eines Operationszustands jedes Prozessorelements zeigt, wenn der Zeitplaner mehrere Prozessorelemente in einem Bereitschaftszustand vor Ausführen geplanter paralleler Verarbeitung (n + 1) veranlasst, vorläufig einen Teil der parallelen Verarbeitung (n + 1) durch die Verarbeitung auszuführen, die in dem Ablaufdiagramm von 8 gezeigt ist;
• 10 ein Operationsdiagramm, das ein Beispiel eines Operationszustands jedes Prozessorelements, wenn der Zeitplaner mehrere Prozessorelemente in einem Bereitschaftszustand vor Ausführen geplanter paralleler Verarbeitung (n + 1) veranlasst, vorläufig einen Teil der parallelen Verarbeitung (n + 1) auszuführen, gemäß einer vierten Ausführungsform zeigt;
• 11 ein Operationsdiagramm, das ein Beispiel eines Operationszustands jedes Prozessorelements, wenn der Zeitplaner ein Prozessorelement in einem Bereitschaftszustand vor Ausführen geplanter paralleler Verarbeitung (n + 1) veranlasst, vorläufig einen Teil der parallelen Verarbeitung (n + 1) auszuführen, gemäß einer fünften Ausführungsform zeigt;
• 12 ein Konfigurationsdiagramm, das ein Beispiel einer Konfiguration eines Multiprozessorsystems gemäß einer sechsten Ausführungsform zeigt.

The foregoing and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description when viewed in conjunction with the drawings. Show it:

• 1 Fig. 10 is a configuration diagram showing an example of a configuration of an electronic control unit for a vehicle to which a multiprocessor system is applied;
• 2 Fig. 4 is a configuration diagram showing an example of a configuration of the multiprocessor system;
• 3 Fig. 13 is a flowchart showing an example of processing executed by a scheduler including cache update processing according to a first embodiment;
• 4th Fig. 13 is a flowchart showing an example of processing executed by the scheduler to cancel setting of a memory protection unit;
• 5 Fig. 13 is an operation diagram showing an example of an operating state of each processor element when the scheduler makes a processor element in a standby state before executing scheduled parallel processing (n + 1), provisionally part of the parallel processing (n + 1) by the processing specified in the Flow chart of 3 is shown to perform;
• 6th Fig. 13 is a flowchart showing an example of processing executed by the scheduler including cache update processing according to a second embodiment;
• 7th Fig. 13 is an operation diagram showing an example of an operating state of each processor element when the scheduler places a processor element in a standby state before executing scheduled parallel processing (n + 1) for executing processings for reading instructions and data included in the parallel processing (n + 1 ) are used from a memory and writing of the read instructions and data into a cache caused by the processing in the flowchart of 6th is shown;
• 8th Fig. 13 is a flowchart showing an example of processing executed by the scheduler including cache update processing according to a third embodiment;
• 9 Fig. 8 is an operation diagram showing an example of an operating state of each processor element when the scheduler causes a plurality of processor elements in a standby state before executing scheduled parallel processing (n + 1) to provisionally execute part of the parallel processing (n + 1) by the processing shown in FIG the flowchart of 8th is shown;
• 10 Fig. 8 is an operation diagram showing an example of an operating state of each processor element when the scheduler causes a plurality of processor elements in a standby state before executing scheduled parallel processing (n + 1) to preliminarily execute part of the parallel processing (n + 1) according to a fourth embodiment;
• 11 Fig. 8 is an operation diagram showing an example of an operating state of each processor element when the scheduler causes a processor element in a standby state before executing scheduled parallel processing (n + 1) to provisionally execute part of the parallel processing (n + 1) according to a fifth embodiment;
• 12th Fig. 13 is a configuration diagram showing an example of a configuration of a multiprocessor system according to a sixth embodiment.

(First embodiment)

A first embodiment of a multiprocessor system according to the present disclosure will be described in detail in accordance with the drawings. 1 Fig. 13 is a configuration diagram showing an example of a configuration of an electronic control unit (abbreviated as ECU) for a vehicle to which the multiprocessor system of the present embodiment is applied. The electronic control unit for a Vehicle carries out various processings at high speed and periodically. The multiprocessor system according to the present disclosure is particularly effective when applied to a control device that executes various processings at high speed and periodically as described above. However, the multiprocessor system according to the present disclosure can be applied to a control device in which the same processing is not periodically executed. Further, an application example of the multiprocessor system according to the present disclosure is not limited to the electronic control unit for the vehicle, and can be applied to, for example, an electronic control unit for various equipment such as communication equipment, machine equipment, and construction equipment.

An electronic control unit 10 for a vehicle that is in 1 shown can be used, for example, as an internal combustion engine control device for controlling an internal combustion engine mounted on the vehicle. The following describes an example in which the electronic control unit for the vehicle is used as the internal combustion engine control device.

The engine control device 10 operates by receiving a power supply from a battery 1 that is mounted on the vehicle. As in 1 shown includes the engine control device 10 mainly a power supply circuit 12th , an input circuit 14th , a microcomputer 16 and an output circuit 32 .

The power supply circuit 12th converts a voltage of the energy supply from the battery 1 is fed into a voltage, each for the input circuit 14th , the microcomputer 16 and the output circuit 32 is suitable, and provides the converted voltage. The input circuit 14th inputs detection signals from various sensors and input signals from various switches required for controlling the internal combustion engine, and carries out signal processing such as signal shaping or signal amplification of these signals in order from the microcomputer 16 to be processed. For example, include the detection signals fed into the input circuit 14th are input, detection signals from various sensors that detect engine speed, fuel pressure, accelerator opening, intake air amount, engine cooling water temperature and so on. The input signals going into the input circuit 14th include input signals from switches such as a starter switch, an idle switch and standby switch, respectively, and so on.

The microcomputer 16 includes an input / output circuit 18th (I / O), a CPU 20th , a ROM 22nd , a RAM 24 , an AD converter 26th (A / D), a timer 28 and a system bus 30th to connect these configurations. The CPU 20th runs the engine control program stored in the ROM 22nd is stored, while a temporary memory function of the RAM 24 is used. By executing this engine control program, the CPU acquires 20th Sensor detection signals and switch input signals received from the input circuit 14th are entered and into the microcomputer 16 via the input / output circuit 18th be included. The signal going into the input circuit 14th input as an analog signal is converted into a digital signal by the AD converter 26th when converted into the microcomputer 16 is recorded. The CPU 20th calculates ignition timing, fuel injection timing, fuel injection amount, and so on, which are optimal for each cylinder of the internal combustion engine, based on the acquired sensor detection signals and switch input signals.

Then the microcomputer gives 16 an ignition signal to an igniter of each cylinder via the output circuit 32 according to the calculated ignition timing to ignite the air-fuel mixture compressed in each cylinder. The microcomputer also calculates 16 a fuel injection period based on the calculated fuel injection amount and the fuel pressure of fuel supplied to an injector immediately before the fuel injection timing. When an injection timing occurs based on the calculated fuel injection timing, the microcomputer outputs 16 a drive signal to the corresponding injector via the output circuit 32 the end. The drive signal opens the injector and the injector begins to inject fuel. When a lapse of the calculated fuel injection period from the start of fuel injection, for example, by a timer 28 is counted, the microcomputer stops 16 the output of the drive signal to close the injector. The microcomputer also gives 16 a signal indicating a control state of the internal combustion engine, a signal indicating an abnormal state when any abnormality occurs, and the like to another ECU (s) through the output circuit 32 the end.

The engine control program described above tends to be complicated and sophisticated in order to improve fuel efficiency of the internal combustion engine and comply with emission regulations. In this embodiment, the CPU 20th several Processor elements as described below so that the CPU 20th can adequately process such an engine control program. The engine control program is configured to include parallel processing that is executed synchronously and in parallel on the plurality of processor elements. In other words, complicated processing and heavy-load processing are divided and executed as parallel processing by the plural processor elements. As described above, the microcomputer is 16 configured as a multiprocessor system in this embodiment.

The following is the configuration of the CPU 20th in the microcomputer (multiprocessor system) 16 according to 2 described. As in 2 shown has the CPU 20th multiple processor elements 40a until 40n . Processor element numbers (PE numbers) # 1 to #n for identifying the respective processor elements 40a until 40n are the multiple processor elements 40a until 40n assigned accordingly. There are also L1 caches 42a until 42n individually for each of the multiple processor elements 40a until 40n However, in this embodiment, the L1 caches 42a until 42n can be omitted. Furthermore, the CPU 20th with an L2 cache 44 equipped by the multiple processor elements 40a until 40n is shared. the L1 -Caches 42a until 42n and the L2 cache 44 are located between: the processor elements 40a until 40n ; and both a ROM 22nd as well as a RAM 24 . Both the ROM 22nd as well as the RAM 24 are a memory. When a processing (task) performed by each of the processor elements 40a until 40n is assigned, running, storing and holding the L1 caches 42a until 42n and the L2 cache 44 the instruction or data that are used in the processing, this instruction or data from the ROM 22nd (or RAM 24 ), together with an address indicating the storage location of the ROM 22nd (or RAM 24 ) or in the ROM 22nd (or RAM 24 ) indicates.

When each of the processor elements 40a until 40n a request to execute the assigned processing from a scheduler 48 which is described later, reads each of the processor elements 40a until 40n the instruction or data necessary to carry out the assigned processing from the ROM 22nd (or RAM 24 ) by a read request specifying the address. The read requests from the processor elements 40a until 40n are first put into the corresponding L1 caches 42a until 42n entered. Each of the L1 caches 42a until 42n investigates whether or not it is holding the instruction or data corresponding to the input read request. If there is the appropriate instruction or data passed through the L1 caches 42a until 42n are held by the L1 caches 42a until 42n the corresponding instruction or data to the processor elements 40a until 40n ready. If the corresponding instruction or data is not through the L1 caches 42a until 42n are held transfer the L1 caches 42a until 42n the read request from the processor elements 40a until 40n to the L2 cache 44 . Like the L1 caches 42a until 42n examines the L2 cache 44 also at high speed whether or not it is holding the instruction or data corresponding to the input read request. When the corresponding instruction or corresponding data through the L2 cache 44 are held by the L2 cache 44 the corresponding instruction or data to the processor elements 40a until 40n via the L1 caches 42a until 42n ready. If the corresponding instruction or data is not through the L2 cache 44 are held, the L2 cache transfers 44 the read request from the processor elements 40a until 40n to the memory (ROM 22nd and / or RAM 24 ).

For each processor element, a memory protection unit MPU 46 can permit or prohibit a read request and a write request from each of the processor elements 40a until 40n set for memory. In the present embodiment, the memory protection unit is 46 through a scheduler 48 set to write requests from the processor elements 40a until 40n that are provisionally performing parallel processing sub-processing for the memory (ROM 22nd , RAM 24 ) or a register of a peripheral device such as an AD converter 26th and a timer 28 to block.

The scheduler 48 issues a processing execution request to each of the plurality of processor elements 40a until 40n out, making the multiple processor elements 40a until 40n caused to start the execution of the respectively assigned processing. Further, as will be described in detail later, the scheduler causes 48 at least one of the processor elements 40a until 40n in a standby state to provisionally execute sub-processing that is part of the parallel processing scheduled to be executed by issuing a processing execution request to the at least one of the processor elements 40a until 40n in the standby state to preliminarily execute the sub-processing. Further, when each of the processor elements 40a until 40n completes the assigned processing, the scheduler receives 48 a processing completion notification from each of the processor elements 40a until 40n .

The processings (task) that the several processor elements 40a until 40n assigned are determined based on information those in the ROM 22nd or the RAM 24 are stored. For example, the RAM 24 have a processing waiting area for storing a task ID indicating processing for which an execution request has been made. For example, if certain processing is in the CPU 20th When this processing includes an instruction requesting execution of at least one other processing, the task ID of the other instruction is stored in the aforementioned processing waiting area. Further, when a predetermined signal is detected by a sensor, when a predetermined time is counted by a timer, when a predetermined signal is input from another ECU, or the like, the processing execution request is generated and the task ID of the corresponding processing can be specified in the processing waiting area described above can be stored. When the task IDs of a plurality of processings are stored in the aforementioned processing waiting area at the same time, an execution order of the processings can be determined according to a predetermined rule (for example, “first come, first served” basis, priority rank, processing time rank, or any combination thereof ). Alternatively, the order in which the CPU 20th that executes processings can be predetermined in the engine control program, and task IDs indicating the respective processings can be stored in the aforementioned processing waiting area according to the predetermined order of processing.

Further, the processor element information (hereinafter PE information) is stored in the ROM 22nd (or RAM 24 ) pre-stored. The PE information includes PE numbers # 1 to #n, which indicate which processing is carried out by which processor element 40a until 40n is assigned for each processing, and an address of an area storing instructions and data for performing each processing. The scheduler 48 refers to the PE information and determines the processor elements 40a until 40n assigned the processing to be performed based on the PE numbers # 1 to #n corresponding to the respective processings. Then the scheduler gives 48 a processing execution request to the corresponding processor elements 40a until 40n while designating the address of the processing to be performed. As a result, the assigned processing is carried out in each of the processor elements 40a until 40n started. Furthermore, when several sub-processing operations each have several processor elements 40a until 40n and the subprocessings are for parallel processing that are synchronized by the plurality of processor elements 40a until 40n the scheduler indicates 48 Processing execution requests to the multiple processor elements at substantially the same time 40a until 40n that execute the corresponding sub-processing involved in the parallel processing.

In 2 is the scheduler 48 outside the CPU 20th intended. However, if, for example, a data flow processor is used as the CPU 20th can be used, the scheduler 48 into the CPU 20th be built in.

Next, according to a flow chart of FIG 3 an example of processing that the scheduler 48 to increase the likelihood that instructions and data required to perform parallel processing will be in the L2 cache 44 exist by the multiple processor elements 40a until 40n is shared, that is, to increase a cache hit rate. The processing shown in the flowchart of 3 is shown when a power-on reset of the microcomputer is enabled 16 started as a trigger. However, the microcomputer 16 be configured to start processing in response to receipt of a trigger signal from a timer, an input / output interface, another ECU, or the like.

In the first step S100 attains the scheduler 48 Information regarding a process (s) scheduled to be executed next. In particular, the scheduler takes 48 Refers to the processing waiting area and determines the processing (s) scheduled to be executed next. Furthermore, the scheduler takes 48 Regarding the PE information that is in the ROM 22nd (or RAM 24 ) are stored and a PE number # 1 to #n is obtained, which the processor elements 40a until 40n indicates to which the processing (s) is assigned and an address indicating an area in which the instruction or data for the processing (s) is stored (when the processing (s) is parallel processing, the PE number becomes # 1 to #n and the address of each sub-processing included in the processing (n)). At step S110 determines the scheduler 48 whether or not the processing (s) scheduled to be executed next is parallel processing. When it is determined that the next processing is parallel processing, the scheduler runs 48 with step S120 away. If it is determined that the next processing is not parallel processing, the scheduler returns 48 to step S100 return.

At step S120 attains the scheduler 48 Information regarding processing (n + 1), for which is scheduled to be executed next to processing (s) or next to processing (s), in the same way as in step S100 . Then at step S130 determines whether or not the processing is (n + 1) parallel processing. If it is determined that the processing is (n + 1) parallel processing, the scheduler runs 48 with step S140 away. If it is determined that the processing (n + 1) is not parallel processing, the scheduler returns 48 to step S100 return. Will at step S110 or step S130 a negative determination is made, that is, when at least one of the processing (n) and the processing (n + 1) is not the parallel processing, the scheduler gives 48 at an appropriate time, a request to start execution of the processing (s) to the processor elements 40a until 40n assigned the processing (s) in another routine not shown.

At step S140 the scheduler chooses 48 the processor element (s) 40a until 40n that is / should provisionally perform sub-processing that is at least a part of the parallel processing (n + 1) from the processor elements 40a until 40n to which subprocessings of the parallel processing (s) are not assigned. For example, the scheduler 48 the processor element 40a until 40n with the lowest PE number among the processor elements 40a until 40n that are not assigned the parallel processing sub-processing (s) as the processor element 40a until 40n select to provisionally execute the sub-processing that is at least the part of the parallel processing (n + 1). Alternatively, another method can be used to create a processor element (s) 40a until 40n that provisionally performs the sub-processing that is at least the part of the parallel processing (n + 1). Furthermore, the number of processor elements 40a until 40n that preliminarily perform the sub-processing of the parallel processing (n + 1) may be one or more. The scheduler also determines 48 likewise the sub-processing provisionally carried out by the selected processor elements 40a until 40n is performed.

For example shows 5 an example in which when the CPU 20th three processor elements 40a until 40c has and the three processor elements 40a until 40c execute parallel processing A as the parallel processing (n) and parallel processing B as the next parallel processing (n + 1), sub-processings of each parallel processing A and B by the processor elements 40a until 40c are executed. In particular, the parallel processing A includes the sub-processing A1 and A2 . The sub-processing A1 is the processor element 40a assigned. The sub-processing A2 is the processor element 40b assigned. Furthermore, the parallel processing B includes sub-processing B1 , B2 and B3 . The sub-processing B1 is the processor element 40a assigned. The sub-processing B2 is the processor element 40b assigned. The sub-processing B3 is the processor element 40c assigned. In the example shown in 5 shown, when the parallel processing A is executed, is the processor element 40c in a standby state. Accordingly, the processor element 40c is selected as the processor element for provisionally executing the sub-processing that is at least a part of the parallel processing. Furthermore, in the in 5 example shown the processor element 40c provisionally the sub-processing B1 and B2 as the sub-processing, which is at least the part of the parallel processing B. is.

The scheduler 48 may make a determination as to which sub-processing (s) are provisionally performed by the processor element 40c is to be performed in the standby state. For example, the scheduler 48 a sub-processing (e.g. sub-processing B1 ) that includes processing (also called specific processing) that takes the longest time to get instructions and data from the ROM 22nd (or RAM 24 ) from the sub-processing B1 , B2 and B3 of the parallel processing B as the preliminary processing. As a result, the time required to complete the parallel processing B can be effectively reduced. In this case, the scheduler can 48 simply determine the sub-processing provisionally executed, for example, by configuring so that the PE information described above includes information on the time required to read out the instruction and data of each sub-processing or information indicating the sub-processing, which takes the longest time. Alternatively, the PE information of each parallel processing may include information that directly indicates the sub-processing to be provisionally performed.

Alternatively, the scheduler can 48 a sub-processing of the parallel processing B including the sub-processing B3 (also referred to as specific processing) that is scheduled to be performed by the processor element 40c is executed in the standby state (also referred to as certain processing) than determine the sub-processing being preliminarily executed. As a result, the instruction and data of the sub-processing B3 in the L1 cache 42c stored on the at higher speed than on the L2 cache 44 can be accessed so that the processor element 40c the sub-processing B3 can complete earlier. The scheduler can also 48 all the subprocesses B1 until B3 that are in parallel processing B. are included as a target for preliminary execution.

At step S150 of the flowchart of 3 provides the scheduler 48 the memory protection unit 46 so that the memory protection unit 46 allows outputs of the processor elements 40a until 40n that execute the sub-processing of the parallel processing (s) pass, and write request outputs of the processor elements 40a until 40n that are provisionally performing the sub-processing (s) of the parallel processing (n + 1) are blocked. In the example shown in 5 is shown represents the scheduler 48 the memory protection unit 46 so that the memory protection unit 46 Passing the outputs of the processor elements 40a and 40b allowed that the sub-processing A1 and A2 parallel processing A. execute, and the write request output of the processor element 40c that provisionally the sub-processing B1 and B2 executing parallel processing B is blocked. In the present embodiment, preliminary execution of the sub-processing (s) of the parallel processing (n + 1) is carried out at an unintended timing in terms of control specifications. Thus, in order to prevent the preliminary execution of the sub-processing (s) from affecting engine control, the memory protection unit is 46 set to the write request outputs from the processor elements 40a until 40n temporarily performing the sub-processing (s) to the memory (ROM 22nd , RAM 24 ), a register of a peripheral device such as the AD converter 26th and the timer 28 block and so on.

It should be noted that blocking the write request outputs can also be implemented using software, besides the method of using hardware such as the memory protection unit 46 . For example, the software may be configured so that the software determines whether or not the sub-processing executed by the processor element is for preliminary execution, and if it is determined that it is for preliminary execution, a write request is not issued .

At step S160 sends the scheduler 48 Processing execution requests to all of the processor elements at substantially the same time 40a until 40n that perform the sub-processing of the parallel processing (s) and all of the processor element (s) 40a until 40n that preliminarily perform the sub-processing (s) of the parallel processing (n + 1). In the example shown in 5 is shown, the scheduler sends 48 the processing execution requests to the processor elements at substantially the same time 40a and 40b who have made the sub-processing A1 respectively. A2 execute the parallel processing A, and the processor element 40c that is provisionally the sub-processing B1 and B2 parallel processing B. executes. Accordingly, the processor element starts 40c the preliminary execution of the sub-processing B1 and B2 the parallel processing B scheduled to be executed after the parallel processing A. As a result, before the parallel processing B. is started, the instructions and data that are in the sub-processing B1 and B2 of the parallel processing B can be used by the ROM 22nd (or RAM 24 ) and in the L2 cache 44 get saved.

At step S170 determines the scheduler 48 whether or not a processing completion notice from all of the processor elements 40a until 40n that perform the sub-processing of the parallel processing (s). In this determination processing, when it is determined that the processing completion notice of all of the processor elements 40a until 40n that execute the sub-processing of the parallel processing (s), the scheduler runs 48 with step S180 away. On the other hand, when it is determined that the processing completion notice is not from all of the processor elements 40a until 40n executing the sub-processing of the parallel processing (s) becomes step S170 repeatedly until receiving the processing completion notification is completed. At step S180 In order to update a designation of the processing which is a goal of determination as to whether or not it is parallel processing, the variable n specifying the destination processing is incremented by one. After that, the scheduler returns 48 to step S 100 back and leads repeatedly S 100 until S180 described above.

After the memory protection unit 46 at step S150 of the flowchart of 3 is set, to cancel this setting, the processing shown in a flowchart of 4th is shown by the scheduler 48 executed.

At step S190 determines the scheduler 48 whether or not the scheduler 48 a final notice of preliminary execution by each processor element 40a until 40n has received the parallel processing sub-processing (n + 1) and / or whether the scheduler 48 a processing execution request for parallel processing (n + 1) to each processor element 40a until 40n sent. When the preliminary execution is completed or the processing execution request for parallel processing (n + 1) is sent, the memory protection unit 46 no longer a write request issue from each processor element 40a until 40n block to which the parallel processing sub-processing (n + 1) is assigned. Accordingly, the scheduler drives 48 with step S195 away and cancels the output blocking setting of the memory protection unit 46 on. However, when the parallel processing (n + 1) is executed when at least one of the processor elements 40a until 40n temporarily executes the sub-processing of the next parallel processing (n + 2), the memory protection unit keeps 46 the output blockage setting for blocking the write request output from the processor element provisionally executing the sub-processing of the next parallel processing (n + 2).

As in 5 is shown once the sub-processing A1 and A2 the parallel processing A is completed and the scheduler 48 is ready, the processing execution request for the next parallel processing B. the scheduler sends 48 the processing execution request to each processor element 40a until 40c . At this time, the scheduler must 48 does not take into account whether or not the processor element 40c that provisionally the sub-processing B1 and B2 parallel processing B. executes the preliminary execution of the sub-processing B1 and B2 has completed. Even if the subprocesses B1 and B2 are interrupted in the middle, the engine control is not adversely affected in any way and the instructions and data relating to the sub-processing B1 and B2 that have been provisionally executed up to this point will be in the L2 cache 44 saved. Accordingly, the effect of improving the cache hit rate in the parallel processing B carried out after that can be sufficiently expected.

According to the multiprocessor system 16 of the first embodiment described above, when the parallel processing (n + 1) to be carried out synchronously is scheduled to have a plurality of processor elements 40a until 40n is assigned, the sub-processing (s) that are at least a part of the parallel processing (n + 1) will be provisionally executed in order to convert at least part of the instructions and data included in the parallel processing (n + 1) used by the ROM 22nd or the RAM 24 read out and the read instructions and data in the L2 cache 44 by using the processor elements 40a until 40n that are in the standby state before executing the parallel processing (n + 1). Accordingly, it is possible that when the plurality of processor elements 40a until 40n start executing parallel processing (n + 1) at least part of the instructions and data used in parallel processing (n + 1) in the L2 cache 44 as the stored instruction (s) and / or data in the L2 cache 44 is. As a result, when the multiprocessor system 16 If the present embodiment executes the parallel processing (n + 1), the probability that at least a part of the instructions and data required for the parallel processing (n + 1) are in the L2 cache 44 exists, that is, the cache hit rate should be increased.

In the first embodiment described above, when the parallel processing (n) by the plurality of processor elements 40a until 40n before the parallel processing (n + 1) is executed, the sub-processing (s) of the parallel processing (n + 1) are provisionally performed by the processor element (s) 40a until 40n executed in the standby state during the execution period of the parallel processing (n). The reason for this is that if the parallel processing (n) is performed before the parallel processing (n + 1) is performed, it may be relatively easy to keep the processor element (s) in the standby state during the execution of the parallel processing ( n) to cause the sub-processing (s) of the parallel processing (n + 1) to be carried out. Reasons why it may be relatively easy to cause the processor element (s) in the standby state during the execution of the parallel processing (n) to execute the sub-processing (s) of the parallel processing (n + 1) is that it is easy to the processor element (s) 40a until 40n To determine that is / are in the standby state during the execution of the parallel processing (s), the start of the preliminary execution of the sub-processing (s) of the parallel processing (n + 1) is compared with the start of the parallel processing (n) can, and so on.

However, even if the processing performed before the parallel processing (n + 1) is not the parallel processing (n), it is possible to use the processor element (s) 40a until 40n in the standby state to provisionally execute the sub-processing (s) of the parallel processing (n + 1) as long as processings do not include all of the processor elements 40a until 40n in the processing prior to the parallel processing (n + 1) are assigned, and thus at least one of the processor elements 40a until 40n left in the standby state.

(Second embodiment)

Next, a second embodiment of the multiprocessor system according to the present disclosure will be described in accordance with the drawings. As the basic configuration of the multiprocessor system 16 of the present embodiment is the same as that of the multiprocessor system 16 according to the first embodiment, the description thereof is omitted.

In the multiprocessor system 16 According to the first embodiment described above, the sub-processing (s) that are at least a part of the parallel processing (n + 1) are actually provisionally performed by the processor elements 40a until 40n , which are in the standby state before the parallel processing (n + 1), to transfer at least a part of instructions and data used in the parallel processing (n + 1) from the ROM 22nd or the RAM 24 read out and the stored instructions and data in the L2 cache 44 save.

On the other hand, in the multiprocessor system 16 In the present embodiment, at least the part of the instructions and data used in the parallel processing (n + 1) from the ROM 22nd or the RAM 24 read out and the read out instructions and data are in the L2 cache 44 stored by at least one of the processor elements 40a in the standby state prior to the parallel processing (n + 1), causing the processings to read out at least the part of the instructions and data used in the parallel processing (n + 1) from the ROM 22nd or RAM 24 and writing the read instructions and data to the L2 cache 44 to execute.

In the present embodiment, a program is prepared for each parallel processing and is stored in the ROM 22nd or RAM 24 and the program is used to retrieve at least part of the instructions and data used in any parallel processing from the ROM 22nd or RAM 24 read out and the read instructions and data in the L2 cache 44 to write. At that time, the instructions and data can be read from memory and placed in the L2 cache 44 are to be written in units of sub-processing B1 , B2 and B3 of the parallel processing B, in other words, can be determined for each sub-processing B1 , B2 , B3 can be determined or statements and data corresponding to part or all of the sub-processing B1 , B2 and B3 be. In order to adopt this embodiment, it is necessary that the L2 cache 44 has a hardware function to allow direct writing from the processor elements 40a until 40n to accept.

The flowchart of 6th shows an example of processing performed by a scheduler 48 of a multiprocessor system 16 of the present embodiment is carried out. As the processing of the steps S200 until S230 of the flowchart of 6th the same as processing the steps S100 until S130 of the flowchart of 3 the description thereof is omitted.

At step S240 the scheduler chooses 48 a processor element (s) 40a until 40n , the processing (s) for reading out at least a part of instructions and data used in the parallel processing (n + 1) from a memory and for writing the read-out instructions and data into the L2 cache 44 should execute / should execute, from the processor elements 40a until 40n to which subprocessings of the parallel processing (s) are not assigned. The method of selecting the processor elements 40a until 40n may be the same as that of the first embodiment. For example, in the example presented in 7th when parallel processing A is performed, there is shown a processor element 40 in the standby state. Accordingly, the processing is for reading the instructions and data from the memory and for writing the read instructions and data into the L2 cache 44 by the processor element 40c executed.

At step S260 sends similar to step S160 in the flow chart of 3 the scheduler 48 Processing execution requests to processor elements at substantially the same time 40a until 40n that perform the sub-processing of the parallel processing (s) and processor elements 40a until 40n that the processings for reading at least the part of the instructions and data used in the parallel processing (n + 1) from the memory and for writing the read instructions and data into the L2 cache 44 carry out. As the processing of the steps S270 until S280 in the flow chart of 6th the same as processing the steps S170 until S180 in the flow chart of 3 the description thereof is omitted.

In the present embodiment, as described above, the processor elements read 40a until 40n in the standby state before the parallel processing (n + 1), only the instruction and data from the memory and write the read-out instruction and the read-out data to the L2 cache 44 . In other words, lead elements 40a until 40n does not perform write processing to the memory and peripheral devices in the standby state. Therefore, unlike the first embodiment, setting processing of the memory protection unit is 46 not necessary. Accordingly, in this embodiment, the memory protection unit 46 can be omitted.

Similar to the multiprocessor system 16 of the first embodiment can according to the multiprocessor system 16 the second embodiment that is described above before the multiple processor elements 40a until 40n perform the parallel processing (n + 1), at least the portion of the instructions and data used in the parallel processing (n + 1) in the L2 cache 44 get saved. As a result, in the multiprocessor system 16 According to the present embodiment, when the parallel processing (n + 1) is performed, the probability that at least a part of the instructions and data required for the parallel processing (n + 1) is in the L2 cache 44 exists, that is, the cache hit rate should be increased.

(Third embodiment)

Next, a third embodiment of the multiprocessor system according to the present disclosure will be described in accordance with the drawings. As the basic configuration of the multiprocessor system 16 of the present embodiment is the same as that of the multiprocessor system 16 according to the first embodiment, the description thereof is omitted.

In the multiprocessor system 16 In the first embodiment described above, at least the part of the sub-processing of the parallel processing (n + 1) is provisionally executed only by the processor elements to which the sub-processing of the parallel processing (n) which was carried out before the parallel processing (n + 1) are not assigned.

On the other hand, will be in the multiprocessor system 16 In the present embodiment, the sub-processing (s) of parallel processing (n + 1) are provisionally performed by the processor elements 40a until 40n assigned a sub-processing of the parallel processing (s) by the processor element (s) 40a until 40n (also referred to as a first processor) executing the assigned sub-processing earlier than the other processor elements 40a until 40n (also referred to as second processors) executes / execute, in addition to or instead of the processor element (s) 40a until 40n who are not assigned the sub-processing of the parallel processing (s).

The flowchart of 8th shows an example of processing performed by a scheduler 48 of a multiprocessor system 16 of the present embodiment is carried out. As the processing of the steps S300 until S380 of the flowchart of 8th the same as processing the steps S100 until S180 of the flowchart of 3 the description thereof is omitted.

At step S370 determines the scheduler 48 whether processing completion notifications have been received from all of the processor elements executing sub-processing of the parallel processing (s). When the scheduler 48 at step S370 determines that processing completion notifications have not been received from all of the processor elements performing sub-processing of the parallel processing (s), the scheduler runs 48 with step S390 away. At step S390 determines the scheduler 48 whether or not the processor element 40a until 40n that is in a standby state after completion of the assigned sub-processing exists based on the processing completion notification received from each processor element 40a until 40n Will be received. In this determination processing, it is determined that the processor element 40a until 40n exists in the standby state, the scheduler runs 48 with step S400 away. On the other hand, when it is determined that the processor element 40a until 40c In the standby state does not exist, the scheduler returns 48 to step S370 return.

At step S400 provides the scheduler 48 a memory protection unit 46 on to a write request output from the processor element 40a until 40n to block in the standby state. Then choose at S410 the scheduler 48 at least one of unexecuted sub-processing among the parallel processing sub-processing (n + 1), and sends a processing execution request to the processor element 40a until 40n in the standby state to the processor element 40a until 40n in the standby state to provisionally execute the selected sub-processing.

For example shows 9 an example in which a processor element 40c , the sub-processing A1 and A2 parallel processing A. are not assigned, temporary sub-processing B1 parallel processing B. executes, and also a processor element 40b which is a sub-processing A2 is assigned to the parallel processing A, sub-processing is provisionally B2 the parallel processing B after the completion of the sub-processing A2 executes. As in 9 is shown, the processor element transmits 40b a processing completion notice to the scheduler 48 when the sub-processing A2 the parallel processing A is completed. So the scheduler knows 48 that the processor element 40b is in the standby state. At that time as the scheduler 48 the processing completion notification from the processor element 40a not received, the scheduler determines 48 , the processor element 40b in the standby state to provisionally cause unexecuted sub-processing B2 of under-processing B1 , B2 and B3 the parallel Execute processing B. After performing necessary processing such as setting the memory protection unit 46 sends the scheduler 48 a processing execution request to the processor element 40b for preliminary execution of sub-processing B2 parallel processing B.

This way the sub-processing B1 , B2 tentatively carried out by using: the processor element 40b that is the assigned subprocessing A2 the parallel processing A completes and then is in the standby state; and the processor element 40c to which the sub-processing of parallel processing A is not assigned. As a result, it is possible to have more instructions and data used in parallel processing B in an L2 cache 44 save.

(Fourth embodiment)

Next, a fourth embodiment of the multiprocessor system according to the present disclosure will be described in accordance with the drawings. As the basic configuration of the multiprocessor system 16 of the present embodiment is the same as that of the multiprocessor system 16 according to the first embodiment, the description thereof is omitted.

In the multiprocessor system 16 According to the present embodiment, even if sub-processing of the parallel processing (n) performed before the parallel processing (n + 1) can be all of a plurality of processor elements 40a until 40n are assigned, at least part of the sub-processings of the next parallel processing (n + 1) are provisionally executed. In particular, points in the multiprocessor system 16 of the present embodiment the scheduler 48 a preliminary execution of the sub-processing of the next parallel processing (n + 1) at the processor element (s) 40a until 40n that the assigned sub-processing of the parallel processing (s) earlier than other processor elements 40a until 40n complete / complete.

Furthermore, in the example shown in 10 is shown a processor element 40b the sub-processing A2 parallel processing A. earliest of all the processor elements 40a , 40b and 40c away. Accordingly, the scheduler asks 48 the processor element 40b on, for the time being, a sub-processing B2 the next parallel processing B in response to receiving a processing completion notice from the processor element 40 to execute. The processor element then closes 40c a sub-processing A3 of the parallel processing A and sends a processing completion notice to the scheduler 48 . At that time, the processor element 40a a sub-processing A1 the parallel processing A not yet completed and the Zeitolaner 48 has a processing completion instruction from the processor element 40a not received yet. Thus, as the scheduler 48 the processing completion notifications from all of the processor elements 40a until 40c who received the sub-processing A1 , A2 and A3 are assigned to parallel processing, the scheduler requests 48 the preliminary execution of the sub-processing B3 the next parallel processing B. the processor element 40c from which the processing completion notice is received.

Then, in response to receiving the processing completion notifications from all of the processor elements, prompts 40a until 40c that the subprocesses A1 , A2 and A3 assigned to parallel processing A is the scheduler 48 each of the processor elements 40a until 40c on, the assigned subprocessing B1 until B3 the next parallel processing B.

(Fifth embodiment)

Next, a fourth embodiment of the multiprocessor system according to the present disclosure will be described in accordance with the drawings. As the basic configuration of the multiprocessor system 16 of the present embodiment is the same as that of the multiprocessor system 16 according to the first embodiment, the description thereof is omitted.

In the multiprocessor system 16 according to the present embodiment, the scheduler performs 48 the following control. In cases where the scheduler 48 no cache update processing a processor element (s) 40a until 40n in the standby state, the scheduler causes 48 these standby processor elements 40a until 40n to be in an energy saving state. The cache update processing mentioned above is the preliminary execution of the sub-processing of the next parallel processing as described in the first embodiment, the processing for reading out instructions and data from a memory and writing the read out instructions and data in an L2 cache 44 as described in the second embodiment, etc.

For example, in the example shown in 11 is shown is none of the sub-processing A1 and A2 the parallel processing A to the processor element 40c and further the cache update processing such as preliminary execution of sub-processing of the next parallel processing is assigned B. the processor element 40c unallocated. In such a case, the scheduler can 48 the processor element 40c set to a low power consumption mode to put it in a power saving state. For example, the scheduler 48 the processor element 40c to the low power mode by turning off at least one of a clock signal and a power supply to the processor element 40c is provided.

The preferred embodiments of the present disclosure have been described. However, the present disclosure is not limited to the above-described embodiments and can be variously modified within the spirit and scope of the present disclosure.

For example, in each of the above-described embodiments, there is an example of a multiprocessor system in which one CPU 20th multiple processor elements 40a until 40n and an L2 cache 44 includes that of the plurality of processor elements 40a until 40n shared is explained. However, for example, a multiprocessor system can be configured by multiple CPUs, each of which includes at least one processor element and an L2 cache that is shared by multiple CPUs.

Furthermore, as in 12th As shown, the multiprocessor system can be configured such that the system has multiple CPUs 20a and 20b includes, but the L2 cache 44 not through all of the processor elements 40a until 40n and 50 , but only through some of the processor elements 40a until 40n is shared.

Furthermore, for example, the scheduler initiates 48 in the first embodiment the processor elements 40a until 40n in the standby state during the parallel processing (n) executed immediately before the parallel processing (n + 1), to provisionally perform at least one of sub-processings of the parallel processing (n + 1). However, at least one of the sub-processing of the parallel processing (n + 1) does not have to be provisionally executed during the parallel processing (n) immediately before the parallel processing (n + 1), and can be provisionally executed in the (parallel) processing that was performed before the parallel processing (s) is performed.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• JP 2017058738 A [0003]

Claims (14)

Multiprocessor system, comprising: multiple processors (40a to 40n); a scheduler (48) directing each of the plurality of processors to start executing an assigned task; a memory (22,24) for storing instructions and data used by the plurality of processors to perform the respective tasks; and a cache (44) provided between the plurality of processors and the memory and shared by the plurality of processors, whereby, when parallel processing is scheduled to be allocated to the multiple processors, the parallel processing being a task to be performed synchronously by the multiple processors, the scheduler is configured to perform cache update processing that includes at least a portion of instructions and data stored in the parallel Processing is used, reads out from the memory and stores the read instructions and data in the cache, assigns to a processor in a standby state and instructs execution start of cache update processing before instructing execution start of parallel processing. Multiprocessor system according to Claim 1 wherein the multiprocessor system is mounted on a vehicle and is used to control an in-vehicle device, the multiprocessor system further comprising: an input circuit (14) for inputting a signal necessary for controlling the in-vehicle device; and an output circuit (32) for outputting a control signal for controlling the in-vehicle device. Multiprocessor system according to Claim 1 or 2 wherein: the cache update processing assigned to the processor in the standby state includes preliminarily executing at least the part of the parallel processing; and the scheduler (S140, S160, S340, S360, S410) instructs the processor in the standby state to start executing at least the part of the parallel processing to cause the processor in the standby state to provisionally execute at least the part of the parallel processing, whereby at least the part of instructions and data used in the parallel processing is caused to be read out from the memory and stored in the cache. Multiprocessor system according to Claim 3 , further comprising a blocking unit (S150, S195, S350, S400) that blocks a write request output from the processor which is provisionally executing at least the part of the parallel processing. Multiprocessor system according to Claim 4 , wherein at or before the instruction by the scheduler of the plurality of processors to start the execution of the parallel processing, the blocking unit (S195) unblocks the write request output from the processor which is provisionally executing at least the part of the parallel processing. Multiprocessor system according to one of the Claims 3 until 5 , wherein at least the part of the processing that the processor provisionally executes in the standby state includes a certain processing of the parallel processing, the certain processing being one of processings of the parallel processing and the longest time for reading out instructions and data from the memory of the processings of parallel processing when the processings are assigned to and executed by the plural processors. Multiprocessor system according to one of the Claims 3 until 5 wherein at least the part of the parallel processing that the processor provisionally executes in the standby state that is a particular processor includes a particular processing of the parallel processing, the particular processing being scheduled to be performed by the particular processor according to the assignment the parallel processing to the plural processors is performed. Multiprocessor system according to Claim 1 or 2 , wherein the cache update processing assigned to the processor in the standby state includes processing for reading out at least a part of the instructions and data used in the parallel processing from the memory and writing the read-out instructions and data to the cache, and the The scheduler (S240, S260) instructs the processor in the standby state to start executing the processings involved in the cache update processing, thereby causing at least the part of instructions and data used in the parallel processing to be read out from the memory to be and stored in the cache. Multiprocessor system according to one of the Claims 1 until 8th , wherein when other parallel processing is assigned to the plural processors and the other parallel processing by the plurality of processors is executed before the parallel processing scheduled to be assigned to the plurality of processors, the scheduler assigns the cache update processing to the processor in the standby state during the execution of the other parallel processing, and instructs execution start of the cache update processing. Multiprocessor system according to Claim 9 wherein the other parallel processing is performed immediately before the parallel processing scheduled to be assigned to the plural processors. Multiprocessor system according to Claim 9 or 10 wherein the processor in the standby state during the execution of the other parallel processing is a processor to which the other parallel processing is not assigned. Multiprocessor system according to one of the Claims 9 until 11 wherein the processor in the standby state during execution of the other parallel processing from the plurality of processors is a first processor that is assigned at least a portion of the other parallel processing and that completes assigned processing earlier than one or more second processors that the plurality of Processors other than the first processor. Multiprocessor system according to one of the Claims 1 until 12th wherein the scheduler places the processor in the standby state in a power saving state when the scheduler does not assign the cache update processing to the processor in the standby state. Multiprocessor system according to Claim 13 wherein the processor in the standby state is placed in the energy-saving state by switching off at least one of a clock signal and a power supply which are provided to the processor in the standby state.

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