JP2017053926A - Control device, liquid crystal display, and control method of liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control device that can properly drive moving images and still images, respectively without complicating a circuit configuration.SOLUTION: A control device (200) comprises: image determination means (210) that determines to which of still images and moving images an input signal corresponds; frame rate setting means (220) that changes the frame rate on the basis of a result of determination by the image determination means; and panel control means (230) that controls a liquid crystal panel according to the frame rate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a liquid crystal display device with improved display image quality.

  In recent years, products using liquid crystal display devices such as liquid crystal televisions, mobile phones, and liquid crystal projectors have been provided. A liquid crystal display device requires different driving methods for moving images and still images from the viewpoint of human visibility. That is, a high frame rate is required for moving images, and gradation is required for still images.

  Patent Document 1 discloses a liquid crystal display device that reduces the number of samplings by reducing the number of data latches for panel drive data in order to reduce the sampling clock frequency and increase the number of gradations, and separately latches data for insufficient data. It is disclosed.

JP 2011-33906 A

  However, in the liquid crystal display device disclosed in Patent Document 1, the configuration of writing voltage to the storage capacitor in the liquid crystal panel becomes complicated, and a complicated control method needs to be added.

  Therefore, the present invention provides a control device, a liquid crystal display device, and a control method for the liquid crystal display device that can appropriately drive a moving image and a still image without complicating the circuit configuration.

  A control device according to one aspect of the present invention changes an image determination unit that determines whether an input signal is a signal corresponding to a still image or a moving image, and changes a frame rate based on a determination result of the image determination unit Frame rate setting means and panel control means for controlling the liquid crystal panel according to the frame rate.

  A liquid crystal display device as another aspect of the present invention includes a liquid crystal panel and the control device.

  A method for controlling a liquid crystal display device according to another aspect of the present invention includes a step of determining whether an input signal is a signal corresponding to a still image or a moving image, and a step of changing a frame rate based on the signal. And controlling the liquid crystal panel according to the frame rate.

  Other objects and features of the invention are described in the following embodiments.

  According to the present invention, it is possible to provide a control device, a liquid crystal display device, and a control method for a liquid crystal display device that can appropriately drive a moving image and a still image without complicating the circuit configuration.

It is a block diagram of the liquid crystal display device in this embodiment. It is a block diagram of the liquid crystal panel in this embodiment. In this embodiment, it is a figure which shows the movement of the display target within the display area | region of a video signal. FIG. 4 is a diagram illustrating a lamp voltage generated by a lamp voltage generation circuit in the present embodiment. It is a flowchart which shows operation | movement of the liquid crystal display device in this embodiment. In this embodiment, it is a figure which shows 10 bit gradation based on a ramp voltage and a sampling frequency (CCLK). In this embodiment, it is a figure which shows 11 bit gradation based on a ramp voltage and a sampling frequency (CCLK). 4 is a timing chart showing timing at the time of horizontal scanning by the liquid crystal panel control circuit in the present embodiment. In this embodiment, it is a timing chart which shows the timing of the signal output from a sampling control circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, the configuration of the liquid crystal display device according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram of a liquid crystal display device 10 according to this embodiment. The liquid crystal display device 10 includes a liquid crystal panel 100, a control circuit 200 (control device), and a lamp voltage generation circuit 300 (DAC: D / A converter). In the liquid crystal display device 10, predetermined signals from the control circuit 200 and the ramp voltage generation circuit 300 are input to the liquid crystal panel 100, and the pixel region 130 is defined with a resolution of horizontal 1024 pixels × vertical 768 pixels (XGA: eXtended Graphics Array). To drive.

  The liquid crystal panel 100 includes an H drive circuit 110, a V shift register 120, and a pixel region 130. The control circuit 200 includes an input image determination unit 210 (image determination unit), a frame rate setting unit 220, a liquid crystal panel control circuit 230 (panel control unit), and a sampling control circuit 240 (gradation control unit). The

  The input image determination unit 210 determines whether the input image (video signal or input image data) is a moving image or a still image using a motion detection algorithm. When the input image determination unit 210 determines that the input image is a moving image, the input image determination unit 210 instructs the frame rate setting unit 220 to set the frame rate for the moving image. On the other hand, when the input image determination unit 210 determines that the input image is a still image, the input image determination unit 210 instructs the frame rate setting unit 220 to set the frame rate for the still image.

  The frame rate setting unit 220 sets the frame rate according to the instruction from the input image determination unit 210. The liquid crystal panel control circuit 230 drives the liquid crystal panel 100 according to the frame rate (driving frequency) set by the frame rate setting means 220. When the liquid crystal panel control circuit 230 receives, for example, an instruction for double speed drive (120 Hz) drive, the liquid crystal panel control circuit 230 generates an intermediate frame for input image data of 60 Hz and transmits video data (DATA) to the liquid crystal panel 100. In addition, the liquid crystal panel control circuit 230 receives a digitized video signal from a scaler (not shown) or the like, and generates drive control signals (HS, HCLK) to the liquid crystal panel 100. The liquid crystal panel control circuit 230 includes a gamma processing circuit, a color unevenness processing circuit, and a data correction circuit that perform gamma processing, color unevenness processing, and other data correction processing on the video signal.

  The sampling control circuit 240 receives the frame rate (information relating to the frame rate) set by the frame rate setting means 220 from the liquid crystal panel control circuit 230. Then, the sampling control circuit 240 selects the 10-bit mode ramp voltage generation data table in the case of the moving image frame rate. On the other hand, the sampling control circuit 240 selects the 11-bit mode ramp voltage generation data table in the case of the still image frame rate.

  The ramp voltage generation circuit 300 (voltage generation means) generates a ramp voltage based on the data output from the sampling control circuit 240 (that is, the ramp voltage generation data table selected by the sampling control circuit 240). The liquid crystal panel control circuit 230 samples the lamp voltage output from the lamp voltage generation circuit 300 as the luminance voltage of the liquid crystal panel 100 and applies the voltage to the liquid crystal panel 100.

  Next, the configuration of the liquid crystal panel 100 will be described with reference to FIG. FIG. 2 is a configuration diagram of the liquid crystal panel 100. The H drive circuit 110 is driven based on various signals (HS, HCLK) such as a drive signal from the liquid crystal panel control circuit 230 in the control circuit 200 and video data (DATA). The H drive circuit 110 receives the sampling count clock (CCLK) from the sampling control circuit 240 and the count reset signal (CRT) for resetting the count number of CCLK, and drives in the horizontal direction.

  The input data register 111 in the H drive circuit 110 sequentially receives video data (DATA) that has been subjected to gamma processing, color unevenness processing, and other data correction processing by the liquid crystal panel control circuit 230, and N + 1 in the horizontal direction. Stores video data for a line. The data memory 112 stores video data for the 1H line of the Nth line received by the input data register 111. The data comparator 113 compares the video data stored in the data memory 112 with the count value of the counter clock (CCLK) input to the data comparator 113. Based on the output from the data comparator 113, the SW controller 114 converts the SW signal 132 for switching the analog SW 133 into a voltage that can be turned ON / OFF, and outputs it. Then, the analog SW 133 controls connection of the RV 131 that is the ramp voltage generated by the ramp voltage generation circuit 300 to the video lines 134 that are wired vertically to the pixel region 130 (768 display areas in the case of XGA).

  The V shift register 120 controls the V scanning signal 135 based on the control signals (VS signal and VCLK signal) output from the liquid crystal panel control circuit 230. RV 131 that is a ramp voltage supplied to the video line 134 via the analog SW 133 is connected to the drain of the pixel transistor 136. The gate of the pixel transistor 136 is connected to the V scanning signal 135 and performs on / off control of the pixel transistor 136. The pixel capacitor 137 is connected to the source of the pixel transistor 136, receives the ramp voltage applied to the video line 134, and charges the ramp voltage as a liquid crystal drive voltage.

  One end of the pixel capacitor 137 is connected to the source of the pixel transistor 136. In the pixel capacitor 137, the wiring functions as a capacitor capacitance, and has a capacitance (several hundred times to several tens of thousands times) larger than the capacitance of the pixel transistor 136. A predetermined voltage VcomC is applied to the other end of the pixel capacitor 137. The LC 138 that is a liquid crystal is driven based on a potential difference between a voltage charged in the pixel capacitor 137 and a predetermined voltage VcomL applied to a transparent electrode (not shown). The LC 138 changes according to the potential difference (effective value) of the pixel electrode, whereby liquid crystal display is performed. In the case of XGA, in the pixel region 130, a pixel transistor 136 and a pixel capacitor 137 constituting a pixel are provided at each of the intersection positions together with 768 rows of V scanning signals 135 and 1024 columns of video lines 134.

  In the present embodiment, as the effective voltage value held by the pixel capacitor 137 approaches zero, the light transmittance of the LC 138 decreases and approaches black display, while the amount of transmitted light increases as the effective voltage value increases. The normally black mode will be described. However, the present embodiment is not limited to this.

  Next, operations of the lamp voltage generation circuit 300 and the liquid crystal panel 100 based on the control of the control circuit 200 will be described in detail with reference to FIGS. 1, 2, 4, 8, and 9. FIG. 4 is a diagram showing the lamp voltage generated by the lamp voltage generation circuit 300. As shown in FIG. FIG. 8 is a timing chart showing the timing at the time of horizontal scanning (H scanning) of the liquid crystal display device 10. FIG. 9 is a timing chart showing the timing of signals output from the sampling control circuit 240.

  The control circuit 200 performs video data (DATA) for driving the liquid crystal panel 100 obtained by performing gamma processing, color unevenness processing, and other data correction on the video signal by the liquid crystal panel control circuit 230. Generate. The generated video data is input to the H drive circuit 110 of the liquid crystal panel 100 through the DATA line.

  The video data input to the H drive circuit 110 is stored in the input data register 111 of the H drive circuit 110. At this time, the video data is received and stored in synchronization with the horizontal clock (HCLK) from the horizontal start signal (HS signal) from the liquid crystal panel control circuit 230 as shown in FIG. The That is, as described above, the input data register 111 stores video data 1024 in the horizontal direction when the resolution of the liquid crystal panel 100 is XGA horizontal: 1024 × vertical: 768. The data memory 112 stores the video data of the Nth line for the 1H line received by the input data register 111. The input data register 111 receives the next H line and (N + 1) th video data.

  As shown in FIG. 9, the data comparator 113 includes a counter that counts the clock CCLK starting from the CRST signal output from the sampling control circuit 240. The data comparator 113 compares the video data stored in the data memory 112 with the count value counted by the counter. Here, for example, it is assumed that the video data has a 10-bit gradation and the data D1 is 100. In this case, if it is assumed that the comparator output is CK100 and the data D2 is 4, for example, the comparator output is output to the SW controller 114 at CK4. This comparator output provides 1024 outputs for horizontal rows.

  The SW controller 114 receives 1024 outputs from the horizontal row from the data comparator 113, converts the voltage, and outputs a control signal to the analog SW 133. By turning ON / OFF the analog SW 133 based on this control signal, it is possible to control to apply the lamp voltage RV 131 output from the lamp voltage generation circuit 300 to the video line 134. In the analog SW 133, all the SWs of 1024 are turned on by the CRST signal, and the lamp voltage RV131 is applied to the video line 134. When receiving the output from the data comparator 113, the SW controller 114 controls the analog SW 133 to be turned off.

  Next, generation of the ramp voltage by the ramp voltage generation circuit 300 will be described. In the present embodiment, the lamp voltage generation circuit 300 is described as including a D / A converter, but the present invention is not limited to this. As the ramp voltage, data (D / A_DATA) for generating a voltage is input from the sampling control circuit 240 to the ramp voltage generation circuit 300 (D / A converter). The clock (D / A_CLK) and data (D / A_DATA) input to the D / A converter are output in synchronization with the clock (CCLK) starting from the above-mentioned CRST signal.

  The data (D / A_DATA) is output from the sampling control circuit 240 as data that is incremented according to the number of clocks (D / A_CLK). In the present embodiment, for example, when the gradation (number of gradations) of the ramp voltage generation circuit 300 is 10 bits, the ramp voltage generation circuit 300 has a ramp waveform with 1024 resolution (that is, with a gradation according to the number of bits). Is generated.

  As a result, the ramp voltage generation circuit 300 (D / A converter) generates a ramp voltage as shown in FIG. That is, the lamp voltage RV131 output from the lamp voltage generation circuit 300 is turned on by the CRST signal. For the data D1, for example, the D / A converter of the ramp voltage generation circuit 300 applies the voltage shown as (D / A_DATA: 100) = (D1: 100) in FIG. In the case where the liquid crystal display device 10 operates at a 1024 resolution of 10 bits, if the Δ voltage of the lamp voltage is 4V, the voltage of the data D1 = (100−1) / 1024 × 4V, which is +0 with respect to the start voltage of the lamp voltage. .367V is applied to the video line 134.

  Regarding the data D2, the voltage shown as (D / A_DATA: 4) = D2: 4 in FIG. 4 is voltage = (4-1) /1024×4=0.117V, which is the start voltage of the lamp voltage. In contrast, + 0.0117V is applied to the video line 134. Such sampling is performed, and a voltage is applied to 1024 columns of video lines 134. The voltage applied to the video line 134 is connected to the gates of the pixel transistors 136 of H1 to H1024 in one column in the H direction by a V scanning signal 135 output from the V shift register 120. The pixel transistor 136 is turned on. When the pixel transistor 136 is turned on, the video line 134 and the pixel capacitor 137 are connected via the pixel transistor 136, and the pixel capacitor 137 is charged with a desired voltage sampled according to the ramp voltage RV. A driving voltage is applied to the LC 138 serving as a liquid crystal with a voltage charged in each of the pixel capacitors 137 of H1 to H1024.

  The V shift register 120 of the liquid crystal panel 100 receives a vertical scanning start signal (VS signal) and a VCLK vertical scanning clock (clock VCLK) signal from the liquid crystal panel control circuit 230. The V shift register 120 scans the V scanning signal 135 in the vertical direction sequentially from V1 to V768 in the vertical direction for each clock VCLK. By this scanning, the driving voltage writing (charging) control of the liquid crystal LC 138 is performed on the entire pixel region 130 of the liquid crystal panel 100. Then, a display image is generated by a predetermined voltage applied to a transparent electrode (not shown) and a driving voltage of the liquid crystal LC138.

  Next, the operation of the liquid crystal display device 10 in the present embodiment will be described with reference to FIG. FIG. 5 is a flowchart showing the operation of the liquid crystal display device 10. Each step in FIG. 5 is mainly executed by each unit of the control circuit 200.

  First, in step S101, the input image determination unit 210 of the control circuit 200 determines whether a video signal (external input signal) is input from an external device such as a signal output device. When the video signal is not input, the standby state is entered until the video signal is input (step S101 is repeated). Here, it is determined whether or not a video signal has been input by monitoring digital data such as an HS signal, a VS signal, or a data signal input from an external device. For example, when these signals change from Hi to Lo or from Lo to Hi, the input image determination unit 210 determines that a video signal is input from an external device. However, the present embodiment is not limited to this, and other methods may be used to determine the presence or absence of a video signal. Hereinafter, a case where it is determined that a video signal is input from an external device will be described.

  When the video signal is input, the process proceeds to step S102, and the input image determination unit 210 determines whether the image corresponding to the video signal is a moving image (that is, whether the image corresponding to the video signal is a moving image or a still image). Is determined). The input image determination unit 210 includes a memory called a frame memory (not shown). The frame memory can store a plurality of frame data, and one frame memory stores video data (image data) for one frame. In addition, regarding the video data of the continuous frames of the video data of the still image, the data difference is reduced. Therefore, the input image determination unit 210 determines the moving image or the still image by comparing the differences of the video data.

  First, the frame memory (first frame memory) of the input image determination unit 210 stores video data (image data) of the first frame of the video signal. In the input image determination unit 210, the second frame memory stores the video data (image data) of the second frame of the video signal while maintaining the storage in the first frame memory. Then, the input image determination unit 210 compares the video data of the first frame and the second frame. Here, when the same block as the data block existing in the first frame exists at different coordinates in the second frame, the input image determination unit 210 regards that the data block has moved, and the video (image) corresponding to the video signal. Is determined to be a video.

  FIG. 3 is a diagram illustrating the movement of the display target within the display area of the video signal. Consider the case where an alphabet A consisting of four pixels is displayed in the first frame from the coordinates (H5, V5) in the H and V directions. In the second frame, the alphabet A is moved from the display position in the first frame by +1 pixel in the H direction and +1 pixel in the V direction. At this time, the image data in the first frame is cut out by pixel blocks (here, 4 × 4), and a search is made for a place where the image data of the cut-out block matches in the second frame. In the case of FIG. 3, the first frame and the second frame coincide with each other. For this reason, the input image determination unit 210 calculates the coordinate difference of the pixel block, and if there is a difference, the input image determination unit 210 regards that there is a motion and determines that the image related to the video signal is a moving image. On the other hand, when there is no coordinate difference, the input image determination unit 210 determines that the image related to the video signal is a still image. In the method of searching for pixel blocks that match each other, one pixel is moved in the H direction from the coordinate (H1, V1), and when the right end of the pixel block has advanced to H1024, the pixel block is shifted by +1 pixel in the V direction. Again, all areas in the frame are searched by a method of moving one pixel at a time in the H direction. Although the present embodiment has shown a motion detection method using a motion vector, the present invention is not limited to this, and other motion detection methods such as a luminance difference detection method may be adopted. Further, the method for simplifying the algorithm is not questioned.

  If it is determined in step S102 that the image corresponding to the video signal is a moving image, the process proceeds to step S103. On the other hand, if it is determined that the image is a still image, the process proceeds to step S106. In steps S103 and S106, the frame rate setting means 220 determines the frame rate (drive frequency). In the present embodiment, the frame rate is 120 Hz (double speed drive) for moving images, and the frame rate is 60 Hz (constant speed drive) for still images. That is, when the input image determination unit 210 determines that the video signal is a signal corresponding to a moving image (when the input image is a moving image), the input image determination unit 210 determines that the frame rate setting unit 220 Instructs the frame rate to be set to 120 Hz. On the other hand, when it is determined that the video signal is a signal corresponding to a still image (when the input image is a still image), the input image determination unit 210 sets the frame rate to 60 Hz with respect to the frame rate setting unit 220. Instruct to set. The frame rate setting unit 220 sets the frame rate in accordance with the instruction received from the input image determination unit 210 and outputs the result to the liquid crystal panel control circuit 230.

  Subsequently, in steps S104 and S107, the liquid crystal panel control circuit 230 determines a sampling data table (frame data) for generating a ramp voltage according to the frame rates determined in steps S103 and S106, respectively. When the video signal is a signal corresponding to a moving image and the frame rate is set to 120 Hz, the liquid crystal panel control circuit 230 selects a moving image driving mode (10-bit mode) (step S104). On the other hand, when the video signal is a signal corresponding to a still image and the frame rate is set to 60 Hz, the liquid crystal panel control circuit 230 selects a still image drive mode (11 bit mode) (step S107). Then, the liquid crystal panel control circuit 230 outputs a signal indicating information regarding which of the moving image driving mode or the still image driving mode to the sampling control circuit 240.

  In step S105, the liquid crystal panel control circuit 230 complements the image for each frame to generate an intermediate frame. There are various methods for generating the intermediate frame, and any method may be used. For example, when complementing a frame between n frames and n + 1 frames, an interpolation frame may be generated using the same image data as the n frame. Further, a frame memory may be mounted on the liquid crystal panel control circuit 230, and n frames of image data and n + 1 frames of image data may be stored to generate a moving intermediate frame. In this embodiment, as an example, a frame rate (drive frequency) of 60 Hz is set for a still image and 120 Hz for a moving image, but the present invention is not limited to these. If the frame rate set for a moving image is higher than the frame rate set for a still image, another frame rate may be set.

  The liquid crystal panel control circuit 230 uses the 120 Hz frame data for moving images generated in step S104 or the 60 Hz frame data for still images generated in step S107 to generate image data for driving the liquid crystal panel 100. Output to the liquid crystal panel 100. At this time, the liquid crystal panel control circuit 230 outputs image data generated by performing gamma processing, color unevenness processing, and other data correction on the input image data.

  Subsequently, in step S <b> 108, the liquid crystal panel 100 writes image data for one line in the input data register 111 using the nth HS signal output from the liquid crystal panel control circuit 230 as a starting point. Subsequently, in step S109, all the image data written in the input data register 111 in step S108 is transferred from the input data register 111 to the data memory 112 in the blank period (blanking period) until the output of the (n + 1) th HS signal. Forward. Then, starting from the (N + 1) th HS signal, data for one line is written in the input data register 111. At this time, the data memory 112 stores the nth 1-line data, and the input data register 111 stores the (n + 1) th data.

  In parallel with steps S108 and S109, in step S110, the ramp voltage generation circuit 300 starts generating the ramp voltage and counting the clock CCLK. At this time, driving is performed using the same CCLK frequency in each mode of 60 Hz, which is a frame rate of still images, and 120 Hz, which is a frame rate for moving images. With this operation, the frame rate of 60 Hz for a still image is twice as long as the 1H period of the frame rate for moving images of 120 Hz. For this reason, the count number of CCLK in the 1 C period of the same CCLK is the same as that of the still image frame rate of 60 Hz and the frame rate of 120 Hz for the moving image is 120 Hz for the moving image. Double. That is, the gradation (number of gradations) increases by 1 bit.

  6 and 7 are diagrams showing a 10-bit gradation and an 11-bit gradation based on the ramp voltage and the sampling frequency (CCLK), respectively. FIG. 6 shows a case where the sampling frequency (CCLK2) for still images is originally driven at 100 MHz and the sampling frequency (CCLK1) for moving images is 200 MHz. At this time, with regard to still image driving, half the frequency is used for both the frame rate (60 Hz, 120 Hz) and CCLK (100 MHz, 200 MHz) compared to moving image driving. For this reason, only a 10-bit gradation can be expressed in either a moving image or a still image. On the other hand, as shown in FIG. 7, by using a sampling frequency (CCLK2) of 200 MHz even when driving a still image, the count period can be ensured twice, so that 11-bit gradation can be obtained. It becomes. That is, in either case of a moving image or a still image, by making the sampling frequency constant, it is possible to increase the gradation when driving a still image.

  Subsequently, in step S111 of FIG. 5, the data comparator 113 compares the image data (luminance data) for all pixels for one line stored in the data memory 112 with the count number of the sampling frequency (CCLK). To do. For example, when the image data is 100 hex (256 dec), the image data and the clock number of CCLK coincide with each other when the sampling frequency (CCLK) is 256 counts. At this time, the SW controller 114 turns on the analog SW 133 in step S112. On the other hand, when the image data and the clock number of CCLK do not match each other, the analog SW 133 remains OFF. That is, the voltage is sequentially written from the low gradation pixel in one line. Thus, when the comparison is made up to the maximum gradation in the 1HS period, the numerical value of CCLK is reset in step S113. In step S114, the liquid crystal panel control circuit 230 determines whether or not the VS signal (vertical scanning start signal) has been output (whether or not the VS signal has become Hi), that is, whether or not one frame period has ended. To do. Steps S108 to S114 are repeated until the VS signal is output, that is, until the end of one frame period. When the operation for one frame period ends, the process returns to the start.

  In the above series of operations, by changing the frame rate according to the video signal (input image) and adjusting the frequency of CCLK, a higher gradation can be obtained in the case of a still image, and in the case of a moving image. A higher frame rate can be obtained. As a result, the visibility of still images and moving images can be improved.

  In the present embodiment, the resolution of the liquid crystal panel, the number of horizontal scanning lines, and the input format (parallel / serial / data phase number) of the image signal are not limited. In the present embodiment, switching of the frame rate (driving frequency) to either constant speed (60 Hz) or double speed (120 Hz) is described, but the present invention is not limited to these frame rates. The liquid crystal display device of the present embodiment can be applied to electronic devices such as a liquid crystal projector, a liquid crystal television, a mobile phone, a notebook computer, or a digital still camera car navigation device.

  As described above, the control device (control circuit 200) of the present embodiment includes the image determination unit (input image determination unit 210), the frame rate setting unit 220, and the panel control unit (liquid crystal panel control circuit 230). The image determination means determines whether the input signal (video signal) corresponds to a still image or a moving image. The frame rate setting means changes the frame rate (drive frequency) based on the determination result of the image determination means. The panel control means controls the liquid crystal panel 100 according to the frame rate. Preferably, the frame rate setting means sets a first frame rate (for example, 120 Hz) as the frame rate when the input signal is a signal corresponding to a moving image. The frame rate setting means sets a second frame rate (for example, 60 Hz) lower than the first frame rate as the frame rate when the input signal is a signal corresponding to a still image.

  Preferably, the control device has gradation control means (sampling control circuit 240) for controlling the gradation of each of the still image and the moving image in accordance with the frame rate. Here, the gradation is the number of stages at which the color density can be expressed. As the number of gradations increases, richer colors and smooth gradations can be expressed. More preferably, the gradation control means sets the first gradation (for example, 10 bits) as the gradation when the input signal is a signal corresponding to a moving image. Further, when the input signal is a signal corresponding to a still image, the gradation control unit sets a second gradation (for example, 11 bits) larger than the first gradation as the gradation.

  Preferably, the control device periodically generates a voltage that monotonously increases or monotonously decreases in accordance with the number of clocks included in the reset interval of the clock (CCLK) output from the gradation control unit. Voltage generation circuit 300). Here, the reset interval is an output interval of a reset signal (CRST signal) for resetting the clock count output from the gradation control means. As an example, the reset interval means the number of clocks (CCLK) included between the left reset signal (CRST signal and Hi signal) and the right reset signal (CRST signal and Hi signal) in FIG. The gradation control means controls the clock frequency to be constant even when the frame rate is changed. The voltage generation unit is provided outside the control circuit 200 in FIG. 1, but may be provided as a part of the control circuit 200. More preferably, the voltage generated by the voltage generating unit is a ramp voltage supplied to each pixel of the liquid crystal panel (for example, supplied to the drain of the pixel transistor 136 via the analog SW 133 and the video line 134). The one cycle of the ramp voltage and the frame rate coincide with each other, and the number of clocks included in one cycle of the ramp voltage changes according to the frame rate.

  Preferably, when the input signal is a signal corresponding to a moving image, the voltage generation unit generates the voltage at a first gradation (for example, 1024 resolution) corresponding to the first number of bits. When the input signal is a signal corresponding to a still image, the voltage generation means generates the voltage with a second gradation (for example, 2048 resolution) corresponding to a second bit number larger than the first bit number. To do. Preferably, when the input signal is a signal corresponding to a moving image, one cycle of the ramp voltage is the first cycle (1/120 (s)), and the number of clocks included in the first cycle is the first. The number of clocks (1024). On the other hand, when the input signal is a signal corresponding to a still image, one cycle of the lamp voltage is a second cycle (1/60 (s)) that is twice the first cycle, and is included in the second cycle. The number of clocks generated is a second clock number (2048) which is twice the first clock number.

  The liquid crystal display device according to the present embodiment can improve gradation at a constant frame rate for displaying a still image by switching sampling control according to constant speed / double speed driving conditions. Therefore, according to the present embodiment, it is possible to provide a control device, a liquid crystal display device, and a control method for the liquid crystal display device that can appropriately drive a moving image and a still image without complicating the circuit configuration. it can.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

200 Control circuit (control device)
210 Input image determination means (image determination means)
220 Frame rate setting means 230 Liquid crystal panel control circuit (panel control means)

Claims (10)

Image determining means for determining whether the input signal is a signal corresponding to a still image or a moving image;
Frame rate setting means for changing the frame rate based on the determination result of the image determination means;
And a panel control means for controlling the liquid crystal panel according to the frame rate. The frame rate setting means includes
When the input signal is a signal corresponding to the moving image, a first frame rate is set as the frame rate,
2. The control according to claim 1, wherein when the input signal is a signal corresponding to the still image, a second frame rate lower than the first frame rate is set as the frame rate. apparatus.   The control apparatus according to claim 1, further comprising a gradation control unit that controls the gradation of each of the still image and the moving image in accordance with the frame rate. The gradation control means includes
When the input signal is a signal corresponding to the moving image, the first gradation is set as the gradation,
4. The control according to claim 3, wherein when the input signal is a signal corresponding to the still image, a second gradation larger than the first gradation is set as the gradation. 5. apparatus. Voltage generating means for periodically generating a monotonically increasing or monotonically decreasing voltage according to the number of clocks included in the clock reset interval output from the gradation control means,
The control apparatus according to claim 3 or 4, wherein the gradation control unit controls the frequency of the clock to be constant even when the frame rate is changed. The voltage generated by the voltage generating means is a lamp voltage supplied to each pixel of the liquid crystal panel,
The one period of the lamp voltage and the frame rate coincide with each other,
The control device according to claim 5, wherein the number of the clocks included in one cycle of the ramp voltage changes according to the frame rate. The voltage generating means includes
When the input signal is a signal corresponding to the moving image, the voltage is generated with a first gradation corresponding to the first number of bits,
When the input signal is a signal corresponding to the still image, the voltage is generated with a second gradation corresponding to a second bit number larger than the first bit number. The control device according to claim 5 or 6. When the input signal is a signal corresponding to the moving image, one cycle of the ramp voltage is a first cycle, and the number of clocks included in the first cycle is a first clock number,
When the input signal is a signal corresponding to the still image, one cycle of the ramp voltage is a second cycle that is twice the first cycle, and the number of clocks included in the second cycle The control device according to claim 6, wherein is a second clock number that is twice the first clock number. LCD panel,
A liquid crystal display device comprising: the control device according to claim 1. Determining whether the input signal corresponds to a still image or a moving image;
Changing the frame rate based on the signal;
And a step of controlling the liquid crystal panel in accordance with the frame rate.