KR101450871B1 - Flat Panel Display Device and Driving Method Thereof - Google Patents

Abstract

A flat panel display device suitable for improving image quality of an image is disclosed.

A flat panel display device includes: a flat panel panel having pixels connected to a corresponding one of a plurality of data lines and a plurality of gate lines and a corresponding gate line; A gate driver for causing the plurality of gate lines to be enabled for a gradually longer period of time as the data line advances; And a data driver for supplying the pixel driving signal to the plurality of data lines for a gradually longer period of time as the data line advances.

Liquid crystal panel, Delay, Deviation, Image quality, Brightness, Uniformity, Line, Deterioration.

Description

Technical Field [0001] The present invention relates to a flat panel display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display using a flat panel and a driving method thereof.

2. Description of the Related Art Recently, various flat panel display devices capable of reducing weight and volume, which are disadvantages of cathode ray tubes (CRTs), have been developed. As such a flat panel display device, a liquid crystal display device, a field emission display device, a plasma display device, and an electro-luminescence display device may be used. have. A flat panel, such as a liquid crystal panel, a field emission panel, a plasma panel, and an electro-luminescent panel, which are used in flat panel display devices, (Or data lines) and a plurality of scan lines (or gate lines).

Each of the source lines and scan lines on the flat panel must have resistivity and parasitic capacitance. The resistivity value is determined by the material and shape (i.e., width and length) of the source line or the scan line. The parasitic capacitance value is determined by the sum of the interference capacitance value existing between the lines and the value of the holding capacitance formed around each line.

The intrinsic resistance and parasitic capacitance of these lines cause the pixel drive signal and the scan signal to be supplied to each pixel cell to be delayed through the source line and the scan line. Actually, the delay amount of the pixel drive signal on the source line increases exponentially in accordance with the advancing direction of the scan line. The amount of delay of the scan signal on the scan line also exponentially increases in accordance with the traveling direction of the source line. The amount of delay of the pixel drive signal and the amount of delay of the scan signal are inevitably varied depending on the position of the pixel on the flat panel.

The delay deviation of the signal makes it impossible for the pixel on one end of the source line or one end of the scan line to sufficiently charge the pixel drive signal. Thus, in the flat panel, the brightness is uneven and the degraded image is inevitably displayed. The image quality of the image displayed by the flat panel display device has been inevitably deteriorated. Particularly, in a liquid crystal panel that applies an electric field corresponding to a pixel drive signal to a liquid crystal cell, the image quality of an image displayed by the liquid crystal display device drops more severely because a delay variation of a signal depending on the pixel becomes larger.

Accordingly, an object of the present invention is to provide a flat panel display device and a driving method thereof, which are suitable for improving the image quality of an image.

Another object of the present invention is to provide a flat panel display device and a method of driving the same that are suitable for preventing unevenness of brightness and deterioration of an image.

According to an aspect of the present invention, there is provided a flat panel display comprising: a flat panel including pixels connected to corresponding data lines and corresponding gate lines of a plurality of data lines and a plurality of gate lines; A gate driver for causing the plurality of gate lines to be enabled for a gradually longer period of time as the data line advances; And a data driver for supplying the pixel driving signal to the plurality of data lines for a gradually longer period of time as the data line advances.

According to another aspect of the present invention, there is provided a method of driving a flat panel display, the method comprising: scanning a plurality of gate lines on the flat panel panel for a gradually longer period of time as the data lines on the flat panel panel progress; And supplying pixel drive signals to the plurality of data lines for a gradually longer period of time as the data line proceeds.

Other objects, other features, and other advantages of the present invention, besides the above-described embodiments, will be apparent from the detailed description of the embodiments associated with the accompanying drawings.

According to the above-described configuration, the flat panel display device and the driving method thereof according to the embodiments are lengthened in a linear form or an exponential form as the signal charging period of the pixels on the flat panel panel moves away from the data driver. All the pixels on the flat panel panel can sufficiently charge the pixel driving signal despite the delay of the signal on the data line and the gate line. All the pixels on the flat panel panel respond correctly to the pixel driving signal. Accordingly, the luminance is uniformed at the front surface of the flat panel, and the deterioration of the image displayed on the flat panel is minimized. As a result, the flat panel display device and the driving method thereof according to the embodiments can display images of improved image quality.

Hereinafter, embodiments of a flat panel display capable of improving image quality and a driving method thereof will be described in detail with reference to the accompanying drawings. FIG. 1 illustrates a liquid crystal display capable of improving an image quality according to an embodiment. 1 includes a liquid crystal panel 10 connected to a gate driver 12 and a data driver 14. [ The liquid crystal panel 10 is divided into a plurality of pixel regions by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. The plurality of gate lines GL1 to GLn on the liquid crystal panel 10 are electrically connected to the gate driver 12 and the plurality of data lines DL1 to DLm are electrically connected to the data driver 14. [ A plurality of pixel regions are arranged in a matrix form. In each of these pixel regions, a liquid crystal pixel LCP electrically connected to the corresponding gate line GL and the corresponding data line DL is formed.

2, the liquid crystal pixel LCP includes a thin film transistor MN responsive to a scan signal Vsn on a corresponding gate line GL and a thin film transistor MN connected in parallel to the common voltage line CML A cell CLC and a storage capacitor Cst. The thin film transistor MN is turned on in response to the logic state (or voltage level) of the scan signal Vsn on the corresponding gate line GL so that the pixel drive signal Vds on the corresponding data line DL is supplied to the liquid crystal cells CLC and To be supplied to the storage capacitor Cst. Actually, when the scan signal Vsn of high logic (that is, high potential voltage) is supplied to the corresponding gate line GL, the thin film transistor MN is turned on and turned on to the corresponding data line DL To the liquid crystal cell CLC and the storage capacitor Cst. At this time, the liquid crystal cell CLC and the storage capacitor Cst charge the voltage of the pixel driving signal Vds. Alternatively, when the scan signal Vsn of the low logic level (that is, the low potential level) is supplied to the corresponding gate line GL, the thin film transistor MN is turned off to turn on the corresponding data line DL from the liquid crystal cell CLC and the storage capacitor Cst. The voltage charged in the liquid crystal cell CLC is maintained until the thin film transistor MN is turned on again. The liquid crystal cell CLC adjusts the amount of transmitted light according to the voltage level of the charged pixel driving signal Vds to display a picture dot. The storage capacitor Cst compensates for the amount of leakage charge in the liquid crystal cell CLC. By replenishing the charge by the storage capacitor Cst, the liquid crystal cell CLC can more accurately respond to the pixel drive signal Vds. The voltage stored in the storage capacitor Cst is also maintained until the thin film transistor MN is turned on again.

1, the gate driver 12 sequentially and exclusively supplies the gate lines GL1 to GLn on the liquid crystal panel 10 every frame period (i.e., a period of one vertical synchronization signal Vsync) And generates a plurality of scan signals (Vsn1 to Vsnn) that enable the scan signals. The plurality of scan signals Vsn1 to Vsnn each have an enable pulse of a specific logic sequentially shifted (i.e., a high potential voltage). The enable pulses included in each of the scan signals Vsn have a width that is long in a linear form as shown in FIG. 3 depending on the position of the gate line GL. The scan signals Vsn1 to Vsn4 to be supplied to the gate line positioned close to the data driver 14 have enable pulses of a short width as shown in FIG. The scan signals Vsn-3 to Vsnn to be supplied have enable pulses of a long width as shown in FIG. Alternatively, the width of the enable pulses included in the plurality of scan signals (Vsn1 to Vsnn) may have a width that becomes longer in the form of an exponential function depending on the position of the gate line GL as shown in FIG. In this case, the scan signals Vsn1 (n) to be supplied to the gate lines (e.g., the gate lines GL1 to GL (n / 2) positioned at the upper half of the liquid crystal panel 10) (For example, a gate line (not shown) located at the lower half of the liquid crystal panel 10) far from the data driver 14, The scan signals Vsn (n / 2) to Vsnn to be supplied to the data lines GL (n / 2) to GLn have enable pulses of a relatively small width. A period during which the plurality of gate lines GL1 to GLn on the liquid crystal panel 10 are enabled by the enable pulse of the scan signal Vsn that gradually becomes longer as the gate line GL is farther away from the gate line GL And becomes gradually longer as it is farther from the data driver 14. In another form, The enable pulses included in the arcs Vsn1 to Vsnn gradually increase in length in the form of a linear shape or an exponential function as the gate line GL is moved away from the data driver 14, In other words, the scan signals Vsn may be generated in such a manner that the width of the enable pulse is extended in the form of a linear shape or an exponential function, The pixel driving signal Vds transmitted through the data line DL is greatly delayed in the form of an exponential function as it moves away from the data driver 14. Accordingly, It is preferable that each of the scan signals Vsn has an enable pulse that gradually increases in width in the form of an exponential function but changes in the form of a stepped waveform. The width of the enable pulses included may vary within a range of about 50% based on the duration of one horizontal synchronizing signal Hsync. Preferably, the width of the enable pulse is one horizontal synchronizing signal Hsync ) Is preferably set to be long in the range of about 占 40% on the basis of the period of the period.

The gate driver 12 responds to the gate control signal GCS in order to generate a plurality of scan signals Vsn such that the enable period becomes longer in the form of an exponential function. The gate control signal GCS includes a gate start pulse GSP and at least one gate shift clock GSC. The gate start pulse GSP is supplied with a specific logic (for example, high level) during a certain period (for example, a period corresponding to 60% of the period of one horizontal synchronizing signal) Potential or low potential voltage) state. At least one gate shift clock GSC is gradually increased in the form of an exponential function during a period from the time point when the gate start pulse GSP is enabled to the time when it is enabled again in the next frame period, Lt; / RTI > When the gate control signal GCS includes one or two gate shift clocks GSC, the gate shift clock GSC has an impact coefficient of 50%, but the gate control signal GSC has at least three gate shift clocks GSC. (GSC), the gate shift clock GSC has a duty factor of 50% or less (for example, a duty factor of 1/3).

When any one of the plurality of gate lines GL1 to GLn on the liquid crystal panel 10 is enabled and the data driver 14 supplies the pixel drive signal for one line during the period in which the gate line GL is enabled Vds1 to Vdsm to the plurality of data lines DL1 to DLm on the liquid crystal panel 10. [ The period in which the pixel drive signals Vds1 to Vdsm for one line are supplied to the data lines DL1 to DLm is also adjusted in accordance with the position of the enabled gate line GL. As the enabled gate line GL is away from the data driver 14, the output period of the pixel drive signals Vds1 to VdsM for one line gradually becomes longer as shown in Fig. The output period of the pixel drive signal Vds becomes longer in the form of a linear form or an exponential function as the enabled gate line GL is away from the data driver 14. [ The data driver 14 inputs the pixel data VDi for one line in a half period of the horizontal synchronous signal and supplies the pixel data VDi for one line at a time to the pixel driving signals Vds1 To Vdsm). In order to perform the input operation of the pixel data VDi and the output operation of the pixel drive signal Vds, the data driver 14 responds to the data control signal DCS. The data control signal DCS includes a multiplied data clock MCLK, a data transfer enable signal DTE and a source output enable signal SOE. The data transfer enable signal DTE indicates the length of the pixel data for one line and the source output enable signal SOE indicates the transfer period of the pixel data, Of the pixel driving signals (Vds1 to Vdsm). The period and the duty cycle of the multiplied data clock MCLK and the data transfer enable signal DTE are set to be constant while the period and the duty cycle of the source output enable signal SOE are set to be the gate line GL to be enabled, Lt; / RTI > In other words, the enable period of the source output enable signal SOE is either a linear form, as in Fig. 3 or Fig. 5, or a < RTI ID = 0.0 > It expands to exponential form. The data driver 14 inputs one line of pixel data VDi transmitted in a data clock (MCLK) period which is multiplied every time the data transfer enable signal DTE is enabled. The data driver 14 supplies the pixel drive signal Vds for one line to the data lines DL on the liquid crystal panel 10 during the period in which the source output enable signal SOE is enabled.

1 includes a variable timing controller 18 for controlling the operation timings of the gate driver 12, the data driver 14, and the rate conversion unit 16. The variable- The rate conversion unit 16 inputs a pixel data stream (VDf) at a frame level from an external video source (for example, a graphics module of a computer system or a video demodulation module of a television receiver). The pixel data stream VDf on a frame basis is divided-aligned by one line by the rate conversion unit 16 and supplied to the data driver 14. The rate conversion unit 16 supplies the pixel data stream VDi for each line by line to the data driver 14 at a speed twice that of the input data rate. To this end, the rate conversion unit 16 inputs a pixel data stream (VDf) for each frame in response to a synchronization signal (SYNC) from an external video source. The synchronizing signal SYNC from an external video source includes a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DOE and a data clock DCLK. The data clock DCLK has a period twice (that is, a half of the frequency) as the multiplied data clock MCLK. The rate conversion unit 16 supplies the data driver 14 with the pixel data stream VDi for each line by line in response to the data control signal DCS from the variable timing controller 18. [ In response to the synchronizing signal SYNC, the rate converting unit 16 inputs a pixel data stream (VDf) for each frame transmitted from an external video source in a data clock cycle. In addition, the rate conversion unit 16 supplies the data driver 14 with the pixel data stream VDi for one line in response to the data control signal DCS.

The variable timing controller 18 generates a gate control signal GCS necessary for the gate driver 12 and the data driver 14 and the rate conversion section 16 using the synchronization signal SYNC from the external video source And generates a necessary data control signal DCS. The gate control signal GCS generated in the variable timing controller 18 is supplied to the gate driver 12. On the other hand, the data control signal DCS generated in the variable timing controller 18 is supplied to the data driver 14 and the rate conversion unit 16 in common. The variable timing controller 18 may be configured to include a rate conversion unit 16 in order to simplify the circuit configuration of the liquid crystal display device.

The liquid crystal pixels LCP on the liquid crystal panel 10 also charges the pixel drive signal Vds for a period of time gradually getting longer from the data driver 14. [ The first gate The liquid crystal pixels LCP for one line in response to the scan signal Vsn1 on the line GL1 are supplied with the pixel drive signal Vds (for example, a period corresponding to 60% of the horizontal synchronization signal) ). The liquid crystal pixels LCP for one line in response to the scan signal Vsnn on the last gate line GLn are supplied with the pixel drive signal (for example, a period corresponding to 140% of the horizontal synchronization signal) Vds). As the liquid crystal pixels LCP on the liquid crystal panel 10 move away from the data driver 14, the charging period of the pixel driving signal of the liquid crystal pixel LCP becomes long in the form of a linear form or an exponential function.

Since the signal charging period of the liquid crystal pixels LCP on the liquid crystal panel 10 becomes longer in the form of a linear or exponential function as the signal charging period of the liquid crystal pixels LCP on the liquid crystal panel 10 moves away from the data driver 14, The pixel drive signal Vds can be sufficiently charged despite the delay of the signal in the data line DL and the gate line GL. Thus, all of the liquid crystal pixels LCP on the liquid crystal panel 10 are allowed to transmit an amount of light corresponding to the voltage level of the pixel drive signal Vds. The brightness is uniformed on the entire surface of the liquid crystal panel 10 and the deterioration of the image displayed on the liquid crystal panel 10 is minimized. As a result, the liquid crystal display device according to the embodiment can display an image of improved image quality.

6 is a detailed block diagram illustrating the rate conversion unit 16 shown in FIG. 1 in detail. Referring to FIG. 6, the rate conversion unit 16 includes an access controller 22 for controlling the access timing of the memory 20. The memory 20 stores pixel data VDf in units of frames from an external video source and reads pixel data VDf stored in units of frames one line at a time and stores pixel data VDi To the data driver 14 of Fig. The memory 20 has a storage capacity corresponding to pixel data of at least two frames in order to prevent the loss of pixel data due to the difference in speed of writing and reading.

The access controller 22 responds to a synchronizing signal SYNC (e.g., a data clock DCLK, a data enable signal DOE and a vertical synchronizing signal Hsync) from an external video source, Signal (WCS). By the write control signal WCS, the memory 20 sequentially stores the pixel data transmitted from the external video source in the cycle of the data clock DCLK in itself. In addition, the access controller 22, in response to the data control signal DCS (i.e., the multiplied data clock MCLK and the transfer enable signal DTE) from the variable timing controller 18, (RCS). This read control signal RCS causes the memory 20 to supply the pixel data stored in the memory 20 to the data driver 14 at a cycle of the multiplied data clock MCLK. As a result, the access controller 22 causes the memory 20 to supply the data driver 14 with the pixel data VDi for one line at a speed twice as fast as the period of the pixel data from the external video source.

7 is a detailed block diagram illustrating the variable timing controller 18 in FIG. 1 in detail. The variable timing controller 18 in Fig. 7 includes a frequency multiplier 30 and an edge detector 32 for inputting a data clock DCLK and a vertical synchronization signal Vsync from an external video source, respectively. The frequency multiplier 30 multiplies the data clock DCLK by a frequency twice and generates a multiplication data clock MCLK having a period corresponding to 1/2 of the data clock DCLK. The multiplied data clock signal MCLK is synchronized with the data clock signal DCLK. In addition, the multiplication data clock MCLK is commonly supplied to the data driver 14 and the rate conversion unit 16 (i.e., the access controller 22 in Fig. 6) in Fig.

The edge detector 32 detects a specific edge of the vertical synchronization signal Vsync (e.g., a rising edge indicating a time point of the vertical scanning period). The edge detector 32 generates an edge detection pulse synchronized with a specific edge of the vertical synchronization signal Vsync. This edge detection pulse is supplied to the monostable multivibrator 34. [

The monostable multivibrator 34 generates a gate start pulse (GSP) in response to an edge detection pulse from the edge detector 32. The gate start pulse GSP is synchronized with a specific edge of the edge detection pulse (for example, a rising or falling edge), and during a period of the horizontal synchronization signal or a period corresponding to 60% (E. G., High logic). This gate-start pulse (GSP) is supplied to the gate driver 12 of Fig.

The variable timing controller 18 is provided with first to third comparators 40, 42 and 44 connected in common to a counter 36 and an enable section setter (not shown) responsive to an edge detection pulse from the edge detector 32 38 are provided. The counter 36 counts the multiplication data clock MCLK from the frequency multiplier 30 and supplies the count value to the first to third comparators 40, The counter 36 initializes the count value every cycle of the source enable signal SOE in response to the source enable signal SOE fed back from the second comparator 42. [ Specifically, the counter 36 initializes the count value in the disable period of the source enable signal SOE and counts the multiplication data clock MCLK in the enable period of the source enable signal SOE.

The enable section setter 38 also outputs the value of the enable section of the source output enable signal SOE and the value of the enable signal of the specific logical section of the gate shift clock GSC in response to the edge detection pulse of the specific logic from the edge detector 32 Initialize the value. The enable section setter 38 sets the source output enable signal SOE in the form of a linear or exponential function as the number of disable pulses of the source output enable signal SOE from the second comparator 42 increases, (SOE) and the value of the specific logic section of the gate shift clock (GSC). The enable interval value of the source output enable signal SOE generated in the enable interval setter 38 is supplied to the second comparator 42 and the gate interval of the gate shift clock GSC) is supplied to the third comparator 44. The third comparator 44 compares the value of the specific logical section with a predetermined value.

The first comparator 40 inputs a fixed transmission interval value. Also, the first comparator 40 compares the count value from the counter 36 with the transmission interval value. When the count value of the counter 36 is lower than the transmission interval value, the first comparator 36 enables the data transfer enable signal DTE to the base logic (e.g., low logic) state. Conversely, if the count value of the counter 36 is higher than the transmission interval value, the first comparator 40 disables the data transfer enable signal DTE to a specific logic (e.g., high logic) state. By this comparison operation, the first comparator 40 generates the data transfer enable signal DTE whose enable period is constant. The data transfer enable signal DTE generated in the first comparator 40 is supplied to the data driver 14 and the rate conversion unit 16 (i.e., the access controller 22 in Fig. 6) in Fig.

The second comparator 42 inputs the count value from the counter 36 and the output enable interval value from the enable interval setter 38. [ In addition, the second comparator 42 inputs the fixed disabling interval value. The second comparator 42 disables the source output enable signal SOE to a specific logic (e.g., high logic) state when the count value of the counter 36 reaches the enable interval value. Further, the second comparator 42 compares the source output enable signal SOE with the base logic (for example, low level) when the count value of the counter 36 reaches the sum of the enable interval value and the disable interval value, Logic) state. The second comparator 42 determines whether the enable period is a linear form or a form of an exponential function, such as a linear form or a form of an exponential function And generates a source output enable signal SOE that becomes longer. The source output enable signal SOE generated in the second comparator 42 is fed back to the counter 34 and the enable interval setter 38 and supplied to the data driver 14 in Fig. A second edge detector (not shown) is connected to the feedback path from the second comparator 42 to the counter 36 to ensure a stable counting operation during the period of the source output enable signal SOE of the counter 34. [ Can be additionally installed. In this case, the second edge detector generates an edge detection pulse which is synchronized with a specific edge (for example, a falling edge) of the source output enable signal SOE and a width smaller than the period of the multiplication data clock MCLK. By the edge detection pulse generated by the second edge detector, the counter 36 initializes the count value.

The third comparator 44 compares the count value of the counter 36 with the specific logical interval value from the enable interval setter 38 and outputs a gate shift clock GSC ). Actually, the third comparator 44 causes the gate shift clock GSC to maintain a specific logic (e.g., high logic) state when the count value of the counter 36 is lower than a specific logic section value. Conversely, when the count value of the counter 36 is higher than the specific logical section value, the third comparator 44 causes the gate shift clock GSC to transition to the base logic (e.g., low logic) state. The gate shift clock GSC generated in the third comparator 44 is supplied to the gate driver 12 of FIG. In addition, when the gate driver 12 of FIG. 1 requires at least two gate shift clocks, the variable timing controller 18 may additionally comprise at least one third comparator 44.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the exemplary embodiments or constructions. Various changes and modifications may be made without departing from the spirit and scope of the invention. It will be apparent that modifications, variations and equivalents of other embodiments are possible. For example, the liquid crystal panel in Fig. 1 may be replaced with any one of a plasma display panel, an electroluminescence display panel, and an electron emission panel. Therefore, the technical idea and scope disclosed in this specification should not be limited to the description of the embodiment but should be set by the matters described in the appended claims.

1 is a block diagram illustrating a liquid crystal display of an embodiment for improving picture quality.

2 is a circuit diagram showing the liquid crystal pixel included in the liquid crystal panel in FIG. 1 in detail.

3 is a view for explaining the linear characteristics of the enable period of the scan signal and the pixel drive signal.

4 is a timing chart for explaining the output signals of the respective parts in Fig.

5 is a diagram for explaining the exponential function characteristic of the enable period of the scan signal and the pixel drive signal.

FIG. 6 is a detailed block diagram illustrating the rate conversion unit in FIG. 1 in detail.

FIG. 7 is a detailed block diagram illustrating the variable timing controller in FIG. 1 in detail.

DESCRIPTION OF REFERENCE NUMERALS

10: liquid crystal panel 12: gate driver

14: Data driver 16: Rate conversion section

18: variable timing controller 20: memory

22: access controller 30: frequency multiplier

32: edge detector 34: monostable multivibrator

36: Counter 38: Enable interval setter

40: first comparator 42: second comparator

44: third comparator CLC: liquid crystal cell

Cst: storage capacitor MN: thin film transistor

Claims (10)

A flat panel including pixels connected to a corresponding one of a plurality of data lines and a plurality of gate lines and a corresponding gate line; A plurality of thin film transistors that are turned on by a high logic enabled scan signal on the plurality of gate lines; Capacitors corresponding to each of the thin film transistors and respectively connected to a common voltage line; A gate driver for supplying the scan signal; A data driver for supplying a pixel driving signal to each of the plurality of data lines corresponding to each of the gate lines to charge a voltage of the pixel driving signal into the capacitors; And The enable pulse width of the high logic is gradually increased from the time when the gate start pulse is enabled to the high logic once every frame period to the time when the gate start pulse is enabled again in the next frame period from the time when the gate start pulse is enabled And a timing controller for generating a gate shift clock signal, Wherein the scan signal has a pulse width that is synchronized with the gate shift clock and is enabled to the high logic for a gradually longer period from the gate line closer to the data driver to the data driver and the far gate line, Wherein an output time of the pixel driving signal supplied to each of the capacitors corresponding to each of the gate lines gradually becomes longer toward a gate line closer to the data driver and a gate line closer to the data driver. The method according to claim 1, Further comprising a rate converter for rapidly changing a transmission rate of pixel data to be supplied to the data driver. The method according to claim 1, The pulse width of the scan signal that is enabled to go from the gate line closer to the data driver to the data line and the far gate line becomes longer, Wherein an output time of the pixel driving signal supplied to each of the capacitors corresponding to each of the gate lines is linearly longer in a gate line closer to the data driver from the data driver to a far gate line. The method according to claim 1, The pulse width of the scan signal which is enabled in the gate line closer to the data driver to the data driver and the far gate line becomes longer in the form of an exponential function, Wherein the output time of the pixel driving signal supplied to each of the capacitors corresponding to each of the gate lines is a flat display state in which the output time of the pixel driving signal from the data driver to the data driver and the distant gate line becomes longer in the form of an exponential function Device. The method according to claim 1, Wherein an enable period of the gate line is varied within a range of +/- 40% based on a period of the horizontal synchronizing signal. The method according to claim 1, Wherein the flat panel panel is a liquid crystal panel. A flat panel including pixels connected to a corresponding one of a plurality of data lines and a plurality of gate lines and a corresponding gate line; A plurality of thin film transistors that are turned on by a high logic enabled scan signal on the plurality of gate lines; Capacitors corresponding to each of the thin film transistors and respectively connected to a common voltage line; A gate driver for supplying the scan signal; A data driver for supplying a pixel driving signal to each of the plurality of data lines corresponding to each of the gate lines to charge a voltage of the pixel driving signal into the capacitors; And The enable pulse width of the high logic is gradually increased from the time when the gate start pulse is enabled to the high logic once every frame period to the time when the gate start pulse is enabled again in the next frame period from the time when the gate start pulse is enabled And a timing controller for generating a gate shift clock signal which is delayed by a predetermined time, The scan driver supplies the scan signal having a pulse width that is enabled to the high logic for a gradually longer period to the gate line in the gate line closest to the data driver in synchronization with the gate shift clock step; And And supplying the pixel driving signal to each of the capacitors corresponding to each of the gate lines, the pixel driving signal gradually increasing in output time from the data driver to a distant gate line in a gate line close to the data driver, A method of driving a display device. 8. The method of claim 7, The pulse width of the scan signal that is enabled to go from the gate line closer to the data driver to the data line and the far gate line becomes longer, Wherein the output time of the pixel driving signal supplied to each of the capacitors corresponding to each of the gate lines is linearly longer in a gate line closer to the data driver to the data driver and a farther gate line Driving method. 8. The method of claim 7, The pulse width of the scan signal which is enabled in the gate line closer to the data driver to the data driver and the far gate line becomes longer in the form of an exponential function, Wherein the output time of the pixel driving signal supplied to each of the capacitors corresponding to each of the gate lines is a flat display state in which the output time of the pixel driving signal from the data driver to the data driver and the distant gate line becomes longer in the form of an exponential function A method of driving a device. 8. The method of claim 7, Wherein an enable period of the gate line is varied within a range of +/- 40% based on a period of the horizontal synchronizing signal.

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