JP2017041503A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOSFET which has improved channel mobility and excellent anti-dielectric properties by a novel gate insulation layer which has excellent flatness of a semiconductor/insulation film interface and ensures inhibition of an interface state.SOLUTION: A semiconductor device having a gate insulation layer on a SiC substrate 2 comprises a gate insulation layer of a laminated structure in which an intermediate layer composed of an epitaxial silicon oxynitride film E-SiON3 on the SiC substrate 2 and an insulation layer h-BN4 composed of an insulating layer compound on the intermediate layer are sequentially formed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a structure of a gate insulating film on a SiC substrate, and more particularly to a semiconductor device related to formation of a gate insulating film on an epitaxial SiON and a manufacturing method thereof.

  In recent years, SiC (silicon carbide: silicon carbide) has attracted attention as a substrate material capable of increasing the breakdown voltage of transistors. SiC has a dielectric breakdown strength about 10 times that of Si and GaAs, which are conventional substrate materials. In particular, MOSFETs using SiC can be downsized as much as the breakdown voltage can be maintained. From this, it is expected that the use of SiC as a substrate significantly reduces the ratio of the drift resistance to the on-resistance compared to a conventional element made of a substrate material, and can reduce the energy loss generated during the on-operation. . However, it is known that the on-resistance value of an element using a current SiC substrate is larger than a theoretically expected value. As a cause thereof, in the element using the SiC substrate, the contribution of the channel resistance to the on-resistance is large. Although the element using the current SiC substrate can greatly reduce the drift resistance value by downsizing, the total resistance value is almost equal to that of the conventional element because of the large channel resistance. Therefore, in manufacturing an element using a SiC substrate, it is important to develop a technique for reducing the channel resistance value, specifically, to develop a control method at the semiconductor / insulating film interface when forming the insulating film.

In a MOSFET using a SiC substrate, a thermal oxidation method is generally used as a method for forming a gate insulating film. This thermal oxidation method is a method of forming SiO ₂ as an insulating film on the surface of the SiC substrate by oxidizing the surface of the SiC substrate by heating in an oxidizing gas. Thus, there is an advantage that the insulating film forming process can be simplified and the cost can be reduced. On the other hand, the disadvantage is that it is difficult to control the state at the semiconductor / insulator interface due to the principle of film formation, and the interface irregularities and interface states, which are the main causes of carrier scattering, are not intended during the oxidation process. As a result, it is known that the channel mobility is lowered. In recent years, the post-annealing technology has made it possible to suppress the interface state to some extent, but it is difficult to suppress the interface unevenness as long as the thermal oxidation method is used. Therefore, the channel mobility at the time of using the thermal oxidation method has peaked at about 100 cm ² / Vs at present, and is far from the bulk value of 1000 cm ² / Vs.

WO2012 / 131898

H. Tochihara, T .; Shirawa, Progress In Surface Science 86 (2011) p. 295-327

A deposition method is known as a method for forming a gate insulating film in place of the thermal oxidation method. The deposition method is a method of forming a gate insulating film by depositing an insulating material using a film forming apparatus. The advantages of the deposition method are (1) the state of the semiconductor / gate insulating film interface can be controlled in advance, (2) the film quality of the insulating film is relatively easy to control, and (3) so-called Al ₂ O ₃ and HfO _2. High-k material can also be used. In particular, with respect to (1), it is possible to suppress the generation of interface irregularities and interface states, which are in principle difficult to control with the thermal oxidation method, by applying appropriate pretreatment to the substrate surface. In terms of easy control of the interface state, the deposition method is superior in principle for improving channel mobility. As a prior example of channel mobility improvement by the deposition method, a method of treating the surface of a SiC substrate by nitrogen ion implantation as disclosed in Patent Document 1 has been proposed. However, in this surface treatment method, the surface of the SiC substrate is roughened, and as a result, there is a problem that unevenness of the interface occurs. In addition, this surface treatment method does not sufficiently control the interface state in that the causal relationship between introducing nitrogen into the interface and improving the channel mobility is unknown.

In addition, when a SiO ₂ (silicon oxide) film is formed on a SiC substrate by a method such as CVD, the defect density at the interface between SiC and SiO becomes large. Therefore, the channel mobility becomes one digit or more smaller than Si and SiO. Therefore, an insulating layer having a low defect density is necessary.

  Therefore, regarding the control of the interface state before the gate insulating film deposition for the purpose of improving the channel mobility in the MOSFET including the SiC substrate, the surface of the SiC substrate before the deposition has excellent flatness and no dangling bonds. It is necessary to be formed in a state. Further, it is necessary that the defect density at the interface between the SiC and the insulating film is low.

  Therefore, an object of the present invention is to propose a new structure of a gate oxide film using a SiC substrate, and to provide a MOSFET excellent in channel mobility and insulation resistance.

  The present invention is a semiconductor device having a gate insulating layer on a SiC substrate, wherein the gate insulating layer is formed on the intermediate layer made of an epitaxial silicon oxynitride film formed on the SiC substrate and on the intermediate layer And an insulating layer made of an insulating layered compound.

  The band gap of the insulating layered compound may be 5.9 eV or more.

  As the insulating layered compound, hexagonal boron nitride can be used.

  The film thickness of the insulating layered compound may be 10 nm or more and 100 nm or less.

  As the SiC substrate, a 4H—SiC substrate or a 6H—SiC substrate can be used.

  The off angle in the [11-20] direction of the SiC substrate may be 0 ° or more and 8 ° or less.

  The insulating layered compound can be formed by stacking a plurality of insulating atomic layers having a two-dimensional structure.

  The present invention is a semiconductor device having a MOSFET structure, wherein the MOSFET is an SiC substrate and a gate insulating layer formed on the SiC substrate, and an epitaxial silicon oxynitride formed on the SiC substrate. A gate insulating layer including an intermediate layer made of a film and an insulating layer made of an insulating layered compound formed on the intermediate layer; and a part of the gate insulating layer formed on the upper surface of the SiC substrate. A source region that is in contact, a drain region that is formed on the top surface of the SiC substrate, and that is partially in contact with the gate insulating layer at a position away from the source region, and is electrically connected to the gate insulating layer A gate electrode; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region. That.

  The present invention relates to a method of manufacturing a semiconductor device having a gate insulating layer on a SiC substrate, the step of cleaning the surface of the SiC substrate to planarize the surface, and the step of epitaxial silicon on the SiC substrate. A step of forming an intermediate layer made of an oxynitride film, and a step of forming an insulating layer made of an insulating layered compound of hexagonal boron nitride on the intermediate layer, the intermediate layer and the insulating layer being It can be configured as a gate insulating layer.

  The present invention is a method of manufacturing a semiconductor device having a MOSFET structure, the step of cleaning the surface of the SiC substrate to planarize the surface, and the step of forming a source region on the upper surface of the SiC substrate And forming a drain region on the upper surface of the SiC substrate at a position away from the source region, and epitaxial silicon on the upper surface of the SiC substrate at a position partially in contact with the source region and the drain region. A step of forming an intermediate layer made of an oxynitride film, a step of forming an insulating layer made of an insulating layered compound of hexagonal boron nitride on the intermediate layer, and an electrical connection on the gate insulating layer Forming a gate electrode; forming a source electrode electrically connected on the source region; and electrically connecting on the drain region And forming a drain electrode, and said insulating layer and the intermediate layer may be configured as a gate insulating layer of the MOSFET.

It is explanatory drawing which shows the structure in the gate insulating layer of the semiconductor device which is the 1st Embodiment of this invention. It is explanatory drawing which shows the example which comprised the semiconductor device as MOSFET. It is a flowchart which shows the manufacturing method which produces the gate insulating layer which is the 2nd Embodiment of this invention. It is explanatory drawing which shows the example which forms h-BN on E-SiON by CVD method. It is explanatory drawing which shows the example which forms h-BN on E-SiON by the transfer method.

[Semiconductor device]
The configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
<Gate insulation layer>
FIG. 1 shows a configuration example of the gate insulating layer 1 of the semiconductor device.

  The gate insulating layer 1 includes an intermediate layer 3 made of an epitaxial silicon oxynitride film (E-SiON) formed on the SiC substrate 2 and an insulating layer 4 made of an insulating layered compound formed on the intermediate layer 3. Including.

Hereinafter, the configuration of each unit will be described.
(SiC substrate)
The SiC substrate 2 has a sufficiently flat surface, and for example, a 4H—SiC substrate or a 6H—SiC substrate can be used. In this case, the off angle in the [11-20] direction of the SiC substrate 2 may be 0 ° or more and 8 ° or less. The off angle is an angle of the surface of the SiC substrate with respect to the (0001) plane of SiC.
(E-SiON)
The epitaxial silicon oxynitride film (E-SiON) constituting the intermediate layer 3 is epitaxially grown on the surface of the SiC substrate 2 having sufficient flatness such as a 4H—SiC substrate or a 6H—SiC substrate. The E-SiON is an extremely thin insulating film having a thickness of about 0.6 nm.

  The E-SiON is composed of silicon, oxygen, and nitrogen in a composition ratio of 4: 5: 3, respectively. In addition, while general SiON (silicon oxynitride) has an amorphous structure, the E-SiON has a laminated structure of a silicon nitride monoatomic layer and a silicon oxide monoatomic layer (heteromonoatomic double layer structure). It is a crystalline thin film. The E-SiON is ideal as a surface state before the gate insulating film is deposited on the SiC substrate 2 because there is no dangling bond due to its structure. The E-SiON is a film epitaxially grown on the SiC substrate, and the film itself has few defects. Furthermore, the defect density at the interface between SiC and the E-SiON can also be lowered. Note that when a general amorphous SiON (silicon oxynitride) is formed on a SiC substrate, the defect density at the interface is high and the channel mobility is low.

  Since E-SiON has a band gap of about 8 eV, it can be used as a buffer layer before the insulating layer 4 is deposited. Therefore, in the process of depositing the insulating layer 4, by forming E-SiON before depositing the insulating layer 4, a semiconductor / insulator interface with a flat and suppressed interface state can be formed. Moreover, the point which can form in nitrogen heating is also preferable at the point of simplicity. However, since the film thickness of the E-SiON is very thin, this alone causes problems peculiar to SiON such as dielectric breakdown and leakage current, which is insufficient as a structure of the gate insulating layer of the MOSFET. .

The identification of E-SiON is confirmed by a √3 × √3 spot in the LEED diffraction image of the substrate surface, and the diffraction intensity VS electron beam energy curve for the √3 × √3 spot. The curve indicating the peak of (IV curve) is applied to the energy position of the maximum value of the theoretical curve of E-SiON. Preferably, the Pendry Rfactor (R _p ) is 0.3 or less. The Pendry Rfactor (R _p ) is an index quantifying the degree of coincidence of the maximum energy positions between the two curves, and has a property that the value becomes smaller as the degree of coincidence becomes better.

(Insulating layered compound: h-BN)
As the insulating layered compound constituting the insulating layer 4, hexagonal boron nitride (h-BN) can be used. The band gap of the insulating layered compound is 5.9 eV or more. The film thickness of the insulating layered compound is 10 nm or more and 100 nm or less.

  The insulating layered compound is a compound in which insulating monoatomic layers having a two-dimensional structure (sheet-like structure) are stacked as two or more layers while maintaining a constant distance from each other. . Each monoatomic layer has no dangling bonds on its surface and the insulating layered compound is chemically inert. The insulating layered compound is a substance in which the monoatomic layers are bonded together by van der Waals force to form the whole.

  Normally, in order to deposit an insulating film on a SiC substrate, atoms on the surface of the SiC substrate must react with source atoms of the deposited film to form a bond, but the surface of E-SiON has a chemical surface. Due to the mechanically inactive structure, there is a problem that the film is not attached by the film formation according to the normal principle, or the high quality of the deposited film is difficult. That is, it is difficult to form a normal film such as SiO or SiN on E-SiON. This is considered that a film having a dangling bond on a chemically inactive film is difficult to grow. Therefore, an insulating layered compound formed by laminating an originally inactive atomic layer is used as an insulating film material. This makes it possible to form a deposited film by physical adsorption caused by van der Waals force even on an inert surface such as E-SiON. Further, by using the insulating layered compound, in principle, the film can be formed with little damage to the E-SiON, so that the gate insulating layer 1 can be formed without destroying the structure of the E-SiON. It becomes possible.

  In addition, even if it tried to form the said h-BN in a SiC substrate or SiO layer, adhesiveness was not acquired and the characteristic of the said h-BN was not acquired as knowledge. This is probably because the surface of the SiC substrate or the SiO layer has dangling bonds, and h-BN having no dangling bonds cannot be stably grown.

<MOSFET>
FIG. 2 shows an example in which the semiconductor device is configured as a MOSFET 10.

  MOSFET 10 is formed on SiC substrate 2, gate insulating layer 1 shown in FIG. 1 above, source region 11 formed on the upper surface of SiC substrate 2, a part of which contacts gate insulating layer 1, and on the upper surface of SiC substrate 2. The drain region 12 is in contact with the gate insulating layer 1 at a position away from the source region 11, the gate electrode 13 is electrically connected to the gate insulating layer 1, and is electrically connected to the source region 11. And a drain electrode 15 electrically connected to the drain region 12.

The SiC substrate 2 is n-type SiC, and a low-concentration P-type layer (p ⁻ ) is epitaxially grown thereon. The source region 11 and the drain region 12 are epitaxially grown high concentration n-type layers (n ⁺ ).

In the case of a MOSFET using the SiC substrate 2, since the band gap of 4H—SiC is 3.26 eV, a gate insulating film of 5 eV or more is generally required as the gate insulating layer 1. Currently, HfO ₂ has been studied as an insulating film material for the SiC substrate 2, which has a band gap of 5.8 eV, and therefore a band gap required for the gate insulating film. In order to ensure the reliability, it is preferable that it is at least this value or more.

  A typical example of the substance having a band gap of 5.8 eV or more in the insulating layered compound in the present invention is hexagonal boron nitride (h-BN). Since h-BN has a band gap of 5.9 eV, it is an insulating layered compound that can be used as the gate insulating film of the SiC substrate 2.

  As described above, a laminated structure composed of E-SiON (intermediate layer 3) formed on SiC substrate 2 and h-BN (insulating layered compound: insulating layer 4) formed on E-SiON; Therefore, it is possible to newly form the gate insulating layer 1 that has no damage to the SiON, has a low defect density at the semiconductor / insulating film interface, and is excellent in flatness and interface state suppression. Thus, a MOSFET having excellent insulation resistance can be manufactured.

[Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.

<Manufacturing method of gate insulating layer>
First, a method for manufacturing the gate insulating layer will be described.

  FIG. 3 shows a flowchart of a method for producing the gate insulating layer 1 of FIG.

  In step S1, the surface of the SiC substrate 2 is cleaned, and the surface of the SiC substrate 2 is planarized.

  In step S2, intermediate layer 3 made of an epitaxial silicon oxynitride film (E-SiON) is formed on SiC substrate 2.

  In step S3, an insulating layer 4 made of an insulating layered compound of hexagonal boron nitride (h-BN) is formed on E-SiON that is the intermediate layer 3.

  Hereinafter, a method for forming h-BN on E-SiON will be described using h-BN as a representative example. The CVD method and the transfer method will be described as the forming method.

<Production method 1: CVD method>
First, the CVD method will be described as production method 1.

  FIG. 4 is a schematic diagram showing an example in which h-BN is directly formed on E-SiON using a thermal CVD method. The SiC substrate 2 on which E-SiON is formed is heated at about 1000 ° C. in the heating furnace 20, and h-BN is formed on the E-SiON by thermal decomposition of the raw material gas supplied to the heating furnace 20. .

  In the CVD method, the film thickness can be controlled by increasing or decreasing the film formation time. Regarding the raw material, diborane can be used as the boron raw material, and ammonia or hydrazine can be used as the nitrogen raw material. In addition, compounds containing both boron atoms and nitrogen atoms such as borazine and ammonia borane may be used as a raw material. In addition to thermal CVD, film formation using plasma CVD is also possible.

  Hereinafter, Production Examples 1 to 4 and Comparative Examples will be described as specific production examples of the gate insulating layer 1 by the CVD method.

(Production Example 1)
First, step S1 will be described.

The SiC substrate 2 was a 4H—SiC having a thickness of 430 μm cut into 10 mm square, an off angle of 4 °, and a Si surface substrate. The SiC substrate 2 was subjected to ultrasonic cleaning with an organic solvent and pure water for 10 minutes each to remove surface impurities. Next, the cleaned SiC substrate 2 was placed on a graphite susceptor 21 installed in a horizontal heating furnace 20 and evacuated until the in-furnace vacuum was 10 ⁻³ Pa. After evacuation, hydrogen gas was introduced into the furnace until atmospheric pressure was reached, and the surface of SiC substrate 2 was planarized by heating at a flow rate of 1000 sccm and a temperature of 1400 ° C. for 20 minutes. After heating, the substrate was cooled for 15 minutes until the substrate temperature reached room temperature, and then the introduction of hydrogen gas was stopped, and evacuation was performed until the degree of vacuum in the furnace became 10 ⁻³ Pa. In addition, the said temperature can be performed at 1400 degreeC or more and 1600 degrees C or less.

  The planarization process for the surface of SiC substrate 2 will be described.

  As a method of planarizing the SiC substrate 2 before growing E-SiON, generally, a method of forming a facet surface including an epitaxial thin film on the step-terrace structure of the SiC substrate 2, There is a method of smoothing the unevenness of the step-terrace structure. In this example, the substrate surface state of the SiC substrate 2 before the growth of E-SiON is a unit half height (0.5 nm at 4H, 0.75 nm at 6H) or a unit height (1.0 nm at 4H). , 6H, 1.5 nm) step-terrace structure is preferably formed with a uniform terrace width. In addition, about the board | substrate, it does not ask | require the presence or absence of epitaxial film formation or the presence or absence of doping.

  Next, step S2 will be described.

  Then, nitrogen gas was introduced into the furnace until atmospheric pressure was reached, and heating was performed at a flow rate of 1000 sccm and a temperature of 1400 ° C. for 20 minutes, thereby forming E-SiON with a thickness of 0.6 nm on the SiC substrate 2. Note that oxygen may remain in the furnace. After heating, the substrate was cooled for 15 minutes until the substrate temperature reached room temperature, and then the introduction of nitrogen gas was stopped, the heating furnace was opened to the atmosphere, and the sample was taken out. In addition, the said temperature can be performed at 1300 to 1500 degreeC. More preferably, it is 1400 degreeC. When the temperature is 1300 ° C. or lower, surface nitriding does not proceed, and when the temperature is 1500 ° C. or higher, surface roughness occurs.

  Next, step S3 will be described.

Subsequently, the prepared sample was transported onto a susceptor in another horizontal tube furnace of the same type. After conveyance, vacuuming was performed until the degree of vacuum in the furnace reached 10 ⁻³ Pa, and then hydrogen was flowed at 500 sccm as a carrier gas, and ammonia borane as a raw material was sublimated by heating to 100 ° C. and supplied. Then, by raising the temperature to 1000 ° C. under atmospheric pressure and heating for 30 minutes, h-BN was grown to a thickness of 50 nm on the E-SiON. After heating, after cooling for 15 minutes until the substrate temperature reaches room temperature, the introduction of gas is stopped, vacuuming is performed until the degree of vacuum in the furnace reaches 10 ⁻³ Pa, and then the inside of the furnace is vented with outside air. A sample was removed. In addition, the said temperature can be performed at 900 to 1100 degreeC. More preferably, it is 1000 degreeC. When the temperature is 900 ° C. or lower, the film quality of h-BN is poor, and when it is 1100 ° C. or higher, the uniformity of the film thickness is lost.

(Production Example 2)
In the process of Step S3 of Production Example 1, the film thickness of h-BN was set to 100 nm by changing the heating time of h-BN growth to 60 minutes. Other than that, it produced in the same process.

(Production Example 3)
In the process of Step S1 of Production Example 1, the polytype of the SiC substrate 2 was changed to a 6H—SiC substrate. Other than that, it produced in the same process.

(Production Example 4)
In the process of Step S1 of Production Example 1, the off angles in the [11-20] direction of the SiC substrate were changed to 0 °, 8 °, and 12 °. Other than that, it produced in the same process.

(Comparative example)
In the process of Step S3 of Production Example 1, the film formation of h-BN was changed to the film formation of Al ₂ O ₃ by sputtering. Hereinafter, the sputtering process will be described.

First, E-SiON produced in the step S2 of Production Example 1 is placed on a pedestal installed in a helicon type high-frequency magnetron sputtering apparatus, and evacuated to 10 ^-3 Pa. 10 sccm of gas and 1 sccm of oxygen gas were introduced into the chamber. Then, after adjusting the pressure in the chamber to 1 Pa, aluminum was sputtered onto the E-SiON with a cathode power of 150 W for 2 minutes to form Al ₂ O ₃ having a thickness of 50 nm.

  When sputtering, which is a conventional method, is used, atoms need to collide with the substrate surface of the SiC substrate 2 with high energy due to the principle of sputtering, so the structure of ultrathin SiON is destroyed at the initial stage of deposition. There is a problem. Therefore, in the deposition of the gate insulating film on the E-SiON that is the intermediate layer 3, it is required to realize the formation of the insulating layer 4 that does not destroy the E-SiON as shown in Step S3 of FIG.

<Evaluation of manufacturing method 1>
Next, the samples produced in Production Examples 1 to 4 and the Comparative Example are evaluated.

  As an evaluation method. In a cross-sectional photographic image taken using a TEM (transmission electron microscope), it was confirmed whether or not E-SiON was damaged at the SiC / insulating film interface. By this evaluation, the defect density of the interface can be qualitatively evaluated. That is, it can be said that what can be confirmed to be damaged has many defects at the interface, and the defect density is high. Hereinafter, the evaluation results will be described.

  Table 1 summarizes the influence of the deposition method on the SiC / insulating film interface.

Specifically, it is the result of evaluating the presence or absence of damage of E-SiON at the interface of two samples of h-BN produced in Production Example 1 and Al ₂ O ₃ produced in Comparative Example. Thereby, it was confirmed that the E-SiON structure was maintained for the sample on which h-BN was formed, and that the E-SiON was damaged for the sample on which Al ₂ O ₃ was formed.

  Table 2 summarizes the influence of the film thickness of h-BN on the SiC / insulating film interface after the film formation of h-BN.

  Specifically, it is the result of confirming the presence or absence of damage of E-SiON at the interface of the two samples with the film thicknesses of 50 nm and 100 nm of h-BN produced in Production Example 1 and Production Example 2. Thereby, it was confirmed that the structure of E-SiON was maintained in any sample.

  Table 3 summarizes the influence of the substrate polytype on the SiC / insulating film interface after h-BN film formation.

  Specifically, it is the result of evaluating the presence or absence of damage of E-SiON in two samples of 4H—SiC and 6H—SiC manufactured in Preparation Example 1 and Preparation Example 3. This confirmed that the SiON structure was maintained in all samples.

  Table 4 summarizes the effect of the off angle in the [11-20] direction of the substrate on the SiC / insulating film interface after the h-BN film is formed.

  Specifically, the results are obtained by evaluating the interface states of the samples with the off angles of 0 °, 4 °, 8 °, and 12 ° prepared in Production Example 1 and Production Example 3, respectively. As a result, it was confirmed that the SiON structure was maintained in the samples having off angles of 0 °, 4 °, and 8 °, and that the E-SiON was damaged in the 12 ° samples.

<Production method 2: Transfer method>
Next, as the production method 2, a transfer method will be described.

  5A to 5D show a manufacturing method in which h-BN is formed on E-SiON using a transfer method.

  In FIG. 5A, the transfer film 32 is pressed against the h-BN 31 formed on the appropriate h-BN transfer substrate 30.

  In FIG. 5B, the h-BN 31 is peeled from the h-BN transfer substrate 30.

  In FIG.5 (c), E-SiON33 is stuck to the SiC substrate 34 previously formed separately. The SiC substrate 34 having the E-SiON 33 prepared in advance corresponds to the substrate at the time when the step S2 in FIG. 3 is completed. In this case, it is desirable that impurities are sufficiently removed from the surface of E-SiON 33 before transfer.

  In FIG. 5D, the transfer film 32 is removed using organic cleaning or the like.

<Manufacturing method of MOSFET>
Next, a method for manufacturing the MOSFET shown in FIG. 3 will be described.

First, a low-concentration p layer (p ⁻ ) is epitaxially grown on the n-type SiC substrate 2. Next, a mask material for ion implantation is patterned on the p layer, and a high concentration n well layer (n ⁺ ) is formed by ion implantation as the formation of the source region 11 and the drain region 12. Next, after removing the mask material, activation annealing of the n-well layer is performed. Next, the surface of the SiC substrate 2 after the activation annealing. Surface processing is performed by CMP (chemical mechanical polishing). Thereby, the step bunching of the surface generated by the activation annealing is removed, and the surface of the SiC substrate 2 is flattened.

After that, the following processing is performed according to step S1 to step S3 of FIG.
In the step-terrace structure on the surface of the SiC substrate 2 after the source region 11 and the drain region 12 are formed, planarization treatment by hydrogen heating is performed. Next, E-SiON (intermediate layer 3) is formed on the SiC substrate 2 by epitaxial growth by heating with nitrogen. Next, h-BN (insulating layer 4) is formed on E-SiON by epitaxial growth. Next, a dry etching mask material is patterned on h-BN. Next, only the gate insulating layer 1 (E-SiON and h-BN) on the surface of the well layer is dry-etched. Next, the mask material is removed. Finally, the source electrode 14 and the drain electrode 15 are formed on the source region 11 and the drain region 12, respectively, and the gate electrode 13 is formed on the gate insulating layer 1.

  As described above, since the gate insulating layer 1 having a laminated structure in which E-SiON is formed on the SiC substrate 2 and h-BN is formed on the E-SiON is created, there is no damage to the SiON and defects The gate insulating layer 1 excellent in the flatness of the semiconductor / insulating film interface having a low density and in suppressing the interface state can be formed, whereby a MOSFET with improved channel mobility and excellent insulation resistance is manufactured. be able to.

1 Gate insulating layer 2 SiC substrate 3 Intermediate layer (E-SiON)
4 Insulating layer (insulating layered compound, h-BN)
10 MOSFET
11 Source region 12 Drain region 13 Gate electrode 14 Source electrode 15 Drain electrode 20 Heating furnace 21 Susceptor 30 h-BN transfer substrate 31 h-BN
32 Transfer film 33 E-SiON
34 SiC substrate

Claims (10)

A semiconductor device having a gate insulating layer on a SiC substrate,
The gate insulating layer is
An intermediate layer made of an epitaxial silicon oxynitride film formed on the SiC substrate;
A semiconductor device comprising: an insulating layer made of an insulating layered compound formed on the intermediate layer.   The semiconductor device according to claim 1, wherein a band gap of the insulating layered compound is 5.9 eV or more.   The semiconductor device according to claim 1, wherein the insulating layered compound is hexagonal boron nitride.   4. The semiconductor device according to claim 1, wherein a film thickness of the insulating layered compound is 10 nm or more and 100 nm or less.   The semiconductor device according to claim 1, wherein a 4H—SiC substrate or a 6H—SiC substrate is used as the SiC substrate.   The semiconductor device according to claim 1, wherein an off angle of the SiC substrate in a [11-20] direction is 0 ° or more and 8 ° or less.   The semiconductor device according to claim 1, wherein the insulating layered compound is formed by stacking a plurality of insulating atomic layers having a two-dimensional structure. A semiconductor device having a MOSFET structure,
The MOSFET is
A SiC substrate;
A gate insulating layer formed on the SiC substrate, an intermediate layer made of an epitaxial silicon oxynitride film formed on the SiC substrate, and an insulating layer made of an insulating layered compound formed on the intermediate layer The gate insulating layer comprising:
A source region formed on an upper surface of the SiC substrate and partially in contact with the gate insulating layer;
A drain region formed on an upper surface of the SiC substrate, a part of which is in contact with the gate insulating layer at a position away from the source region;
A gate electrode electrically connected to the gate insulating layer;
A source electrode electrically connected to the source region;
A semiconductor device comprising: a drain electrode electrically connected to the drain region. A method of manufacturing a semiconductor device having a gate insulating layer on a SiC substrate,
Cleaning the surface of the SiC substrate and planarizing the surface;
Forming an intermediate layer made of an epitaxial silicon oxynitride film on the SiC substrate;
Forming an insulating layer made of an insulating layered compound of hexagonal boron nitride on the intermediate layer,
A method of manufacturing a semiconductor device, wherein the intermediate layer and the insulating layer are configured as the gate insulating layer. A method of manufacturing a semiconductor device having a MOSFET structure,
Cleaning the surface of the SiC substrate and planarizing the surface;
Forming a source region on the upper surface of the SiC substrate;
Forming a drain region on the upper surface of the SiC substrate at a position away from the source region;
Forming an intermediate layer made of an epitaxial silicon oxynitride film on the upper surface of the SiC substrate at a portion of which is in contact with the source region and the drain region;
Forming an insulating layer made of an insulating layered compound of hexagonal boron nitride on the intermediate layer;
Forming a gate electrode electrically connected to the gate insulating layer;
Forming a source electrode electrically connected to the source region;
Forming a drain electrode electrically connected to the drain region,
A method of manufacturing a semiconductor device, wherein the intermediate layer and the insulating layer are configured as a gate insulating layer of the MOSFET.