JP2017037873A - Semiconductor light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element in which luminous efficiency can be improved.SOLUTION: According to an embodiment, a semiconductor light emitting element includes first and second semiconductor layers, first and second well layers and first and second barrier layers. The first well layer is provided between the first and second semiconductor layers and includes InGaN(0<w1<1). The second well layer is provided between the first well layer and the second semiconductor layer and includes InGaN(0<w2<1). The firs barrier layer is provided between the first semiconductor layer and the first well layer and includes a high Al concentration region which contacts the first well layer and includes AlGaN(0<x1<1) and a low Al concentration region which contacts the high Al concentration region between the high Al concentration region and the first semiconductor layer and includes AlGaN(0≤y1<x1). The second barrier layer is provided between the first and second well layers and contacts the second well layer and includes AlGaN(0≤z2<x1).SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  For example, there is a semiconductor light emitting element (for example, a light emitting diode) using a nitride semiconductor. In semiconductor light emitting devices, improvement in light emission efficiency is required.

JP2012-114328A

  Embodiments of the present invention provide a semiconductor light emitting device capable of improving luminous efficiency.

According to an embodiment of the present invention, a semiconductor light emitting device includes a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer, a first well layer, a second well layer, and a first conductivity type. A barrier layer and a second barrier layer are included. The first well layer is provided between the first semiconductor layer and the second semiconductor layer and includes In _w1 Ga _1-w1 N (0 <w1 <1). The second well layer is provided between the first well layer and the second semiconductor layer, and includes _{Inw2Ga1 -w2N} (0 <w2 <1). The first barrier layer is provided between the first semiconductor layer and the first well layer. The first barrier layer is in contact with the first well layer and includes a high Al concentration region including Al _x1 Ga _1-x1 N (0 <x1 <1), and between the high Al concentration region and the first semiconductor layer. And a low Al concentration region containing Al _y1 Ga _1-y1 N (0 ≦ y1 <x1) in contact with the high Al concentration region. The second barrier layer is provided between the first well layer and the second well layer, is in contact with the first well layer and the second well layer, and Al _z2 Ga _{1 -z2} N (0 ≦ z2 <x1). )including.

FIG. 1A and FIG. 1B are schematic cross-sectional views illustrating the semiconductor light emitting element according to the embodiment. 2A and 2B are schematic cross-sectional views illustrating a semiconductor light emitting element of a reference example. FIG. 3A to FIG. 3F are schematic views illustrating semiconductor light emitting elements. FIG. 4A to FIG. 4C are schematic views illustrating semiconductor light emitting elements. FIG. 5A and FIG. 5B are graphs illustrating characteristics of the semiconductor light emitting device. 6A and 6B are graphs illustrating characteristics of the semiconductor light emitting device. FIG. 7 is a schematic cross-sectional view illustrating another semiconductor light emitting element according to the embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(Embodiment)
FIG. 1A and FIG. 1B are schematic cross-sectional views illustrating the semiconductor light emitting element according to the embodiment.
As shown in FIG. 1A, the semiconductor light emitting device 110 according to the embodiment includes a first semiconductor layer 10, a second semiconductor layer 20, a first well layer WL1, a second well layer WL2, and a first well layer. The barrier layer BL1 and the second barrier layer BL2 are included.

  The first semiconductor layer 10 is the first conductivity type. The second semiconductor layer 20 is of the second conductivity type. The first conductivity type is n-type. The second conductivity type is p-type. A direction from the first semiconductor layer 10 toward the second semiconductor layer 20 is defined as a Z-axis direction (first direction). For example, an n-type nitride semiconductor (for example, n-type GaN) is used for the first semiconductor layer 10. For example, a p-type nitride semiconductor (for example, p-type GaN) is used for the second semiconductor layer 20. The second semiconductor layer 20 may include a nitride semiconductor containing Al (for example, p-type AlGaN).

The first well layer WL <b> 1 is provided between the first semiconductor layer 10 and the second semiconductor layer 20. The first well layer WL1 includes In _w1 Ga _1-w1 N (0 <w1 <1).

The second well layer WL2 is provided between the first well layer WL1 and the second semiconductor layer 20. The second well layer WL2 includes _{Inw2Ga1 -w2N} (0 <w2 <1).

  The first barrier layer BL1 is provided between the first semiconductor layer 10 and the first well layer WL1. The first barrier layer BL1 is in contact with the first well layer WL1. The first barrier layer BL1 includes a high Al concentration region 31x and a low Al concentration region 31y.

The high Al concentration region 31x is in contact with the first well layer WL1. The high Al concentration region 31x includes Al _x1 Ga _1-x1 N (0 <x1 <1).

The low Al concentration region 31 y is in contact with the high Al concentration region 31 x between the high Al concentration region 31 x and the first semiconductor layer 10. The low Al concentration region 31y includes Al _y1 Ga _1-y1 N (0 ≦ y1 <x1).

The second barrier layer BL2 is provided between the first well layer WL1 and the second well layer WL2, and is in contact with the first well layer WL1 and the second well layer WL2. The second barrier layer BL2 includes In _{z2Ga1 -z2N} (0 ≦ z2 <x1).

  The first well layer WL1 includes InGaN. The second well layer WL2 includes InGaN. The high Al concentration region 31x of the first barrier layer BL1 includes AlGaN. The low Al concentration region 31y of the first barrier layer BL1 includes, for example, GaN. The second barrier layer BL2 includes, for example, GaN.

  In the semiconductor light emitting device 110, for example, along the direction from the first semiconductor layer 10 to the second semiconductor layer 20, for example, a GaN layer (low Al concentration region 31y), an AlGaN layer (high Al concentration region 31x), an InGaN layer ( The first well layer WL1), the GaN layer (second barrier layer BL2), and the InGaN layer (second well layer WL2) are provided in contact with each other in this order.

  In the semiconductor light emitting device 110, the light emitting unit 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20. The well layer and the barrier layer are included in the light emitting unit 30. The light emitting unit 30 includes a plurality of well layers 32 and a plurality of barrier layers 31. The plurality of well layers 32 and the plurality of barrier layers 31 are alternately arranged along the Z-axis direction.

  One of the plurality of well layers 32 and one of the plurality of barrier layers 31 are taken as one pair. The one of the plurality of barrier layers 31 includes one of the plurality of well layers 32, the one of the plurality of well layers 32, the first semiconductor layer 10, and the first semiconductor layer 10. Touch.

  In the semiconductor light emitting device 110, the barrier layer 31 included in the pair close to the first semiconductor layer 10 among the plurality of pairs includes the high Al concentration region 31x. The barrier layer 31 included in the pair close to the second semiconductor layer 20 among the plurality of pairs does not include the high Al concentration region 31x.

  For example, in this example, the third barrier layer BL3 is provided as a pair close to the second semiconductor layer 20 among the plurality of pairs. The third barrier layer BL3 includes the low Al concentration region 31y and does not include the high Al concentration region 31x.

  That is, the semiconductor light emitting device 110 further includes a third well layer WL3 and a third barrier layer BL3.

The third well layer WL3 is provided between the second well layer WL2 and the second semiconductor layer 20. The third well layer WL3 includes _{Inw3Ga1 -w3N} (0 <w3 <1). The third well layer WL3 includes, for example, InGaN.

The third barrier layer BL3 is provided between the second well layer WL2 and the third well layer WL3, and is in contact with the second well layer WL2 and the third well layer WL2. The third barrier layer BL3 includes Al _z3 Ga _1-z3 N (0 ≦ z3 <x1). The third barrier layer BL3 includes, for example, GaN.

  In the embodiment, a fourth well layer and a fourth barrier layer may be further provided. The fourth well layer is provided between the third well layer WL3 and the second semiconductor layer 20. The fourth well layer includes, for example, InGaN. The fourth barrier layer is provided between the third well layer WL3 and the fourth well layer, and is in contact with the third well layer WL3 and the fourth well layer. The fourth barrier layer includes, for example, GaN. As will be described later, in the embodiment, the number of well layers 32 provided between the first well layer WL1 and the second semiconductor layer 20 is preferably one or two.

In the embodiment, a barrier layer 31 (p-side barrier layer BLp) may be provided between the second semiconductor layer 20 and the well layer 32 closest to the second semiconductor layer 20 among the plurality of well layers 32. . The p-side barrier layer BLp is, for example, a low Al concentration region 31y. That is, the semiconductor light emitting device 110 further includes the p-side barrier layer BLp. The p-side barrier layer BLp is provided between the third well layer WL3 and the second semiconductor layer 20. The p-side barrier layer BLp includes Al _zp Ga _1-zp N (0 ≦ zp <x1). The p-side barrier layer BLp includes, for example, GaN.

  On the other hand, in the semiconductor light emitting device 110, another well layer 32 is provided between the first well layer WL <b> 1 and the first semiconductor layer 10. This other well layer 32 is referred to as an n-side well layer WLn. An n-side barrier layer BLn is provided. The n-side barrier layer BLn forms a pair with the n-side well layer WLn.

That is, the semiconductor light emitting device 110 further includes an n-side well layer WLn and an n-side barrier layer BLn. The n-side well layer WLn is provided between the first semiconductor layer 10 and the first well layer WL1. The n-side well layer WLn includes In _wn Ga _1-wn N (0 <wn <1).

  The n-side barrier layer BLn is provided between the first semiconductor layer 10 and the n-side well layer WLn. The n-side barrier layer BLn is in contact with the n-side well layer WLn.

The n-side barrier layer BLn includes an n-side high Al concentration region 31xn and an n-side low Al concentration region 31yn. The n-side high Al concentration region 31xn is in contact with the n-side well layer WLn. The n-side high Al concentration region 31xn includes Al _xn Ga _1-xn N (0 <xn <1). The n-side high Al concentration region 31xn includes, for example, AlGaN.

The n-side low Al concentration region 31yn is in contact with the n-side high Al concentration region 31xn between the n-side high Al concentration region 31xn and the first semiconductor layer 10. The n-side low Al concentration region 31yn includes Al _yn Ga _1-yn N (0 ≦ yn <xn). The n-side low Al concentration region 31yn includes, for example, GaN.

  The n-side well layer WLn is in contact with the first barrier layer BL1.

  In this example, a plurality of n-side well layers WLn are provided, and a plurality of n-side barrier layers BLn are provided. The plurality of n-side well layers WLn and the plurality of n-side barrier layers BLn are alternately arranged along the direction from the first semiconductor layer 10 toward the second semiconductor layer 20 (Z-axis direction).

  In this example, the number of the plurality of n-side well layers WLn is five. In the embodiment, this number is preferably 3 or more and 9 or less.

  In this example, all of the plurality of n-side barrier layers BLn include an n-side high Al concentration region 31xn and an n-side low Al concentration region 31yn. In the embodiment, at least one of the plurality of n-side barrier layers BLn may include an n-side high Al concentration region 31xn and an n-side low Al concentration region 31yn. At least one of the plurality of n-side barrier layers BLn may include the n-side low Al concentration region 31yn and may not include the n-side high Al concentration region 31xn. That is, at least one of the plurality of n-side barrier layers BLn may include an AlGaN layer and a GaN layer. At least one of the plurality of n-side barrier layers BLn does not include an AlGaN layer and may include a GaN layer.

  The semiconductor light emitting device 110 can be manufactured, for example, by forming a semiconductor crystal layer on a substrate.

FIG. 1B shows an example of manufacturing the semiconductor light emitting device 110.
As shown in FIG. 1B, a substrate 50s is prepared. The substrate 50s is, for example, a silicon substrate. The plane orientation of the silicon substrate is, for example, the (111) plane. In the embodiment, the plane orientation is arbitrary.

  A buffer layer 50 is provided on the substrate 50s. In this example, the low impurity concentration layer 10 i is provided on the buffer layer 50. The first semiconductor layer 10, the light emitting unit 30, and the second semiconductor layer 20 are provided in this order on the low impurity concentration layer 10i. The impurity concentration in the low impurity concentration layer 10 i is lower than the impurity concentration in the first semiconductor layer 10. For example, undoped GaN is used for the low impurity concentration layer 10i. The low impurity concentration layer 10i may be provided as necessary and may be omitted. These layers are formed on the substrate 50s by epitaxial growth.

  The buffer layer 50 includes, for example, an AlN layer 51, an AlGaN buffer layer 52, a low Al composition layer 53, and a high Al composition layer 54.

  The AlN layer 51 is provided on the substrate 50s. The AlN layer 51 is a high-temperature grown AlN layer. By providing the AlN layer 51, the reaction between the layer thereon and the substrate 50s (for example, a silicon substrate) is suppressed.

  An AlGaN buffer layer 52 is provided on the AlN layer 51. A low Al composition layer 53 is provided on the AlGaN buffer layer 52. A high Al composition layer 54 is provided on the low Al composition layer 53. In this example, a plurality of combinations of the low Al composition layer 53 and the high Al composition layer 54 are provided. For example, an excessive stress may be applied to the nitride semiconductor layer due to a difference in thermal expansion coefficient between the substrate 50s (for example, a silicon substrate) and the nitride semiconductor layer. For example, this stress is adjusted by the combination of the low Al composition layer 53 and the high Al composition layer 54. The high Al composition layer 54 may have a stacked structure of, for example, an AlGaN region and an AlN region. This AlN region is grown at a low temperature.

  The low impurity concentration layer 10i is formed on the buffer layer 50, and the first semiconductor layer 10, the light emitting unit 30, and the second semiconductor layer 20 are formed on the buffer layer 50 in this order, so that the semiconductor light emitting device 110 is formed. can get. When a voltage is applied between the electrode electrically connected to the first semiconductor layer 10 and the electrode electrically connected to the second semiconductor layer 20, a current is supplied to the light emitting unit 30. Light is emitted from the light emitting unit 30. The peak wavelength of the light (emitted light) emitted from the light emitting unit 30 is, for example, not less than 435 nanometers (nm) and not more than 460 nm. The emitted light is, for example, blue.

  As already described, in the semiconductor light emitting device 110, the barrier layer 31 included in the pair close to the first semiconductor layer 10 among the plurality of pairs includes the high Al concentration region 31x. The barrier layer 31 included in the pair close to the second semiconductor layer 20 among the plurality of pairs does not include the high Al concentration region 31x. Thereby, luminous efficiency can be improved.

  Hereinafter, an example of the evaluation result of the characteristics of the semiconductor light emitting device 110 having such a configuration will be described. Hereinafter, sample preparation conditions will be described.

  The buffer layer 50, the low impurity concentration layer 10i, the first semiconductor layer 10, the light emitting unit 30, and the second semiconductor layer 20 are sequentially epitaxially grown on the silicon substrate 50s. The conditions for forming these layers are as follows.

As the buffer layer 50, an AlN layer (AlN layer 51) of 210 nm at 1070 ° C., an Al _0.5 Ga _0.5 N layer (a part of the AlGaN buffer layer 52) of 200 nm at 1050 ° C., an Al _{0. 3} Ga _0.7 N layer (another part of AlGaN buffer layer 52), 350 nm Al _0.15 Ga _0.85 N layer (another part of AlGaN buffer layer 52), and GaN layer ( The low Al composition layer 53) is formed in this order.
If necessary, a high Al composition layer 54 is provided on the GaN layer (low Al composition layer 53). In this example, a plurality of combinations including the low Al composition layer 53 and the high Al composition layer 54 are provided.

  On the buffer layer 50, a GaN layer of 1000 nm is formed at 1060 ° C. as the low impurity concentration layer 10i.

  A Si-doped GaN layer having a thickness of 1000 nm is formed as the first semiconductor layer 10 on the low impurity concentration layer 10 i at 1060 ° C.

  A 4.0 nm GaN layer is formed as the n-side low Al concentration region 31yn that becomes a part of the n-side barrier layer BLn. At this time, the lower layer of 1.0 nm in the GaN layer is formed at 800 ° C., and the upper layer of 3.0 nm in the GaN layer is formed at 850 ° C.

  On the n-side low Al concentration region 31yn, an AlGaN layer of 1.0 nm is formed at 800 ° C. as an n-side high Al concentration region 31xn that is another part of the n-side barrier layer BLn.

  On the n-side barrier layer BLn, a 3.5 nm InGaN layer is formed as a well layer 32 at 800 ° C.

  Five pairs of n-side barrier layer BLn and n-side well layer WLn are formed.

  The first barrier layer BL1 is formed on the uppermost n-side well layer WLn. As a part of the low Al concentration region 31y of the first barrier layer BL1, a 4.0 nm GaN layer is formed. At this time, the lower layer of 1.0 nm in the GaN layer is formed at 800 ° C., and the upper layer of 3.0 nm in the GaN layer is formed at 850 ° C.

  On the low Al concentration region 31y, an AlGaN layer of 1.0 nm is formed at 800 ° C. as another high Al concentration region 31x of another part of the first barrier layer BL1.

  On the first barrier layer BL1, a 3.5 nm InGaN layer is formed at 800 ° C. as the first well layer WL1.

  On the first well layer WL1, a GaN layer of 5.0 nm is formed as the second barrier layer BL2. At this time, the formation of the lower layer of 1.0 nm of the GaN layer is performed at 800 ° C., the formation of the middle layer of 3.5 nm of the GaN layer is performed at 850 ° C. The upper layer of 5 nm is formed at 800 ° C.

  A second well layer WL2 is formed on the second barrier layer BL2. A third barrier layer BL3 is formed on the second well layer WL2. A third well layer WL3 is formed on the third barrier layer BL3. A p-side barrier layer BLp is formed on the third well layer WL3. The conditions for forming the second well layer WL2 and the third well layer WL3 are the same as the conditions for forming the first well layer WL1. The conditions for forming the third barrier layer BL3 and the p-side barrier layer BLp are the same as the conditions for forming the second barrier layer BL2.

  Thereby, the light emission part 30 is formed. A 5 nm Mg-doped AlGaN layer, an 80 nm Mg-doped GaN layer, and a 5 nm Mg-doped GaN contact layer are formed in this order on the light emitting unit 30 as the second semiconductor layer 20. Thereby, the semiconductor light emitting device 110 is obtained.

  In the experiment, the In composition ratio is 0.15 in InGaN to be the well layer 32 (first well layer WL1, second well layer WL2, n-side well layer WLn, etc.).

  The Al composition ratio in the high Al concentration region 31x and the n-side high Al concentration region 31xn is changed to 0.075, 0.15, and 0.3.

  The Al composition ratio in the low Al concentration region 31y and the n-side low Al concentration region 31yn is zero. That is, the low Al concentration region 31y and the n-side low Al concentration region 31yn are GaN layers.

In the experiment, samples of the following reference examples were further prepared.
2A and 2B are schematic cross-sectional views illustrating a semiconductor light emitting element of a reference example.
In the semiconductor light emitting device 119a of the first reference example shown in FIG. 2A, the barrier layer 31 is not provided with the high Al concentration region 31x. The barrier layer 31 has only the low Al concentration region 31y (GaN layer). Except this, it is the same as the semiconductor light emitting device 110.

  In the semiconductor light emitting device 119b of the second reference example shown in FIG. 2B, all the barrier layers 31 are provided with a high Al concentration region 31x and a low Al concentration region 31y (GaN layer). Except this, it is the same as the semiconductor light emitting device 110. That is, in the semiconductor light emitting device 119b, the second barrier layer BL2 and the third barrier layer BL3 of GaN are not provided as compared with the semiconductor light emitting device 110.

FIG. 3A to FIG. 3F are schematic views illustrating semiconductor light emitting elements.
3A to 3C correspond to a sample in which the Al composition ratio x of the high Al concentration region 31x is 0.15 in the semiconductor light emitting device 119b of the second reference example. FIGS. 3A to 3C correspond to a sample in which the Al composition ratio x of the high Al concentration region 31x is 0.3 in the semiconductor light emitting device 119b of the second reference example. 3A and 3D are HAADF-STEM (high angle scattering annular dark field scanning transmission microscope). FIG. 3B and FIG. 3E are TEM-EDX (transmission electron microscope energy dispersive X-ray spectroscopy) and show an In composition distribution. In FIG. 3B and FIG. 3E, In is large in a bright region. FIG. 3C and FIG. 3F are TEM-EDX and show an Al composition distribution. In FIG. 3C and FIG. 3F, there is much Al in the bright region.

FIG. 4A to FIG. 4C are schematic views illustrating semiconductor light emitting elements.
These figures show the evaluation results of the sample using a three-dimensional atom probe. FIG. 4A corresponds to the semiconductor light emitting device 119a. FIG. 4B corresponds to a sample in which the Al composition ratio x of the high Al concentration region 31x is 0.15 in the semiconductor light emitting device 119b. FIG. 4C corresponds to a sample in which the Al composition ratio x of the high Al concentration region 31x is 0.3 in the semiconductor light emitting device 119b. In these drawings, the horizontal axis is the position Pz in the Z-axis direction. The vertical axis represents the In composition ratio CIn or the Al composition ratio CAl.

  As shown in FIG. 4A, a plurality of In peaks are observed in the semiconductor light emitting device 119a. These peaks correspond to the plurality of well layers 32.

  As shown in FIG. 4B, in the semiconductor light emitting device 119b (x = 0.15), in addition to a plurality of In peaks (a plurality of well layers 32), a plurality of Al peaks are observed. The plurality of Al peaks correspond to the high Al concentration region 31x. The height of the plurality of Al peaks corresponds to 0.15.

  As shown in FIG. 4C, also in the semiconductor light emitting device 119b (x = 0.3), a plurality of In peaks (a plurality of well layers 32) and a plurality of Al peaks (a high Al concentration region 31x). ) Is observed. The height of the plurality of Al peaks corresponds to 0.3.

  In this way, an In-containing region (well layer 32) and an Al-containing region (such as a high Al concentration region 31x) are observed by TEM-EDX and a three-dimensional atom probe.

  In the semiconductor light emitting device 110, an Al-containing region (such as a high Al concentration region 31x) is observed in a part of the barrier layer 31 close to the first semiconductor layer 10, and a part of the barrier layer 31 close to the second semiconductor layer 20 is observed. No Al-containing region (such as the high Al concentration region 31x) is not observed.

FIG. 5A and FIG. 5B are graphs illustrating characteristics of the semiconductor light emitting device.
These drawings show measurement results of characteristics of the samples of the semiconductor light emitting device 119a and the semiconductor light emitting device 119b. For the semiconductor light emitting device 119b, the results of three samples having Al composition ratios x of 0.75, 0.15, and 0.3 in the high Al concentration region 31y are shown. The horizontal axis of these graphs represents current density J (A / cm ² ). The vertical axis represents the external quantum efficiency Ex1. In FIG. 5A, the vertical axis is displayed as a logarithm.

  As shown in FIGS. 5A and 5B, in the semiconductor light emitting device 119b having an Al composition ratio x of 0.3, the external quantum efficiency Ex1 is low.

  In the semiconductor light emitting device 119b having the Al composition ratio x of 0.075 or 0.15, the external quantum efficiency Ex1 is higher than that of the semiconductor light emitting device 119a at a low current density. However, in the semiconductor light emitting device 119b having an Al composition ratio x of 0.075 or 0.15, the external quantum efficiency Ex1 is lower than that of the semiconductor light emitting device 119a at a high current density. That is, when the Al composition ratio x is 0.075 or 0.15, the efficiency of the semiconductor light emitting device 119b can be improved at a low current density, but the efficiency becomes low at a high current density due to droop.

6A and 6B are graphs illustrating characteristics of the semiconductor light emitting device.
These drawings show the measurement results of the characteristics of the samples of the semiconductor light emitting device 110, the semiconductor light emitting device 119a, and the semiconductor light emitting device 119b. In the semiconductor light emitting device 110 and the semiconductor light emitting device 119b, the Al composition ratio x in the high Al concentration region 31y is an example of 0.15. The horizontal axis of these graphs is the current density J (A / cm ² ), and the vertical axis is the external quantum efficiency Ex1.

  As can be seen from FIGS. 6A and 6B, in the semiconductor light emitting device 110, the external quantum efficiency Ex1 is higher than that of the semiconductor light emitting device 119b at a low current density. In the semiconductor light emitting device 110, the external quantum efficiency Ex1 maintains the same high external quantum efficiency Ex1 as that of the semiconductor light emitting device 119a at a high current density. That is, in the A semiconductor light emitting device 110, the efficiency is improved at a low current density, droop is suppressed, and a high efficiency is obtained even at a high current density. According to the embodiment, it is possible to provide a semiconductor light emitting device capable of improving the luminous efficiency.

  In a semiconductor light emitting device using a nitride semiconductor, in addition to improvement of the peak value of light emission efficiency (light emission efficiency in a region having a relatively low current density), improvement of light emission efficiency at a high current density is required. In general, the luminous efficiency decreases with an increase in current density. There is a need for droop suppression.

  In order to improve the peak value of luminous efficiency, there are attempts to reduce defects in the light emitting layer and improve the structure of the light emitting layer. In order to reduce defects in the light emitting layer, for example, it is conceivable to reduce the thickness of the light emitting layer. By reducing the thickness of the light emitting layer, the overlap integral of holes and electrons increases. However, in these structures, the droop is likely to deteriorate.

  Droop can be suppressed by reducing the carrier density of the light emitting layer. However, when the thickness of the light emitting layer is increased in order to reduce the carrier density of the light emitting layer, defects are introduced into the light emitting layer, and in particular, the peak value of the light emission efficiency is lowered.

  As described above, in the conventional technique, it is difficult to improve the peak value of luminous efficiency (luminous efficiency in a region having a relatively low current density) and suppress droop.

  In contrast, as can be seen from FIGS. 6A and 6B, in the semiconductor light emitting device 110 according to the embodiment, the droop can be suppressed while the efficiency is improved at a low current density.

  In the embodiment, the high Al concentration region 31x (and the n-side high Al concentration region 31xn) is provided in the barrier layer 31 (the first barrier layer BL1 and the n-side barrier layer BLn, etc.) on the first semiconductor layer 10 side. Thus, the hole density in the light emitting layer is increased, and the light emission efficiency is improved.

  In the barrier layer 31 (second barrier layer BL2 and third barrier layer BL3, etc.) on the second semiconductor layer 20 side, the high Al concentration region 31x is not provided, but only the low Al concentration region 31y is provided. Crystallinity is obtained.

  In the embodiment, in the region close to the second semiconductor layer 20, the number of the barrier layers 31 not including the high Al concentration region 31 x but having only the low Al concentration region 31 y is set to two or more. Thereby, carrier density is reduced and droop is suppressed.

  For example, as compared with the semiconductor light emitting device 119b in which the high Al concentration region 31x is provided in all the barrier layers 31, the barrier not including the high Al concentration region 31x and having only the low Al concentration region 31y on the side closer to the second semiconductor layer 20. By providing the layer 31, droop is improved.

For example, in the semiconductor light emitting device 119b, all the barrier layers 31 are provided with the high Al concentration region 31x. In this configuration, it is considered that holes are concentrated in the first well layer WL1. That is, the hole density is considered to be low in the second well layer WL2 and the third well layer WL3.
On the other hand, a barrier layer 31 that does not include the high Al concentration region 31x but includes only the low Al concentration region 31y is provided on the side close to the second semiconductor layer 20, and the high Al concentration region is located away from the second semiconductor layer 20. By providing the barrier layer 31 (the first barrier layer BL1 and the like) including the concentration region 31x and the low Al concentration region 31y, holes that are considered to be concentrated in the first well layer WL1 in the semiconductor light emitting device 119b are formed. The second well layer WL2 and the third well layer WL3 can be dispersed. Thereby, droop is suppressed.

  For example, in the well layer 32 away from the second semiconductor layer 20, hole injection is poor. In the embodiment, for example, the number of well layers 32 provided between the first well layer WL1 and the second semiconductor layer 20 is one or two. Thereby, for example, an increase in the number of well layers 32 with poor hole injection can be suppressed.

FIG. 7 is a schematic cross-sectional view illustrating another semiconductor light emitting element according to the embodiment.
As shown in FIG. 7, also in the semiconductor light emitting device 111 according to the embodiment, the first semiconductor layer 10, the second semiconductor layer 20, the first well layer WL1, the second well layer WL2, the first barrier layer BL1 and the second barrier layer BL1. A barrier layer BL2 is provided. These are the same as those of the semiconductor light emitting device 110. In the semiconductor light emitting device 111, the n-side high Al concentration region 31xn is not provided in the n-side barrier layer BLn, but the n-side low Al concentration region 31yn is provided.

  As already described, one barrier layer 31 (first barrier layer BL1) including the high Al concentration region 31x is provided, and the high Al concentration region 31x is provided between the one barrier layer 31 and the second semiconductor layer 20. By providing the barrier layer 31 that does not contain (such as the second barrier layer BL2), it is possible to improve efficiency at a low current density and suppress droop. Like the semiconductor light emitting device 111, the high Al concentration region 31x may be provided in the first barrier layer BL1, and the n side high Al concentration region 31xn may not be provided in the n side barrier layer BLn.

  When there are many nitride semiconductor regions containing Al like the high Al concentration region 31x, for example, the crystallinity may be lowered. High crystallinity can be maintained by providing the high Al concentration region 31x (that is, providing the first barrier layer BL1) while reducing the nitride semiconductor region containing Al. This makes it easy to obtain high efficiency.

  In the embodiment, the first barrier layer BL1 includes a low Al concentration region 31y (for example, a GaN layer) and a high Al concentration region 31x (AlGaN layer) provided thereon. A first well layer WL1 (InGaN layer) is provided in contact with the high Al concentration region 31x (AlGaN layer). There is a large difference in lattice constant between AlGaN and InGaN. In general, it is difficult to provide an InGaN layer in contact with an AlGaN layer on an AlGaN layer having a large difference in lattice constant. For example, the crystallinity of the InGaN layer is lowered.

  In the embodiment, a low Al concentration region 31y (for example, a GaN layer) is provided below the high Al concentration region 31x (AlGaN layer). A flat surface is obtained by the low Al concentration region 31y (for example, GaN layer). By providing the high Al concentration region 31x (AlGaN layer) on the flat surface, high crystallinity is maintained even when the first well layer WL1 is provided in contact with the high Al concentration region 31x (AlGaN layer). it can. For example, a high Al concentration region 31x (AlGaN layer) having a flat expression can be obtained. By forming the first well layer WL1 thereon, high crystallinity is obtained in the first well layer WL1.

  In the embodiment, the Al composition ratio x1 in the high Al concentration region 31x of the first barrier layer BL1 is preferably 0.05 or more and 0.3 or less. When x1 is less than 0.05, for example, the improvement of the light emission efficiency at a low current density by increasing the hole density may be insufficient. When x1 exceeds 0.3, for example, crystallinity deteriorates and luminous efficiency decreases.

  In the embodiment, the Al composition ratio xn in the n-side high Al concentration region 31xn of the n-side barrier layer BLn is preferably 0.3 or less. When xn exceeds 0.3, for example, the crystallinity deteriorates and the light emission efficiency decreases. The Al composition ratio xn in the n-side high Al concentration region 31xn of the n-side barrier layer BLn is higher than zero. The Al composition ratio xn in the n-side high Al concentration region 31xn of the n-side barrier layer BLn may be 0.05 or more.

  In the embodiment, the Al composition ratio y1 in the low Al concentration region 31y of the first barrier layer BL1 is preferably 0 or more and 0.01 or less. When y1 exceeds 0.01, for example, the crystallinity deteriorates and the light emission efficiency decreases. The low Al concentration region 31y is, for example, GaN.

  In the embodiment, the Al composition ratio yn in the n-side low Al concentration region 31yn of the n-side barrier layer BLn is preferably 0 or more and 0.01 or less. When yn exceeds 0.01, for example, the crystallinity is deteriorated and the light emission efficiency is lowered. The n-side low Al concentration region 31yn is, for example, GaN.

  In the embodiment, the Al composition ratio z2 in the second barrier layer BL2 is, for example, 0 or more and 0.01 or less. The Al composition ratio z3 in the third barrier layer BL3 is, for example, 0 or more and 0.01 or less. The second barrier layer BL2 and the third barrier layer BL3 are, for example, GaN layers.

  In the first barrier layer BL1, the thickness of the high Al concentration region 31x is not less than 0.2 times and not more than 0.5 times the thickness of the low Al concentration region 31y. When the thickness of the high Al concentration region 31x is less than 0.2 times the thickness of the low Al concentration region 31y, for example, the high Al concentration region 31x is thin and the effect of increasing the hole density is reduced. If the thickness of the high Al concentration region 31x exceeds 0.5 times the thickness of the low Al concentration region 31y, for example, the flatness tends to deteriorate in the high Al concentration region 31x. Therefore, the flatness in the InGaN layer is likely to deteriorate, and the flatness recovery effect in the GaN layer is likely to be reduced. For this reason, crystallinity tends to deteriorate.

  In the n-side barrier layer BLn, the thickness of the n-side high Al concentration region 31xn is not more than 0.5 times the thickness of the n-side low Al concentration region 31yn. If the thickness of the n-side high Al concentration region 31xn exceeds 0.5 times the thickness of the n-side low Al concentration region 31yn, for example, the flatness tends to deteriorate in the n-side low Al concentration region 31xn. Therefore, the flatness in the InGaN layer is likely to deteriorate, and the flatness recovery effect in the GaN layer is likely to be reduced. For this reason, crystallinity tends to deteriorate.

  The thickness of the first barrier layer BL1 is, for example, not less than 3 nanometers and not more than 5.5 nanometers. When the thickness of the first barrier layer BL1 is less than 3 nm, for example, the flatness recovery effect in the GaN layer is likely to decrease. Therefore, the flatness tends to deteriorate in the high Al concentration region 31x, and the flatness in the InGaN layer tends to deteriorate. For this reason, crystallinity tends to deteriorate. When the thickness of the first barrier layer BL1 exceeds 5.5 nm, for example, the operating voltage increases.

  The thickness of the second barrier layer BL2 is, for example, not less than 3 nanometers and not more than 5.5 nanometers. When the thickness of the second barrier layer BL2 is less than 3 nm, for example, the average In composition ratio of the light emitting layer is increased, and defects are easily introduced into the light emitting layer. When the thickness of the second barrier layer BL2 is less than 3 nm, for example, the flatness of the light emitting layer tends to deteriorate. When the thickness of the second barrier layer BL2 exceeds 5.5 nm, for example, the hole injection effect is reduced and the light emission efficiency is lowered. When the thickness of the second barrier layer BL2 exceeds 5.5 nm, the operating voltage increases.

  The In composition ratio in the well layer 32 may be changed between a region close to the second semiconductor layer 20 and a region far from the second semiconductor layer 20. The thickness of the well layer 32 may be changed between a region near the second semiconductor layer 20 and a region far from the second semiconductor layer 20.

  For example, the In composition ratio w1 may be higher than the In composition ratio w2 (In composition ratio in the second well layer WL2).

  For example, the thickness of the third well layer WL3 may be thicker than the thickness of the first well layer WL1. The thickness of the second well layer WL2 may be thicker than the thickness of the first well layer WL1. By setting the thickness as described above, for example, the carrier density is reduced and the droop is easily reduced.

  For example, when the thickness of the third well layer WL3 is thicker than that of the first well layer WL1, the In composition ratio w3 (In composition ratio in the first well layer WL3) is set to the In composition ratio w1 (first well layer WL1). It may be lower than the In composition ratio). For example, when the thickness of the second well layer WL2 is thicker than that of the first well layer WL1, the In composition ratio w2 (In composition ratio in the first well layer WL2) is set to the In composition ratio w1 (first well layer WL1). It may be lower than the In composition ratio). For example, if the thickness is increased with the same In composition ratio, the wavelength increases. By reducing the In composition ratio, substantially the same wavelength can be obtained.

  For example, at least one of the In composition ratios w1 and w2 is 0.12 or more and 0.16 or less. For example, the In composition ratio wn is 0.14 or more and 0.16 or less.

  Increasing the thickness with the same In composition ratio increases the wavelength. By reducing the In composition ratio, the same wavelength can be obtained. For example, when the thickness of the InGaN well layer is 3.5 nm and the In composition ratio is 0.14, the wavelength is 440 nm (photoluminescence measurement). On the other hand, when the thickness of the InGaN well layer is 4.5 nm and the In composition ratio is 0.125, the wavelength is 440 nm (photoluminescence measurement).

  The number of the n-side well layers WLn (the number of the well layers 32 provided between the first well layers WL1 and the first semiconductor layer 10: the first number) is the number of the first well layers WL1 and the second semiconductor layers 20 It is preferable that it is larger than the number (second number) of the well layers 32 provided between the two. By making the first number larger than the second number, for example, lattice relaxation occurs in the n-side well layer WLn, and the well layer 32 provided between the first well layer WL and the second semiconductor layer 20 Lattice relaxation is suppressed and the introduction of defects is suppressed.

  In the embodiment, the number of well layers 32 is preferably 12 or less. When the number of the well layers 32 exceeds 12, for example, defects are easily introduced into the well layers 32 due to lattice relaxation, and the light emission efficiency is lowered.

  In the embodiment, the first semiconductor layer 10 includes an n-type impurity. As the n-type impurity, at least one of Si, Ge, Te, and Sn is used. The first semiconductor layer includes, for example, an n-side contact layer.

  The second semiconductor layer 20 includes a p-type impurity. As the p-type impurity, at least one of Mg, Zn, and C is used. The second semiconductor layer includes, for example, a p-side contact layer.

  In the embodiment, an intermediate portion (for example, a superlattice layer) of the multilayer film may be provided between the light emitting unit 30 and the first semiconductor layer 10.

  In the semiconductor light emitting device and the method for manufacturing the semiconductor light emitting device according to the embodiment, examples of the method for growing the semiconductor layer include a metal-organic chemical vapor deposition (MOCVD) method, a metal organic chemical vapor deposition (Metal). -Organic Vapor Phase Epitaxy (MOVPE) method, Molecular Beam Epitaxy (MBE) method, Halide Vapor Phase Epitaxy (HVPE) method and the like can be used.

For example, when the MOCVD method or the MOVPE method is used, the following can be used as raw materials for forming each semiconductor layer. For example, TMGa (trimethyl gallium) and TEGa (triethyl gallium) can be used as the Ga raw material. As a source of In, for example, TMIn (trimethylindium), TEIn (triethylindium), or the like can be used. As a raw material for Al, for example, TMAl (trimethylaluminum) can be used. As a raw material of N, for example, NH ₃ (ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine) and the like can be used. As a Si raw material, SiH ₄ (monosilane), Si ₂ H ₆ (disilane), or the like can be used.

  According to the embodiment, it is possible to provide a semiconductor light emitting device capable of improving the luminous efficiency.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element such as a semiconductor layer, a light emitting portion, a well layer, and a barrier layer included in a semiconductor light emitting device, the present invention can be similarly implemented by appropriately selecting from a known range by those skilled in the art. As long as the same effect can be obtained, it is included in the scope of the present invention.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor light-emitting elements that can be implemented by those skilled in the art based on the semiconductor light-emitting elements described above as embodiments of the present invention are included in the scope of the present invention as long as they include the gist of the present invention. Belonging to.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 10i ... Low impurity concentration layer, 20 ... 2nd semiconductor layer, 30 ... Light emission part, 31 ... Barrier layer, 31x ... High Al concentration area | region, 31xn ... High Al concentration area | region of n side 31y ... Low Al concentration region, 31yn ... n-side low Al concentration region, 32 ... well layer, 50 ... buffer layer, 50s ... substrate, 51 ... AlN layer, 52 ... AlGaNN buffer layer, 53 ... low Al composition layer, 54 ... high Al composition 110, 111, 119a, 119b ... semiconductor light emitting device, BL1-BL3 ... first barrier layer, BLn ... n-side barrier layer, BLp ... p-side barrier layer, CAl ... Al composition ratio, CIn ... In composition ratio, Ex1 ... external quantum efficiency, J ... current density, Pz ... position, WL1-WL3 ... first to third well layers, WLn ... n-side well layer

Claims (20)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type;
A first well layer comprising _{In w1 Ga 1-w1 N (} 0 <w1 <1) provided between the second semiconductor layer and the first semiconductor layer,
A second well layer comprising _{In w2 Ga 1-w2 N (} 0 <w2 <1) provided between the second semiconductor layer and the first well layer,
A first barrier layer provided between the first semiconductor layer and the first well layer,
A high Al concentration region containing Al _x1 Ga _1-x1 N (0 <x1 <1) in contact with the first well layer;
A low Al concentration region containing Al _y1 Ga _1-y1 N (0 ≦ y1 <x1) in contact with the high Al concentration region between the high Al concentration region and the first semiconductor layer;
The first barrier layer comprising:
The second barrier layer including the first contact with the well layer and the second well layer _{Al z2 Ga 1-z2 N (} 0 ≦ z2 <x1) is provided between the second well layer and the first well layer When,
A semiconductor light emitting device comprising:   The semiconductor light emitting element according to claim 1, wherein x1 is 0.05 or more and 0.3 or less.   The semiconductor light emitting device according to claim 1, wherein z2 is 0.01 or less. A third well layer comprising _{In w3 Ga 1-w3 N (} 0 <w3 <1) provided between the second well layer second semiconductor layer,
Third barrier layer comprising the said second well layer disposed third well layer and in contact with _{Al z3 Ga 1-z3 N (} 0 ≦ z3 <x1) between the second well layer and the third well layer When,
The semiconductor light-emitting device according to claim 1, further comprising:   The semiconductor light emitting device according to claim 4, wherein z3 is 0, 01 or less.   6. The semiconductor light emitting element according to claim 4, wherein a thickness of the third well layer is thicker than a thickness of the first well layer. The p-side barrier layer that is provided between the third well layer and the second semiconductor layer and further includes Al _zp Ga _1-zp N (0 ≦ zp <x1). The semiconductor light emitting element as described in any one. An n-side well layer including In _wn Ga _1-wn N (0 <wn <1) provided between the first semiconductor layer and the first well layer;
An n-side barrier layer provided between the first semiconductor layer and the n-side well layer;
Further comprising
The n-side barrier layer is
An n-side high Al concentration region containing Al _xn Ga _1-xn N (0 <xn <1) in contact with the n-side well layer;
An n-side low Al concentration region containing Al _yn Ga _{1 -yn} N (0 ≦ yn <xn) in contact with the n-side high Al concentration region between the n-side high Al concentration region and the first semiconductor layer;
The semiconductor light emitting element of any one of Claims 1-7 containing these.   The semiconductor light emitting device according to claim 8, wherein yn is 0.01 or less.   10. The semiconductor light emitting element according to claim 8, wherein xn is 0.05 or more and 0.3 or less.   11. The semiconductor light emitting element according to claim 8, wherein wn is 0.14 or more and 0.16 or less.   The semiconductor light emitting element according to claim 8, wherein the n-side well layer is in contact with the first barrier layer. A plurality of the n-side well layers are provided,
A plurality of the n-side barrier layers are provided,
The plurality of n-side well layers and the plurality of n-side barrier layers are alternately arranged in a direction from the first semiconductor layer toward the second semiconductor layer. The semiconductor light emitting element as described.   The semiconductor light emitting element according to claim 13, wherein the number of the plurality of n-side well layers is 3 or more and 9 or less.   The semiconductor light emitting element according to claim 1, wherein w1 is higher than w2.   The semiconductor light emitting element according to claim 1, wherein at least one of w1 and w2 is 0.12 or more and 0.16 or less.   17. The semiconductor light emitting device according to claim 1, wherein a thickness of the second well layer is thicker than a thickness of the first well layer.   The semiconductor light emitting element according to claim 1, wherein y1 is 0.01 or less.   19. The semiconductor light emitting device according to claim 1, wherein a thickness of the first barrier layer is not less than 3 nanometers and not more than 5.5 nanometers.   20. The semiconductor light emitting element according to claim 1, wherein the thickness of the high Al concentration region is not less than 0.2 times and not more than 0.5 times the thickness of the low Al concentration region.