JP5837642B2 - Semiconductor device and nitride semiconductor wafer - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device and a nitride semiconductor wafer.

  Nitride semiconductors are used in various fields such as optical devices typified by light-emitting / light-receiving elements and high-speed electronic devices typified by high-frequency elements. In order to obtain high performance, a high-quality crystal with few dislocations is desired.

Japanese Patent No. 4622466

  Embodiments of the present invention provide a semiconductor device with less dislocations and a nitride semiconductor wafer.

According to the embodiment of the present invention, a semiconductor device including a nitride semiconductor functional layer is provided. The functional layer is provided on the nitride semiconductor layer including the first stacked body. The first stacked body is provided on a main surface of a silicon substrate and is in contact with a base layer including at least one of AlN and AlGaN. The first stacked body includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si at a first concentration and has a first thickness. The first lower layer is in contact with the base layer, and Al _xa1 In _ya1 Ga _1-xa1-ya1 N (0 <xa1 ≦ 1, 0 ≦ ya1 < 1) . The first intermediate layer is provided on and in contact with the first lower layer on the first lower layer, contains Si at a second concentration lower than the first concentration, and has a second thickness that is thicker than the first thickness. Al _xb1 In _yb1 Ga _1-xb1-yb1 N (0 <xb1 ≦ 1, 0 ≦ yb1 <1) . The first upper layer is provided on and in contact with the first _intermediate layer on the first _intermediate layer, contains Si at a third concentration lower than the second concentration, and has a third thickness, Al _xc1 In _yc1 Ga _1-xc1-yc1 N (0 <xc1 ≦ 1, 0 ≦ yc1 <1) . The xb1 is different from the xa1, the xc1 is different from the xa1, and the xc1 is different from the xb1. The first thickness is not less than 10 nanometers and less than 350 nanometers. The second thickness is not less than 200 nanometers and not more than 800 nanometers, and is thicker than the first thickness. The third thickness is not less than 100 nanometers and not more than 800 nanometers, and is thinner than the second thickness. The first concentration is 1 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²² cm ⁻³ , and the second concentration is 2 × 10 ¹⁷ cm ⁻³ or more and less than 1 × 10 ¹⁹ cm ⁻³ , The third concentration is less than 2 × 10 ¹⁷ cm ⁻³ . The first lower layer includes a discontinuous island-shaped portion containing Si provided on and in contact with the base layer. At least a part of the dislocations in at least a part of the first middle layer and the first upper layer bends in a direction along the main surface from a direction along a direction perpendicular to the main surface from bottom to top. The lattice constant of the first upper layer is larger than the lattice constant of the first middle layer, and the lattice constant of the first middle layer is larger than the lattice constant of the first lower layer.
According to another embodiment of the present invention, a nitride semiconductor wafer is provided that includes a silicon substrate having a major surface, an underlayer, and a nitride semiconductor layer. The underlayer is provided on the main surface and includes at least one of AlN and AlGaN. The nitride semiconductor layer includes a first stacked body provided in contact with the base layer. The first stacked body contains Si at a first concentration, has a first thickness, is a nitride semiconductor in contact with the base layer, and Al _xa1 In _ya1 Ga _1-xa1-ya1 N (0 <xa1 ≦ 1) , 0 ≦ ya1 <1) , and is provided on and in contact with the first lower layer on the first lower layer and contains Si at a second concentration lower than the first concentration, and is greater than the first thickness. a first intermediate layer of have a thick second thickness _{Al xb1 in yb1 Ga 1-xb1} -yb1 N (0 <xb1 ≦ 1,0 ≦ yb1 <1), the first intermediate layer on the first intermediate layer contains Si at a third concentration is lower than the second concentration is provided in contact have a third thickness _{Al xc1 in yc1 Ga 1-xc1} -yc1 N (0 <xc1 ≦ 1,0 ≦ yc1 <1) And a first upper layer. The xb1 is different from the xa1, the xc1 is different from the xa1, and the xc1 is different from the xb1. The first thickness is not less than 10 nanometers and less than 350 nanometers. The second thickness is not less than 200 nanometers and not more than 800 nanometers, and is thicker than the first thickness. The third thickness is not less than 100 nanometers and not more than 800 nanometers, and is thinner than the second thickness. The first concentration is 1 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²² cm ⁻³ . The second concentration is 2 × 10 ¹⁷ cm ⁻³ or more and less than 1 × 10 ¹⁹ cm ⁻³ . The third concentration is less than 2 × 10 ¹⁷ cm ⁻³ . The first lower layer includes a discontinuous island-shaped portion containing Si provided on and in contact with the base layer. At least a part of the dislocations in at least a part of the first middle layer and the first upper layer bends in a direction along the main surface from a direction along a direction perpendicular to the main surface from bottom to top. The lattice constant of the first upper layer is larger than the lattice constant of the first middle layer. The lattice constant of the first middle layer is larger than the lattice constant of the first lower layer.

1 is a schematic cross-sectional view showing a nitride semiconductor wafer according to a first embodiment. 1 is a schematic cross-sectional view showing a part of a nitride semiconductor wafer according to a first embodiment. FIG. 3A and FIG. 3B are graphs showing a nitride semiconductor wafer. It is a flowchart figure which shows the manufacturing method of the nitride semiconductor wafer which concerns on 1st Embodiment. FIG. 5A to FIG. 5F are schematic views showing the method for manufacturing the nitride semiconductor wafer according to the first embodiment. FIG. 6A to FIG. 6E are schematic cross-sectional views showing a method for manufacturing a nitride semiconductor wafer according to the first embodiment. It is a microscope picture image which shows the nitride semiconductor wafer concerning a 1st embodiment. FIG. 8A and FIG. 8B are micrograph images showing a nitride semiconductor wafer. It is a typical sectional view showing a nitride semiconductor wafer concerning a 2nd embodiment. It is a typical sectional view showing a nitride semiconductor wafer concerning a 2nd embodiment. It is typical sectional drawing which shows the semiconductor element which concerns on 3rd Embodiment. It is typical sectional drawing which shows the semiconductor element which concerns on 3rd Embodiment. It is typical sectional drawing which shows the semiconductor element which concerns on 3rd Embodiment. It is typical sectional drawing which shows the semiconductor element which concerns on 3rd Embodiment.

Each embodiment will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
The first embodiment relates to a nitride semiconductor wafer. The nitride semiconductor wafer is provided with, for example, at least a part of the semiconductor element or a part that becomes at least a part of the semiconductor element. This semiconductor element includes, for example, a semiconductor light emitting element, a semiconductor light receiving element, and an electronic device. The semiconductor light emitting element includes, for example, a light emitting diode (LED) and a laser diode (LD). The semiconductor light receiving element includes a photodiode (PD) and the like. The electronic device includes, for example, a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a field transistor (FET), a Schottky barrier diode (SBD), and the like.

FIG. 1 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor wafer according to the first embodiment.
As shown in FIG. 1, the nitride semiconductor wafer 110 according to this embodiment includes a substrate 50 and a nitride semiconductor layer 55. The nitride semiconductor layer 55 includes a first stacked body SL1.

  The substrate 50 has a main surface 50a. The first stacked body SL1 is provided on the main surface 50a.

  The first stacked body SL1 includes a first lower layer LA1 of nitride semiconductor, a first middle layer LB1 of nitride semiconductor, and a first upper layer LC1 of nitride semiconductor.

  The first lower layer LA1 contains Si at a first concentration and has a first thickness t1.

  The first intermediate layer LB1 is provided on and in contact with the first lower layer LA1 on the first lower layer LA1. The first intermediate layer LB1 contains Si at a second concentration lower than the first concentration, and has a second thickness t2 that is thicker than the first thickness t1.

  The first upper layer LC1 is provided on and in contact with the first intermediate layer LB1 on the first intermediate layer LB1. The first upper layer LC1 contains Si at a third concentration lower than the second concentration, and has a third thickness t3. For example, the third thickness t3 is thicker than the first thickness t1. For example, the third thickness t3 is thicker than the second thickness t2. For example, the third thickness t3 may be equal to or less than the second thickness t2.

  A direction perpendicular to the main surface 50a is taken as a Z-axis direction. The direction from the first lower layer LA1 to the third upper layer LC1 is the + Z-axis direction.

  As will be described later, the nitride semiconductor layer 55 may include a plurality of stacked bodies. That is, the nitride semiconductor layer 55 may further include, for example, a second stacked body in addition to the first stacked body SL1. Hereinafter, an example in which one stacked body (first stacked body SL1) is provided in the nitride semiconductor layer 55 will be described.

  For example, a silicon substrate is used as the substrate 50. For the substrate 50, for example, a Si (111) substrate is used. The embodiment is not limited to this, and the plane orientation of the substrate 50 is arbitrary. In addition, the substrate 50 may be a substrate such as sapphire, GaN, or SiC.

  In this example, the nitride semiconductor wafer 110 further includes a functional layer 40 of nitride semiconductor. The functional layer 40 is provided on the nitride semiconductor layer 55. The functional layer 40 includes, for example, a layer having a light emitting function of a semiconductor light emitting element. The functional layer 40 includes, for example, a layer having a light receiving function of a semiconductor light receiving element. The functional layer 40 includes, for example, a layer having at least one function of rectification, switching, and amplification of an electronic device. An example of the configuration of the functional layer 40 will be described later.

  In this example, the nitride semiconductor wafer 110 further includes a foundation layer 51. The foundation layer 51 is provided on the main surface 50a. The foundation layer 51 is provided between the substrate 50 and the nitride semiconductor layer 55 (first stacked body SL1 in this example).

  In the specification of the present application, “the state in which the second layer is provided on the first layer” refers to the state of the first layer in addition to the state in which the second layer is disposed in contact with the first layer on the first layer. It also includes a state in which the third layer is inserted above and the second layer is disposed on the third layer.

  In this example, the foundation layer 51 includes a first foundation layer 51a, a second foundation layer 51b, and a third foundation layer 51c. The second foundation layer 51b is provided on the first foundation layer 51a. The third foundation layer 51c is provided on the second foundation layer 51b.

  For example, AlN is used for the first base layer 51a. For the first underlayer 51a, for example, an AlN layer grown at a low temperature is used. The first foundation layer 51 a can have a function as a nucleation layer provided on the main surface 50 a of the substrate 50. The thickness of the first foundation layer 51a is, for example, not less than 10 nanometers (nm) and not more than 200 nm.

For example, Al _z2 Ga _1-z2 N (0 <z2 <1) is used for the second underlayer 51b. For example, AlGaN is used for the second underlayer 51b. The thickness of the second base layer 51b is, for example, not less than 10 nm and not more than 400 nm.

For example, Al _z3 Ga _1-z3 N (0 ≦ z3 <1, z3 <z2) is used for the third base layer 51b. For example, GaN is used for the third base layer 51c. The thickness of the third foundation layer 51c is, for example, not less than 10 nm and not more than 300 nm.

FIG. 2 is a schematic cross-sectional view illustrating the configuration of a part of the nitride semiconductor wafer according to the first embodiment.
FIG. 2 illustrates the configuration of the functional layer 40 when the nitride semiconductor wafer 110 is applied to a semiconductor light emitting device.

  As illustrated in FIG. 2, in this example, the functional layer 40 includes an n-type semiconductor layer 10, a p-type semiconductor layer 20, and a light emitting layer 30. The n-type semiconductor layer 10 is provided on the nitride semiconductor layer 55. The n-type semiconductor layer 10 includes a nitride semiconductor. The p-type semiconductor layer 20 is provided on the n-type semiconductor layer 10. The p-type semiconductor layer 20 includes a nitride semiconductor.

  The light emitting layer 30 is provided between the n-type semiconductor layer 10 and the p-type semiconductor layer 20. The light emitting layer 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31. The number of well layers 32 may be one or plural. That is, the light emitting layer 30 can have an SQW (Single-Quantum Well) structure or an MQW (Multi-Quantum Well) structure.

  The band gap energy of the barrier layer 31 is larger than the band gap energy of the well layer 32. For the well layer 32, for example, InGaN is used. GaN is used for the barrier layer 31. When InGaN is used for the barrier layer 31, the In composition ratio in the barrier layer 31 is smaller than the In composition ratio in the well layer 32. The peak wavelength of light emitted from the light emitting layer 30 is, for example, not less than 200 nm and not more than 1300 nm.

  In this example, the functional layer 40 is provided with the n-type semiconductor layer 10. As will be described later, the nitride semiconductor layer 55 may function as an n-type semiconductor layer. In this case, the n-type semiconductor layer 10 can be omitted.

Incidentally, the nitride semiconductor wafer 110 includes a substrate 50, a nitride semiconductor layer 55 includes, for example, function layer 40 may be omitted.

  FIG. 1 also illustrates the configuration of the semiconductor element 210 according to this embodiment. The semiconductor element 210 includes a functional layer 40 of a nitride semiconductor. The functional layer 40 is provided on the nitride semiconductor layer 55 including the first stacked body SL1.

  In the semiconductor element 210, at least a part of the nitride semiconductor layer 55 may be removed after the nitride semiconductor layer 55 is formed on the substrate 50. Then, the substrate 50 may be removed. Thus, in the semiconductor element 210, at least a part of the nitride semiconductor layer 55 may be omitted. The substrate 50 may be omitted.

  In the semiconductor element 210, the nitride semiconductor layer 55 includes a first stacked body SL1 provided on the main surface 50a of the substrate 50. The first stacked body SL1 includes the first lower layer LA1, the first intermediate layer LB1, and the first upper layer LC1. These configurations are the same as those in the nitride semiconductor wafer 110.

  Hereinafter, an example of the configuration of the nitride semiconductor layer 55 in the nitride semiconductor wafer 110 and the semiconductor element 210 will be described.

FIG. 3A and FIG. 3B are graphs illustrating the configuration of a nitride semiconductor wafer.
These drawings illustrate the measurement results of the Si concentration profile in the nitride semiconductor layer 55 (first stacked body SL1). FIG. 3A corresponds to the nitride semiconductor wafer 110 (and the semiconductor element 210) according to this embodiment. FIG. 3B corresponds to the nitride semiconductor wafer 119 of the reference example. In the nitride semiconductor wafer 119 of the reference example, the first lower layer LA1 and the first upper layer LC1 are provided in the first stacked body SL1, and the first intermediate layer LB1 is not provided. The horizontal axis in these drawings is the position in the Z-axis direction (depth D (nm)). The vertical axis represents the Si concentration C (Si). In these examples, the base layer 51 is provided.

As shown in FIG. 3A, in the nitride semiconductor wafer 110 (semiconductor element 210) according to this embodiment, the first lower layer LA1 contains Si at the first concentration C1. The first concentration C1 is 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. In this example, the first concentration C1 is 1 × 10 ¹⁹ cm ⁻³ or more and about 2 × 10 ²⁰ cm ⁻³ or less. The first concentration C1 may be, for example, the maximum value of the Si concentration in the first lower layer LA1. The first concentration C1 may be, for example, an average value of Si concentration in the first lower layer LA1.

The first intermediate layer LB1 contains Si at the second concentration C2. The second concentration C2 is lower than the first concentration C1. In this example, the second concentration C2 is about 2 × 10 ¹⁷ cm ⁻³ or more and less than about 1 × 10 ¹⁹ cm ⁻³ .

The first upper layer LC1 has a third concentration C3. The third concentration C3 is lower than the second concentration C2. In this example, the third concentration C3 is 1 × 10 ¹⁶ cm ⁻³ or more and less than 2 × 10 ¹⁷ cm ⁻³ . The third concentration C3 may be, for example, the minimum value of the Si concentration in the first upper layer LC1. The third concentration C3 may be, for example, an average value of Si concentration in the first upper layer LC1.

  In this example, the first thickness t1 of the first lower layer LA1 is about 200 nm. The second thickness t2 of the first intermediate layer LB1 is about 500 nm. The third thickness t3 of the first upper layer LC1 is about 300 nm.

Thus, in the embodiment, the first lower layer LA1, the second middle layer LB1, and the first upper layer LC1 are provided in the first stacked body SL1. The second concentration C2 is lower than the first concentration C1, and the third concentration C3 is lower than the second concentration C2. The second thickness t2 is thicker than the first thickness t1. In the nitride semiconductor wafer 110 (semiconductor element 210) having such a configuration, an example of the measurement result of the edge dislocation density on the upper surface of the nitride semiconductor layer 55 is 4.3 × 10 ⁸ cm ⁻² .

On the other hand, as shown in FIG. 3B, in the nitride semiconductor wafer 119 of the reference example, the first lower layer LA1 and the first upper layer LC1 are provided. That is, in the reference example, the first intermediate layer LB1 having a two-layer structure of a layer having a high Si concentration (first lower layer LA1) and a layer having a low concentration (first upper layer LC1) and having an intermediate Si concentration is provided. Not. In the nitride semiconductor wafer 119, the first concentration C1 of the first lower layer LA1 is about 1 × 10 ²⁰ cm ⁻³ . The third concentration C3 of the first upper layer LC1 is not less than about 1 × 10 ¹⁶ cm ^{−3 and not} more than 8 × 10 ¹⁶ cm ⁻³ . The first thickness t1 of the first lower layer LA1 is about 30 nm.

In the nitride semiconductor wafer 119 having such a configuration, the measurement result of the edge dislocation density on the upper surface of the nitride semiconductor layer 55 is 5.3 × 10 ⁹ cm ⁻² .

  On the other hand, as described above, in the embodiment, a three-layer configuration of the first lower layer LA1, the first middle layer LB1, and the first upper layer LC1 is applied. The edge dislocation density in the embodiment having the three-layer structure is about one-tenth of the edge dislocation density in the reference example having the two-layer structure.

  Thus, according to the embodiment, a semiconductor element and a nitride semiconductor wafer with few dislocations can be provided.

  An example of the method for manufacturing the nitride semiconductor wafer 110 and the semiconductor element 210 according to the embodiment will be described.

FIG. 4 is a flowchart illustrating the method for manufacturing the nitride semiconductor wafer according to the first embodiment.
This manufacturing method includes a process (step S101) of forming the nitride semiconductor layer 55 including the first stacked body SL1 on the main surface 50a of the substrate 50. Further, a process (step S210) for forming the functional layer 40 may be provided. The first stacked body SL1 includes the first lower layer LA1, the first intermediate layer LB1, and the first upper layer LC1.

  As shown in FIG. 4, the formation of the nitride semiconductor layer 55 (step S101) includes a process of forming the first lower layer LA1 (step S110), a process of forming the first intermediate layer LB1 (step S120), 1 upper layer LC1 (step S130).

  In forming the first lower layer LA1, the first lower layer LA1 is formed with the first V / III ratio (R1) and the first temperature (T1).

  In forming the first intermediate layer LB1, the first intermediate layer LB1 is formed on the first lower layer LA1 in contact with the first lower layer LA1. At this time, at least a part of the first intermediate layer LB1 is formed with the second V / III ratio (R2) and the second temperature (T2). The second V / III ratio (R2) is lower than the first V / III ratio (R1). The second temperature (T2) is equal to or higher than the first temperature (T1).

  In forming the first upper layer LC1, the first upper layer LC1 is formed on the first intermediate layer LB1 in contact with the first intermediate layer LB1. At this time, the first upper layer LC1 is formed with the third V / III ratio (R3) and the third temperature (T3). The third V / III ratio (R3) is lower than the first V / III ratio (R1). The third temperature (T3) is higher than the second temperature (T2).

  The V / III ratio is the ratio of the number of group V elements introduced into the reactor per unit time (N5) to the number of group III elements introduced per unit time (N3) (ie, N5 / N3). ).

  In the embodiment, for example, the MOVPE method is used to form the nitride semiconductor layer 55.

FIG. 5A to FIG. 5F are schematic views illustrating the method for manufacturing the nitride semiconductor wafer according to the first embodiment.
FIG. 5A is a schematic cross-sectional view illustrating the configuration of the nitride semiconductor wafer 110 (and the semiconductor element 210).
FIG. 5B to FIG. 5F are graphs illustrating conditions for forming the nitride semiconductor layer 55. The horizontal axis of these figures represents time t. The time t substantially corresponds to the formation position (position in the Z-axis direction) of each layer illustrated in FIG.
The vertical axis in FIG. 5B represents the flow rate F (Si) of the gas containing Si to be supplied in a normalized manner.
The vertical axis in FIG. 5C shows the normalized flow rate F (V) of the gas containing the V group element to be supplied.
The vertical axis in FIG. 5D shows the normalized flow rate F (III) of the gas containing the group III element to be supplied.
The vertical axis | shaft of FIG.5 (e) represents V / III ratio R (V / III) in the gas to supply.
The vertical axis in FIG. 5F represents the film forming temperature T.

For example, the base layer 51 is formed on the main surface 50a of the substrate 50 before the first time tm1. At this time, for example, a gas containing Si is not introduced, and the flow rate F0 (Si) of the gas containing Si is zero. And the flow volume F0 (V) of the gas containing a V group element is 4 * 10 < ⁵ > micromol, for example. The flow rate F0 (III) of the gas containing the group III element is, for example, 65 μmol. At this time, the V / III ratio R0 in the supplied gas is 6500. The film forming temperature T0 is 1000 ° C.

Thereafter, a first lower layer LA1 is formed on the base layer 51. For example, between the first time tm1 and the second time tm2, for example, the flow rate F1 (Si) of the gas containing Si is 9 × 10 ⁻² μmol. And the flow volume F1 (V) of the gas containing a V group element is 4 * 10 < ⁵ > micromol, for example. The flow rate F1 (III) of the gas containing the group III element is, for example, 65 μmol. At this time, the V / III ratio (first V / III ratio R1) in the supplied gas is 6500. The first temperature T1 is 1000 ° C. Thereby, for example, at least a part of the first lower layer LA1 is formed. In this case, the lower part of the first lower layer LA1 is formed.

At the second time tm2, the flow rate of the gas containing Si is made smaller than the flow rate F1 (Si). Then, at the second time tm2, the flow rate F2 (V) of the gas containing the group V element is set to 2 × 10 ⁵ μmol, for example. Then, the flow rate F2 (III) of the gas containing the group III element is set to 130 μmol, for example. At this time, the V / III ratio (second V / III ratio R2) in the supplied gas is 1500. And the temperature remains at 1000 ° C. Thereby, another part (upper part) of the first lower layer LA1 is formed.

A first intermediate layer LB1 is formed on the first lower layer LA1. For example, the flow rate F2 (Si) of the gas containing Si is 0 until the third time tm3 after the above formation of the first lower layer LA1. And the flow volume F2 (V) of the gas containing a V group element is 2 * 10 < ⁵ > micromol, for example. The flow rate F2 (III) of the gas containing the group III element is, for example, 130 μmol. At this time, the V / III ratio (second V / III ratio R2) in the supplied gas is 1500. And the 2nd temperature T2 is 1000 degreeC. Thus, the second V / III ratio R2 is lower than the first V / III ratio R1. Thereby, for example, at least a part of the first intermediate layer LB1 is formed. In this case, a lower part of the first middle layer LB1 is formed.

Thereafter, at the third time tm3, the flow rate F (V) of the gas containing the group V element is increased. For example, between the third time tm3 and the fourth time tm4, for example, the flow rate F (Si) of the gas containing Si remains zero. The flow rate F (V) of the gas containing the group V element is, for example, 4 × 10 ⁵ μmol (for example, the same as the flow rate F1 (V)). The flow rate F (III) of the gas containing the group III element is, for example, 130 μmol. At this time, the V / III ratio in the supplied gas is 3000. The film formation temperature T is 1000 ° C. (for example, the same as the first temperature T1). Thereby, for example, the remaining part (upper part) of the first middle layer LB1 is formed.

Thereafter, the first upper layer LC1 is formed on the first middle layer LB1. For example, after the fourth time tm4 after the third time tm3, for example, the flow rate F3 (Si) of the gas containing Si is zero. And the flow volume F3 (V) of the gas containing a V group element is 4 * 10 < ⁵ > micromol, for example. The flow rate F3 (III) of the gas containing the group III element is, for example, 130 μmol. At this time, the V / III ratio (third V / III ratio R3) in the supplied gas is 3000. The third temperature T3 is 1100 ° C. Thus, the third V / III ratio R3 is higher than the second V / III ratio R2. In this example, the third V / III ratio R3 is lower than the first V / III ratio R1. The third temperature T3 is higher than the second temperature T2. Thereby, for example, the first upper layer LC1 is formed.

  Furthermore, the functional layer 40 is formed as needed. Thus, the nitride semiconductor wafer 110 (and the semiconductor element 210) according to the present embodiment is formed.

FIG. 6A to FIG. 6E are schematic cross-sectional views illustrating the method for manufacturing a nitride semiconductor wafer according to the first embodiment.
These drawings illustrate the configuration of the nitride semiconductor wafer 110 (and the semiconductor element 210) in the order of steps.

  As shown in FIG. 6A, for example, the first film Laf is formed between the first time tm1 and the second time tm2. The first film Laf becomes at least a part of the first lower layer LA1. The first film Laf is formed in an island shape on the main surface 50a of the substrate 50 (in this example, on the base layer 51). The foundation layer 51 is exposed from the portion where the first film Laf is not formed. The first film Laf may have, for example, a SiN configuration.

  As illustrated in FIG. 6B, for example, the second film Lbf of the nitride semiconductor is formed between the second time tm2 and the third time tm3. The second film Lbf becomes at least a part of the first lower layer LA1. A part of the second film Lbf may be the first intermediate layer LB1. For example, the second film Lbf is not substantially formed on the island-shaped first film Laf. Alternatively, the growth rate of the crystal on the first film Laf is slower than the growth rate on the other layer (underlayer 51). The first film Lbf is selectively formed on the base layer 51 exposed from the portion where the first film Laf is not formed.

  As shown in FIG. 6C, when the formation of the second film Lbf is further continued, the thickness (height) of the second film Lbf increases. At this time, dislocations DI (threading dislocations) are formed in the second film Lbf. The direction in which the dislocation DI extends is mainly along the Z-axis direction. That is, at this stage, the dislocation DI extends in the vertical direction.

  In the processing illustrated in FIGS. 6B and 6C, the second film Lbf is grown under the condition that the second film Lbf is grown in the vertical direction. Under the conditions in which the second film Lbf grows in the vertical direction (longitudinal growth mode), the growth rate in the vertical direction (direction along the Z-axis direction) grows in the horizontal direction (direction perpendicular to the Z-axis direction). Greater than speed. In the vertical growth mode, the second V / III ratio R2 and the second temperature T2 are employed. As described above, the second V / III ratio R2 is lower than the first V / III ratio R1. The second temperature T2 is equal to or higher than the first temperature T1.

Thereafter, after the fourth time tm4, the V / III ratio in the supplied gas is set higher than the second V / III ratio R2. Then, the film formation temperature T is set to a third temperature T3 that is higher than the second temperature T2. As a result, the formed film grows in the lateral direction. Under the horizontal growth condition (horizontal growth mode), the horizontal growth rate is larger than the vertical growth rate.
That is, as shown in FIG. 6D, the third film Lcf is formed after the formation of the second film Lbf. The third film Lcf grows so as to cover the first film Laf.

  At this time, the third film Lcf grows in the lateral direction, and the direction in which the dislocation DI extends is in the lateral direction. The direction in which the dislocation DI extends is bent from the vertical direction to the horizontal direction. A plurality of dislocations bent in the lateral direction are combined with each other. A part of the dislocation DI disappears. For this reason, the number (density) of dislocations DI extending in the vertical direction decreases. For this reason, in the third film Lcf, for example, the dislocation density is reduced as compared with the second film Lbf. Note that some dislocations DI may continue to extend in the vertical direction even during the formation of the third film Lcf. In this film formation, the flatness of the surface of the third film Lcf is higher than the flatness of the second film Lbf.

  As shown in FIG. 6E, the first upper layer LC1 is formed after the fifth time tm5. The first upper layer LC1 is formed so as to grow in the lateral direction, for example. Thereby, a plurality of dislocations existing in the first upper layer LC1 are united with each other. This further reduces the dislocation density.

  As shown in FIG. 6E, the first lower layer LA1 is formed by the first film Laf and at least a part of the second film Lbf. Then, at least a part of the first intermediate layer LB1 is formed by the third film Lcf. A part of the second film Lbf may be included in the first intermediate layer LB1. In this film formation, the surface of the first upper film LC1 is flattened.

  In the first intermediate layer LB1 (third film Lcf), when the dislocation density is sufficiently reduced, the first upper layer LC1 may be formed in the longitudinal mode.

  Thus, in the present embodiment, at least a part of the dislocations DI in at least a part of the first middle layer LB1 and the first upper layer LC1 extends in the vertical direction (perpendicular to the main surface 50a) from the bottom to the top. Bend in the lateral direction (direction along the main surface 50a) from the direction along the direction). Thereby, the dislocation density can be reduced.

  Thereby, the dislocation density in the first upper layer LC1 can be lower than the dislocation density in the first lower layer LA1. Also, the dislocation density can be lowered in the functional layer 40 formed on the nitride semiconductor layer 55. That is, in the embodiment, the dislocation density in the functional layer 40 is lower than the dislocation density in the first lower layer LA1.

FIG. 7 is a photomicrograph illustrating the configuration of the nitride semiconductor wafer according to the first embodiment.
FIG. 7 illustrates a cross-sectional TEM (Transmission Electron Microscope) image of the nitride semiconductor wafer 110 (and the semiconductor element 210).
As can be seen from FIG. 7, in the first intermediate layer LB1, the dislocation DI is bent from the vertical direction (direction along the Z-axis direction) to the horizontal direction (direction along the main surface 50a). This reduces the dislocation density. A high-quality nitride semiconductor layer with few dislocations is obtained in the layer above the first intermediate layer LB1.

  On the other hand, in the nitride semiconductor wafer 119 of the reference example described with reference to FIG. 3B, for example, the first intermediate layer LB1 is not formed. For this reason, the growth described with reference to FIGS. 6C and 6D is not performed. For this reason, the dislocation DI existing in the first lower layer LA1 hardly disappears, and the dislocation DI remains. For this reason, the dislocation density is high.

  In contrast, in the embodiment, the formation of the island-shaped first film Laf, the growth of the second film Lbf in the vertical growth mode, and the third film Lcf in the horizontal growth mode are employed. Thereby, the dislocation density can be reduced.

  In the present embodiment, the first film Laf is formed in an island shape, and the size of the island and the interval between the islands are set to be relatively large. Accordingly, the growth described with reference to FIGS. 6B to 6D is efficiently performed.

FIG. 8A and FIG. 8B are photomicrographs illustrating the configuration of the nitride semiconductor wafer.
These drawings illustrate SEM (Scanning Electron Microscope) images of the surface of the crystal during the formation of the nitride semiconductor layer 55. FIG. 8A corresponds to the nitride semiconductor wafer 110 (and the semiconductor element 210) according to the embodiment. FIG. 8B corresponds to a reference example. In the reference example, the second film Lbf and the third film Lcf are not formed.

  FIG. 8A shows the surface of the sample after the formation of the second film Lbf in the embodiment. The grains in the image correspond to the shape of the island-shaped first film Laf. Portions other than the grains in the image correspond to the second film Lbf grown from the surface not covered with the first film Laf. As can be seen from FIG. 8B, in the embodiment, the size of the grains is about 0.2 micrometers (μm) or more and about 1 μm or less.

  As can be seen from FIG. 8B, in the reference example, the grain size is often about 0.1 μm, and the grain size is small. In the reference example, the dislocation density is high.

  In the embodiment, the first thickness t1 of the first lower layer LA1 is, for example, not less than 10 nm and not more than 500 nm. The second thickness t1 of the first intermediate layer LB2 is, for example, not less than 200 nm and not more than 800 nm, and is thicker than the first thickness t1. The third thickness t3 of the first upper layer LC1 is, for example, not less than 100 nm and not more than 800 nm, and is thinner than the second thickness t2.

  The first thickness t1 is, for example, not less than 10 nm and less than 350 nm. The second thickness t2 is, for example, not less than 350 nm and not more than 800 nm. The third thickness t3 is, for example, not less than 100 nm and less than 350 nm.

The Si concentration (first concentration C1) in the first lower layer LA1 is, for example, 1 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²² cm ⁻³ . The Si concentration (second concentration C2) in the first intermediate layer LB1 is, for example, 2 × 10 ¹⁷ cm ⁻³ or more and less than 1 × 10 ¹⁹ cm ⁻³ . The Si concentration (third concentration C3) in the first upper layer LC1 is, for example, less than 2 × 10 ¹⁷ cm ⁻³ .

  In the embodiment, as described with reference to FIG. 5B, for example, Si is introduced at a high concentration in at least a part of the formation of the first lower layer LA1. For example, in the formation of the first intermediate layer LB1 (for example, the formation of the second film Lbf and the third film Lcf), Si may not be introduced. For example, after the second time tm2 (for example, the second time tm2 to the third time tm3), the second high temperature T2 (a relatively high temperature equal to or higher than the first temperature T1) is applied. In this high temperature second temperature T2, the growth mode changes from the vertical direction to the horizontal direction, and Si atoms contained in the first film Laf are taken into the second film Lbf. Further, Si atoms are further taken into the third film Lcf. As a result, Si is taken into the first intermediate layer LB1 by the second film Lbf and the third film Lcf. Thereby, the second concentration C2 is obtained in the first intermediate layer LB1. When such a process is performed, the Si concentration in the first middle layer LB1 changes in the thickness direction.

  As shown in FIG. 3A, the first middle layer LB1 includes a first lower portion LBa1 and a first upper portion LBb1. The first upper portion LBb1 is provided between the first lower portion LBa1 and the first upper layer LC1. At this time, the Si concentration in the first lower portion LBa1 is higher than the Si concentration in the first upper portion LBb1.

  In this manner, a Si concentration distribution is formed in the first intermediate layer LB1. In such a case, the Si concentration (second concentration C2) in the first intermediate layer LB1 can be, for example, the average of the Si concentration in the first lower portion LBa1 and the Si concentration in the first upper portion LBb1. .

  For example, the change rate of the Si concentration with respect to the thickness in the first lower portion LBa1 is lower than the change rate of the Si concentration with respect to the thickness in the first upper portion LBb1.

  In the present embodiment, for example, GaN is used for the first lower layer LA1, the first middle layer LB1, and the first upper layer LC1. AlGaN may be used for the first lower layer LA1, the first middle layer LB1, and the first upper layer LC1.

The first lower layer LA1 may be, for example, Al _xa1 In _ya1 Ga _1-xa1-ya1 N (0 <xa1 ≦ 1, 0 ≦ ya1 <1). First intermediate layer LB1, for _{example, Al xb1 In yb1 Ga 1-} xb1-yb1 N (0 <xb1 ≦ 1,0 ≦ yb1 <1) may be used. The first upper layer LC1 may be, for example, Al _xc1 In _yc1 Ga _1-xc1-yc1 N (0 <xc1 ≦ 1, 0 ≦ yc1 <1).

  xb1 is the same as xa1, for example. xb1 may be different from xa1. xc1 is the same as xa1, for example. xc1 may be different from xa1. xc1 is the same as xb1, for example. xc1 may be different from xb1.

  For example, yb1 is the same as ya1. yb1 may be different from ya1. For example, yc1 is the same as ya1. yc1 may be different from ya1. yc1 is the same as yb1, for example. yc1 may be different from yb1.

  In the present embodiment, the lattice constant of the first upper layer LC1 may be set larger than the lattice constant of the first intermediate layer LB1. The lattice constant of the first intermediate layer LB1 may be set larger than the lattice constant of the first lower layer LA1. That is, the lattice constant is increased from the bottom to the top. A compressive stress is applied to the first upper layer LC1. A compressive stress is applied to the first middle layer LB1.

  For example, when silicon is used as the substrate 50, nitriding occurs when the temperature of the nitride semiconductor layer 55 is increased from room temperature to room temperature due to a difference in thermal expansion coefficient between the silicon and the nitride semiconductor layer 55. A tensile stress may be applied to the physical semiconductor layer 55 to cause a crack.

  In such a case, by adopting a configuration in which compressive stress is applied to the first upper layer LC1 and compressive stress is applied to the first middle layer LB1, compressive stress (compressive strain) is applied to the nitride semiconductor layer 55 during crystal growth. store. Thereby, the crack resulting from the difference in a thermal expansion coefficient can be suppressed, for example.

  In the present embodiment, for example, a low temperature growth AlN layer to be the first underlayer 51a is formed on the main surface 50a of the silicon substrate 50, for example. The formation temperature of the first foundation layer 51a is, for example, 900 ° C. or less. The formation temperature of the first foundation layer 51a is, for example, about 700 ° C. The thickness of the first foundation layer 51a is, for example, 30 nm. If necessary, a second underlayer 51b (for example, an AlGaN layer) is formed on the first underlayer 51a. If necessary, a third underlayer 51c (for example, a GaN layer) is formed on the second underlayer 51b. Thereby, the foundation layer 51 is formed. The nitride semiconductor layer 55 is formed on the base layer 51.

  In the embodiment, an n-type GaN layer to be the n-type semiconductor layer 10 is formed on the nitride semiconductor layer 55, for example. The formation temperature of the n-type semiconductor layer 10 is 1100 ° C., for example. The n-type semiconductor layer 10 is doped with, for example, Si. The n-type semiconductor layer 10 has a thickness of 2 μm, for example.

A light emitting layer 30 is formed on the n-type semiconductor layer 10. In the formation of the light emitting layer 30, for example, an In _0.15 Ga _0.85 N layer that becomes the well layer 32 and a GaN layer that becomes the barrier layer 31 are stacked at a temperature of, for example, 700 ° C. or more and 900 ° C. or less. .

  A p-type GaN layer to be the p-type semiconductor layer 20 is formed on the light emitting layer 30. The p-type semiconductor layer 20 is doped with Mg. The formation temperature of the p-type semiconductor layer 20 is, for example, 950 ° C.

  Thereby, the nitride semiconductor wafer 110 according to the present embodiment is formed. Further, after forming the p-side electrode and the n-side electrode, the semiconductor element 210 (semiconductor light emitting element) is formed by dividing into individual elements.

(Second Embodiment)
FIG. 9 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor wafer according to the second embodiment.
FIG. 9 also illustrates the configuration of the semiconductor element 211 according to this embodiment.
As shown in FIG. 9, the nitride semiconductor wafer 111 (and the semiconductor element 211) according to this embodiment is also provided with the substrate 50 and the nitride semiconductor layer 55. In the present embodiment, the nitride semiconductor layer 55 further includes a second stacked body SL2 in addition to the first stacked body SL1. As described above, the nitride semiconductor layer 55 is provided with a plurality of stacked bodies. Since the other configuration is the same as that of the first embodiment, the description thereof is omitted.

  In this example, the nitride semiconductor layer 55 further includes a third stacked body SL3. The number of stacked bodies provided in the nitride semiconductor layer 55 is, for example, 2 or more and 10 or less. However, the number is arbitrary.

  The second stacked body SL2 includes a second lower layer LA2 of nitride semiconductor, a second middle layer LB2 of nitride semiconductor, and a second upper layer LC2 of nitride semiconductor.

  The second lower layer LA2 is provided on the first upper layer LC1. The second lower layer LA2 contains Si at a fourth concentration and has a fourth thickness t4.

  The second intermediate layer LB2 is provided on and in contact with the second lower layer LA2 on the second lower layer LA2. The second intermediate layer LB2 contains Si at the fifth concentration and has the fifth thickness t5. The fifth concentration is lower than the fourth concentration. The fifth thickness t5 is thicker than the fourth thickness t4.

  The second upper layer LC2 is provided on and in contact with the second intermediate layer LB2 on the second intermediate layer LB2. The second upper layer LC2 contains Si at a sixth concentration and has a sixth thickness t6. The sixth concentration is lower than the fifth concentration. For example, the sixth thickness t6 is thicker than the fourth thickness t4. For example, the sixth thickness t6 is thicker than the fifth thickness t5. The sixth thickness t6 may be, for example, the fifth thickness t5 or less.

  The third stacked body SL3 includes a third lower layer LA3 of nitride semiconductor, a third middle layer LB3 of nitride semiconductor, and a third upper layer LC3 of nitride semiconductor.

  The third lower layer LA3 is provided on the second upper layer LC2. The third lower layer LA3 contains Si at a seventh concentration and has a seventh thickness.

  The third middle layer LB3 is provided on and in contact with the third lower layer LA3 on the third lower layer LA3. The third middle layer LB3 contains Si at an eighth concentration and has an eighth thickness. The eighth concentration is lower than the seventh concentration. The eighth thickness is thicker than the seventh thickness.

  The third upper layer LC3 is provided on and in contact with the third middle layer LB3 on the third middle layer LB3. The third upper layer LC3 contains Si at the ninth concentration and has a ninth thickness. The ninth concentration is lower than the eighth concentration. For example, the ninth thickness is thicker than the seventh thickness. For example, the ninth thickness is thicker than the eighth thickness. For example, the ninth thickness may be equal to or less than the eighth thickness.

  For example, the configurations of the second lower layer LA2, the second middle layer LB2, and the second upper layer LC2 may be the same as or different from the configurations of the first lower layer LA1, the first middle layer LB1, and the first upper layer LC1, respectively. You may employ | adopt the same structure from the simplicity of a manufacturing process.

  For example, the configurations of the third lower layer LA3, the third middle layer LB3, and the third upper layer LC3 may be the same as or different from the configurations of the first lower layer LA1, the first middle layer LB1, and the first upper layer LC1, respectively. You may employ | adopt the same structure from the simplicity of a manufacturing process.

  In the present embodiment, the manufacturing conditions of the first stacked body SL1 and its modifications can be applied to the manufacturing conditions of the second stacked body SL2 and the third stacked body SL3. Also in this embodiment, the dislocation density can be reduced. By providing a plurality of stacked bodies, the dislocation density can be further reduced as compared with the case of providing a single stacked body.

  In the embodiment, by providing a plurality of stacked bodies, at least a part of the nitride semiconductor layer 55 can function as an n-type semiconductor. Therefore, in this embodiment, when the functional layer 40 is provided on the nitride semiconductor layer 55, the n-type semiconductor layer provided on the functional layer 40 can be omitted.

FIG. 10 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor wafer according to the second embodiment.
FIG. 10 also illustrates the configuration of the semiconductor element 211 according to this embodiment.
As shown in FIG. 10, in the nitride semiconductor wafer 111 (and the semiconductor element 211) according to the present embodiment, the provided functional layer 40 includes a nitride semiconductor light emitting layer 30 and a nitride semiconductor p-type semiconductor layer. 20 and. In this example, the light emitting layer 30 is in contact with the nitride semiconductor layer 55.

  The light emitting layer 30 is provided on the nitride semiconductor layer 55 described above. The p-type semiconductor layer 20 is provided on the light emitting layer 30. A nitride semiconductor layer 55 containing Si is used as the n-type semiconductor layer. With this configuration, the process can be omitted.

(Third embodiment)
The third embodiment relates to a semiconductor element.
The semiconductor element according to the embodiment includes, for example, a semiconductor light emitting element, a semiconductor light receiving element, and an electronic device. The semiconductor device according to the embodiment is manufactured based on the wafer according to the first embodiment and the second embodiment.

  The semiconductor element according to the third embodiment includes, for example, the semiconductor element 210 described with respect to the first embodiment and the semiconductor element 211 described with respect to the second embodiment. Below, another example is demonstrated regarding this embodiment.

FIG. 11 is a schematic cross-sectional view illustrating the configuration of a semiconductor element according to the third embodiment.
As shown in FIG. 11, the semiconductor element 212 according to this embodiment includes the nitride semiconductor layer 55 according to the above-described embodiment and the functional layer 40. The functional layer 40 is formed on the nitride semiconductor layer 55. That is, in this example, after the nitride semiconductor layer 55 and the functional layer 40 are formed, the substrate 50 (and the base layer 51) is removed.

  In this example, the nitride semiconductor layer 55 is provided with a plurality of stacked bodies (a first stacked body SL1, a second stacked body SL2, a third stacked body SL3, and the like). The surface of the nitride semiconductor layer 55 is provided with unevenness 55ue. The nitride semiconductor layer 55 has an upper surface 55u facing the functional layer 40, and a lower surface 55l opposite to the upper surface. The unevenness 55ue is provided on the lower surface 55l.

  The depth of the unevenness 55 ue is, for example, ½ or more of the wavelength of light emitted from the light emitting layer 30 provided in the functional layer 40. The depth of the unevenness 55ue is, for example, 200 nm or more. The depth of the unevenness 55 ue is not more than 5 times the wavelength of the light emitted from the light emitting layer 30. The depth of the unevenness 55ue is, for example, 2 μm or less.

  By providing the unevenness 55 ue, the traveling direction of the light emitted from the light emitting layer 30 can be changed. Thereby, the light extraction efficiency is improved.

FIG. 12 is a schematic cross-sectional view illustrating the configuration of the semiconductor element according to the third embodiment.
As shown in FIG. 12, in the semiconductor element 213 according to the present embodiment, the n-type semiconductor layer 10 has a first portion 11 and a second portion 12. The second portion 12 is aligned with the first portion 11 along a direction perpendicular to the Z-axis direction. A light emitting layer 30 is provided on the second portion 12. A p-type semiconductor layer 20 is provided on the light emitting layer 30.

  On the 1st part 11, the 1st electrode 10e electrically connected to the 1st part 11 is provided. A second electrode 20 e electrically connected to the p-type semiconductor layer 20 is provided on the p-type semiconductor layer 20 on the second portion 12. A current is supplied to the light emitting layer 30 via the first electrode 10 e and the second electrode 20 e, and light is emitted from the light emitting layer 30.

FIG. 13 is a schematic cross-sectional view illustrating the configuration of the semiconductor element according to the third embodiment.
As shown in FIG. 13, in the semiconductor element 214 according to this embodiment, the n-type semiconductor layer 10 is omitted from the functional layer 40. The nitride semiconductor layer 55 functions as an n-type semiconductor layer.

  The nitride semiconductor layer 55 has a first portion 55p and a second portion 55q. The second portion 55q is aligned with the first portion 55p along a direction perpendicular to the Z-axis direction. The light emitting layer 30 is provided on the second portion 55p. A p-type semiconductor layer 20 is provided on the light emitting layer 30. In this example, the light emitting layer 30 is in contact with the nitride semiconductor layer 55 (second portion 55q).

  A first electrode 10e electrically connected to the first portion 55p is provided on the first portion 55p. On the p-type semiconductor layer 20 on the second portion 55q, the second electrode 20e electrically connected to the p-type semiconductor layer 20 is provided.

  In the semiconductor elements 212, 213, and 214 according to this embodiment, there are few dislocations in the nitride semiconductor layer 55, and as a result, there are also few dislocations in the functional layer 40. Thereby, for example, characteristics with high efficiency (for example, light emission efficiency) can be obtained.

FIG. 14 is a schematic cross-sectional view illustrating the configuration of the semiconductor element according to the third embodiment.
As shown in FIG. 14, in the semiconductor element 220 according to this embodiment, an n-type semiconductor layer 71, an undoped semiconductor layer 71 a, and an upper semiconductor layer 72 are provided as the functional layer 40. Further, the semiconductor element 220 further includes a source electrode 73, a drain electrode 74, and a gate electrode 75.

  The n-type semiconductor layer 71 is provided on the nitride semiconductor layer 55. The undoped semiconductor layer 71 a is provided on the n-type semiconductor layer 71. The upper semiconductor layer 72 is provided on the undoped semiconductor layer 71a. The band gap energy of the upper semiconductor layer 72 is larger than the band gap energy of the n-type semiconductor layer 71.

  The undoped semiconductor layer 71a becomes a channel layer. The upper semiconductor layer 72 becomes a barrier layer. For example, the upper semiconductor layer 72 has a heterojunction with the undoped semiconductor layer 71a.

The n-type semiconductor layer 71 includes, for example, undoped Al _α Ga _1-α N (0 ≦ α ≦ 1) that does not contain impurities. The undoped semiconductor layer 71 a includes, for example, Al _α Ga _1-α N (0 ≦ α ≦ 1) having the same Al composition as the n-type semiconductor layer 71. The upper semiconductor layer 72 includes, for example, _{Al β Ga 1-β N (} 0 ≦ β ≦ 1, α <β) of undoped or n-type a. For example, an undoped GaN layer is used for the n-type semiconductor layer 71. For the upper semiconductor layer 72, an undoped or n-type AlGaN layer is used.

  A source electrode 73, a drain electrode 74, and a gate electrode 75 are provided on the upper semiconductor layer 72. The drain electrode 74 is separated from the source electrode 73. The source electrode 73 and the drain electrode 74 are in ohmic contact with the surface of the upper semiconductor layer 72. A gate electrode 75 is provided between the source electrode 73 and the drain electrode 74. The gate electrode 75 is in Schottky contact with the surface of the upper semiconductor layer 72.

  The lattice constant of the upper semiconductor layer 72 is smaller than the lattice constant of the undoped semiconductor layer 71a. As a result, distortion occurs in the upper semiconductor layer 72. Piezoelectric polarization occurs in the upper semiconductor layer 72 due to the piezoelectric effect. As a result, a two-dimensional electron gas 71g is formed in the vicinity of the interface between the undoped semiconductor layer 71a and the upper semiconductor layer 72.

  In the semiconductor element 220, by controlling the gate voltage applied to the gate electrode 75, the concentration of the two-dimensional electron gas 71g under the gate electrode 75 changes, and the current flowing between the source electrode 73 and the drain electrode 74 is controlled. Is done. The semiconductor element 220 is, for example, a HEMT (High Electron Mobility Transistor).

  In the semiconductor element 220, there are few dislocations in the nitride semiconductor layer 55, and as a result, there are also few dislocations in the functional layer 40. As a result, the performance is stabilized and the reliability can be improved.

(Fourth embodiment)
The present embodiment relates to a method for forming a nitride semiconductor layer.
In the present manufacturing method, for example, the processes described with reference to FIGS. 4, 5A to 5F, and FIGS. 6A to 6E are performed.

  The manufacturing method includes a step (step S101) of forming the nitride semiconductor layer 55 including the first stacked body SL1 on the main surface 50a of the substrate 50.

  The first stacked body SL1 includes the first lower layer LA1, the first intermediate layer LB1, and the first upper layer LC1.

  The formation of the nitride semiconductor layer 55 (step S101) includes the step of forming the first lower layer LA1 (step S110), the step of forming the first middle layer LB1 (step S120), and the step of forming the first upper layer LC1 (step S120). Step S130).

  In step S110, the first lower layer LA1 is formed with the first V / III ratio R1 and the first temperature T1.

  In step S120, at least a part of the first intermediate layer LB1 is formed on the first lower layer LA1 in contact with the first lower layer LA1 with the second V / III ratio R2 and the second temperature T2. The second V / III ratio R2 is lower than the first V / III ratio R1.

  In step S130, the first upper layer LC1 is formed on the first intermediate layer LB1 in contact with the first intermediate layer LB2 at the third V / III ratio R3 and the third temperature T3. The third V / III ratio R3 is lower than the first V / III ratio R1 and higher than the second V / III ratio R2. The third temperature T3 is higher than the second temperature T2.

  Thereby, the dislocation density can be reduced in the nitride semiconductor layer 55.

  In the present embodiment, the first lower layer LA1 is formed by forming a first film Laf containing Si to be the first lower layer LA1 in a discontinuous island shape on the base layer 51 formed on the main surface 50a. Including doing.

  The formation of the first intermediate layer LB1 includes formation of the second film Lbf of the nitride semiconductor and formation of the third film Lcf of the nitride semiconductor. In forming the second film Lbf, the second film Lbf is formed on the base layer 51 not covered with the discontinuous island-shaped first film. The third film Lcf is formed by growing a third film Lcf containing a nitride semiconductor on the second film Lbf in a direction parallel to the main surface 50a, and then forming the first film Laf into the third film Lcf. Cover with.

  In this manufacturing method, the dislocation density in the first upper layer LC1 is lower than the dislocation density in the first lower layer LA1.

  In the present manufacturing method, the formation of the first intermediate layer LB1 is performed such that at least a part of dislocations included in the first intermediate layer LB1 is moved from the bottom to the top in a direction along the direction perpendicular to the main surface 50a. Bending in the direction along

  The formation of the first upper layer LC1 bends at least a part of dislocations included in the first upper layer LC1 from the direction along the main surface 50a from the direction perpendicular to the main surface 50a from the bottom to the top. You may include that.

In the manufacturing method, the nitride semiconductor layer 55 may further include a second stacked body SL2 provided on the first stacked body SL1.
The second stacked body SL2 includes a second lower layer LA2 of nitride semiconductor, a second middle layer LB2 of nitride semiconductor, and a second upper layer LC2 of nitride semiconductor. The second lower layer LA2 is provided on the first upper layer LC1. The second lower layer LA2 contains Si at a fourth concentration and has a fourth thickness t4. The second intermediate layer LB2 is provided on and in contact with the second lower layer LA2 on the second lower layer LA2. The second intermediate layer LB2 contains Si at a fifth concentration lower than the fourth concentration, and has a fifth thickness t5 that is thicker than the fourth thickness t4. The second upper layer LC2 is provided on and in contact with the second intermediate layer LB2 on the second intermediate layer LB2. The second upper layer LC2 contains Si at a sixth concentration lower than the fifth concentration, and has a sixth thickness t6.

  At this time, the formation of the nitride semiconductor layer 55 further includes formation of the second lower layer LA2, formation of the second middle layer LB2, and formation of the second upper layer LC2.

  In the formation of the second lower layer LA2, the second lower layer LA2 is formed with the fourth V / III ratio and the fourth temperature.

  The second middle layer LB2 is formed on the second lower layer LA2 in contact with the second lower layer LA2 so that at least a part of the second middle layer LB2 has a fifth V / III ratio lower than the fourth V / III ratio. And a fifth temperature not lower than the fourth temperature.

  The second upper layer LC2 is formed on the second middle layer LB2 in contact with the second middle layer LB2 so that the second upper layer LC2 is lower than the fourth V / III ratio and higher than the fifth V / III ratio. 6 and a sixth temperature higher than the fifth temperature.

  Thereby, dislocations can be further reduced in the second stacked body SL2.

  Thus, in this embodiment, you may form a some laminated body. In this case, in the formation of the first film Laf in the upper stacked body (for example, the second stacked body SL2), the base layer is the lower stacked body (the first stacked body SL1). 1 upper layer LC1). For example, in the formation of the first film Laf in the third stacked body SL3, the base layer is the second stacked body SL2, specifically, the second upper layer LC2.

  In the embodiment, the semiconductor layer is grown by, for example, metal-organic chemical vapor deposition (MOCVD) method, metal-organic vapor phase epitaxy (MOVPE) method, molecular beam epitaxy. (Molecular Beam Epitaxy: MBE) method, halide vapor phase epitaxy method (HVPE) method and the like can be used.

For example, when the MOCVD method or the MOVPE method is used, the following can be used as raw materials for forming each semiconductor layer. For example, TMGa (trimethyl gallium) and TEGa (triethyl gallium) can be used as the Ga raw material. As a source of In, for example, TMIn (trimethylindium), TEIn (triethylindium), or the like can be used. As a raw material for Al, for example, TMAl (trimethylaluminum) can be used. As a raw material of N, for example, NH ₃ (ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine) and the like can be used.

For example, the following can be used as the impurity source. For example, silane (SiH ₄ ) can be used as the Si source gas. As a raw material of Mg, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) can be used. For example, tricarbonyl manganese (MMT) can be used as a raw material of Mn. For example, iron carbonyl (Fe (CO) ₅ ) or ferrocene (Cp ₂ Fe) can be used as a raw material for Fe. As a raw material for oxygen (O), for example, oxygen plasma can be used.

  According to the embodiment, a semiconductor device, a nitride semiconductor wafer, and a method for forming a nitride semiconductor layer with few dislocations are provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

  The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, a substrate, nitride semiconductor layer, laminate, lower layer, middle layer, upper layer, functional layer, n-type semiconductor layer, light emitting layer, p-type semiconductor layer, underlayer, and electrode included in a nitride semiconductor wafer or semiconductor element With regard to the specific configuration of each element such as those described above, the present invention is similarly implemented by appropriately selecting from the well-known ranges by those skilled in the art, and is included in the scope of the present invention as long as similar effects can be obtained. .

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, based on the semiconductor element, nitride semiconductor wafer, and nitride semiconductor layer forming method described above as embodiments of the present invention, all semiconductor elements and nitrides that can be implemented by those skilled in the art with appropriate design changes The semiconductor semiconductor wafer and the method of forming the nitride semiconductor layer also belong to the scope of the present invention as long as they include the gist of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... n-type semiconductor layer, 10e ... 1st electrode, 11 ... 1st part, 12 ... 2nd part, 20 ... p-type semiconductor layer, 20e ... 2nd electrode, 30 ... Light emitting layer, 31 ... Barrier layer, 32 ... Well layer 40 ... Functional layer 50 ... Substrate 50a ... Main surface 51 ... Base layer 51a-51c ... First to third base layers 55 ... Nitride semiconductor layer 55l ... Bottom surface 55p ... First part 55q ... second part, 55u ... upper surface, 55ue ... concave, 71 ... n-type semiconductor layer, 71a ... undoped semiconductor layer, 71g ... two-dimensional electron gas, 72 ... upper semiconductor layer, 73 ... source electrode, 74 ... drain electrode 75 ... gate electrode 110, 111, 119 ... nitride semiconductor wafer, 210-214, 220 ... semiconductor element, C (Si) ... concentration, C1-C3 ... first to third concentration, D ... depth F0 (III), F1 (III), F2 (III), F3 (III) ... flow rate, F0 (V), F1 (V), F2 (V), F3 (V) ... flow rate, F (Si) ... flow rate , LA1 to LA3 ... first to third lower layers, LB1 to LB3 ... first to third middle layers, LBa1 ... first lower portion, LBb1 ... first upper portion, LC1 to LC3 ... first to third upper layers, Laf ... 1st film, Lbf ... 2nd film, Lcf ... 3rd film, R (V / III), R0 ... V / III ratio, R1-R3 ... 1st-3rd ratio, SL1-SL3 ... 1st- 3rd laminated body, T, T0 ... Film-forming temperature, T1-T3 ... 1st-3rd temperature, t ... Time, t1-t6 ... 1st-6th thickness, tm1-tm4 ... 1st-4th Times of Day

Claims (9)

A first stacked body provided on and in contact with an underlayer including at least one of AlN and AlGaN provided on a main surface of a silicon substrate,
Having a first thickness and containing Si at a first concentration, and contact to the underlying _{layer, Al xa1 In ya1 Ga 1-} xa1-ya1 N first (0 <xa1 ≦ 1,0 ≦ ya1 <1) The lower layer,
Contains Si at low second concentration than the first concentration is provided in contact with the first lower layer on the first lower layer have a thick second thickness than said first thickness Al _xb1 In _yb1 Ga _{A first intermediate layer of 1-xb1-yb1} N (0 <xb1 ≦ 1, 0 ≦ yb1 <1) ;
Have a third thickness containing Si in the third concentration is lower than the second concentration is provided in contact with the first intermediate layer on the first intermediate layer _{Al xc1 In yc1 Ga 1-xc1} -yc1 N ( A first upper layer of 0 <xc1 ≦ 1, 0 ≦ yc1 <1) ;
A nitride semiconductor functional layer provided on the nitride semiconductor layer including the first stacked body including:
Xb1 is different from xa1,
Xc1 is different from xa1,
Xc1 is different from xb1,
The first thickness is not less than 10 nanometers and less than 350 nanometers;
The second thickness is not less than 200 nanometers and not more than 800 nanometers and is thicker than the first thickness,
The third thickness is not less than 100 nanometers and not more than 800 nanometers, and is thinner than the second thickness,
The first concentration is 1 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²² cm ⁻³ ,
The second concentration is 2 × 10 ¹⁷ cm ⁻³ or more and less than 1 × 10 ¹⁹ cm ⁻³ ,
The third concentration is less than 2 × 10 ¹⁷ cm ⁻³ ;
The first lower layer includes a discontinuous island-shaped portion including Si provided on and in contact with the base layer,
At least a part of the dislocations in at least a part of the first middle layer and the first upper layer bends from the direction along the main surface from the direction perpendicular to the main surface from the bottom to the top,
The lattice constant of the first upper layer is larger than the lattice constant of the first middle layer,
The semiconductor element in which the lattice constant of the first middle layer is larger than the lattice constant of the first lower layer.   The semiconductor element according to claim 1, wherein a dislocation density in the functional layer is lower than a dislocation density in the first lower layer. The first middle layer includes a first lower portion, and a first upper portion provided between the first lower portion and the first upper layer,
3. The semiconductor device according to claim 1, wherein a concentration of Si in the first lower portion is higher than a concentration of Si in the first upper portion. The nitride semiconductor layer is
A second lower layer of nitride semiconductor provided on the first upper layer and containing Si at a fourth concentration and having a fourth thickness;
A nitride semiconductor first layer provided on the second lower layer and in contact with the second lower layer and containing Si at a fifth concentration lower than the fourth concentration and having a fifth thickness greater than the fourth thickness. 2 middle layers,
A second upper layer of nitride semiconductor provided on and in contact with the second intermediate layer and containing Si at a sixth concentration lower than the fifth concentration and having a sixth thickness;
The semiconductor element according to claim 1, further comprising a second laminate including The functional layer is
An n-type nitride semiconductor layer provided on the nitride semiconductor layer;
An undoped nitride semiconductor layer provided on the n-type semiconductor layer;
An upper nitride semiconductor layer provided on the undoped nitride semiconductor layer;
The semiconductor element of any one of Claims 1-4 containing. A silicon substrate having a main surface;
An underlayer containing at least one of AlN and AlGaN provided on the main surface;
A first laminated body provided on and in contact with the underlayer,
Having a first thickness and containing Si at a first concentration, and contact to the underlying _{layer, Al xa1 In ya1 Ga 1-} xa1-ya1 N first (0 <xa1 ≦ 1,0 ≦ ya1 <1) The lower layer,
Contains Si at low second concentration than the first concentration is provided in contact with the first lower layer on the first lower layer have a thick second thickness than said first thickness Al _xb1 In _yb1 Ga _{A first intermediate layer of 1-xb1-yb1} N (0 <xb1 ≦ 1, 0 ≦ yb1 <1) ;
Have a third thickness containing Si in the third concentration is lower than the second concentration is provided in contact with the first intermediate layer on the first intermediate layer _{Al xc1 In yc1 Ga 1-xc1} -yc1 N ( A first upper layer of 0 <xc1 ≦ 1, 0 ≦ yc1 <1) ;
A nitride semiconductor layer including a first stacked body including:
With
Xb1 is different from xa1,
Xc1 is different from xa1,
Xc1 is different from xb1,
The first thickness is not less than 10 nanometers and less than 350 nanometers;
The second thickness is not less than 200 nanometers and not more than 800 nanometers and is thicker than the first thickness,
The third thickness is not less than 100 nanometers and not more than 800 nanometers, and is thinner than the second thickness,
The first concentration is 1 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²² cm ⁻³ ,
The second concentration is 2 × 10 ¹⁷ cm ⁻³ or more and less than 1 × 10 ¹⁹ cm ⁻³ ,
The third concentration is less than 2 × 10 ¹⁷ cm ⁻³ ;
The first lower layer includes a discontinuous island-shaped portion including Si provided on and in contact with the base layer,
At least a part of the dislocations in at least a part of the first middle layer and the first upper layer bends from the direction along the main surface from the direction perpendicular to the main surface from the bottom to the top,
The lattice constant of the first upper layer is larger than the lattice constant of the first middle layer,
The nitride semiconductor wafer, wherein the lattice constant of the first intermediate layer is larger than the lattice constant of the first lower layer.   The nitride semiconductor wafer according to claim 6, wherein a dislocation density in the first upper layer is lower than a dislocation density in the first lower layer. The first middle layer includes a first lower portion, and a first upper portion provided between the first lower portion and the first upper layer,
The nitride semiconductor wafer according to claim 6 or 7, wherein a concentration of Si in the first lower portion is higher than a concentration of Si in the first upper portion. The nitride semiconductor layer is
A second lower layer of nitride semiconductor provided on the first upper layer and containing Si at a fourth concentration and having a fourth thickness;
A nitride semiconductor first layer provided on the second lower layer and in contact with the second lower layer and containing Si at a fifth concentration lower than the fourth concentration and having a fifth thickness greater than the fourth thickness. 2 middle layers,
A second upper layer of nitride semiconductor provided on and in contact with the second intermediate layer and containing Si at a sixth concentration lower than the fifth concentration and having a sixth thickness;
The nitride semiconductor wafer according to claim 6, further comprising a second laminate including