JP5597663B2 - Semiconductor light emitting device, nitride semiconductor wafer, and method of manufacturing nitride semiconductor layer - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor light emitting device, a nitride semiconductor wafer, and a method for manufacturing a nitride semiconductor layer.

  In semiconductor light emitting devices using nitride semiconductors such as LDs (Laser Diodes), LEDs (Light Emitting Diodes), and HEMTs (High Electron Mobility Transistors), the degradation of the nitride semiconductor layer that occurs during the process from crystal growth to mounting, There is a demand for suppression of destruction.

  For example, when a nitride semiconductor layer is grown on a silicon substrate, various configurations such as a structure in which the composition is continuously inclined and a superlattice structure in which two layers having different compositions are alternately stacked have been proposed. However, the conventional method is insufficient in terms of suppressing deterioration and destruction of the nitride semiconductor layer, and there is room for improvement.

JP 2009-158804 A

  Embodiments of the present invention provide a semiconductor light emitting device, a nitride semiconductor wafer, and a method for manufacturing a nitride semiconductor layer in which deterioration and destruction of the semiconductor layer are suppressed.

According to an embodiment of the present invention, a semiconductor light emitting device including an underlayer, a first semiconductor layer, a light emitting unit, and a second semiconductor layer is provided. The foundation layer is formed on a silicon substrate. The first semiconductor layer is provided on the base layer and includes a nitride semiconductor and has a first conductivity type. The light emitting unit is provided on the first semiconductor layer. The light emitting unit includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers and containing Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1). The second semiconductor layer is provided on the light emitting unit and has a second conductivity type that includes a nitride semiconductor and is different from the first conductivity type. The underlayer includes an AlN buffer layer formed on the silicon substrate, an AlGaN buffer layer formed on the AlN buffer layer, a GaN layer formed on the AlGaN buffer layer, and the GaN An Al-containing intermediate layer formed on the layer and having a thickness of 2 nm to 100 nm and including AlN. The said Al containing intermediate | middle layer has a dot-shaped uneven | corrugated | grooved part provided in the surface by the side of the said 1st semiconductor layer.
According to another embodiment of the present invention, a silicon substrate, a base layer provided on the silicon substrate, a first semiconductor of a first conductivity type provided on the base layer and including a nitride semiconductor. And a light emitting portion provided on the first semiconductor layer, the Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1) provided between the plurality of barrier layers and the plurality of barrier layers. A well layer including a light emitting portion, and a second semiconductor layer that is provided on the light emitting portion and has a second conductivity type that includes a nitride semiconductor and is different from the first conductivity type, and The underlayer includes an AlN buffer layer formed on the silicon substrate, an AlGaN buffer layer formed on the AlN buffer layer, a GaN layer formed on the AlGaN buffer layer, and the GaN layer. 100 Na 2 nm or more is formed on the An Al-containing intermediate layer containing AlN , and the Al-containing intermediate layer has a dot-shaped uneven portion provided on the surface on the first semiconductor layer side. A nitride semiconductor wafer is provided.
According to another embodiment of the present invention, an AlN buffer layer on a silicon substrate, an AlGaN buffer layer formed on the AlN buffer layer, and a GaN layer formed on the AlGaN buffer layer; A step of forming an underlayer including an Al-containing intermediate layer formed on the GaN layer and having an Al-containing intermediate layer having a thickness of 2 to 100 nanometers , and on the underlayer, A step of forming a first semiconductor layer of a first conductivity type including a nitride semiconductor; a plurality of barrier layers on the first semiconductor layer; and Ga ₁₋ disposed between the plurality of barrier layers. a step of forming a light emitting portion including a well layer including _z1 In _z1 N (0 <z1 ≦ 1), and a second conductivity different from the first conductivity type including a nitride semiconductor on the light emitting portion. Forming a second semiconductor layer having a shape; Wherein the Al-containing intermediate layer, the manufacturing method of the nitride semiconductor layer and having a dot-like uneven portion provided on a surface side of said first semiconductor layer is provided.

1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a part of a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a part of a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. FIG. 5A and FIG. 5B are Nomarski microscope images showing the characteristics of the semiconductor light emitting device. It is an electron micrograph image which shows the characteristic of the semiconductor light-emitting device concerning a 1st embodiment. FIG. 7A and FIG. 7B are schematic cross-sectional views showing other semiconductor light emitting devices according to the first embodiment. FIG. 8A and FIG. 8B are schematic cross-sectional views showing another semiconductor light emitting device according to the first embodiment. It is a typical sectional view showing a semiconductor light emitting element concerning a 2nd embodiment. It is a typical sectional view showing another semiconductor light emitting element concerning a 2nd embodiment. FIG. 11A and FIG. 11B are Nomarski microscope images showing the characteristics of the semiconductor light emitting device. 12A and 12B are schematic cross-sectional views showing another semiconductor light emitting device according to the second embodiment. FIGS. 13A and 13B are schematic cross-sectional views showing a nitride semiconductor wafer according to the third embodiment. FIG. 14 is a schematic cross-sectional view showing another nitride semiconductor wafer according to the third embodiment. FIG. 15A and FIG. 15B are flowcharts showing a method for manufacturing a nitride semiconductor layer according to the fourth embodiment. FIG. 16 is a flowchart showing another method for manufacturing a nitride semiconductor layer according to the fourth embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
The present embodiment relates to a semiconductor light emitting device such as a light emitting diode (LED) and a laser diode (LD).

  FIG. 1 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. As shown in FIG. 1, the semiconductor light emitting device 110 according to this embodiment includes a first semiconductor layer 10, a light emitting unit 30, a second semiconductor layer 20, and an In-containing intermediate layer 60.

  The first semiconductor layer 10 is formed on the silicon substrate 40 via the base layer 50. The first semiconductor layer 10 includes a nitride semiconductor and has a first conductivity type.

  The light emitting unit 30 is provided on the first semiconductor layer 10. The light emitting unit 30 is provided, for example, on the [0001] direction side of the first semiconductor layer 10. An example of the light emitting unit 30 will be described later.

  The second semiconductor layer 20 is provided on the light emitting unit 30. The second semiconductor layer 20 includes a nitride semiconductor and has a second conductivity type. The second conductivity type is a conductivity type different from the first conductivity type.

  For example, the first conductivity type is n-type and the second conductivity type is p-type. Alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type. In the following description, it is assumed that the first conductivity type is n-type and the second conductivity type is p-type.

  The In-containing intermediate layer 60 is provided between at least one of the first semiconductor layer 10 and the light emitting unit 30 and between the second semiconductor layer 20 and the light emitting unit 30. In this example, the In-containing intermediate layer 60 is provided between the first semiconductor layer 10 and the light emitting unit 30.

  Here, a direction from the first semiconductor layer 10 toward the light emitting unit 30 is a Z-axis direction. One axis perpendicular to the Z axis is taken as the X axis. A direction perpendicular to the Z axis and the X axis is taken as a Y axis.

  The first semiconductor layer 10, the light emitting unit 30, the second semiconductor layer 20, and the In-containing intermediate layer 60 included in the functional unit 10s of the semiconductor light emitting device 110 are stacked along the Z axis.

  In the specification of the application, “stacking” includes not only the case of being stacked in contact with each other but also the case of being stacked with another layer inserted therebetween. Further, “provided on” includes not only the case of being provided in direct contact but also the case of being provided with another layer interposed therebetween.

  The silicon substrate 40 is, for example, a Si (111) substrate. However, in the embodiment, the plane orientation of the silicon substrate 40 may not be the (111) plane. The surface orientation of the main surface of the silicon substrate 40 (the surface on which the underlayer 50 is formed) has various surface orientations such as (111), (110), and (100) and surfaces inclined from these surface orientations. be able to.

  The silicon substrate 40 may be removed (peeled) by any method after the functional unit 10 s is formed on the silicon substrate 40. The position where the silicon substrate 40 is peeled is, for example, in the underlayer 50 or in the functional unit 10s. Further, at least a part of the silicon substrate 40 may remain.

FIG. 2 is a schematic cross-sectional view illustrating the configuration of a part of the semiconductor light emitting element according to the first embodiment.
As shown in FIG. 2, the light emitting unit 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31. Each of the plurality of well layers 32 includes Ga _1-z1 In _z1 N (0 <z1 ≦ 1). The barrier layer 31 includes, for example, GaN. That is, the well layer 32 contains In, and the barrier layer 31 does not substantially contain In. Alternatively, the barrier layer 31 contains In at a composition ratio lower than the In composition ratio contained in the well layer 32. The band gap energy in the barrier layer 31 is larger than the band gap energy in the well layer 32.

  For example, a plurality of barrier layers 31 and a plurality of well layers 32 are alternately stacked along the Z axis.

  The light emitting unit 30 may have a single quantum well (SQW) configuration. At this time, the light emitting unit 30 includes two barrier layers 31 and a well layer 32 provided between the barrier layers 31. Alternatively, the light emitting unit 30 may have a multi quantum well (MQW) configuration. At this time, the light emitting unit 30 includes three or more barrier layers 31 and a well layer 32 provided between the barrier layers 31.

  That is, the light emitting unit 30 includes (n + 1) barrier layers 31 and n well layers 32 (n is an integer of 2 or more). The (i + 1) th barrier layer BL (i + 1) is disposed between the i-th barrier layer BLi and the second semiconductor layer 20 (i is an integer of 1 or more and (n−1) or less). The (i + 1) th well layer WL (i + 1) is disposed between the i-th well layer WLi and the second semiconductor layer 20. The first barrier layer BL1 is provided between the first semiconductor layer 10 and the first well layer WL1. The nth well layer WLn is provided between the nth barrier layer BLn and the (n + 1) th barrier layer BL (n + 1). The (n + 1) th barrier layer BL (n + 1) is provided between the nth well layer WLn and the second semiconductor layer 20.

  The energy of light emitted from the light emitting unit 30 includes, for example, a range of 0.4 electron volts (eV) or more and 6.5 eV or less. The peak wavelength of light (emitted light) emitted from the light emitting unit 30 is, for example, not less than 380 nanometers (nm) and not more than 650 nm. However, in the embodiment, the peak wavelength is arbitrary.

  The In-containing intermediate layer 60 includes a nitride semiconductor containing In at a composition ratio different from the In composition ratio z <b> 1 included in the well layer 32. The In-containing intermediate layer 60 has a thickness of 10 nm to 1000 nm.

FIG. 3 is a schematic cross-sectional view illustrating the configuration of a part of the semiconductor light emitting element according to the first embodiment.
That is, this figure illustrates the configuration of the In-containing intermediate layer 60.
As illustrated in FIG. 3, the In-containing intermediate layer 60 includes a plurality of first layers 61 and a plurality of second layers 62 that are alternately stacked. The first layer 61 includes, for example, Ga _1-X2 In _X2 N (0 <x2 ≦ 1). The second layer 62 includes Ga _1-X3 In _X3 N (0 ≦ x3 ≦ 1, x3 <x2).

For example, the number (for example, the number of pairs) of the first layer 61 and the second layer 62 is 20, for example. For example, an In _0.08 Ga _0.92 N layer having a thickness of 1 nm is used for the first layer 61. For the second layer 62, for example, a GaN layer having a thickness of 3 nm is used. The second layer 62 can include an n-type impurity.
The In-containing intermediate layer 60 may not be a multilayer structure in which a plurality of layers as described above are alternately stacked. The In-containing intermediate layer 60 may be a single layer depending on the case, as will be described later.

  FIG. 4 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. As shown in FIG. 4, in the semiconductor light emitting device 111 of the specific example according to the present embodiment, the base layer 50 is formed on the AlN buffer layer 55 formed on the silicon substrate 40 and the AlN buffer layer 55. The formed AlGaN buffer layer 54 and a multilayer buffer layer 53 provided on the AlGaN buffer layer 54 are included.

The multilayer buffer layer 53 includes a plurality of GaN layers 51 and a plurality of AlN layers 52 that are alternately stacked along the Z-axis.
The functional unit 10 s is stacked on the base layer 50. In this example, the In-containing layer 60 has the multilayer structure of the first layer 61 and the second layer 62 illustrated in FIG.

  The semiconductor light emitting devices 110 and 111 according to the embodiment having such a configuration can provide a semiconductor light emitting device in which deterioration and destruction of the semiconductor layer are suppressed.

  Hereinafter, the result of evaluating the characteristics of the semiconductor light emitting device 111 will be described together with a reference example. The semiconductor light emitting device 111 was manufactured as follows.

  The MOVPE (metal organic vapor phase epitaxy) method was used for crystal growth of the following semiconductor layers.

First, the Si (111) silicon substrate 40 was washed with a 1: 1 mixture of H ₂ O ₂ and H ₂ SO ₄ for 13 minutes. Next, the silicon substrate 40 was cleaned using 2% HF for 10 minutes. After cleaning, the silicon substrate 40 was introduced into the MOVPE reactor.

The susceptor was heated to 720 ° C. in a hydrogen atmosphere, and TMA was supplied for 8 seconds. Thereafter, by further supplying NH ₃ , an AlN layer having a thickness of 40 nm, which becomes the AlN buffer layer 55, was formed.

Subsequently, the temperature of the susceptor was raised to 1030 ° C., and an Al _0.25 Ga _0.75 N layer having a thickness of 40 nm was formed to be the AlGaN buffer layer 54.

  Next, the susceptor was heated to 1080 ° C. to form a GaN layer 51 having a thickness of 300 nm.

Next, the temperature of the susceptor is lowered to 800 ° C., and the ratio of NH ₃ , H ₂ , and N ₂ in the total flow rate is 20%, 80%, and 0%, respectively, and the AlN layer having a thickness of 12 nm becomes the AlN layer 52. Formed.

Furthermore, after changing the proportions of NH ₃ , H ₂ , and N _{2 in} the total flow rate to 63%, 19%, and 18%, respectively, the susceptor is heated to 1080 ° C. to become the GaN layer 51, with a thickness of 300 nm. The formation of the GaN layer and the formation of the AlN layer 52 were alternately repeated three times.

Next, the temperature of the susceptor is lowered to 800 ° C., and a 12 nm AlN layer is formed, which becomes the AlN layer 52 with NH ₃ , H ₂ , and N ₂ occupying 20%, 80%, and 0% of the total flow rate, respectively. did.
Thereby, the foundation layer 50 in which the plurality of GaN layers 51 and the plurality of AlN layers 52 are alternately stacked is formed.

  Next, the temperature of the susceptor was raised to 1120 ° C., and an n-type GaN layer having a thickness of 1.2 μm that was to be the first semiconductor layer 10 was formed.

Next, the temperature of the susceptor is lowered to 810 ° C., the formation of an In _0.08 Ga _0.92 N layer having a thickness of 1 nm to be the first layer 61, and the n layer having a thickness of 3 nm to be the second layer 62 The formation of the GaN layer was repeated 20 times alternately. Thereby, the In-containing intermediate layer 60 is formed.

  Next, the light emitting part 30 of LED was formed. Further, a p-type GaN layer to be the second semiconductor layer 20 was formed. Thereby, the semiconductor light emitting element 111 is formed.

  On the other hand, the In-containing intermediate layer 60 is not provided in the semiconductor light emitting device 191 (not shown) of the first comparative example. That is, the light emitting unit 30 is formed in contact with the first semiconductor layer 10. Except this, it is the same as the semiconductor light emitting device 111.

The semiconductor light emitting device 111 according to the embodiment and the semiconductor light emitting device 191 of the first reference example manufactured as described above were observed with a Nomarski microscope.
FIG. 5A and FIG. 5B are Nomarski microscope images illustrating the characteristics of the semiconductor light emitting device.
As shown in FIG. 5A, no crack was observed in the semiconductor light emitting device 111 according to the embodiment.
As shown in FIG. 5B, a large number of cracks CR were observed in the first reference example.

  As described above, in the present embodiment, by providing the In-containing intermediate layer 60, the crack CR is not substantially generated, and deterioration and destruction of the semiconductor layer are suppressed.

  For example, when a semiconductor layer (such as a GaN layer) is formed on a substrate, a tensile stress may act on the semiconductor layer due to a difference in thermal expansion coefficient, causing the substrate to warp downward. Thus, when stress is applied to the semiconductor layer, a crack CR is generated. On the other hand, there is a configuration in which a layer for adjusting stress is provided so that the substrate is warped upward in the process of growth of the semiconductor layer, and the substrate becomes flat when returned to room temperature. However, it has been found that in the configuration in which the nitride semiconductor layer is formed on the silicon substrate 40, the generation of the crack CR cannot be sufficiently suppressed only by introducing such a layer for adjusting the stress.

  That is, in the layer for adjusting the stress, a lattice relaxation layer or the like is used. Therefore, dislocation is likely to occur.

  On the other hand, according to the structure which concerns on embodiment, generation | occurrence | production of a dislocation | rearrangement can also be suppressed, suppressing generation | occurrence | production of crack CR.

FIG. 6 is an electron micrograph image illustrating the characteristics of the semiconductor light emitting device according to the first embodiment.
This figure is a transmission electron micrograph image of the cross section of the functional part 10 s of the semiconductor light emitting device 111. As can be seen from FIG. 6, dislocations gradually decrease from the lower surface in the first semiconductor layer 10 toward the upper surface in the first semiconductor layer 10. Thus, by the structure which concerns on this embodiment, generation | occurrence | production of a dislocation | rearrangement can also be suppressed, suppressing generation | occurrence | production of crack CR.

FIG. 7A and FIG. 7B are schematic cross-sectional views illustrating the configuration of another semiconductor light emitting element according to the first embodiment.
As shown in FIG. 7A, in another semiconductor light emitting device 121 according to this embodiment, the In-containing intermediate layer 60 is provided between the second semiconductor layer 20 and the light emitting unit 30.

  As illustrated in FIG. 7B, in another semiconductor light emitting device 122 according to the present embodiment, the In-containing intermediate layer 60 is provided between the first semiconductor layer 10 and the light emitting unit 30 and the second semiconductor. It is provided both between the layer 20 and the light emitting unit 30.

For example, in the semiconductor light emitting devices 110, 121 and 122, a Ga _1-x1 In _x1 N layer (0 <x1 ≦ 1) can be used for the In-containing intermediate layer 60. That is, the In-containing intermediate layer 60 may be a single layer.

  Further, as illustrated in FIG. 3, when the In-containing intermediate layer 60 includes a plurality of first layers 61 and a plurality of second layers 62 that are alternately stacked, the In-containing intermediate layer 60 includes: It can be provided at least between the first semiconductor layer 10 and the light emitting unit 30 and between the second semiconductor layer 20 and the light emitting unit 30.

FIG. 8A and FIG. 8B are schematic cross-sectional views illustrating the configuration of another semiconductor light emitting element according to the first embodiment.
As shown in FIGS. 8A and 8B, in another semiconductor light emitting device 131 and 132 according to the present embodiment, the underlayer 50 includes an Al-containing intermediate layer 56. The Al-containing intermediate layer 56 includes a nitride semiconductor containing Al. The Al-containing intermediate layer 56 may further include at least one of B and In. The Al-containing intermediate layer 56 includes, for example, Ga _1-y1 Al _y1 N (0 <y1 ≦ 1). The Al-containing intermediate layer 56 has a thickness of 2 nm to 100 nm.

  In the case where the Al-containing intermediate layer 56 is provided as in the semiconductor light emitting devices 131 and 132, the In-containing intermediate layer 60 emits light between the first semiconductor layer 10 and the light emitting unit 30 and between the second semiconductor layer 20 and the light emitting element. It can be provided in at least one of the portions 30.

  Further, when the In-containing intermediate layer 60 includes a plurality of first layers 61 and a plurality of second layers 62 that are alternately stacked, the Al-containing intermediate layer 56 may be provided.

  The thickness of each layer included in the semiconductor light emitting element can be obtained from an electron micrograph of a cross section. The concentration of elements such as In and Al contained in each layer is obtained from the analysis result by TEM-EDX (transmission electron microscope-energy dispersive X-ray spectroscopy) SIMS (secondary ion mass spectrometry), for example. be able to.

(Second Embodiment)
FIG. 9 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the second embodiment.
As shown in FIG. 9, the semiconductor light emitting device 140 according to the present embodiment is provided on the base layer 50 formed on the silicon substrate 40, and is provided on the base layer 50 and includes a nitride semiconductor and includes a first conductive material. First semiconductor layer 10, light emitting unit 30 provided on first semiconductor layer 10, second semiconductor layer 20 of second conductivity type provided on light emitting unit 30 and including a nitride semiconductor, . Also in this case, the light emitting unit 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31 and including Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1). .

  The underlayer 50 includes an Al-containing intermediate layer 56 having a thickness of 2 nm to 100 nm and including a nitride semiconductor containing Al. The Al-containing intermediate layer 56 has a concavo-convex portion 56 d provided on the surface on the first semiconductor layer 10 side. The surface roughness Ra of the uneven portion 56d is 1 nm or more and 10 nm or less. For example, the surface roughness Ra is about 3 nm.

  With such a configuration, it is possible to obtain a semiconductor light emitting element in which deterioration and destruction of the semiconductor layer are suppressed.

FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting element according to the second embodiment.
As shown in FIG. 10, in the semiconductor light emitting device 141 of the specific example according to the present embodiment, the AlN buffer layer 55 and the AlGaN buffer layer 54 described with reference to FIG. 4 are provided, and the multilayer buffer layer 53 is formed thereon. Provided. The multilayer buffer layer 53 includes a plurality of GaN layers 51 and a plurality of AlN layers 52 that are alternately stacked along the Z-axis.

  In this example, the AlN layer 52 has a concavo-convex portion 56 d provided on the surface on the first semiconductor layer 10 side. That is, the AlN layer 52 corresponds to the Al-containing intermediate layer 56 having the uneven portion 56d.

  In the semiconductor light emitting device 141, the In-containing intermediate layer 60 is not provided. Other than this, it is the same as the semiconductor light emitting device 111, and the description is omitted.

  Hereinafter, the result of evaluating the characteristics of the semiconductor light emitting device 141 will be described together with a reference example. The semiconductor light emitting device 141 was manufactured as follows.

  The MOVPE (metal organic vapor phase epitaxy) method was used for crystal growth of the following semiconductor layers.

First, the Si (111) silicon substrate 40 was washed with a 1: 1 mixture of H ₂ O ₂ and H ₂ SO ₄ for 13 minutes. Next, the silicon substrate 40 was cleaned using 2% HF for 10 minutes. After cleaning, the silicon substrate 40 was introduced into the MOVPE reactor.

The susceptor was heated to 720 ° C. in a hydrogen atmosphere, and TMA was supplied for 8 seconds. Thereafter, by further supplying NH ₃ , an AlN layer having a thickness of 40 nm, which becomes the AlN buffer layer 55, was formed.

Subsequently, the temperature of the susceptor was raised to 1030 ° C., and an Al _0.25 Ga _0.75 N layer having a thickness of 40 nm was formed to be the AlGaN buffer layer 54.

  Next, the susceptor was heated to 1080 ° C. to form a GaN layer 51 having a thickness of 300 nm.

Next, the temperature of the susceptor is lowered to 800 ° C., and the ratio of NH ₃ , H ₂ , and N ₂ in the total flow rate is 20%, 80%, and 0%, respectively, and the AlN layer 52 is formed. A layer was formed.

Furthermore, after changing the ratio of NH ₃ , H ₂ , and N _{2 in} the total flow rate to 32%, 52%, and 16%, respectively, the susceptor is heated to 1120 ° C. to become the GaN layer 51, with a thickness of 300 nm. A GaN layer was formed. The formation of the AlN layer 52 and the formation of the GaN layer 51 were alternately repeated three times.

Next, the temperature of the susceptor is lowered to 800 ° C., and the ratio of NH ₃ , H ₂ , and N ₂ in the total flow rate is 20%, 80%, and 0%, respectively, and the AlN layer 52 is formed. A layer was formed. Thereby, the multilayer buffer layer 53 is formed.

  Under the above conditions, the uneven portion 56d is formed in the AlN layer 52. That is, the AlN layer 52 is formed in a dot shape. The surface roughness Ra of the uneven portion 56d was about 3 nm.

  Thereafter, the first semiconductor layer 10 was formed, the light emitting unit 30 was formed without forming the In-containing intermediate layer 60, and the second semiconductor layer 20 was formed. Thereby, the semiconductor light emitting element 141 was formed.

  On the other hand, in the semiconductor light emitting device 192 (not shown) of the second comparative example, the formation conditions of the multilayer buffer layer 53 were set similarly to the semiconductor light emitting device 111. In this case, the uneven portion 56d is not formed in the AlN layer 52, and the upper surface of the AlN layer 52 is substantially flat. Then, the first semiconductor layer 10, the light emitting unit 30, and the second semiconductor layer 20 were formed without forming the In-containing intermediate layer 60.

The semiconductor light emitting device 141 according to the embodiment and the semiconductor light emitting device 192 of the second reference example manufactured as described above were observed with a Nomarski microscope.
FIG. 11A and FIG. 11B are Nomarski microscope images illustrating the characteristics of the semiconductor light emitting device.
As shown in FIG. 11A, no crack was observed in the semiconductor light emitting device 141 according to the embodiment.
As shown in FIG. 11B, a large number of cracks CR were observed in the second reference example.

  As described above, in the present embodiment, by providing the Al-containing intermediate layer 56 (AlN layer 52) having the concavo-convex portion 56d in the underlayer 50, the generation of the crack CR is very effectively suppressed. As in this example, when the Al-containing intermediate layer 56 having the concavo-convex portion 56d is used, the occurrence of crack CR can be suppressed without providing the In-containing intermediate layer 60 described in regard to the first embodiment. However, the Al-containing intermediate layer 56 may be further provided while the In-containing intermediate layer 60 is provided. As a result, crack CR is less likely to occur.

FIG. 12A and FIG. 12B are schematic cross-sectional views illustrating the configuration of another semiconductor light emitting element according to the second embodiment.
As shown in FIG. 12A, in another semiconductor light emitting device 151 according to this embodiment, an In-containing intermediate layer 60 is provided between the first semiconductor layer 10 and the light emitting unit 30, and An Al-containing intermediate layer 56 having an uneven portion 56d is provided.

  As shown in FIG. 12B, in another semiconductor light emitting device 152 according to this embodiment, the In-containing intermediate layer 60 is provided between the second semiconductor layer 20 and the light emitting unit 30, An Al-containing intermediate layer 56 having an uneven portion 56d is provided.

  Furthermore, the In-containing intermediate layer 60 is provided between the first semiconductor layer 10 and the light emitting unit 30 and between the second semiconductor layer 20 and the light emitting unit 30 while providing the Al-containing intermediate layer 56 having the uneven portion 56d. You may provide in both.

  A layer containing GaN (in this example, the GaN layer 51 in the multilayer buffer layer 53) is provided below the Al-containing intermediate layer 56 having the uneven portion 56d (in this example, the AlN layer 52 in the multilayer buffer layer 53). The provision is effective in suppressing deterioration and destruction of the semiconductor layer.

  The Al-containing intermediate layer 56 having the uneven portion 56d may be provided not only in the underlayer 50 but also at an arbitrary position above the underlayer 50. In the semiconductor light emitting device 141, the Al-containing intermediate layer 56 (AlN layer 52) having the uneven portion 56d and the layer containing GaN (GaN layer 51) are alternately stacked. The Al-containing intermediate layer 56 may be one layer (for example, one pair).

(Third embodiment)
FIG. 13A and FIG. 13B are schematic cross-sectional views illustrating the configuration of a nitride semiconductor wafer according to the third embodiment.
As illustrated in FIGS. 13A and 13B, the nitride semiconductor wafers 210 and 211 according to the present embodiment include a silicon substrate 40, a base layer 50 provided on the silicon substrate 40, A first semiconductor layer 10 including a nitride semiconductor and having a first conductivity type, a light emitting unit 30 provided on the first semiconductor layer 10, and a light emitting unit 30. The second semiconductor layer 20 including the nitride semiconductor and having the second conductivity type, and the In-containing intermediate layer 60 are provided.

The light emitting unit 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31 and including Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1).

  In the nitride semiconductor wafer 210, the In-containing intermediate layer 60 is provided between the first semiconductor layer 10 and the light emitting unit 30. In the nitride semiconductor wafer 211, the In-containing intermediate layer 60 is provided between the second semiconductor layer 20 and the light emitting unit 30. The In-containing intermediate layer 60 may be provided between the first semiconductor layer 10 and the light emitting unit 30 and between the second semiconductor layer 20 and the light emitting unit 30.

  The In-containing intermediate layer 60 includes a nitride semiconductor containing In at a composition ratio different from the In composition ratio z <b> 1 included in the well layer 32. The In-containing intermediate layer 60 has a thickness of 10 nm to 1000 nm.

FIG. 14 is a schematic cross-sectional view illustrating the configuration of another nitride semiconductor wafer according to the third embodiment.
As shown in FIG. 14, another nitride semiconductor wafer 240 according to the present embodiment is provided on the silicon substrate 40, the foundation layer 50 provided on the silicon substrate 40, the foundation layer 50, A first semiconductor layer 10 including a nitride semiconductor and having a first conductivity type, a light emitting unit 30 provided on the first semiconductor layer 10, and a second conductive layer provided on the light emitting unit 30 and including a nitride semiconductor. A second semiconductor layer 20 having a shape. The light emitting unit 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31 and including Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1).

  The underlayer 50 includes an Al-containing intermediate layer 56 having a thickness of 2 nm to 100 nm and including a nitride semiconductor containing Al. The Al-containing intermediate layer 56 has a concavo-convex portion 56 d provided on the surface on the first semiconductor layer 10 side. The surface roughness Ra of the uneven portion 56d is 1 nm or more and 10 nm or less.

  According to the nitride semiconductor wafers 210, 211, and 240, it is possible to provide a nitride semiconductor wafer for a semiconductor light emitting device that suppresses deterioration and destruction of a semiconductor layer.

(Fourth embodiment)
FIG. 15A and FIG. 15B are flowcharts illustrating the method for manufacturing the nitride semiconductor layer according to the fourth embodiment.
As shown in FIGS. 15A and 15B, the nitride semiconductor layer manufacturing method according to the present embodiment provides a nitride semiconductor layer on the base layer 50 provided on the silicon substrate 40. Forming a first semiconductor layer 10 of the first conductivity type (step S110).

Furthermore, in this manufacturing method, a plurality of barrier layers 31 and Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1) disposed between the plurality of barrier layers 31 are formed on the first semiconductor layer 10. And a step of forming the light emitting unit 30 including the well layer 32 (step S120).

  Furthermore, the manufacturing method includes a step (step S130) of forming a second semiconductor layer 20 including a nitride semiconductor and having a second conductivity type different from the first conductivity type on the light emitting unit 30.

  Further, the manufacturing method forms the In-containing intermediate layer 60 between at least one of the first semiconductor layer 10 and the light emitting unit 30 and between the second semiconductor layer and the light emitting unit 30 (step S140). )including. The In-containing intermediate layer 60 includes a nitride semiconductor containing In at a composition ratio different from the In composition ratio z <b> 1 included in the well layer 32. The In-containing intermediate layer 60 has a thickness of 10 nm to 1000 nm.

FIG. 16 is a flowchart illustrating another method for manufacturing a nitride semiconductor layer according to the fourth embodiment.
As shown in FIG. 16, the method for manufacturing a nitride semiconductor layer according to the present embodiment includes a step (step S <b> 150) of forming the foundation layer 50 including the Al-containing intermediate layer 56 on the silicon substrate 40. The Al-containing intermediate layer 56 has a thickness of 2 nm to 100 nm and includes a nitride semiconductor containing Al.

  Further, the manufacturing method includes a step (step S110) of forming the first semiconductor layer 10 including the nitride semiconductor and having the first conductivity type on the base layer 50.

Furthermore, in this manufacturing method, a plurality of barrier layers 31 and Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1) disposed between the plurality of barrier layers 31 are formed on the first semiconductor layer 10. And a step of forming the light emitting unit 30 including the well layer 32 (step S120).

  Furthermore, the manufacturing method includes a step (step S130) of forming a second semiconductor layer 20 including a nitride semiconductor and having a second conductivity type different from the first conductivity type on the light emitting unit 30.

  The Al-containing intermediate layer 56 has an uneven portion 56d provided on the surface (upper surface) of the first semiconductor layer 10, and the surface roughness Ra of the uneven portion 56d is 1 nm or more and 10 nm or less.

  A nitride semiconductor layer in which deterioration and destruction of the semiconductor layer are suppressed can be manufactured by the manufacturing method described with reference to FIGS.

  In the embodiment, the semiconductor layer is grown by, for example, metal-organic chemical vapor deposition (MOCVD) method, metal-organic vapor phase epitaxy (MOVPE) method, molecular beam epitaxy. (Molecular Beam Epitaxy: MBE) method, halide vapor phase epitaxy method (HVPE) method and the like can be used.

For example, when the MOCVD method or the MOVPE method is used, the following can be used as raw materials for forming each semiconductor layer. For example, TMGa (trimethyl gallium) and TEGa (triethyl gallium) can be used as the Ga raw material. For example, TMIn (trimethylindium), TEIn (triethylindium), or the like can be used as the In material. As a raw material for Al, for example, TMAl (trimethylaluminum) can be used. As a raw material of N, for example, NH ₃ (ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine) and the like can be used. As a Si raw material, SiH ₄ (monosilane), Si ₂ H ₆ (disilane), or the like can be used.

  According to the embodiment, it is possible to provide a semiconductor light emitting device, a nitride semiconductor wafer, and a method for manufacturing a nitride semiconductor layer in which deterioration and destruction of the semiconductor layer are suppressed.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. is good.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, substrates included in semiconductor light emitting devices and nitride semiconductor wafers, AlN buffer layers, AlGaN buffer layers, underlayers, multilayer buffer layers, AlN layers, GaN layers, In-containing intermediate layers, Al-containing intermediate layers, semiconductor layers, light emission The specific configuration of each element such as a unit and a functional unit is not limited as long as a person skilled in the art can appropriately implement the present invention by selecting appropriately from a known range and obtain the same effect. Included in the range.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor light-emitting elements and nitrides that can be implemented by a person skilled in the art with appropriate design modifications based on the semiconductor light-emitting elements, nitride semiconductor wafers, and nitride semiconductor layer manufacturing methods described above as embodiments of the present invention The manufacturing method of the semiconductor wafer and the nitride semiconductor layer also belongs to the scope of the present invention as long as it includes the gist of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 10s ... Functional part, 20 ... 2nd semiconductor layer, 30 ... Light emission part, 31 ... Barrier layer, 32 ... Well layer, 40 ... Silicon substrate, 50 ... Underlayer, 51 ... GaN layer, 52 ... AlN layer, 53 ... Multi-layer buffer layer, 54 ... AlGaN buffer layer, 55 ... AlN buffer layer, 56 ... Al-containing intermediate layer, 56d ... Uneven portion, 60 ... In-containing intermediate layer, 61 ... First layer, 62 ... First 2 layers, 110, 111, 121, 122, 131, 132, 140, 141, 151, 152, 191, 192 ... semiconductor light emitting device, 210, 211, 240 ... nitride semiconductor wafer, BL ... barrier layer, WL ... well layer

Claims (9)

An underlayer formed on a silicon substrate;
A first semiconductor layer of a first conductivity type including a nitride semiconductor provided on the underlayer;
A light emitting portion provided on the first semiconductor layer, the light emitting portion including a plurality of barrier layers and Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1) provided between the plurality of barrier layers. A light emitting portion including a well layer;
A second semiconductor layer of a second conductivity type provided on the light emitting unit and including a nitride semiconductor and different from the first conductivity type;
With
The underlayer includes an AlN buffer layer formed on the silicon substrate, an AlGaN buffer layer formed on the AlN buffer layer, a GaN layer formed on the AlGaN buffer layer, and the GaN An Al-containing intermediate layer formed on the layer and having a thickness of 2 nanometers to 100 nanometers and comprising AlN;
The said Al containing intermediate | middle layer has a dot-shaped uneven | corrugated | grooved part provided in the surface at the side of the said 1st semiconductor layer, The semiconductor light-emitting device characterized by the above-mentioned.   A composition ratio different from the In composition ratio z1 provided in at least one of the first semiconductor layer and the light emitting section and between the second semiconductor layer and the light emitting section and included in the well layer. The semiconductor light-emitting device according to claim 1, further comprising an In-containing intermediate layer including a nitride semiconductor containing In and having a thickness of 10 to 1000 nanometers. The In-containing intermediate layer includes a plurality of first layers containing Ga _1-X2 In _X2 N (0 <x2 ≦ 1), Ga _1-X3 In _X3 N (0 ≦ x3 ≦ 1, 3. The semiconductor light emitting element according to claim 2, further comprising: a plurality of second layers including x 3 <x 2). A silicon substrate;
An underlayer provided on the silicon substrate;
A first semiconductor layer of a first conductivity type including a nitride semiconductor provided on the underlayer;
A light emitting portion provided on the first semiconductor layer, the light emitting portion including a plurality of barrier layers and Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1) provided between the plurality of barrier layers. A light emitting portion including a well layer;
A second semiconductor layer of a second conductivity type provided on the light emitting unit and including a nitride semiconductor and different from the first conductivity type;
With
The underlayer includes an AlN buffer layer formed on the silicon substrate, an AlGaN buffer layer formed on the AlN buffer layer, a GaN layer formed on the AlGaN buffer layer, and the GaN An Al-containing intermediate layer formed on the layer and having a thickness of 2 nanometers to 100 nanometers and comprising AlN,
The nitride-containing semiconductor wafer, wherein the Al-containing intermediate layer has dot-shaped uneven portions provided on a surface on the first semiconductor layer side.   A composition ratio different from the In composition ratio z1 provided in at least one of the first semiconductor layer and the light emitting section and between the second semiconductor layer and the light emitting section and included in the well layer. 5. The nitride semiconductor wafer according to claim 4, further comprising an In-containing intermediate layer including a nitride semiconductor containing In and having a thickness of 10 to 1000 nanometers. The In-containing intermediate layer includes a plurality of first layers containing Ga _1-X2 In _X2 N (0 <x2 ≦ 1), Ga _1-X3 In _X3 N (0 ≦ x3 ≦ 1, The nitride semiconductor wafer according to claim 5, further comprising: a plurality of second layers including x3 <x2). On the silicon substrate, an AlN buffer layer, an AlGaN buffer layer formed on the AlN buffer layer, a GaN layer formed on the AlGaN buffer layer, and 2 nanometers formed on the GaN layer. has a 100 nm or less in thickness or more meters, forming a base layer comprising a Al-containing intermediate layer containing AlN,
Forming a first semiconductor layer of a first conductivity type including a nitride semiconductor on the underlayer;
Light emission including a plurality of barrier layers and a well layer containing Ga _{1 -z1} In _z1 N (0 <z1 ≦ 1) disposed between the plurality of barrier layers on the first semiconductor layer. Forming a part;
Forming a second semiconductor layer including a nitride semiconductor and having a second conductivity type different from the first conductivity type on the light emitting unit;
With
The method for producing a nitride semiconductor layer, wherein the Al-containing intermediate layer has dot-shaped uneven portions provided on a surface on the first semiconductor layer side.   A composition ratio different from the In composition ratio z1 provided in at least one of the first semiconductor layer and the light emitting section and between the second semiconductor layer and the light emitting section and included in the well layer. The method for producing a nitride semiconductor layer according to claim 7, further comprising: forming an In-containing intermediate layer including a nitride semiconductor containing In and having a thickness of not less than 10 nanometers and not more than 1000 nanometers. The step of forming the In-containing intermediate layer includes a plurality of first layers containing Ga _{1 -X 2} In _{X 2} N (0 <x2 ≦ 1) and Ga _{1 -X 3} In _{X 3} N (0 9. The method of manufacturing a nitride semiconductor layer according to claim 8, further comprising a step of forming a plurality of second layers including ≦ x3 ≦ 1 and x3 <x2).