JP2017034443A - Signal processing apparatus and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing apparatus capable of executing wide-band signal processing while reducing the number of multipliers to be used, and a signal processing method.SOLUTION: A signal processing apparatus comprises: a frequency conversion part 12 which converts a frequency of an analog signal to be measured into a predetermined intermediate frequency F; an A/D conversion part 13 by which the frequency-converted signal to be measured is sampled in a sampling frequency Fs that is four times as high as the intermediate frequency F, and converted into digital data A(n); an ADCIF 21 by which the digital data A(n) is demultiplexed into N pieces of parallel data by performing serial/parallel conversion thereon and the N pieces of parallel data are successively outputted as a 1/N rate of the sampling frequency Fs; a quadrature demodulation part 22 which performs quadrature demodulation on the N pieces of parallel data; an FIR filter 23 which applies band limit processing to a quadrature signal outputted from the quadrature demodulation part 22; and an I/Q timing control part 30 for controlling timing between quadrature signals I'(n) and Q'(m) outputted from the FIR filter 23.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a signal processing apparatus and a signal processing method.

  2. Description of the Related Art Conventionally, a signal processing apparatus such as a signal analyzer that receives a broadband RF signal output from a device under test as a signal under measurement and performs frequency analysis of the signal under measurement is known.

Such a signal processing device samples a frequency conversion unit that converts the carrier frequency of the input signal under measurement into an intermediate frequency F _IF , and samples the signal under measurement that has been frequency converted by the frequency conversion unit at a predetermined sampling frequency Fs. An A / D conversion unit that converts the digital data A (n) into an I / Q signal, and an orthogonal demodulation unit that orthogonally demodulates the digital data A (n) (see, for example, Patent Document 1). Here, n is an index representing a sampling point by the sampling frequency Fs, and is an integer of 0 or more.

  In a signal processing device, when a signal processing unit that performs digital signal processing is realized by hardware, the signal processing unit is configured by a device such as a field programmable gate array (FPGA). Since there is a limit to the maximum operation speed of the FPGA, there are cases where a plurality of lanes are configured in the FPGA and the digital data A (n) is parallelized for signal processing.

  Furthermore, in the future, it is assumed that there is a demand to analyze a wider band signal such as IEEE802.11ad or 5G cellular using the millimeter wave band. Thus, as the signal under measurement becomes wider, the higher sampling frequency Fs is required in the A / D converter, and the need for increasing the number of lanes in the FPGA increases.

  The conventional quadrature demodulating unit converts N digital data A (n) parallelized with N orthogonal signals I (n) at the timing of the operation clock of the FPGA according to the following equations (1) and (2). Quadrature demodulation is performed on N orthogonal signals Q (n).

  As shown in FIG. 11, the conventional quadrature demodulating unit has N input lanes to which N digital data A (n) parallelized are input and quadrature signals I (n) and Q (n). 2N output lanes to be output, 2N multipliers 31 arranged corresponding to 2N output lanes, and sin used for orthogonal demodulation of N digital data A (n) parallelized / Cos table 32.

The sin / cos table 32 gives values of the trigonometric function parts of the equations (1) and (2). The digital data A (n) input to each input lane is multiplied by a value given from the sin / cos table 32 in the multiplier 31, and is output as a quadrature signal from the corresponding two output lanes of I phase and Q phase. The

  Further, 2N half-band filters (HBFs) configured as shown in FIG. 12 are arranged at the subsequent stage of the orthogonal demodulator as described above, corresponding to each output lane of the orthogonal demodulator. There is a case.

The output of an HBF with 11 taps as shown in FIG. 12 is expressed as in equation (3). Here, d _k is I (n + k) or Q (n + k) (n and k are integers of 0 or more), and K = 10. The filter coefficients C _{0 to} C ₁₀ include C ₁ = C ₃ = C ₇ = C ₉ = 0, C ₀ = C ₁₀ ≠ 0, C ₂ = C ₈ ≠ 0, C ₄ = C ₆ ≠ 0, Since there is a relationship of C ₅ ≠ 0, the filter coefficients are substantially _four of C ₀ , C ₂ , C ₄ , and C ₅ .

Here, the seven pieces of data d ₀ , d ₂ , d ₄ , d ₅ , d ₆ , d ₈ , and d ₁₀ in the expression (3) are changed to D ₀ , D ₁ , D ₂ , D ₃ , D _{4, respectively.} , D ₅ , D ₆ , the expression (3) is expressed as the following expression (4).

Therefore, as shown in FIG. 12, HBF number conventional taps 11, _{D 0} and _D a multiplier 33a for multiplying the filter coefficients _{C 0} to the sum of _{6, D 1} and the filter coefficients _{C 2} to the sum of _{D 5} a multiplier 33b for multiplying a multiplier 33c for multiplying the filter coefficients _{C 4} to the sum of _{D 2} and _{D 4,} a multiplier 33d multiplies the filter coefficients _{C 5} to _{D 3,} adds the multiplication result by the multiplier 33a~33d And an adder 34.

  For this reason, when the conventional HBF of FIG. 12 is arranged after the orthogonal demodulation unit of FIG. 11, the number of multipliers allocated per lane of 2N output lanes of the orthogonal demodulation unit is four. .

Japanese Patent No. 3916617

  However, in the conventional signal processing apparatus, if an attempt is made to increase the number of lanes of a device such as an FPGA in order to perform analysis processing of a wide-band signal under measurement, the number of multipliers used is increased accordingly, and the use of devices is increased. There was a problem that the upper limit of the number of possible resources was greatly exceeded.

  In order to solve this problem, for example, it is possible to increase the number of FPGAs mounted on the signal processing device. However, in that case, the mounting efficiency is remarkably lowered, and the entire device becomes very large and expensive. In addition, since power consumption increases, it is not realistic.

  The present invention has been made to solve such a conventional problem, and is a signal processing apparatus and a signal processing method capable of performing wideband signal processing by reducing the number of multipliers used. The purpose is to provide.

  In order to solve the above-described problems, a signal processing apparatus according to claim 1 of the present invention includes a frequency conversion unit that converts an analog signal under measurement into a predetermined intermediate frequency, and a device under measurement that is frequency-converted by the frequency conversion unit. A / D conversion means for sampling a signal at a sampling frequency four times the intermediate frequency and converting it into digital data A (n) (n is an index indicating a sampling point according to the sampling frequency); Parallel separation means for separating the data into N pieces (N is a positive even number) of parallel data and sequentially outputting the N pieces of parallel data at a rate of 1 / N of the sampling frequency; and the N pieces of parallel data Data is orthogonally demodulated and orthogonal signals I (n) and Q (m) (n and m are indexes indicating sampling points based on the sampling frequency) are obtained. Output orthogonal demodulation means, and output orthogonal signals I ′ (n) and Q ′ (m) obtained by subjecting the orthogonal signals I (n) and Q (m) output from the orthogonal demodulation means to band limitation processing. Signal processing, and a timing adjustment means (30) for adjusting the timing between the orthogonal signals I ′ (n) and Q ′ (m) subjected to the band limiting process by the filter processing means. The orthogonal signals I (n), Q (m) take a value of 0 at every other sampling point and at every other sampling point m where I (m) = 0. , Q (m) = A (m), or Q (m) = − A (m), and at every other sampling point n where Q (n) = 0, I (n) = A (N) or I (n) = − A (n), and the orthogonal demodulation means is I (n) The orthogonal signal I (n) that satisfies A (n) or I (n) = − A (n) and Q (m) = A (m) or Q (m) = − A (m) The orthogonal signal Q (m) is output to the filter processing means.

  In the signal processing device according to claim 2 of the present invention, the timing adjustment means may be configured such that the sampling point n at which I (n) = A (n) or I (n) = − A (n) is satisfied. By performing an interpolation process on the orthogonal signal I ′ (n), an orthogonal signal I ″ (m) corresponding to every other sampling point m where n ≠ m is calculated.

  In the signal processing device according to claim 3 of the present invention, the timing adjustment means may be configured such that the sampling point m at which Q (m) = A (m) or I (m) = − A (m) is satisfied. By performing an interpolation process on the orthogonal signal Q ′ (m), an orthogonal signal Q ″ (n) corresponding to every other sampling point n where n ≠ m is calculated.

  In the signal processing device according to claim 4 of the present invention, the filter processing means includes N / 2 filters for the orthogonal signal I (n) output from the orthogonal demodulation means, and the orthogonal demodulation means. N / 2 filters for the quadrature signal Q (m) output from the quadrature signal, and each of the filters for the quadrature signal I (n) outputs one filter coefficient and the quadrature demodulation means. Each of the filters for the orthogonal signal Q (m) has one filter coefficient and the output from the orthogonal demodulation means. It has one multiplier for multiplying the orthogonal signal Q (m).

  According to a fifth aspect of the present invention, there is provided a signal processing method comprising: a frequency conversion step for frequency-converting an analog signal under measurement to a predetermined intermediate frequency; and the signal under measurement subjected to frequency conversion by the frequency conversion step A / D conversion step of sampling at a sampling frequency four times that of the digital signal and converting it into digital data A (n) (n is an index indicating a sampling point according to the sampling frequency), and N digitally converted digital data. (N is a positive even number) parallel data, a parallel separation step of sequentially outputting the N parallel data at a rate of 1 / N of the sampling frequency, and orthogonally demodulating the N parallel data Output quadrature signals I (n) and Q (m) (n and m are indexes indicating sampling points based on the sampling frequency) And orthogonal signals I ′ (n) and Q ′ (m) obtained by subjecting the orthogonal signals I (n) and Q (m) output in the orthogonal demodulation step to band limitation processing are output. A signal processing method comprising: a filter processing step; and a timing adjustment step of adjusting a timing between the orthogonal signals I ′ (n) and Q ′ (m) subjected to band limitation processing by the filter processing step. , The orthogonal signals I (n) and Q (m) take a value of 0 at every other sampling point, and at every other sampling point m where I (m) = 0, Q (m ) = A (m) or Q (m) = − A (m), and at every other sampling point n where Q (n) = 0, I (n) = A (n), Or, I (n) = − A (n), and the orthogonal demodulation step includes: The orthogonal signal I (n) that satisfies (n) = A (n) or I (n) = − A (n) and Q (m) = A (m) or Q (m) = − The orthogonal signal Q (m) that becomes A (m) is output to the filtering step.

  The present invention provides a signal processing apparatus and a signal processing method capable of executing broadband signal processing by reducing the number of multipliers used.

It is a block diagram which shows the structure of the signal processing apparatus as embodiment of this invention. It is a block diagram which shows the detailed structure of FPGA with which the signal processing apparatus as embodiment of this invention is provided. It is a block diagram which shows the detailed structure of the orthogonal demodulation part comprised by FPGA. It is a figure which shows the timing when data are input into the orthogonal demodulation part comprised by FPGA. It is a figure which shows the timing which data are output from the orthogonal demodulation part comprised by FPGA. It is a block diagram of the FIR filter comprised by FPGA. It is a figure which shows the relationship between the input data and filter coefficient in the FIR filter comprised by FPGA. It is a block diagram of the FIR filter arrange | positioned in the back | latter stage of the FIR filter of FIG. It is a figure for demonstrating the interpolation process by the I / Q timing adjustment part with which the signal processing apparatus as embodiment of this invention is provided. It is a flowchart for demonstrating the signal processing by the signal processing apparatus as embodiment of this invention. It is a block diagram which shows the structure of the conventional orthogonal demodulation part. It is a block diagram of the conventional HBF.

  Hereinafter, embodiments of a signal processing device and a signal processing method according to the present invention will be described with reference to the drawings.

  As shown in FIG. 1, the signal processing apparatus 1 as an embodiment of the present invention includes an operation unit 11, a frequency conversion unit 12, an A / D conversion unit 13, an FPGA 14, a waveform memory 15, a data processing unit 16, and a display unit 17. And a control unit 18.

  The operation unit 11 is operated by a user in order to select a communication standard of a signal under measurement output from a device under test (DUT) 100 from a plurality of communication standards. The operation unit 11 includes, for example, a display that displays a plurality of communication standards in a selectable manner and an input device such as a keyboard, a dial, or a mouse.

  The communication standards supported by the DUT 100 include, for example, cellular (LTE, LTE-A, W-CDMA (registered trademark), GSM (registered trademark), CDMA2000, 1xEV-DO, TD-SCDMA, etc.), WLAN (IEEE802.11b). / G / a / n / ac / ad, etc.), Bluetooth (registered trademark), GNSS (GPS, Galileo, GLONASS, BeiDou, etc.), FM, and digital broadcasting (DVB-H, ISDB-T, etc.).

The frequency conversion unit 12 includes a local oscillator 12a and a mixer 12b. The local oscillator 12a is made of, for example, by a PLL circuit, and generates a local oscillation signal of a frequency f _L corresponding to the communication standard selected by the operation unit 11, adapted to deliver to the mixer 12b. The mixer 12b multiplies the local oscillation signal having the frequency f _L input from the local oscillator 12a by the analog measured signal having the frequency f _R input from the DUT 100, and the measured signal is multiplied by a predetermined intermediate frequency F _IF. The frequency is converted to.

The A / D conversion unit 13 samples the signal under measurement frequency-converted by the local oscillator 12a and the mixer 12b at a sampling frequency Fs (F _IF = Fs / 4) that is four times the intermediate frequency F _IF to obtain digital data A The digital data A (n) is output to the FPGA 14 after being converted into (n). Here, n is an index representing a sampling point by the sampling frequency Fs, and is an integer of 0 or more.

  The FPGA 14 orthogonally demodulates the digital data A (n) output from the A / D converter 13 to generate orthogonal signals I ′ (n) and Q ′ (m). Here, n and m are indexes indicating sampling points based on the sampling frequency Fs, and are integers of 0 or more. Further, the FPGA 14 outputs quadrature signals I ″ (n) and Q ″ (m) in which the timings of the quadrature signals I ′ (n) and Q ′ (m) are adjusted by an I / Q timing adjustment unit 30 described later. It may be a thing.

  The waveform memory 15 stores data of the orthogonal signals I ′ (n) and Q ′ (m) output from the FPGA 14. The waveform memory 15 stores data of the orthogonal signals I ″ (n) and Q ″ (m) whose timing is adjusted by an I / Q timing adjusting unit 30 described later.

  The data processing unit 16 reads the data of the orthogonal signals I ″ (n) and Q ″ (m) after timing adjustment from the waveform memory 15 and performs arbitrary data processing such as FFT processing on these data. It has become. Further, the data processing unit 16 may include an I / Q timing adjustment unit 30 described later.

  The display unit 17 is configured by a display device such as an LCD or CRT, for example, and displays various display contents in accordance with a control signal from the control unit 18. This display content may include operation results such as processing results output from the data processing unit 16, soft keys for setting measurement conditions, pull-down menus, text boxes, and the like.

  The control unit 18 is constituted by a microcomputer including, for example, a CPU, a ROM, a RAM, and the like. The control unit 18 controls the operation of each unit constituting the signal processing device 1 and executes a predetermined program, thereby causing the data processing unit 16 to operate. It is configured as software.

  The signal processing device 1 may be configured to be remotely controlled by an external control device via a remote control interface such as GPIB, Ethernet (registered trademark), or USB.

  Hereinafter, the functional configuration of the FPGA 14 will be described with reference to FIG. The FPGA 14 includes an ADC interface (hereinafter also referred to as “ADCIF”) 21, an orthogonal demodulation unit 22, an FIR filter 23, a waveform memory interface (hereinafter also referred to as “waveform memory IF”) 24, and an I / Q timing adjustment unit 30. Have.

  The ADCIF 21 functions as a parallel separator that performs serial-parallel conversion on the digital data A (n) output from the A / D converter 13 and separates it into N (N is a positive even number) parallel data. The operation clock of the FPGA 14 is 1 / N of the sampling frequency Fs, and the ADCIF 21 sequentially outputs the N pieces of parallel data at a rate of Fs / N.

  The orthogonal demodulator 22 performs orthogonal demodulation on the N parallel data output from the ADCIF 21 and outputs baseband orthogonal signals I (n) and Q (m).

  The FIR filter 23 outputs orthogonal signals I ′ (n) and Q ′ (m) obtained by subjecting the orthogonal signals I (n) and Q (m) output from the orthogonal demodulator 22 to band limitation processing. It has become. One or more FIR filters 26 having an arbitrary number of taps for performing the band limiting process may be arranged at the subsequent stage of the FIR filter 23. The number of FIR filters arranged at the subsequent stage of the FIR filter 23 depends on a desired data rate.

  The I / Q timing adjustment unit 30 adjusts the timing between the orthogonal signals I ′ (n) and Q ′ (m) that have been subjected to the band limiting process by the FIR filter 23 or 26.

  The waveform memory IF 24 is an interface that transmits and receives data to and from the waveform memory 15 and the I / Q timing adjustment unit 30. The parallel data of the quadrature signals I ′ (n) and Q ′ (m) after the band limiting process output from the FIR filter 23 or 26 is stored in the waveform memory 15 as waveform data via the waveform memory IF24. Further, the parallel data of the orthogonal signals I ″ (n) and Q ″ (m) whose timing is adjusted by the I / Q timing adjusting unit 30 is also stored in the waveform memory 15 as waveform data via the waveform memory IF24.

Hereinafter, processing performed by the orthogonal demodulation unit 22 of the present embodiment will be described. In the present embodiment, since the intermediate frequency F _IF is a value that is ¼ of the sampling frequency Fs, orthogonal demodulation of the input parallel data is performed according to the following equations (5) and (6). In the expressions (5) and (6), the parentheses of the trigonometric functions of the expressions (1) and (2) are multiples of π / 2. That is, in the trigonometric function parts of the equations (5) and (6), the I-phase side repeats 0, 1, 0, −1,..., And the Q-phase side is 1, 0, −1, 0, Repeatedly.

  Accordingly, the quadrature signal I (n) on the I-phase side is, for example, I (0) = 0, I (1) = A (1), I (2) = 0, I (3) = − A (3), As in..., 0 is taken at every other sampling point. Similarly, for the quadrature signal Q (m) on the Q phase side, for example, Q (0) = A (0), Q (1) = 0, Q (2) = − A (2), Q (3) = It takes a value of 0 at every other sampling point, such as 0,.

  That is, for each sampling point n, one of the quadrature signal on the I-phase side and the quadrature signal on the Q-phase side contains data A (n), and the other is 0. Further, at every other sampling point m where I (m) = 0, Q (m) = A (m) or Q (m) = − A (m). Further, at every other sampling point n where Q (n) = 0, I (n) = A (n) or I (n) = − A (n).

  In the present embodiment, by utilizing this fact, the quadrature demodulator 22 uses the quadrature signal I (n) where I (n) = A (n) or I (n) = − A (n), An orthogonal signal Q (m) satisfying Q (m) = A (m) or Q (m) = − A (m) is output to the FIR filter 23.

  That is, the orthogonal demodulator 22 generates parallel data of N orthogonal signals from the N parallel data. Compared with the conventional quadrature demodulator shown in FIG. 11, the digital data A (n) after quadrature demodulation is thinned out to ½.

  Specifically, as shown in FIG. 3, unlike the conventional quadrature demodulator, the quadrature demodulator 22 can be configured without using a multiplier. Thereby, the number of lanes on the input side and the number of lanes on the output side can be made equal. In FIG. 3, the number of lanes N on both the input side and the output side is 24. Further, the orthogonal demodulator 22 inverts the sign of the digital data A (n) input to the lane in which the code inversion units 22a and 22b are arranged in the code inversion units 22a and 22b.

  As shown in FIG. 4, N parallel data are sequentially input to each lane on the input side of the orthogonal demodulator 22 at a rate of 1 / N of the sampling frequency Fs. Here, the sampling frequency Fs is 4800 MHz, for example.

  Further, as shown in FIG. 5A, from the lanes i0 to i11 on the I-phase output side of the quadrature demodulator 22, N / 2 orthogonal signals are paralleled at a rate of 1 / N of the sampling frequency Fs. Data is output sequentially. Further, as shown in FIG. 5B, from the lanes q0 to q11 on the Q-phase output side of the quadrature demodulator 22, N / 2 orthogonal signals are paralleled at a rate of 1 / N of the sampling frequency Fs. Data is output sequentially.

  Hereinafter, the configuration of the FIR filter 23 of the present embodiment will be described with reference to FIGS. The FIR filter 23 is, for example, a modified HBF with 11 taps, and has a bandwidth that is ½ of the sampling frequency Fs.

  As shown in FIG. 6, the FIR filter 23 of the present embodiment includes N / 2 I-phase filters 23a for the quadrature signal I (n) corresponding to each lane on the I-phase output side of the quadrature demodulator 22. N / 2 Q-phase filters 23b for quadrature signals Q (m) corresponding to the lanes on the Q-phase output side of the quadrature demodulator 22.

FIG. 7A shows that when the I-phase filter 23a is regarded as an HBF with 11 taps, the data set of the orthogonal signal I (n) centered on the timing of n = 5 is the I-phase filter 23a. The relationship between the quadrature signal and the filter coefficient is shown. Here, as an example, the magnitude relationship between the filter coefficients is C ₂ <C ₀ <C ₄ <C ₅ (C ₅ is the maximum value of the filter coefficients).

According to Expression (5), I (n) where n is an even number takes a value of 0, and thus is not output from the orthogonal demodulator 22 to the FIR filter 23. For I (n) where n is an odd number, the corresponding filter coefficient is 0 except for I (5) as shown in FIG. For this reason, the output of the I-phase filter 23a is C ₅ × I (5).

Therefore, as shown in FIG. 6 (a), I phase filter 23a may be any one of the filter coefficients _{C 5} and I (n) (n is an odd number) of the multiplier 25a for multiplying the ones with one . Incidentally, I (n) (n is an odd number) corresponds to the data _{D 3} in FIG. 6 (a). The output of the I-phase filter 23a can be expressed as Equation (7).

  On the other hand, FIG. 7B shows a case where the data set of the quadrature signal Q (m) centered around the timing of m = 4 is Q phase, assuming that the Q phase filter 23b is an HBF with 11 taps. The relationship between an orthogonal signal and a filter coefficient in the case of inputting to the filter 23b is shown.

According to Equation (6), Q (m) where m is an odd number takes a value of 0, and therefore is not output from the orthogonal demodulator 22 to the FIR filter 23. For Q (m) where m is an even number, the corresponding filter coefficient is 0 except for Q (4) as shown in FIG. For this reason, the output of the Q-phase filter 23b is C ₅ × Q (4).

Therefore, as shown in FIG. 6 (b), Q-phase filter 23b may be any (the m even) one filter coefficient _{C 5} and Q (m) a multiplier 25b for multiplying the ones with one . Incidentally, Q (m) (m is an even number) corresponds to the data _{D 3} in FIG. 6 (b). The output of the Q-phase filter 23b can also be expressed as in the above equation (7).

  In this embodiment, as already described, the quadrature signals of each phase are I (0) = 0, I (1) = 1, I (2) = 0, I (3) = − 1,. Thus, the data is such that 0 appears alternately. For this reason, the I-phase filter 23a and the Q-phase filter 23b can be simplified as shown in FIG.

  In FIG. 6, the number of multipliers of the I-phase filter 23a is one, and the number of multipliers of the Q-phase filter 23b is also one. That is, the average number of multipliers assigned per lane on the output side of the quadrature demodulator 22 is one, which is a quarter of the number compared to the conventional HBF of FIG.

  Note that the number of multipliers of the I-phase filter 23a or the Q-phase filter 23b depends on the filter shape, the filter coefficient, and the number of filter taps. For example, if the I-phase filter 23a or the Q-phase filter 23b is designed based on a 121-tap HBF, the number of multipliers is 1/31 compared to a conventional HBF.

  As is clear from the description regarding FIG. 7 above, the timing of the orthogonal signal I ′ (n) and the orthogonal signal Q ′ (m) output from the FIR filter 23 is shifted by one sample. It is stored in the waveform memory 15 in a state.

  As described above, one or more FIR filters 26 that perform the band limiting process may be arranged at the subsequent stage of the FIR filter 23 described above. As the FIR filter 26, for example, a conventional HBF can be used. FIG. 8 shows the configuration of an HBF with 11 taps.

As shown in FIG. 8, the FIR filter 26 includes N HBFs 40 arranged corresponding to the N lanes on the output side of the FIR filter 23. The HBF 40 arranged in each lane on the I-phase side has four filter coefficients C ₀ , C ₂ , C ₄ , C ₅ and I ′ (i), I ′ (i + 2), I ′ ( Four multipliers to which seven data of i + 4), I ′ (i + 6), I ′ (i + 8), I ′ (i + 10), I ′ (i + 12) (i is an odd number of 0 or more) are input.

Note that I ′ (i), I ′ (i + 2), I ′ (i + 4), I ′ (i + 6), I ′ (i + 8), I ′ (i + 10), and I ′ (i + 12) are data D in FIG. _{0, D 1, D 2,} D 3, D 4, D 5, respectively correspond to _{D 6.}

Similarly, the HBF 40 arranged in each lane on the Q-phase side has four filter coefficients C ₀ , C ₂ , C ₄ , C ₅ and temporally continuous Q ′ (j), Q ′ (j + 2), 4 multipliers to which 7 data Q ′ (j + 4), Q ′ (j + 6), Q ′ (j + 8), Q ′ (j + 10), Q ′ (j + 12) (j is an even number of 0 or more) are input. Prepare.

Q ′ (j), Q ′ (j + 2), Q ′ (j + 4), Q ′ (j + 6), Q ′ (j + 8), Q ′ (j + 10), and Q ′ (j + 12) are the data D in FIG. _{0, D 1, D 2,} D 3, D 4, D 5, respectively correspond to _{D 6.}

That is, as shown in FIG. 8, HBF40 is added for adding an adder 25c for adding the data _{D 0} and _{D 6,} and an adder 25d for adding the data _{D 1} and _{D 5,} the data _{D 2} and _{D 4} and vessels 25e, a multiplier 25f for multiplying the filter coefficients _{C 0} to the sum of the data _{D 0} and _{D 6,} a multiplier 25g for multiplying the filter coefficients _{C 2} to the sum of the data _{D 1} and _{D 5,} the data _{D 2} a multiplier 25h by multiplying the sum of D ₄ filter coefficients _{C 4,} a multiplier 25i for multiplying the filter coefficients _{C 5} to the data _{D 3,} and an adder 25j for adding the multiplication result by the multiplier 25F～25i, the It is the composition which has.

  For this reason, when the conventional HBF 40 of FIG. 8 is arranged at the subsequent stage of the FIR filter 23 of FIG. 6, the number of multipliers allocated per lane on the output side of the FIR filter 23 is four.

  As described above, for the quadrature signals I ′ (n) and Q ′ (m) output from the FIR filter 23 or 26, the I-phase data I ′ (n) and the Q-phase data Q ′ (m) Are shifted from each other by one sample. For this reason, the I / Q timing adjustment unit 30 performs interpolation processing described below to correct this timing shift.

  Specifically, the I / Q timing adjustment unit 30 takes in the orthogonal signals I ′ (n) and Q ′ (m) output from the FIR filter 23 or 26 from the waveform memory 15 via the waveform memory IF 24.

  The I / Q timing adjusting unit 30 performs an interpolation process on the orthogonal signal I ′ (n) at the sampling point n where I (n) = A (n) or I (n) = − A (n). By doing so, an orthogonal signal I ″ (m) corresponding to every other sampling point m where n ≠ m is calculated.

  Alternatively, the I / Q timing adjustment unit 30 interpolates the orthogonal signal Q ′ (m) at the sampling point m where Q (m) = A (m) or Q (m) = − A (m). By performing the processing, an orthogonal signal Q ″ (n) corresponding to every other sampling point n where n ≠ m is calculated.

An interpolation value obtained by using each data of the orthogonal signal I ′ (n) is given as shown in Expression (8) using the interpolation function f _int (x). Similarly, an interpolation value obtained using each data of the orthogonal signal Q ′ (m) is given as shown in Expression (9) using the interpolation function f _int (x). As the interpolation function f _int (x), for example, a sinc function as shown in Expression (10) can be used.

  FIG. 9 is a diagram illustrating an interpolation process when the timing of the orthogonal signal Q ′ (m) is matched with the orthogonal signal I ′ (n). Equation (9) is a sinc function value centered on the sampling timing x of Q ″ (x) to be obtained with respect to the data set of the orthogonal signal Q ′ (m) as shown in FIG. 9A illustrates a sinc function centered on the timing of x = 7 as an example.

  By calculating the expression (9) for each sampling timing x, the value of Q ″ (x) other than the sampling point m is obtained as shown in FIG. 9B. ), It is possible to obtain the value of the orthogonal signal Q ″ (n) as shown in FIG. 9B by setting x = n (n ≠ m).

  In the above description, the timing of the orthogonal signal Q ′ (m) is matched with the orthogonal signal I ′ (n). However, the present invention is not limited to this, and the timing of the orthogonal signal I ′ (n) is orthogonal. It may be adjusted to the signal Q ′ (m). In this case, interpolation processing using equation (8) is performed.

  The data of the orthogonal signals I ″ (n) and Q ″ (m) whose timing is adjusted in this way is stored in the waveform memory 15.

  The above interpolation processing can be realized, for example, by forming an FIR filter whose filter coefficient is given by a sinc function as the I / Q timing adjustment unit 30 in the FPGA 14. Alternatively, the above interpolation processing can be realized by software that performs calculations corresponding to the equations (8) to (10).

  Hereinafter, a signal processing method using the signal processing apparatus 1 of the present embodiment will be described with reference to the flowchart of FIG.

First, the frequency converter 12 converts the analog signal under measurement having the frequency f _R into a predetermined intermediate frequency F _IF using the local oscillation signal having the frequency f _L according to the communication standard selected by the operation unit 11. (Step S1).

Next, the A / D converter 13 samples the signal under measurement subjected to frequency conversion in step S1 at a sampling frequency Fs that is four times the intermediate frequency F _IF and converts it into digital data A (n) (step S2). ).

  Next, the ADCIF 21 performs serial-parallel conversion on the digital data A (n) obtained in step S2 and separates it into N pieces (N is a positive even number) of parallel data at a rate of 1 / N of the sampling frequency Fs. The N pieces of parallel data are sequentially output (step S3).

  Next, the orthogonal demodulator 22 performs orthogonal demodulation on the N pieces of parallel data output in step S3, and outputs baseband orthogonal signals I (n) and Q (m) (step S4). Here, the orthogonal signal I (n) output by the orthogonal demodulator 22 is I (n) = A (n) or I (n) = − A (n). The quadrature signal Q (m) output from the quadrature demodulator 22 is Q (m) = A (m) or Q (m) = − A (m).

  Next, the FIR filter 23 applies orthogonal signals I ′ (n) and Q ′ (m) obtained by subjecting the orthogonal signals I (n) and Q (m) obtained in step S4 to band limitation processing. Output (step S5).

  Next, the I / Q timing adjustment unit 30 adjusts the timing between the orthogonal signals I ′ (n) and Q ′ (m) that have been subjected to the band limiting process in step S5 (step S6).

  As described above, the signal processing apparatus of this embodiment performs orthogonal demodulation on N parallel data and outputs orthogonal signals I (n) and Q (m), and is output from the orthogonal demodulation means. The quadrature signals I (n) and Q (m) are provided with filter processing means for performing band limiting processing. The quadrature signal I (n) of n) and the quadrature signal Q (m) of Q (m) = A (m) or Q (m) = − A (m) are output to the filter processing means.

  With the above configuration, the orthogonal demodulation means can be configured without using a multiplier. Thereby, I / Q conversion can be performed without changing the data amount before and after the orthogonal demodulation means.

  Further, in the signal processing apparatus of the present embodiment, the timing adjustment means is the orthogonal signal I ′ (at the sampling point n where I (n) = A (n) or I (n) = − A (n). By performing an interpolation process on n), an orthogonal signal I ″ (m) corresponding to every other sampling point m where n ≠ m is calculated.

  Alternatively, the timing adjustment unit performs an interpolation process on the orthogonal signal Q ′ (m) at the sampling point m where Q (m) = A (m) or I (m) = − A (m). Thus, an orthogonal signal Q ″ (n) corresponding to every other sampling point n where n ≠ m is calculated.

  The I-phase data and the Q-phase data output from the filter processing means are shifted in timing by one sample, but according to the above configuration, the timing of the I-phase data and the Q-phase data can be matched. it can.

  In the signal processing apparatus of the present embodiment, the filter processing means includes N / 2 filters for the orthogonal signal I (n) output from the orthogonal demodulation means and the orthogonal signal Q output from the orthogonal demodulation means. (M) N / 2 filters. Each filter for the orthogonal signal I (n) has one multiplier that multiplies one filter coefficient by the orthogonal signal I (n) output from the orthogonal demodulation means. Each filter for the quadrature signal Q (m) has one multiplier that multiplies one filter coefficient by the quadrature signal Q (m) output from the quadrature demodulation means.

  With the configuration described above, the number of multipliers used in the filter processing means can be significantly reduced as compared with the conventional HBF. In addition, band limiting processing can be performed on the orthogonal signals I (n) and Q (m) output from the orthogonal demodulation means.

DESCRIPTION OF SYMBOLS 1 Signal processing apparatus 11 Operation part 12 Frequency conversion part (frequency conversion means)
12a Local oscillator 12b Mixer 13 A / D converter (A / D converter)
14 FPGA
DESCRIPTION OF SYMBOLS 15 Waveform memory 16 Data processing part 17 Display part 18 Control part 21 ADC interface (parallel separation means)
22 Quadrature demodulator (orthogonal demodulator)
22a, 22b Sign inversion unit (orthogonal demodulation means)
23, 26 FIR filter (filter processing means)
23a I-phase filter (filter processing means)
23b Q-phase filter (filter processing means)
24 waveform memory interface 25a, 25b, 25f-25i multiplier 25c-25e, 25j adder 30 I / Q timing adjustment unit (timing adjustment means)
100 DUT

Claims (5)

A frequency converting means (12) for converting the analog signal under measurement into a predetermined intermediate frequency;
A signal to be measured, frequency-converted by the frequency conversion means, is sampled at a sampling frequency four times the intermediate frequency and converted into digital data A (n) (n is an index indicating a sampling point by the sampling frequency) A / D conversion means (13);
The digital data is serial-parallel converted to be separated into N pieces (N is a positive even number) parallel data, and parallel separation means (21 for sequentially outputting the N pieces of parallel data at a rate of 1 / N of the sampling frequency. )When,
Orthogonal demodulation means (22) for orthogonally demodulating the N parallel data and outputting orthogonal signals I (n) and Q (m) (n and m are indexes indicating sampling points according to the sampling frequency);
Filter processing means (23) for outputting orthogonal signals I ′ (n) and Q ′ (m) obtained by subjecting the orthogonal signals I (n) and Q (m) output from the orthogonal demodulation means to band limitation processing When,
A signal processing device (1) comprising: timing adjustment means (30) for adjusting timing between the orthogonal signals I ′ (n) and Q ′ (m) subjected to band limitation processing by the filter processing means. And
The orthogonal signals I (n) and Q (m) take a value of 0 at every other sampling point,
At every other sampling point m where I (m) = 0, Q (m) = A (m) or Q (m) = − A (m)
At every other sampling point n where Q (n) = 0, I (n) = A (n) or I (n) = − A (n)
The orthogonal demodulator means that the orthogonal signal I (n) that satisfies I (n) = A (n) or I (n) = − A (n) and Q (m) = A (m), or , Q (m) = − A (m), and outputs the orthogonal signal Q (m) to the filter processing means.   The timing adjusting means performs an interpolation process on the orthogonal signal I ′ (n) at a sampling point n where I (n) = A (n) or I (n) = − A (n). 2. The signal processing apparatus according to claim 1, wherein an orthogonal signal I ″ (m) corresponding to every other sampling point m where n ≠ m is calculated by   The timing adjusting unit performs an interpolation process on the orthogonal signal Q ′ (m) at a sampling point m where Q (m) = A (m) or I (m) = − A (m). 2. The signal processing apparatus according to claim 1, wherein an orthogonal signal Q ″ (n) corresponding to every other sampling point n where n ≠ m is calculated. The filter processing means includes N / 2 filters (23a) for the orthogonal signal I (n) output from the orthogonal demodulation means, and for the orthogonal signal Q (m) output from the orthogonal demodulation means. N / 2 filters (23b),
Each of the filters for the orthogonal signal I (n) includes one multiplier (25a) that multiplies one filter coefficient by the orthogonal signal I (n) output from the orthogonal demodulator.
Each of the filters for the orthogonal signal Q (m) includes a multiplier (25b) that multiplies one filter coefficient by the orthogonal signal Q (m) output from the orthogonal demodulation means. The signal processing apparatus according to claim 1, wherein the signal processing apparatus is characterized in that: A frequency conversion step (S1) for converting the analog signal under measurement to a predetermined intermediate frequency;
A to-be-measured signal frequency-converted in the frequency conversion step is sampled at a sampling frequency four times the intermediate frequency and converted into digital data A (n) (n is an index indicating a sampling point based on the sampling frequency) A / D conversion step (S2);
A parallel separation step (S3) of serially parallel-converting the digital data into N (N is a positive even number) parallel data and sequentially outputting the N parallel data at a rate of 1 / N of the sampling frequency. )When,
An orthogonal demodulation step (S4) for orthogonally demodulating the N parallel data and outputting orthogonal signals I (n) and Q (m) (n and m are indexes indicating sampling points according to the sampling frequency);
Filter processing step (S5) for outputting orthogonal signals I ′ (n) and Q ′ (m) obtained by subjecting the orthogonal signals I (n) and Q (m) output in the orthogonal demodulation step to band limitation processing When,
A timing adjustment step (S6) for adjusting a timing between the orthogonal signals I ′ (n) and Q ′ (m) that have been subjected to band limitation processing in the filtering step,
The orthogonal signals I (n) and Q (m) take a value of 0 at every other sampling point,
At every other sampling point m where I (m) = 0, Q (m) = A (m) or Q (m) = − A (m)
At every other sampling point n where Q (n) = 0, I (n) = A (n) or I (n) = − A (n)
The quadrature demodulation step includes I (n) = A (n), or the quadrature signal I (n) where I (n) = − A (n) and Q (m) = A (m), or , Q (m) = − A (m), wherein the orthogonal signal Q (m) is output to the filter processing step.

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