JP2017034074A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit the occurrence of poor connection at an interface of substrates connected by bonding.SOLUTION: A semiconductor device of an embodiment comprises a first substrate and a second substrate bonded to the first substrate. The first substrate has a first conductive pattern and a second conductive pattern. The second substrate has a third conductive pattern and a fourth conductive pattern. The second conductive pattern is formed thinner than the first conductive pattern. A lower layer side of the first conductive pattern is connected to a first via connected to a first lower layer side pattern. Further, the first conductive pattern and the third conductive pattern are connected in an overlapping manner. The second conductive pattern and the fourth conductive pattern are connected in an overlapping manner.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  There is a semiconductor device in which the occupation area can be reduced by stacking semiconductor chips in multiple stages. Such a semiconductor device is manufactured, for example, by laminating substrates on which semiconductor elements and integrated circuits are formed in multiple stages and dicing in units of semiconductor chips.

  An insulating layer is provided on the surface of each substrate to be bonded, and a plurality of electrodes connected by bonding the substrate are provided at corresponding positions on the surface of each insulating layer. However, due to the expansion of the electrodes when the substrates are bonded together, a bonding failure may occur at the bonding surface between the substrates.

JP 2012-256736 A

  An object of one embodiment is to provide a semiconductor device capable of suppressing a connection failure from occurring in a joint portion connected by bonding of substrates.

  According to one embodiment, a semiconductor device is provided. The semiconductor device includes a first substrate and a second substrate bonded to the first substrate. The first substrate has a first conductive pattern and a second conductive pattern. The second substrate has a third conductive pattern and a fourth conductive pattern. The second conductive pattern is formed thinner than the first conductive pattern. The lower layer side of the first conductive pattern is connected to a first via connected to the first lower layer side pattern. Further, the first conductive pattern and the third conductive pattern are overlapped and connected. Further, the second conductive pattern and the fourth conductive pattern are overlapped and connected.

Drawing 1 is a figure for explaining the pasting process of a substrate. FIG. 2 is a diagram for explaining the configuration and thermal expansion of the substrate according to the first embodiment. FIG. 3 is a diagram for explaining the arrangement positions of the dummy electrodes according to the first embodiment. FIG. 4 is a diagram for explaining thermal expansion when the thickness of the dummy electrode is the same as the thickness of the connection electrode. FIG. 5 is a diagram for explaining the arrangement positions of the wiring patterns according to the second embodiment.

  Exemplary embodiments of a semiconductor device will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment. Hereinafter, a so-called Wafer on Wafer for bonding a substrate on which a logic circuit is formed and a substrate on which an image sensor is formed will be described as an example. However, the semiconductor device according to the present embodiment is a chip on Wafer or It can also be used for Chip on Chip. The circuit formed on each substrate is not limited to a logic circuit or an image sensor, and may be an arbitrary semiconductor integrated circuit.

(First embodiment)
Drawing 1 is a figure for explaining the pasting process of a substrate. In addition, in FIG. 1, the component required for bonding of a board | substrate is selectively illustrated among the components with which the bonding apparatus 41 which bonds a board | substrate is equipped.

  The bonding apparatus 41 bonds the first substrate 20A and the second substrate 20B. An insulating layer 21A made of, for example, silicon oxide is formed on the surface of the first substrate 20A. Similarly, an insulating layer 21B made of, for example, silicon oxide is formed on the surface of the second substrate 20B.

  Here, the first substrate 20A and the second substrate 20B are semiconductor substrates such as silicon wafers, for example. A logic circuit (not shown) or the like is already built in the first substrate 20A. In addition, the wiring connected to the logic circuit is already formed in the insulating layer 21A.

  Further, an image sensor (not shown) or the like is already built in the second substrate 20B. Further, the wiring connected to the image sensor is already built in the insulating layer 21B. Note that the first substrate 20A may be a substrate on which an image sensor is formed, and the second substrate 20B may be a substrate on which a logic circuit is formed.

  The board | substrate bonding process is performed by the bonding apparatus 41 shown in FIG. Specifically, the bonding apparatus 41 includes a stage 42, a support body 43, and a pressurizer 44. The stage 42 holds the first substrate 20A by suction. The support body 43 is configured to be movable back and forth in the horizontal direction and supports the second substrate 20B. The pressurizer 44 is configured to be movable up and down and presses the second substrate 20B.

  When the first substrate 20A and the second substrate 20B are bonded by the bonding device 41, as shown in FIG. 1A, first, the insulating layer 21A is placed on the first substrate 20A. It is mounted on the stage 42 in such a manner that it is held by the stage 42.

  Subsequently, the peripheral portion of the surface of the insulating layer 21B (here, the lower surface) is supported by the support body 43 so that the second substrate 20B on which the image sensor has already been formed has the insulating layer 21B below. At this time, for example, by aligning the orientation flats and notches of the first substrate 20A and the second substrate 20B, the first substrate 20A side electrode (a connection electrode 30A described later) and the second substrate 20B are aligned. The vertical position with the side electrode (connection electrode 30B described later) is aligned.

  Further, the vertical positions of the electrode on the first substrate 20A side and the electrode on the second substrate 20B side may be aligned by aligning the pattern positions of the first substrate 20A and the second substrate 20B. In that case, in order to correct the warp of the second substrate 20B, the support 43 of the bonding apparatus 41 preferably has a stage shape that holds the second substrate 20B by suction.

  Thereafter, as shown in FIG. 1B, the pressurizer 44 is lowered and the upper surface center position of the second substrate 20 </ b> B is pressed by the pressurizer 44. As a result, the second substrate 20B is curved, and the center of the surface of the insulating layer 21B on the second substrate 20B side and the surface center of the insulating layer 21A on the first substrate 20A side are joined.

  Subsequently, as shown in FIG. 1C, the support of the second substrate 20 </ b> B is released by retracting the support body 43. Thereby, the junction between the insulating layer 21B on the second substrate 20B side and the insulating layer 21A on the first substrate 20A side spreads from the center to the peripheral portion.

  Thereafter, finally, as shown in FIG. 1D, the entire surface of the insulating layer 21B on the second substrate 20B side and the entire surface of the insulating layer 21A on the first substrate 20A side are bonded. And the pressurizer 44 is raised and the bonding strength between the insulating layers 21A and 21B is increased by applying heat treatment to the bonding substrate, and the bonding between the first substrate 20A and the second substrate 20B is completed. .

  Next, configurations of the first substrate 20A and the second substrate 20B according to the first embodiment will be described. FIG. 2 is a diagram for explaining the configuration and thermal expansion of the substrate according to the first embodiment. 2A to 2C show cross-sectional configurations of the first substrate 20A and the second substrate 20B.

  In the first substrate 20A, a hole is formed in a part of the insulating layer 21A. Then, the connection electrode 30A and the dummy electrode 22A are embedded in the drilled position. Each of the connection electrode 30A and the dummy electrode 22A is a conductive pattern.

  The connection electrode 30A is disposed on the upper layer side of the via 31A and is formed to be joined to the via 31A. The via 31A connects a pattern (not shown) (not shown) on the lower layer side of the via 31A and the connection electrode 30A.

  The dummy electrode 22A is formed in a part of the insulating layer 21A where the connection electrode 30A is not disposed. The dummy electrode 22A is a dummy pattern that is not connected to the pattern on the lower layer side. In the first substrate 20A, since the connection electrode 30A and the dummy electrode 22A are disposed on the insulating layer 21A, the insulating layer 21A can be planarized. The reason why the insulating layer 21A is planarized will be described later.

  Similarly, in the second substrate 20B, a hole is formed in a part of the insulating layer 21B. Then, the connection electrode 30B and the dummy electrode 22B are embedded in the drilled position. Each of the connection electrode 30B and the dummy electrode 22B is a conductive pattern.

  The connection electrode 30B is disposed on the upper layer side of the via 31B and is formed to be joined to the via 31B. The via 31B connects a pattern (not shown) (not shown) on the lower layer side of the via 31B and the connection electrode 30B.

  Further, the dummy electrode 22B is formed in a part of the insulating layer 21B where the connection electrode 30B is not disposed. The dummy electrode 22B is a dummy pattern that is not connected to the lower layer side pattern. In the second substrate 20B, since the connection electrode 30B and the dummy electrode 22B are disposed on the insulating layer 21B, the insulating layer 21B can be planarized. The reason why the insulating layer 21B is planarized will be described later.

  In the first substrate 20A of the present embodiment, the dummy electrode 22A is formed thinner than the connection electrode 30A. Specifically, the connection electrode 30A is embedded in the hole formed at the first depth H1a with respect to the insulating layer 21A, and is formed at the second depth H2a (H1a> H2a) with respect to the insulating layer 21A. A dummy electrode 22A is embedded in the hole. Thereby, the connection electrode 30A has a film thickness of H1a, and the dummy electrode 22A has a film thickness of H2a.

  In the second substrate 20B of the present embodiment, the dummy electrode 22B is formed thinner than the connection electrode 30B. Specifically, the connection electrode 30B is embedded in the hole formed at the third depth H1b with respect to the insulating layer 21B, and is formed at the fourth depth H2b (H1b> H2b) with respect to the insulating layer 21B. A dummy electrode 22B is embedded in the hole. As a result, the connection electrode 30B has a thickness of H1b, and the dummy electrode 22B has a thickness of H2b.

  When the opening for the connection electrode 30A is formed in the first substrate 20A, a resist is applied to the surface of the insulating layer 21A, and the resist is patterned using a lithography technique. Thereby, the resist at the position where the connection electrode 30A is formed is selectively removed.

  Subsequently, using the patterned resist as a mask, for example, anisotropic etching such as RIE (Reactive Ion Etching) is performed to form an opening on the surface of the insulating layer 21A. Here, an opening having a depth H1a reaching the via 31A connected to the logic circuit is formed. Thereafter, the resist is removed.

  Further, when the opening for the dummy electrode 22A is formed in the first substrate 20A, a resist is applied to the surface of the insulating layer 21A, and the resist is patterned using a lithography technique. Thereby, the resist at the position where the dummy electrode 22A is formed is selectively removed.

  Subsequently, using the patterned resist as a mask, for example, anisotropic etching such as RIE is performed to form an opening on the surface of the insulating layer 21A. Here, an opening shallower than the opening for the connection electrode 30A (opening having a depth H2a) is formed as the opening for the dummy electrode 22A.

  Subsequently, after the resist is removed, a barrier metal or a seed metal (illustrated) is formed on the surface of the insulating layer 21A where the opening for the connection electrode 30A and the opening for the dummy electrode 22A are formed by, for example, PVD (Physical Vapor Deposition). Is omitted). Thereafter, copper is deposited by electrolytic plating to fill the opening, thereby forming a metal layer.

  The metal layer may be formed by CVD (Chemical Vapor Deposition). The material of the metal layer may be a material other than copper. Alternatively, the opening for the dummy electrode 22A may be formed first, and the opening for the connection electrode 30A may be formed later.

  Thereafter, for example, the surface of the metal layer is polished by CMP (Chemical Mechanical Polishing) to remove the metal layer, barrier metal, and seed metal (not shown) on the surface of the insulating layer 21A.

  Thereby, as shown in FIG. 2A, in the first substrate 20A, the connection electrode 30A and the dummy electrode 22A, which are embedded in the opening and the surface is flush with the surface of the insulating layer 21A, are formed. The

  In addition, the second substrate 20B bonded to the first substrate 20A is also formed by the same manufacturing process as that of the first substrate 20A. As a result, in the second substrate 20B, the connection electrode 30B and the dummy electrode 22B are formed which are embedded in the opening and the surface is flush with the surface of the insulating layer 21B. Thus, the connection electrodes 30A and 30B and the dummy electrodes 22A and 22B are formed by, for example, a damascene process.

  Here, a process for activating the surfaces of the insulating layers 21A and 21B will be described. The step of activating the surface of the insulating layer 21A and the step of activating the surface of the insulating layer 21B are the same. Therefore, here, the step of activating the surface of the insulating layer 21A will be described, and detailed description of the process of activating the surface of the insulating layer 21B will be omitted.

  The treatment for activating the surface of the insulating layer 21A is performed by an activation device. In the activation device, the reactive gas in the chamber is turned into plasma. Then, the activation device causes cations in the plasma to collide with the insulating layer 21A. Thereby, the activation device generates dangling bonds on the surface of the insulating layer 21A. As a result, the surface of the insulating layer 21A is activated. The insulating layer 21B of the second substrate 20B is also activated in the same manner as the insulating layer 21A.

  Then, as shown in FIG. 2B, the first substrate 20 </ b> A and the second substrate 20 </ b> B are bonded together at the bonding surface 15. In this case, the connection electrode 30A and the connection electrode 30B are overlapped and connected, the dummy electrode 22A and the dummy electrode 22B are overlapped and connected, and the insulating layer 21A and the insulating layer 21B are overlapped and joined. Bonding is performed so that it does. As a result, both the surface of the insulating layer 21A and the surface of the insulating layer 21B are activated, so that the first substrate 20A and the second substrate 20B can be firmly and directly connected without using an adhesive. Can be pasted.

  When the first substrate 20A and the second substrate 20B are bonded, heat treatment is performed on the first substrate 20A and the second substrate 20B. By the heat treatment at this time, the connection electrode 30A on the first substrate 20A side and the connection electrode 30B on the second substrate 20B side are connected by thermal expansion.

  When the heat treatment is performed on the first substrate 20A and the second substrate 20B, the dummy electrodes 22A and 22B also thermally expand in the same manner as the connection electrodes 30A and 30B, as shown in FIG. As a result, in the dummy electrodes 22A and 22B, a force is generated in the peeling direction of the bonding surface 15. In this case, when the thickness of the dummy electrodes 22A and 22B is large, the force in the peeling direction of the bonding surface 15 increases.

  In this embodiment, since the film thickness (H2a) of the dummy electrode 22A is thinner than the film thickness (H1a) of the connection electrode 30A, the force in the peeling direction of the bonding surface 15 is weakened. Further, since the film thickness (H2b) of the dummy electrode 22B is thinner than the film thickness (H1b) of the connection electrode 30B, the force in the peeling direction of the bonding surface 15 is weakened. That is, the bonding surface 15 is peeled off when the thickness of the dummy electrode 22A is smaller than the thickness of the connection electrode 30A than when the thickness of the dummy electrode 22A is the same as the thickness of the connection electrode 30A. The direction force is weakened. Similarly, when the thickness of the dummy electrode 22B is smaller than the thickness of the connection electrode 30B, the thickness of the dummy electrode 22B is smaller than that of the connection electrode 30B. The force in the peeling direction is weakened.

  In this way, by making the depth of the dummy electrodes 22A and 22B formed on the bonding surface 15 shallower than that of the connection electrodes 30A and 30B, the amount of thermal expansion of the dummy electrodes 22A and 22B during heating can be kept small. it can. For this reason, peeling of the joint surface 15 does not occur. Therefore, it is possible to avoid a bonding failure between the connection electrodes 30A and 30B.

  Here, the reason why the dummy electrode 22A is arranged on the insulating layer 21A will be described. One of the steps of forming the connection electrode 30A is a step of polishing the surface of the metal layer by CMP to remove the metal layer on the surface of the insulating layer 21A. In this step, the polishing rate in CMP differs between a region where the metal layer is disposed and a region where the metal layer is not disposed (region of only the insulating layer).

  For this reason, the region where the metal layer is disposed is polished deeper than the region where the metal layer is not disposed. As a result, a step is generated between the region where the metal layer is disposed and the region where the metal layer is not disposed. Therefore, in the first substrate 20A, the dummy electrode 22A is disposed on the insulating layer 21A. For the same reason, the dummy electrode 22B is disposed on the insulating layer 21B in the second substrate 20B. Such an arrangement of the dummy electrodes 22A and 22B can suppress erosion. In other words, the insulating layers 21A and 21B can be planarized.

  Next, the arrangement positions of the dummy electrodes 22A and 22B will be described. FIG. 3 is a diagram for explaining the arrangement positions of the dummy electrodes according to the first embodiment. Since the dummy electrode 22A and the dummy electrode 22B have the same arrangement position, the arrangement position of the dummy electrode 22A will be described here. FIG. 3 shows a view of the first substrate 20A as viewed from above.

  The dummy electrode 22A is disposed around the connection electrode 30A. FIG. 3 shows a case where eight dummy electrodes 22A are arranged around the connection electrode 30A. An insulating layer 21A is disposed between the adjacent dummy electrodes 22A. For example, the dummy electrode 22A is arranged such that the connection electrode 30A and the dummy electrode 22A are arranged at a predetermined interval.

  The dummy electrode 22A may have a top surface shape different from that of the connection electrode 30A, but it is desirable that the dummy electrode 22A has a similar top surface shape. The dummy electrode 22A may have an area different from that of the connection electrode 30A, but is preferably the same area. Further, the dummy electrode 22A may be disposed at a symmetric position as viewed from the connection electrode 30A or may be disposed at an asymmetric position.

  Here, thermal expansion in the case where the film thickness of the dummy electrode is the same as the film thickness of the connection electrode will be described. FIG. 4 is a diagram for explaining thermal expansion when the thickness of the dummy electrode is the same as the thickness of the connection electrode. 4A to 4C show cross-sectional configurations of the substrate 60A and the substrate 60B.

  As shown in FIG. 4A, an insulating layer 61A, a dummy electrode 62A, a via 71A, and a connection electrode 70A are arranged on the substrate 60A. The insulating layer 61A is disposed in the same region as the insulating layer 21A when viewed from the front surface of the substrate 60A, and the dummy electrode 62A is disposed at the same position as the dummy electrode 22A when viewed from the front surface of the substrate 60A. Has been. The via 71A is disposed at the same position as the via 31A when viewed from the front surface of the substrate 60A, and the connection electrode 70A is disposed at the same position as the connection electrode 30A when viewed from the front surface of the substrate 60A. Has been.

  In addition, an insulating layer 61B, a dummy electrode 62B, a via 71B, and a connection electrode 70B are disposed on the substrate 60B. The insulating layer 61B is disposed in the same region as the insulating layer 21B when viewed from the front surface of the substrate 60B, and the dummy electrode 62B is disposed at the same position as the dummy electrode 22B when viewed from the front surface of the substrate 60B. Has been. The via 71B is disposed at the same position as the via 31B when viewed from the front surface of the substrate 60B, and the connection electrode 70B is disposed at the same position as the connection electrode 30B when viewed from the front surface of the substrate 60B. Has been.

  In the substrate 60A, the dummy electrode 62A is formed with the same thickness as the connection electrode 70A. For example, the connection electrode 70A is embedded in a hole formed at the fifth depth H3 with respect to the insulating layer 61A, and the dummy electrode 62A is embedded in a hole formed at the fifth depth H3 with respect to the insulating layer 61A. It is. Thereby, the connection electrode 70A and the dummy electrode 62A have a film thickness of H3.

  In the substrate 60B, the dummy electrode 62B is formed with the same thickness as the connection electrode 70B. For example, the connection electrode 70B is embedded in the hole formed at the sixth depth H4 with respect to the insulating layer 61B, and the dummy electrode 62B is embedded in the hole formed at the sixth depth H4 with respect to the insulating layer 61B. It is. Thus, the connection electrode 70B and the dummy electrode 62B have a film thickness of H4.

  After the substrates 60A and 60B are prepared, the substrate 60A and the substrate 60B are bonded together at the bonding surface 16 as shown in FIG. In this case, the bonding is performed so that the connection electrode 70A and the connection electrode 70B are joined and the dummy electrode 62A and the dummy electrode 62B are joined.

  When the substrate 60A and the substrate 60B are bonded, heat treatment is performed on the substrates 60A and 60B. By this heat treatment, the connection electrode 70A on the substrate 60A side and the connection electrode 70B on the substrate 60B side are connected by thermal expansion.

  When the heat treatment is performed on the substrates 60A and 60B, as shown in FIG. 4C, the dummy electrodes 62A and 62B also thermally expand in the same manner as the connection electrodes 70A and 70B. As a result, in the dummy electrodes 62A and 62B, a force is generated in the peeling direction of the joint surface 16. In this case, if the thickness of the dummy electrodes 62A and 62B is large, the force in the peeling direction of the bonding surface 16 increases.

  In the substrate 60A, since the film thickness (H3) of the dummy electrode 62A is the same as the film thickness (H3) of the connection electrode 70A, the force in the peeling direction of the bonding surface 16 is strong. Further, since the thickness (H4) of the dummy electrode 62B is the same as the thickness (H4) of the connection electrode 70B, the substrate 60B has a strong force in the peeling direction of the bonding surface 16.

  As described above, when the depth of the dummy electrodes 62A and 62B formed on the bonding surface 16 is the same as that of the connection electrodes 70A and 70B, the amount of thermal expansion of the dummy electrodes 62A and 62B during heating increases. For this reason, peeling of the joint surface 16 tends to occur. Therefore, it becomes easy to generate | occur | produce the joining defect of connection electrode 70A, 70B.

  In the present embodiment, the case where the dummy electrodes 22A and 22B are formed thinner than the connection electrodes 30A and 30B has been described. However, it is sufficient that at least one of the dummy electrodes 22A and 22B is thinner than the connection electrodes 30A and 30B. . For example, when the dummy electrode 22A is formed thinner than the connection electrode 30A, the dummy electrode 22B may have the same thickness as the connection electrode 30B. When the dummy electrode 22B is formed thinner than the connection electrode 30B, the dummy electrode 22A may have the same thickness as the connection electrode 30A.

  Moreover, although the case where two board | substrates were bonded was mentioned as an example in this embodiment, this embodiment is applicable also to the manufacturing method of the semiconductor device which bonds three or more board | substrates. In the case of bonding three or more substrates, electrodes are formed on the insulating layers provided on the front and back surfaces of each substrate, the surfaces of each insulating layer are activated, and then the substrates are bonded together. Thereby, even if it is a case where 3 or more board | substrates are bonded, it can suppress that a connection defect generate | occur | produces between the electrodes connected by bonding.

  As described above, according to the first embodiment, since the dummy electrode 22A is formed thinner than the connection electrode 30A, a connection failure occurs in the joint portion connected by bonding the substrates 20A and 20B. It becomes possible to suppress. Further, since the dummy electrode 22B is formed thinner than the connection electrode 30B, it is possible to suppress the occurrence of connection failure in the joint portion connected by bonding the substrates 20A and 20B.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIG. In the second embodiment, a wiring pattern is arranged instead of the dummy electrode for the connection electrode 30A. Then, the wiring pattern is formed so that the thickness of the wiring pattern is thinner than the thickness of the connection electrode 30A.

  FIG. 5 is a diagram for explaining the arrangement positions of the wiring patterns according to the second embodiment. In the present embodiment, the case where the third substrate 20C and the fourth substrate 20D (not shown) are bonded to each other will be described. Since the third substrate 20C and the fourth substrate 20D have the same configuration, the configuration of the third substrate 20C will be described below. FIG. 5 shows a view of the third substrate 20C as viewed from above.

  The third substrate 20C has an insulating layer 21C instead of the insulating layer 21A. Further, the third substrate 20C has a connection electrode 30A. The third substrate 20C has a wiring pattern 22C such as a power supply wiring instead of the dummy electrode 22A.

  The third substrate 20C is formed by the same process as the first substrate 20A. Instead of forming the dummy electrode 22A on the first substrate 20A, the wiring pattern 22C is formed on the third substrate 20C. The wiring pattern 22C is formed thinner than the connection electrode 30A. In addition, the wiring pattern is formed thinner than the connection electrodes also in the fourth substrate 20D.

  The wiring pattern 22C is disposed around the connection electrode 30A. FIG. 5 shows a case where four wiring patterns 22C are arranged around the connection electrode 30A. An insulating layer 21C is disposed between adjacent wiring patterns 22C. For example, the wiring pattern 22C is arranged so as to be arranged at a predetermined interval on the right side and the left side of the connection electrode 30A. Specifically, a plurality of wiring patterns 22C extending in parallel in a predetermined direction are arranged around the connection electrode 30A.

  Then, the connection electrode 30A of the third substrate 20C and the connection electrode of the fourth substrate 20D are overlapped and connected, and the wiring pattern 22C of the third substrate 20C and the wiring pattern of the fourth substrate 20D Are stacked and connected, and the third substrate 20C and the fourth substrate 20D are pasted so that the insulating layer 21C of the third substrate 20C and the insulating layer of the fourth substrate 20D are overlapped and bonded. Combined.

  Note that the wiring pattern 22C may be disposed at a symmetric position as viewed from the connection electrode 30A, or may be disposed at an asymmetric position. When the connection electrode 30A has a rectangular shape surrounded by four sides, the wiring pattern 22C may be disposed at a position adjacent to at least one side. For example, the wiring pattern 22C may be disposed only on the right side, the left side, the upper side, or the lower side of the connection electrode 30A. Further, the wiring pattern 22C is not limited to a linear shape, and may have any shape. Further, it is sufficient that the wiring pattern is thinner than the connection electrode in at least one of the third substrate 20C and the fourth substrate 20D.

  As described above, according to the second embodiment, since the wiring pattern 22C is formed thinner than the connection electrode 30A, the joint portion connected by bonding the third substrate 20C and the fourth substrate 20D. It is possible to suppress the occurrence of connection failure.

  Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  20A ... first substrate, 20B ... second substrate, 20C ... third substrate, 21A-21C ... insulating layer, 22A, 22B ... dummy electrode, 22C ... wiring pattern, 30A, 30B ... connection electrode, 31A, 31B ... via.

Claims (5)

A first substrate;
A second substrate bonded to the first substrate;
With
The first substrate is
Having a first conductive pattern and a second conductive pattern;
The second substrate is
A third conductive pattern and a fourth conductive pattern;
The second conductive pattern is formed thinner than the first conductive pattern, and a lower layer side of the first conductive pattern is connected to a first via connected to the first lower layer side pattern. And
The first conductive pattern and the third conductive pattern are overlapped and connected, and the second conductive pattern and the fourth conductive pattern are overlapped and connected,
A semiconductor device. The fourth conductive pattern is formed thinner than the third conductive pattern, and the lower layer side of the third conductive pattern is connected to a second via connected to the second lower layer pattern. ing,
The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein at least one of the second and fourth conductive patterns is a dummy pattern.   The semiconductor device according to claim 1, wherein at least one of the second and fourth conductive patterns is a wiring pattern.   4. The semiconductor device according to claim 1, wherein at least one of the first to fourth conductive patterns is formed by a damascene process. 5.

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