JP2017017846A - Power supply and image formation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve power efficiency at a light load in an active-clamp power supply.SOLUTION: In the power supply, a control unit 101 enables intermittent operation which alternately repeats a switching period, in which switching operation to alternately switch on/off an FET 1 and an FET 2 is executed with an inserted dead time in which both the FET 1 and the FET 2 are switched off, and a switching stop period in which the switching operation is stopped. The control unit 101, when shifting from the switching period to the switching stop period, switches on the FET 2 and then shifts to the switching stop period ([4]), and also, when shifting from the switching stop period to the switching period, switches on the FET 2 and then shifts to the switching period ([8]).SELECTED DRAWING: Figure 2

Description

  The present invention relates to a power supply device and an image forming apparatus, and more particularly to a switching power supply device using an active clamp system for an isolated converter using a flyback transformer.

  In a switching power supply that converts an AC voltage into a DC voltage such as a commercial power supply, it is required to improve the efficiency of the switching power supply in order to reduce the power consumption of the switching power supply. Here, the efficiency of the switching power supply is represented by the ratio of the power output from the switching power supply to the power supplied to the switching power supply.

  In a switching power supply using an active clamp system for an isolated converter using a flyback transformer, for example, the configuration of Patent Document 1 has been proposed as means for improving the efficiency in a state where the power output from the switching power supply is low. . Hereinafter, a state where the power output from the switching power supply is low is referred to as a light load state.

Japanese Patent No. 4370844

  However, a switching power supply using an active clamp method is required to further improve the efficiency in a light load state.

  The present invention has been made under such circumstances, and an object of the present invention is to improve the power efficiency at the time of light load in an active clamp type power supply device.

  In order to solve the above-described problems, the present invention has the following configuration.

  (1) A transformer having a primary winding and a secondary winding, a first switching element connected in series to the primary winding of the transformer, and a first connected in parallel to the primary winding of the transformer Two switching elements, a capacitor connected in series to the second switching element, and a capacitor connected in parallel to the primary winding of the transformer together with the second switching element, and to the secondary winding of the transformer Feedback means for outputting information according to the induced voltage, and control means for controlling on / off of the first switching element and the second switching element based on the information inputted from the feedback means And the control means has a dead time for turning off both the first switching element and the second switching element. The first switching element and the second switching element are alternately turned on or off, and the first period for performing the switching operation and the second period for stopping the switching operation are alternately repeated. In the power supply device, the control means may turn on the second switching element and then turn on the second switching element when shifting from the first period to the second period. The power supply apparatus is further characterized in that when the second switching element is switched to the first period, the second switching element is turned on and then the first period is shifted to.

  (2) An image forming apparatus comprising: an image forming unit that forms an image on a recording material; and the power supply device according to (1).

  ADVANTAGE OF THE INVENTION According to this invention, the power efficiency at the time of the light load in the power supply apparatus of an active clamp system can be improved.

Schematic of the power supply circuit of Example 1 Explanatory drawing of the control method of Example 1. Simplified circuit diagram for explaining the control method of the first embodiment 1 is a flowchart showing control of the switching power supply circuit according to the first embodiment. Schematic diagram of the power supply circuit of Example 2 7 is a flowchart showing control of the switching power supply circuit according to the second embodiment. FIG. 6 is a diagram illustrating an image forming apparatus according to a third embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail by way of examples with reference to the drawings.

[Power supply]
FIG. 1 is a circuit diagram showing an outline of a switching power supply circuit using an active clamp system according to the first embodiment. The AC power supply 10 such as a commercial power supply outputs an AC voltage, and the voltage rectified by the bridge diode BD1 which is a full-wave rectifying means is input to the switching power supply circuit 100. The smoothing capacitor C3 is used as a means for smoothing the rectified voltage, and the lower potential of the smoothing capacitor C3 is DCL and the higher potential is DCH. The switching power supply circuit 100 outputs the power supply voltage V11 from the input voltage Vin charged in the smoothing capacitor C3 to the insulated secondary side. In this embodiment, the switching power supply circuit 100 outputs a constant voltage of 5 V, for example, as an example of the power supply voltage V11.

  The switching power supply circuit 100 has an insulating transformer T1 having a primary winding P1 and an auxiliary winding P2 on the primary side and a secondary winding S1 on the secondary side. Energy is supplied from the primary winding P1 to the secondary winding S1 of the transformer T1 by a switching operation described later with reference to FIG. The auxiliary winding P2 of the transformer T1 is used to rectify and smooth the forward voltage of the input voltage Vin applied to the primary winding P1 with the diode D4 and the capacitor C4, and supply the power supply voltage V1.

  On the primary side of the switching power supply circuit 100, a field effect transistor (hereinafter referred to as FET) 1 as a first switching element is connected in series to a primary winding P1 of a transformer T1. The capacitor C2 for voltage clamping and the FET2 which is the second switching element are connected in series. The voltage clamping capacitor C2 and FET2 connected in series are connected in parallel to the primary winding P1 of the transformer T1. On the primary side of the switching power supply circuit 100, a control unit 101 and an FET drive unit 102 are provided as control means for the FET1 and FET2. The capacitor C1 for voltage resonance connected in parallel with the FET 1 is provided to reduce the loss when the FET 1 and the FET 2 are switched off. A capacitor between the drain terminal and the source terminal of the FET 1 may be used without providing the voltage resonance capacitor C1. In order to facilitate the operation of turning on the switching element with zero voltage, which will be described later, the capacitor C1 for voltage resonance has a smaller capacitance than the capacitor C2 for voltage clamping. Note that the diode D1 of this embodiment is a body diode of the FET1. Similarly, the diode D2 is a body diode of the FET2.

  The secondary side of the switching power supply circuit 100 has a diode D11 and a capacitor C11 which are rectifying and smoothing means on the secondary side of the flyback voltage generated in the secondary winding S1 of the transformer T1. The voltage induced in the secondary winding S1 of the transformer T1 is rectified and smoothed by the diode D11 and the capacitor C11 and output as the power supply voltage V11. Further, the secondary side of the switching power supply circuit 100 has a feedback unit 115 as feedback means for feeding back information corresponding to the power supply voltage V11 output to the secondary side to the primary side (dotted line in the figure). Frame). Note that the control unit 101 of this embodiment uses arithmetic control means such as a CPU or ASIC that operates with a clock generated by a transmitter or the like. Thereby, complicated waveform control of the control signal DRV1 and the control signal DRV2, which will be described later, can be realized with a simple and inexpensive circuit configuration.

  A power supply voltage V <b> 2 generated by the DC / DC converter 104 is supplied from the OUT terminal of the DC / DC converter 104 between the VC terminal and the G terminal of the control unit 101. The control unit 101 outputs a control signal DRV1 and a control signal DRV2 based on the voltage signal input from the feedback unit 115 to the FB terminal, and controls the FET1 and FET2 via the FET driving unit 102. Here, the control signal DRV1 is a signal for driving the FET1, and the control signal DRV2 is a signal for driving the FET2.

  The FET drive unit 102 is a circuit that generates the gate drive signal DL of the FET 1 according to the control signal DRV1 input from the control unit 101 and the gate drive signal DH of the FET 2 according to the control signal DRV2. A power supply voltage V1 generated by the auxiliary winding P2 is supplied between the VC terminal and the G terminal of the FET driving unit 102. Further, in order to drive the FET 2, a power supply voltage V1 is supplied between the VH terminal and the GH terminal by a charge pump circuit including a capacitor C5 and a diode D5. When the high level control signal DRV1 is input, the FET drive unit 102 sets the gate drive signal DL of the FET 1 to high level, thereby turning the FET 1 on. Similarly, when the high-level control signal DRV2 is input, the FET drive unit 102 sets the gate drive signal DH of the FET2 to high level, thereby turning on the FET2.

  The DC / DC converter 104 is a three-terminal regulator or a step-down switching power supply circuit, converts the power supply voltage V1 input between the VC terminal and the G terminal, and outputs the power supply voltage V2 from the OUT terminal. The starter circuit 103 is a three-terminal regulator or a step-down switching power supply, converts the input voltage Vin input between the VC terminal and the G terminal, and outputs the power supply voltage V1 from the OUT terminal. The startup circuit 103 is a circuit that operates only when the power supply voltage V1 supplied from the auxiliary winding P2 is equal to or lower than a predetermined voltage value, and is used to supply the power supply voltage V1 when the switching power supply circuit 100 is started up.

(Feedback part)
The feedback unit 115 is used to control the power supply voltage V11 to a predetermined constant voltage. The voltage value of the power supply voltage V11 is set by the reference voltage of the reference terminal REF of the shunt regulator IC5, the resistor R52, and the resistor R53. When the power supply voltage V11 becomes higher than a predetermined voltage (here, 5V), a current flows from the cathode terminal K of the shunt regulator IC5, and the secondary side diode of the photocoupler PC5 becomes conductive through the pull-up resistor R51. As a result, the primary side transistor of the photocoupler PC5 operates, and the electric charge is discharged from the capacitor C6. For this reason, the voltage of the FB terminal of the control unit 101 (hereinafter referred to as the FB terminal voltage) decreases. On the other hand, when the power supply voltage V11 becomes lower than 5V, the secondary diode is turned off. As a result, the transistor on the primary side of the photocoupler PC5 is turned off, and a current for charging the capacitor C6 flows from the power supply voltage V2 via the resistor R2. For this reason, the FB terminal voltage of the control unit 101 increases. As described above, the feedback unit 115 changes the FB terminal voltage of the control unit 101 in accordance with the fluctuation of the power supply voltage V11.

  The control unit 101 performs feedback control to control the power supply voltage V11 to a predetermined constant voltage by detecting the FB terminal voltage input from the feedback unit 115. As described above, the control unit 101 can indirectly feedback control the power supply voltage V11 by monitoring the FB terminal voltage. Further, instead of the feedback unit 115, the control unit 101 may be provided on the secondary side, and the power supply voltage V11 may be directly feedback controlled by monitoring the power supply voltage V11. Moreover, since the control part 101 can grasp | ascertain the state of load by monitoring FB terminal voltage, it can perform appropriate control according to the state of load. In order to more accurately determine the state of the load, a current detection unit may be provided in a path for supplying power to the FET 1 or the load of the switching power supply circuit 100. The means for determining the light load state in the present embodiment will be described assuming that the FB terminal voltage of the control unit 101 is used.

[Control method for light load state of switching power supply circuit]
FIG. 2 is an explanatory diagram of a control method for improving the efficiency in the light load state of the switching power supply circuit 100 using the active clamp method by the control unit 101. 2A is a diagram illustrating a control signal DRV1 corresponding to the gate drive signal DL of the FET1, and FIG. 2I is a diagram illustrating a control signal DRV2 corresponding to the gate drive signal DH of the FET2. 2, (iii) is a diagram showing the drain current of FET1, and (iv) is a diagram showing the voltage between the drain terminal and the source terminal of FET1. The horizontal axis indicates time. FIG. 3 shows a current flow in a plurality of periods ([1] to [9]) shown in FIG. 2 together with a simplified circuit diagram. Hereinafter, the operation in each period will be described. In FIG. 3, the transformer T1 is divided into a leakage inductance Lr, a coupling inductance Ls, and an ideal transformer Ti. In the circuit of FIG. 3, the current flowing in each period is indicated by a dark solid arrow. In the present embodiment, the period for controlling FET1 and FET2 is a switching period that is the first period, a period for performing the pre-stop control, a switching stop period for the second period, and a period for performing the post-stop control. Divided as follows.

(Switching period)
The switching period in FIG. 2 is a period in which the control unit 101 repeatedly controls FET1 and FET2 alternately on and off with a dead time for turning off both FET1 and FET2. An operation using the FET 2 and the voltage clamping capacitor C2 in the switching period (hereinafter referred to as an active clamping operation) will be described with reference to [1] to [3] in FIGS.

  While the FET 1 is in the ON state, a current flows through the leakage inductance Lr and the coupling inductance Ls of the transformer T1 (see FIG. 2 (iii)). The period [1] shown in FIG. 3 is a period in which the FET 1 is turned off after the time TL1 is turned on, and the FET 2 is turned on after a dead time. Due to the current that flows while the FET 1 is on, charging is performed from the transformer T1 to the positive terminal side of the voltage clamping capacitor C2 via the FET 2 or the diode D2. Since the kickback voltage due to the leakage inductance Lr can be absorbed by the voltage clamping capacitor C2, the surge voltage applied between the drain terminal and the source terminal of the FET 1 can be suppressed. When the voltage of the voltage clamping capacitor C2 rises, the diode D11 is turned on, and power is supplied to the secondary side of the switching power supply circuit 100 via the secondary winding S1 of the transformer T1.

  In the period [2] shown in FIG. 3, due to resonance between the voltage clamping capacitor C2 and the leakage inductance Lr and coupling inductance Ls of the transformer T1, a current flows from the positive terminal side of the capacitor C2 to the transformer T1 via the FET2. It will be in a flowing state. When the voltage of the voltage clamping capacitor C2 decreases, the secondary-side diode D11 becomes non-conductive, and power is not supplied to the secondary side of the switching power supply circuit 100. Further, by maintaining the conductive state of the FET 2, the current flowing from the voltage clamping capacitor C2 to the leakage inductance Lr and the coupling inductance Ls of the transformer T1 increases.

  The period [3] shown in FIG. 3 is a dead time period in which both FET1 and FET2 are in the OFF state. In the period [3] in FIG. 3, by turning off the FET 2, the capacitance of the capacitor connected to the primary winding P1 of the transformer T1 becomes the combined capacitance of the capacitor C2 for voltage clamping and the capacitor C1 for voltage resonance. From this value, the capacitance of the capacitor C1 for voltage resonance is reduced. Therefore, the electric charge charged in the voltage resonance capacitor C1 can be regenerated in the smoothing capacitor C3 by the current flowing through the leakage inductance Lr and the coupling inductance Ls of the transformer T1. When the above-described regeneration operation is completed, the diode D1 becomes conductive. When the period of [3] shown in FIG. 3 is completed and the diode D1 is in a conductive state, the FET 1 is turned on, so that the FET 1 performs a switching operation to shift from the off state to the on state at zero volts. Can do. Hereinafter, the switching operation in which the FET 1 shifts from the off state to the on state with the zero volt state is referred to as zero volt switching. As described above, the operation from when the FET 2 is turned on until the regeneration operation to the smoothing capacitor C3 is completed is referred to as an active clamp operation. FET1 is then turned on for time TL2.

  Thus, the surge voltage of the FET 1 can be suppressed by the action of the voltage clamping capacitor C2 and the FET 2 in the active clamping operation described in [1] to [3] in FIGS. Further, the electric charge of the voltage resonance capacitor C1 can be regenerated in the smoothing capacitor C3, and further, zero-volt switching of the FET 1 can be performed. Therefore, by using the active clamp method, the efficiency of the switching power supply circuit 100 can be improved in the switching period shown in FIG.

(Control method of power supply voltage V11)
Next, a method for controlling the power supply voltage V11 on the secondary side during the switching period will be described. Control of the power supply voltage V11 on the secondary side of the switching power supply circuit 100 is performed by changing the ratio of the ON time of the FET1 and FET2. When the ratio of the on time of FET1 to FET2 increases, the power supply voltage V11 on the secondary side increases. As a method of controlling the ratio of the ON time of FET1 and FET2, for example, a method of making the ON time of FET2 a fixed time and making the ON time of FET1 variable based on feedback information output from the feedback unit 115, that is, the FB terminal voltage Can be considered. Similarly, a method is conceivable in which the ratio of the ON time of FET1 and the ON time of FET2 is made variable in accordance with the FB terminal voltage output from the feedback unit 115 so that the time of one cycle is constant.

  Further, based on information such as the voltage value of the input voltage Vin and the power supply voltage V11 on the secondary side of the switching power supply circuit 100, the ON time of the FET1 and the ON time of the FET2 are corrected to optimum values. In addition, a method of making the ON time of the FET 1 variable based on the FB terminal voltage output from the feedback unit 115 can be considered. When the input voltage Vin is large, the ON time of the FET 1 is controlled to be short, and when the secondary power supply voltage V11 is large, the ON time of the FET 2 is controlled to be short. Moreover, the structure which provides a current detection means in the primary winding P1 of transformer T1 may be sufficient. Then, after detecting and controlling the optimum FET 2 on time set so that the FET 1 can perform zero volt switching, the FET 1 on time is variably set based on the FB terminal voltage output from the feedback unit 115. You may use the method to do.

(Intermittent operation)
Next, an intermittent operation in which the above-described switching period and a switching stop period described later are alternately controlled will be described. If the control of the switching period is continued as it is in the light load state of the switching power supply circuit 100, the following problems occur. That is, the efficiency of the switching power supply circuit 100 decreases due to resistance loss due to the primary side current of the switching power supply circuit 100, switching loss of the FET1 and FET2, and the like.

  Therefore, when the switching power supply circuit 100 detects a light load state of the switching power supply circuit 100 based on the FB terminal voltage or the like output from the feedback unit 115, the switching power supply circuit 100 shifts to a switching stop period after performing pre-stop control described later. . The switching power supply circuit 100 performs an intermittent operation that repeats a switching period and a switching stop period described later in a light load state. Thereby, the primary side current of the switching power supply circuit 100 and the switching frequency of the FET1 and FET2 can be reduced, and the power efficiency of the switching power supply circuit 100 in a light load state can be improved.

  The switching power supply circuit 100 according to the present embodiment is characterized in that the loss of the switching power supply circuit 100 is improved by the pre-stop control performed when the switching period shown in FIG. 2 transits to the switching stop period. Further, the loss of the switching power supply circuit 100 is improved by post-stop control that is performed when transitioning from the switching stop period to the switching period.

(Period for implementing pre-stop control)
Next, the pre-stop control performed during the period [4] shown in FIG. 3 will be described. The on-time of FET1 in the switching period is TL1, TL2, and the on-time of FET2 is TH1. Further, the ON time of the FET 2 in the period for performing the pre-stop control is TH2, and the ON time of the FET 1 before the FET 2 which is the ON time TH2 is turned on is TL2 (see FIG. 2). Further, the ON time of the FET 2 during the period in which the control after the stop is performed is TH3.

  The operation during the period [4] shown in FIG. 3 is the same as the operation during the period [1] described above. In this embodiment, the FET 2 is turned on in a time shorter than the time during which the switching stop period continues. Further, the FET 2 is turned on in a time (TH2) shorter than the time (TH1) in which the FET 2 is turned on in the switching period. Further, the FET 2 is turned on in a time (≦ TH1 / 2) that is less than half the time (TH1) in which the FET 2 is turned on in the switching period. As described above, in this embodiment, the ON time TH2 of FET2 (period [4]) in the period for performing the pre-stop control is the sum of the ON time TH1 of FET2 ([1] and [2] in the switching period). The period is shorter than the period. In the period in which the pre-stop control of this embodiment is performed, the ratio of the on-time of FET1 and FET2 is a ratio (the ratio of TL2 and TH2) that is half or less of the ratio of on-time of the switching period (ratio of TL1 and TH1) It is controlled to become. As a similar control method for shortening the on-time of FET2, the on-time (TH2) of FET2 is less than half of the on-time (TH1) of FET2 turned on at the end of the switching period (TH2 ≦ TH1 / 2). A control method may be used.

  In this way, the optimum on-time (TH2) of the FET 2 during the pre-stop control is determined from the ratio of the on-time of the FET 1 and FET 2 in the switching period (the ratio of TL1 to TH1). As a result, the FET 2 is turned off before the current flows from the positive terminal of the voltage clamping capacitor C2 to the transformer T1 (period [2] in FIG. 3), and the switching stop period, more specifically, [5] It is possible to shift to the subsequent state. In this embodiment, as will be described in the period [5] to [6] described later, the ON time (TH2) of the FET 2 during the pre-stop control is determined. As a result, without providing a dedicated detection means, it is possible to shift to the switching stop period in a state where the peak voltage of resonance by the transformer T1 and the voltage clamping capacitor C2 is charged in the voltage clamping capacitor C2 (FIG. 2 (iv)). For this reason, the efficiency of the switching power supply circuit 100 can be improved.

  In the period [5] shown in FIG. 3, the following operation is performed. By passing the current that could not be fully charged from the transformer T1 to the voltage clamping capacitor C2 in the period [4], the voltage clamping capacitor C1 and the voltage clamping capacitor C2 are passed through the diode D2. The capacitor C2 is further charged. After the transformer T1, the voltage Clamp capacitor C2 and the resonance peak voltage by the voltage resonance capacitor C1 are charged to the positive terminal side of the voltage clamp capacitor C2, the state of [6] is obtained. Transition.

  In the period [6] shown in FIG. 3, since FET1 and FET2 are in the OFF state, no current flows to the transformer T1 from the positive terminal side of the voltage clamping capacitor C2. Therefore, the above-described resonance peak voltage can be held in the voltage clamping capacitor C2. In this state, the resonance operation of the capacitor C1 for voltage resonance and the transformer T1 (indicated by a double arrow in FIG. 3 [6]) occurs (see FIG. 2 (iv)). Since the voltage resonance capacitor C1 has a low capacitance, a resonance operation having a higher frequency than that of the switching period occurs, and the amplitude of the resonance operation is attenuated in a relatively short time due to a loss due to a resistance component (FIG. 2). (Iv)).

  Here, the effect of the efficiency improvement by the pre-stop control, which is a feature of the present embodiment, will be described. The FET 2 can be turned on by the operation in the period [4] shown in FIG. For this reason, the loss due to the forward voltage of the diode D2 can be reduced as compared with the case where the resonance current by the transformer T1 and the voltage clamping capacitor C2 is conducted only by the diode D2. In particular, when a super junction FET or the like having a low on-resistance value is used for the FET 2, the above-described loss reduction effect is increased.

  In the control method of the switching power supply circuit 100 of this embodiment, the ON time TH2 of the FET 2 in the period [4] shown in FIGS. 2 and 3 is determined based on the ON time TH1 of the FET 2 in the switching period. For this reason, the control method of the switching power supply circuit 100 of the present embodiment is characterized in that it is not necessary to provide a separate detection circuit or the like in order to detect the optimum on-time of the FET 2. In this way, since the ON time TH2 of the FET 2 during the pre-stop control is determined from the ON time TH1 of the FET 2 during the switching period, this control can also be referred to as predictive control. By determining the ON time TH2 of the FET 2 at the time of the pre-stop control, the transition to the switching stop period is made in a state where the peak voltage of resonance by the transformer T1, the voltage clamping capacitor C2, and the voltage resonance capacitor C1 is charged. can do. In addition, by controlling in this way, the effect of reducing the loss due to the forward voltage of the diode D1 can be obtained at the same time.

  Further, even when a detection circuit or the like is provided in order to detect the optimum ON time of the FET 2 during the period [4] shown in FIG. 3, an effect of reducing the loss due to the forward voltage of the diode D1 can be obtained. Can do. Note that the method for determining the ON time of the FET 2 during the switching stop period is not limited to the method described in FIGS. 2 and 3 (method based on TH1) of this embodiment.

(Switching stop period)
Next, the control of the switching stop period shown in FIG. 2 will be described. In the period [7] shown in FIG. 3, the voltage is held in the voltage clamping capacitor C2 (FIG. 2 (iv)), and the FET1 and FET2 are held in the OFF state. Since the voltage is held in the voltage clamping capacitor C2, a current flows from the positive terminal side of the capacitor C2 to the transformer T1 by turning on the FET 2 even after a predetermined stop period has elapsed (in FIG. 3). [2] state). The control unit 101 detects a state in which a load should be supplied to the secondary side of the switching power supply circuit 100 based on the FB terminal voltage or the like output from the feedback unit 115, or when a predetermined time has elapsed. The switching stop period ends. And the control part 101 transfers to a switching period, after performing the control after a stop mentioned later.

(Period for implementing control after stopping)
Next, the post-stop control of [8] to [9] shown in FIG. 3 will be described. The operation during the period [8] shown in FIG. 3 is the same as the operation during the period [2] described above, but the ON time of the FET 2 is shortened during the period [8] shown in FIG. Yes. In this embodiment, the FET 2 is turned on in a time shorter than the time during which the switching stop period continues. Further, the FET 2 is turned on in a time shorter than the time (TH1) in which the FET 2 is turned on in the switching period. Further, the FET 2 is turned on in a time (<TH1 / 2) shorter than half of the time (TH1) in which the FET 2 is turned on in the switching period. In the control of this embodiment, the ratio of the on-time of FET1 and FET2 is controlled to be a ratio (the ratio of TL2 and TH3) smaller than half of the ratio of the on-time of switching period (ratio of TL1 and TH1). Yes.

  As a similar control method for obtaining the same effect, for example, there is the following method. In the post-stop control of [8] shown in FIG. 3, the ON time TH3 of the FET 2 is set to be half of the ON time (TH1) of the FET 2 that was turned on at the end of the switching period (the sum of [1] and [2]). The control may be performed in a short time (TH3 <TH1 / 2). Furthermore, the on time TH3 of the FET 2 may be shorter than the on time TH2 of the pre-stop control FET 2 (TH3 <TH2). In this case, the relation of “TH1 / 2 ≧ TH2> TH3” is established with respect to the ON time (TH3) of the FET2. The efficiency of the switching power supply circuit 100 is improved by shortening the ON time of the FET 2 in the period [8]. That is, since the current flowing from the voltage clamping capacitor C2 to the leakage inductance Lr and the coupling inductance Ls of the transformer T1 can be prevented from increasing more than necessary, the efficiency of the switching power supply circuit 100 is improved. .

  Subsequently, in the period [9] shown in FIG. 3, as in the period [3], the FET1 and the FET2 are in an off state, which is a dead time period. After the elapse of the dead time period [9] in FIG. 3, the FET 1 is turned on, so that the FET 1 can perform zero volt switching as in the description of the period [3].

  In the intermittent operation of this embodiment, the switching period described in [1] to [3] in FIGS. 2 and 3, the pre-stop control described in [4], and the switching stop period described in [5] to [7]. , [8] to [9] The control after stop is repeatedly performed. At this time, a sufficiently long switching stop period is provided for the ON times TH2 and TH3 of the FET2 for the pre-stop control and the post-stop control. Thereby, the primary side current of the switching power supply circuit 100 and the switching frequency of the FET1 and FET2 can be reduced, and the power efficiency of the switching power supply circuit 100 in a light load state can be improved.

[Control of switching power supply circuit]
FIG. 4 is a flowchart for explaining control processing of the switching power supply circuit 100 by the control unit 101 of this embodiment. When the AC power supply 10 is connected to the switching power supply circuit 100 and power is supplied to the switching power supply circuit 100, the control unit 101 starts the following control. In step (hereinafter referred to as S) 301, the control unit 101 detects the FB terminal voltage input from the feedback unit 115 to the FB terminal. In S302, the control unit 101 controls the ON time of the FET 1 according to the FB terminal voltage detected in S301. For example, the control unit 101 controls the driving of the FET 1 with the on-time of the FET 1 as TL1 or TL2.

  In S303, the control unit 101 determines whether or not the FB terminal voltage is smaller than a predetermined voltage FBL1 (FB <FBL1) in order to determine whether or not the switching power supply circuit 100 is in a light load state. Here, the predetermined voltage FBL1 used for determining whether or not it is in a light load state is hereinafter referred to as a stop voltage. When the control unit 101 determines in S303 that the FB terminal voltage is equal to or higher than the stop voltage FBL1, the process proceeds to S304. In S304, the control unit 101 determines the ON time of the FET 2 with a time corresponding to the FB terminal voltage, and returns to the process of S301. For example, the control unit 101 controls the driving of the FET 2 by setting the ON time of the FET 2 as TH1. The control unit 101 stores the ON time (TH1) of the FET 2 in the switching period in a storage unit (not shown) such as a RAM. Note that the control unit 101 performs control by providing the above-described predetermined dead time between the ON time of the FET 1 and the ON time of the FET 2. In this case, since the switching power supply circuit 100 is not in a light load state, the control unit 101 performs a continuous operation for continuously performing the switching period.

  When the control unit 101 determines in step S303 that the FB terminal voltage is smaller than the stop voltage FBL1, the control unit 101 proceeds to the processing in step S305. In S305, the control unit 101 sets the ON time of the FET 2 so that the ON time of the FET 2 is a time (TH2 ≦ TH1 / 2) that is less than or equal to a half (half) of the time (TH1) corresponding to the FB terminal voltage. Control. This control corresponds to the pre-stop control described above. In step S306, the control unit 101 sets the FET1 and FET2 to the OFF state after the ON time (TH2) of the FET2 determined in step S305 has elapsed, and holds it as it is. This control corresponds to the control of the switching stop period described above. The control unit 101 resets and starts a timer (not shown).

  In step S307, the control unit 101 detects whether or not the power supplied as the secondary power supply voltage V11 of the switching power supply circuit 100 is insufficient, so whether or not the FB terminal voltage is greater than the predetermined voltage FBL2. Judging. Here, the predetermined voltage FBL2 used for determining whether or not to transit from the switching stop period to the switching period is hereinafter referred to as a return voltage. The relationship between the stop voltage FBL1 and the return voltage FBL2 is FBL2> FBL1 in order to provide hysteresis.

  If the control unit 101 determines in S307 that the FB terminal voltage is greater than the return voltage FBL2, the process proceeds to S308. In S307, the control unit 101 continues the switching stop period when the FB terminal voltage is equal to or lower than the return voltage FBL2, and repeats the process of S307. In S308, the control unit 101 refers to a timer (not shown), so that the length of the switching stop period started in the process of S306 is the predetermined shortest stop period Tmin stored in the memory (not shown) of the control unit 101. To determine whether it is longer. As described above, the control unit 101 measures the length of the switching stop period using the internal timer of the control unit 101.

  If the control unit 101 determines in S308 that the switching stop period is longer than the shortest stop period Tmin, the process proceeds to S309. When the control unit 101 determines in S308 that the switching stop period is equal to or shorter than the shortest stop period Tmin, the control unit 101 repeats the process of S308 and continues the switching stop period. As described above, in this embodiment, the determination of the return from the switching stop period to the switching period is performed based on the FB terminal voltage and a predetermined time. However, the return from the switching stop period to the switching period may be determined based on the FB terminal voltage, may be determined based on the passage of time, or may be determined based on other factors. In S309, the control unit 101 reads the ON time (TH1) of the FET 2 set according to the FB terminal voltage from the memory stored in S304. The control unit 101 determines the ON time (TH3 <TH1 / 2) of the FET 2 as a time shorter than one half of the ON time (TH1) of the FET 2 in the switching period, turns the FET 2 on, and performs the process of S301. Return. This control corresponds to the post-stop control described above. By repeatedly performing the above-described control, the control unit 101 controls the switching power supply circuit 100.

As described above, when the control unit 101 shifts from the switching period to the switching stop period, the control unit 101 turns on the FET 2 and then shifts to the switching stop period. Further, when the control unit 101 shifts from the switching stop period to the switching period, the control unit 101 turns on the FET 2 and shifts to the switching period. The switching power supply circuit 100 of the present embodiment has the following characteristics.
In the light load state of the switching power supply circuit 100, an intermittent operation is performed in which the switching period and the switching stop period are repeated.
-Pre-stop control is performed to turn on FET2 before the switching stop period.
-Control after stopping to turn on FET2 after the switching stop period.
Control the on time of the FET 2 for the pre-stop control and the post-stop control to be shorter than the on time of the FET 2 in the switching period.

  As described above, according to this embodiment, it is possible to improve the power efficiency at the time of light load in the active clamp type power supply device.

[Configuration of switching power supply circuit]
Next, the switching power supply circuit 400 according to the second embodiment will be described. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The switching power supply circuit 400 shown in FIG. 5 includes a feedback unit 116 and a switching control unit 118 as feedback means. The switching control unit 118 has two states, that is, a standby state that outputs a 24V voltage that is the first voltage as the power supply voltage V12 on the secondary side, and a sleep state that outputs a 5V voltage that is the second voltage. Switch. The present embodiment is different from the configuration of the first embodiment in that it includes the switching control unit 118 that switches between the standby state and the sleep state. Further, in this embodiment, the secondary side rectifier circuit of the switching power supply circuit 400 is different from the first embodiment in that a synchronous rectifier circuit described later and a smoothing circuit are added instead of the diode D11. The synchronous rectifier circuit of this embodiment includes an FET 12, a diode D12, and a synchronous rectification control unit 111. Further, the smoothing circuit of this embodiment includes a coil L11 and a capacitor C12.

  The synchronous rectification circuit 111 of the switching power supply circuit 400 is controlled by the synchronous rectification control unit 111. The synchronous rectification control unit 111 sets the output of the D terminal to a high level only during the conduction period of the diode D12 detected by the S terminal, thereby turning on the FET 12 that is a switching element for synchronous rectification. Thereby, the voltage of the secondary winding S1 of the transformer T1 is rectified. The synchronous rectification control unit 111 is, for example, a control unit integrally formed as a discrete circuit or a semiconductor integrated circuit. The power supply voltage V12 is supplied to the synchronous rectification control unit 111 between the VC terminal and the G terminal. Here, the power supply voltage V12 is an output voltage of the switching power supply circuit 400, and in this embodiment, it is a voltage of 24V or 5V as described later. The voltage rectified by the synchronous rectification control unit 111 is smoothed by the capacitors C11 and C12 and the coil L11 and is output as the power supply voltage V12.

(Feedback part)
The feedback unit 116 is different from the feedback unit 115 of the first embodiment in that it has a feedback voltage switching function using resistors R53, R54, and an FET 51. A resistor R55 is connected between the gate terminal and the source terminal of the FET 51. A 24VOUT signal, which is a signal for switching the feedback voltage, is input to the gate terminal of the FET 51 of the feedback unit 116 from a control unit of an electronic device in which the switching power supply circuit 400 is mounted. When the 24VOUT signal goes high, the FET 51 is turned on and the resistor R54 is short-circuited. For this reason, the voltage input to the reference terminal REF of the shunt regulator IC5 is a voltage obtained by dividing the power supply voltage V12 by the resistors R52 and R53. As a result, the switching power supply circuit 400 enters a state of outputting a 24V voltage as the power supply voltage V12 on the secondary side.

  On the other hand, when the 24VOUT signal becomes low level, the FET 51 is turned off, and the resistor R53 and the resistor R54 are connected in series. For this reason, the voltage input to the reference terminal REF of the shunt regulator IC5 is a voltage obtained by dividing the power supply voltage V12 by the resistor R52 and the combined resistor of the resistor R53 and the resistor R54. As a result, the switching power supply circuit 400 is in a state of outputting a 5V voltage as the power supply voltage V12 on the secondary side. As described above, in this embodiment, the power supply voltage V12 of the switching power supply circuit 400 is switched to 24V or 5V in accordance with the 24VOUT signal input from the outside of the switching power supply circuit 400.

(Switching control unit)
The switching control unit 118 performs switching control between the standby state and the sleep state in accordance with the STANBY signal. A STANBY signal, which is a signal for switching the operation state of the switching power supply circuit 400, is input to the gate terminal of the FET 81 of the switching control unit 118 from a control unit or the like of the electronic device in which the switching power supply circuit 400 is mounted. . A resistor R82 is connected between the gate terminal and the source terminal of the FET 81. When the high-level STANDBY signal is input to the switching control unit 118, the FET 81 is turned on, and the secondary diode of the photocoupler PC8 is turned on via the resistor R81. As a result, the primary transistor of the photocoupler PC8 is turned on, and the charge charged in the capacitor C8 is discharged. One end of the capacitor C8 is connected to the SL terminal of the control unit 101, and when the electric charge of the capacitor C8 is discharged, the voltage of the SL terminal of the control unit 101 (hereinafter referred to as SL terminal voltage) becomes low level.

  On the other hand, when the low-level STANDBY signal is input to the switching control unit 118, the FET 81 is turned off, and the secondary diode of the photocoupler PC8 is turned off. As a result, the primary side transistor of the photocoupler PC8 is also turned off, the capacitor C8 is charged via the resistor R1 from the power supply voltage V2, and the SL terminal voltage of the control unit 101 becomes high level. The control unit 101 determines whether the switching power supply circuit 400 is in a standby state or a sleep state according to the SL terminal voltage. In the present embodiment, the standby state is set when the SL terminal voltage of the control unit 101 is at a low level, and the sleep state is set when the SL terminal voltage of the control unit 101 is at a high level.

  The flowcharts of FIGS. 6A to 6D show four different control methods of the switching power supply circuit 400 by the control unit 101. The control unit 101 can perform various controls as described below according to the electronic device on which the switching power supply circuit 400 is mounted. 6A to 6D are denoted by the same reference numerals and description thereof is omitted. Even in this embodiment, when the intermittent operation is performed, the control unit 101 performs the intermittent operation (switching period, pre-stop control, switching stop period, post-stop control) described in the first embodiment. The method for determining the ON time of the FET 2 in the pre-stop control and the post-stop control is the same as in the first embodiment.

(When 24VOUT signal and STANDBY signal are connected)
(First control sequence)
FIG. 6A is a flowchart for explaining a first control sequence of the switching power supply circuit 400 by the control unit 101 of this embodiment. In the flowchart described with reference to FIG. 6A, it is assumed that the 24VOUT signal and the STANDBY signal are connected. That is, in the first control sequence shown in FIG. 6A, the 24VOUT signal and the STANBY signal are linked. If the 24VOUT signal is high, the STANBY signal is also high. If the 24VOUT signal is low, the STANBY signal is also low. The control unit 101 starts the first control sequence when power is supplied to the switching power supply circuit 400. In step S511, the control unit 101 enables the intermittent operation of the switching power supply circuit 400 described in the first embodiment. Making the intermittent operation effective means that the switching power supply circuit 400 performs not only continuous operation but also intermittent operation as necessary.

  In step S512, the control unit 101 determines whether there is a request to output a 24V voltage to the power supply voltage V12 based on the SL terminal voltage. The SL terminal voltage is a voltage used for determination for switching the switching power supply circuit 400 between a standby state and a sleep state. In FIG. 6A, since the STANBY signal and the 24VOUT signal are connected, it is possible to determine whether the power supply voltage V12 is 24V or 5V based on the SL terminal voltage. Note that the control unit 101 may make the determination in S512 based on the FB terminal voltage that changes in response to the 24VOUT signal. If the control unit 101 determines in S512 that there is a request to output a 24V voltage, the process proceeds to S513. In S513, the intermittent operation described in the first embodiment is disabled, and the process returns to S512. The state in which the intermittent operation is disabled means that the switching power supply circuit 400 does not perform the intermittent operation, that is, always performs the continuous operation. In S512, if the control unit 101 determines that there is no request to output a 24V voltage, that is, outputs a 5V voltage as the power supply voltage V12, the process returns to S511, and the intermittent operation described in the first embodiment is validated in S511. Hold in the state.

  Here, Table 1 is a table for explaining FIGS. 6A and 6B. “A” in the first column of Table 1 corresponds to FIG. 6A, and “B” corresponds to FIG. 6B. The second column in Table 1 shows when the power supply voltage V12 of the switching power supply circuit 400 is 5V, and the third column shows when the power supply voltage V12 of the switching power supply circuit 400 is 24V. Table 1 shows an operation state of the switching power supply circuit 400 in a light load state or a heavy load state when the power supply voltage V12 of the switching power supply circuit 400 is each voltage.

  In the case of FIG. 6A, if there is a request to output a 24V voltage as the power supply voltage V12 of the switching power supply circuit 400, the intermittent operation is invalidated (S513). As a result, the intermittent operation is not performed when outputting a 24 V voltage that requires a high power output, and the responsiveness of the switching power supply circuit 400 can be improved. That is, when there is a request to output 24V voltage to the power supply voltage V12 of the switching power supply circuit 400, the switching power supply circuit 400 performs continuous operation in both the light load state and the heavy load state. On the other hand, when there is no request to output 24V voltage to the power supply voltage V12 of the switching power supply circuit 400, the intermittent operation is validated (S511). In this case, 5V voltage is output as the power supply voltage V12 of the switching power supply circuit 400. Since the intermittent operation is enabled when the power supply voltage V12 of the switching power supply circuit 400 is 5V (S511), the switching power supply circuit 400 performs not only continuous operation but also intermittent operation according to the state of the load. Specifically, when the power supply voltage V12 of the switching power supply circuit 400 is 5V, an intermittent operation is performed in a light load state and a continuous operation is performed in a heavy load state. The power supply voltage V12 is input to the feedback unit 116, and the FB terminal voltage output from the feedback unit 116 to the control unit 101 varies depending on the load state. Therefore, the control unit 101 determines whether the light load state or the heavy load state is based on the FB terminal voltage.

(Second control sequence)
FIG. 6B is a flowchart for explaining a second control sequence of the switching power supply circuit 400 by the control unit 101 of this embodiment. In the flowchart described with reference to FIG. 6B, it is assumed that the 24VOUT signal and the STANDBY signal are connected. The control unit 101 starts the second control sequence when power is supplied to the switching power supply circuit 400. In S521, the control unit 101 controls the switching power supply circuit 400 to always perform an intermittent operation. Since S512 and S513 have already been described, description thereof will be omitted.

  In the case of FIG. 6B, when there is no request to output 24V voltage as the power supply voltage V12 of the switching power supply circuit 400, that is, when 5V voltage is output, control is always performed in an intermittent operation (S521, Table 1). The control in FIG. 6B can be applied to, for example, a power supply device having a specification in which there is no heavy load state when a 5V voltage is output, in other words, a light load state is always obtained. In the case of a power supply device that is always in a light load state when outputting a 5 V voltage, the control unit 101 can determine the light load state based on the SL terminal voltage. That is, in the power supply device having such specifications, the light load state to be intermittently operated can be determined only by the SL terminal voltage. In addition, when the power supply voltage V12 of the switching power supply circuit 400 is 24V, it is the same as that in FIG.

  Note that in the case of performing the control in FIGS. 6A and 6B, the 24VOUT signal and the STANDBY signal are connected. Therefore, instead of the switching control unit 118, an auxiliary winding (not shown) for detecting a flyback voltage may be provided on the primary side of the transformer T1, and the voltage of the auxiliary winding may be detected. Accordingly, the state of the power supply voltage V12 on the secondary side (a state in which a 24V voltage is output or a state in which a 5V voltage is output) may be determined.

(When 24VOUT signal and STANBY signal are separated)
(Third control sequence)
FIG. 6C is a flowchart for explaining a third control sequence of the switching power supply circuit 400 by the control unit 101 of this embodiment. In the flowchart described with reference to FIG. 6C, it is assumed that the 24VOUT signal and the STANBY signal are separated. That is, in the third control sequence shown in FIG. 6C, the 24VOUT signal and the STANBY signal are not linked to each other and are independently a high level signal or a low level signal. The control unit 101 starts the third control sequence when power is supplied to the switching power supply circuit 400.

  In step S511, the control unit 101 sets the intermittent operation to a valid state. In S532, the control unit 101 determines whether or not the switching power supply circuit 400 has a request for transition to the standby state (standby mode) based on the SL terminal voltage. If the control unit 101 determines in S532 that there is a request for transition to the standby state, the control unit 101 proceeds to the process of S513 and invalidates the intermittent operation. In S532, when the control unit 101 determines that there is no request for transition to the standby state, that is, the sleep state, the control unit 101 returns to the process of S511 and holds the intermittent operation in an effective state.

  Here, Table 2 is a table for explaining FIGS. 6C and 6D. “C” in the first column of Table 1 corresponds to FIG. 6C, and “D” corresponds to FIG. 6D. Others are the same as in Table 1, and a description thereof is omitted.

  In the case of FIG. 6C, a high-level STANBY signal is sent to the switching control unit 118 when there is a possibility of outputting large power regardless of whether the power supply voltage V12 of the switching power supply circuit 400 is 24V voltage or 5V voltage. Entered. When the control unit 101 determines that the standby mode is set based on the SL terminal voltage, the control unit 101 invalidates the intermittent operation. In this case, the control unit 101 does not perform the intermittent operation in the standby state, and makes the switching power supply circuit 400 operate continuously regardless of the light load state or the heavy load state. Thereby, the responsiveness of the switching power supply circuit 400 can be improved. On the other hand, if there is no request for the switching power supply circuit 400 to enter the standby state, the intermittent operation is validated in S511. In this case, the switching power supply circuit 400 enters a sleep state. Since the intermittent operation is enabled when the switching power supply circuit 400 is in the sleep state, the switching power supply circuit 400 performs not only continuous operation but also intermittent operation according to the load state. Specifically, when the switching power supply circuit 400 is in a sleep state, an intermittent operation is performed in a light load state, and a continuous operation is performed in a heavy load state.

(Fourth control sequence)
FIG. 6D is a flowchart for explaining a fourth control sequence of the switching power supply circuit 400 by the control unit 101 of this embodiment. In the flowchart described with reference to FIG. 6D, it is assumed that the 24VOUT signal and the STANBY signal are separated as in FIG. 6C. The control unit 101 starts the fourth control sequence when power is supplied to the switching power supply circuit 400. The configuration in FIG. 6D is a combination of the processes described in FIG. 6B and FIG.

  In the case of FIG. 6D, regardless of whether the power supply voltage V12 of the switching power supply circuit 400 is 24V voltage or 5V voltage, the switching power supply circuit 400 is always controlled by intermittent operation according to the mode of the switching power supply circuit 400, or the intermittent operation is invalid. It is decided whether to do it. In the case of FIG. 6D, when there is no request for the switching power supply circuit 400 to enter the standby mode, that is, when it is in the sleep state, it is always controlled by intermittent operation (S521). The control in FIG. 6D can be applied to a power supply device or the like having a specification such that the light load state is always in the sleep state. In the case of a power supply device that is always in a light load state when in the sleep state, the control unit 101 can determine the light load state based on the SL terminal voltage. Note that the case where the switching power supply circuit 400 is in the standby mode is the same as that in FIG.

  Thus, the means for determining the light load state of the switching power supply circuit 400 is not limited to the means using the FB terminal voltage of the control unit 101 described in the first embodiment. As described in the switching power supply circuit 400 of this embodiment, a STANBY signal supplied from the outside may be used. The present invention is characterized by a control method for performing an intermittent operation when it is determined that the switching power supply circuit 400 is in a light load state using any means.

In addition to the characteristics of the switching power supply circuit 100, the switching power supply circuit 400 of this embodiment has the following characteristics.
The power supply voltage V12 of the switching power supply circuit 400 can be set to a plurality of voltages (24V voltage and 5V voltage).
The switching power supply circuit 400 has a plurality of states such as a standby state and a sleep state.
In the standby state (a state in which a 24V voltage is output), the intermittent operation of the switching power supply circuit 400 is invalidated.
In the sleep state (a state in which a 5 V voltage is output), the intermittent operation of the switching power supply circuit 400 is enabled. Alternatively, the switching power supply circuit 400 is always controlled by an intermittent operation.

  As described above, according to this embodiment, it is possible to improve the power efficiency at the time of light load in the active clamp type power supply device.

  The switching power supply circuit that is the power supply apparatus described in the first and second embodiments can be applied as a low-voltage power supply for an image forming apparatus, that is, a power supply that supplies power to a drive unit such as a controller (control unit) or a motor. The configuration of the image forming apparatus to which the power supply apparatus according to the first and second embodiments is applied will be described below.

[Configuration of Image Forming Apparatus]
A laser beam printer will be described as an example of the image forming apparatus. FIG. 7 shows a schematic configuration of a laser beam printer which is an example of an electrophotographic printer. The laser beam printer 300 includes a photosensitive drum 311 as an image carrier on which an electrostatic latent image is formed, a charging unit 317 (charging unit) that uniformly charges the photosensitive drum 311, and an electrostatic latent image formed on the photosensitive drum 311. A developing unit 312 (developing unit) that develops an image with toner is provided. The toner image developed on the photosensitive drum 311 is transferred to a sheet (not shown) as a recording material supplied from the cassette 316 by a transfer unit 318 (transfer means), and the toner image transferred to the sheet is fixed to the fixing device 314. Then, the toner is fixed and discharged onto the tray 315. The photosensitive drum 311, the charging unit 317, the developing unit 312, and the transfer unit 318 are image forming units. The laser beam printer 300 includes the power supply device 500 described in the first to third embodiments. Note that the image forming apparatus to which the power supply device 500 according to the first and second embodiments can be applied is not limited to that illustrated in FIG. 7, and may be an image forming apparatus including a plurality of image forming units, for example. Further, the image forming apparatus may include a primary transfer unit that transfers the toner image on the photosensitive drum 311 to the intermediate transfer belt and a secondary transfer unit that transfers the toner image on the intermediate transfer belt to the sheet.

  The laser beam printer 300 includes a controller 320 that controls an image forming operation by the image forming unit and a sheet conveying operation. The power supply device 500 according to the first and second embodiments supplies power to the controller 320, for example. . The power supply device 500 described in the first and second embodiments supplies power to a driving unit such as a motor for rotating the photosensitive drum 311 or driving various rollers for conveying the sheet. When the power supply device 500 of the present embodiment is the switching power supply circuit 100 of the first embodiment, the control unit 101 performs an intermittent operation based on the FB terminal voltage. In this case, as described in the first embodiment, the control unit 101 performs pre-stop control when shifting from the switching period to the switching stop period, and stops when shifting from the switching stop period to the switching period. Perform post-control. Thereby, the power efficiency at the time of the light load of the power supply device 500 can be improved.

  The image forming apparatus according to the present exemplary embodiment can operate in a normal operation mode, a standby mode, or a sleep mode. The standby mode is a mode in which the image forming operation can be performed as soon as a print instruction is received while reducing power consumption compared to the normal operation mode in which the image forming operation is performed. The sleep mode is a mode in which power consumption is further reduced compared to the standby mode. When the power supply device 500 is the switching power supply circuit 400 according to the second embodiment, for example, the controller 320 outputs a 20VOUT signal or a STANBY signal to the switching power supply circuit 400. The switching power supply circuit 400 performs an intermittent operation in a light load state by the control unit 101 based on the SL terminal voltage as described in Tables 1 and 2 and the like. Note that the control unit 101 controls the intermittent operation described in the first embodiment. Thereby, the power efficiency at the time of the light load of the power supply device 500 can be improved.

  As described above, according to this embodiment, it is possible to improve the power efficiency at the time of light load in the active clamp type power supply device.

T1 transformer FET1 first switch FET2 second switch C2 voltage clamp capacitor 101 control unit (CPU)
115 Feedback section

Claims (15)

A transformer having a primary winding and a secondary winding;
A first switching element connected in series to the primary winding of the transformer;
A second switching element connected in parallel to the primary winding of the transformer;
A capacitor connected in series to the second switching element, and connected in parallel to the primary winding of the transformer together with the second switching element;
Feedback means for outputting information according to the voltage induced in the secondary winding of the transformer;
Control means for controlling on or off of the first switching element and the second switching element based on the information input from the feedback means;
With
The control means performs a switching operation for alternately turning on or off the first switching element and the second switching element with a dead time for turning off both the first switching element and the second switching element. A power supply device capable of performing an operation of alternately repeating a first period to be performed and a second period for stopping the switching operation,
When the control means shifts from the first period to the second period, the control means shifts to the second period after turning on the second switching element, and from the second period to the second period. Also when shifting to the one period, the power supply device shifts to the first period after turning on the second switching element. The control means includes
When shifting from the first period to the second period, and when shifting from the second period to the first period, the second period is shorter than the duration of the period. The power supply device according to claim 1, wherein the second switching element is turned on. The control means includes
When shifting from the first period to the second period and when shifting from the second period to the first period, the second switching element is turned on in the first period. The power supply device according to claim 2, wherein the second switching element is turned on in a time shorter than a predetermined time. The control means includes
When shifting from the first period to the second period, the second switching element is turned on in a time that is half or less of the time during which the second switching element is turned on in the first period. The power supply device according to claim 3. The control means includes
When shifting from the second period to the first period, the second switching element is turned on in a time shorter than half of the time during which the second switching element was turned on in the first period. The power supply device according to claim 3 or 4, wherein   The capacitor is charged when the second switching element is turned on when shifting from the first period to the second period, and the charged state is maintained in the second period. The power supply device according to claim 4.   The power supply device according to claim 6, wherein the capacitor is discharged when the second switching element is turned on when the second period is shifted to the first period.   The control means shifts from the first period to the second period or from the second period to the first period based on at least the information input from the feedback means. The power supply device according to any one of claims 1 to 7, wherein:   The control means shifts from the second period to the first period based on the information input from the feedback means and a time during which the second period is continued. The power supply device according to claim 8. Image forming means for forming an image on a recording material;
The power supply device according to any one of claims 1 to 9,
An image forming apparatus comprising: A control unit that controls the power supply device to output a first voltage or a second voltage lower than the first voltage;
The control means includes
When controlled to output the first voltage from the control unit, control to perform an operation in which the first period continues,
When the control unit is controlled to output the second voltage, the operation in which the first period continues according to the state of the load to which the power supply device supplies power or the first period The image forming apparatus according to claim 10, wherein the control is performed so as to perform an operation in which the second period and the second period are alternately repeated. A control unit that controls the power supply device to output a first voltage or a second voltage lower than the first voltage;
The control means includes
When controlled to output the first voltage from the control unit, control to perform an operation in which the first period continues,
The control is performed so as to perform an operation in which the first period and the second period are alternately repeated when the control unit is controlled to output the second voltage. Item 15. The image forming apparatus according to Item 10. A controller that controls the power supply device to operate in a first mode that consumes predetermined power or a second mode that consumes less power than the first mode;
The control means includes
When the control unit is controlled to operate in the first mode, the control is performed to perform the operation in which the first period continues,
When the control unit is controlled to operate in the second mode, an operation in which the first period continues according to a state of a load to which the power supply device supplies power or the first period The image forming apparatus according to claim 10, wherein the control is performed so as to perform an operation in which the second period and the second period are alternately repeated. A controller that controls the power supply device to operate in a first mode that consumes predetermined power or a second mode that consumes less power than the first mode;
The control means includes
When the control unit is controlled to operate in the first mode, the control is performed to perform the operation in which the first period continues,
The control unit performs control so as to perform an operation in which the first period and the second period are alternately repeated when the control unit is controlled to operate in the second mode. Item 15. The image forming apparatus according to Item 10.   The image forming apparatus according to claim 11, wherein the control unit determines a state of a load to which the power supply device supplies power based on at least the information input from the feedback unit. apparatus.

Images