JP7140572B2 - Power supply and image forming apparatus - Google Patents

Description

The present invention relates to a switching power supply device and an image forming apparatus using an active clamp system for an isolated converter using a flyback transformer.

2. Description of the Related Art An active clamp type power supply using a flyback transformer is known as one configuration of a power supply having high power efficiency for both light load and heavy load. In pursuit of even higher power efficiency, for example, in Patent Document 1, by switching the capacitance of a resonance capacitor connected in parallel to a switching element according to the size of the load to which power is supplied, There has been proposed a power supply device configured to achieve both high power efficiency at the same time. Note that power efficiency (also referred to as power conversion efficiency) is represented by the ratio of the power supplied to the power supply and the power output by the power supply.

JP 2009-100554 A

As described above, in the power supply device, the capacity of the resonant capacitor is switched according to the load to which power is supplied. Especially in a partial resonance type power supply such as an active clamp type power supply using a flyback transformer, the timing for switching the capacitance of the resonance capacitor is limited to achieve stable switching operation and further improvement of power efficiency. is an important issue.

SUMMARY OF THE INVENTION It is an object of the present invention to improve power efficiency in an active clamp power supply.

In order to solve the above problems, the present invention has the following configuration.

(1) A transformer having a primary winding and a secondary winding, a first switching element connected in series with the primary winding of the transformer, and a resonance capacitor connected in parallel with the first switching element. a second switching element connected in parallel to the primary winding of the transformer; and a second switching element connected in series to the second switching element and connected to the primary winding of the transformer together with the second switching element. a capacitor connected in parallel; feedback means for outputting information corresponding to an output voltage obtained by rectifying and smoothing the voltage induced in the secondary winding of the transformer; and based on the information input from the feedback means a control means for controlling on or off of the first switching element by a first control signal, and controlling on or off of the second switching element by a second control signal; is a period during which a switching operation is performed to alternately turn on or off the first switching element and the second switching element with a dead time in which both the first switching element and the second switching element are turned off. A power supply device capable of performing repeated continuous operation and intermittent operation in which a period in which the switching operation is performed and a period in which the switching operation is stopped are alternately performed, wherein the resonance capacitor unit includes a first a resonance capacitor, a second resonance capacitor, and a third switching element connected in series with the second resonance capacitor, wherein the second resonance capacitor and the third switching element are connected to the The control means is connected in parallel with the first resonance capacitor, and the control means turns on the third switching element during the continuous operation, turns off the third switching element during the intermittent operation, and switches the switching element from the intermittent operation to the continuous operation. A power supply device characterized by switching the third switching element from off to on when the first switching element is on after shifting to operation .
(2) a transformer having a primary winding and a secondary winding, a first switching element connected in series with the primary winding of the transformer, and a resonance capacitor connected in parallel with the first switching element a second switching element connected in parallel to the primary winding of the transformer; and a second switching element connected in series to the second switching element and connected to the primary winding of the transformer together with the second switching element. a capacitor connected in parallel; feedback means for outputting information corresponding to an output voltage obtained by rectifying and smoothing the voltage induced in the secondary winding of the transformer; and based on the information input from the feedback means a control means for controlling on or off of the first switching element by a first control signal, and controlling on or off of the second switching element by a second control signal; is a period during which a switching operation is performed to alternately turn on or off the first switching element and the second switching element with a dead time in which both the first switching element and the second switching element are turned off. A power supply device capable of performing repeated continuous operation and intermittent operation in which a period in which the switching operation is performed and a period in which the switching operation is stopped are alternately performed, wherein the resonance capacitor unit includes a first a resonance capacitor, a second resonance capacitor, and a third switching element connected in series with the second resonance capacitor, wherein the second resonance capacitor and the third switching element are connected to the The control means is connected in parallel with the first resonance capacitor, and the control means turns on the third switching element during the continuous operation, turns off the third switching element during the intermittent operation, and switches the switching element from the continuous operation to the intermittent operation. A power supply device characterized by switching said third switching element from ON to OFF after transitioning to operation, when said first switching element is in an ON state or in an OFF state.
(3) An image forming apparatus comprising: image forming means for forming an image on a recording material; and the power supply device according to (1) or (2).
(4) A transformer having a primary winding and a secondary winding, a first switching element connected in series with the primary winding of the transformer, and a resonant capacitor connected in parallel with the first switching element. a second switching element connected in parallel to the primary winding of the transformer; and a second switching element connected in series to the second switching element and connected to the primary winding of the transformer together with the second switching element. a capacitor connected in parallel; feedback means for outputting information corresponding to an output voltage obtained by rectifying and smoothing the voltage induced in the secondary winding of the transformer; and based on the information input from the feedback means , control means for controlling on or off of the first switching element by a first control signal and on or off of the second switching element by a second control signal; and instruction means for instructing to switch the target voltage of the output voltage to a first voltage or a second voltage higher than the first voltage, wherein the control means performs the first switching a continuous operation of repeating a switching operation period of alternately turning on or off the first switching element and the second switching element with a dead time in which both the element and the second switching element are turned off; intermittent operation in which a period of operation and a period of stopping the switching operation are alternately repeated, and the control means can switch the target voltage according to an instruction from the instruction means. wherein the resonant capacitor section includes a first resonant capacitor, a second resonant capacitor, and a third switching element connected in series with the second resonant capacitor. The second resonant capacitor and the third switching element are connected in parallel with the first resonant capacitor, and the control means controls the third switching element when the target voltage is the second voltage. , and turns off the third switching element when the target voltage is the first voltage.
(5) An image forming apparatus comprising: image forming means for forming an image on a recording material; and the power supply device according to (4).

According to the present invention, it is possible to improve power efficiency in an active clamp type power supply device.

Schematic diagram of power supply circuit of embodiment 1 A diagram for explaining the control method of Embodiments 1 and 2, and a simple circuit diagram for explaining the control method. 4A and 4B are diagrams for explaining the circuit operation due to the difference in the capacitance of the resonant capacitor of the first embodiment; Graph showing the relationship between output power and power conversion efficiency in Example 1 FIG. 4 is a diagram for explaining switching timing of resonance capacitors in the first embodiment; Schematic diagram of power supply circuit of embodiment 2 Graph showing the relationship between output power and power conversion efficiency in Example 2 FIG. 11 is a diagram for explaining switching timing of resonance capacitors in the second embodiment; FIG. 10 is a diagram for explaining voltage applied between the drain terminal and the source terminal of the FET of Example 3; FIG. 11 is a diagram for explaining switching timing of resonance capacitors when switching the target voltage from 5 V to 24 V in the third embodiment; FIG. 11 is a diagram for explaining switching timing of the resonant capacitor when switching the target voltage from 24 V to 5 V in the third embodiment; FIG. 4 shows an image forming apparatus according to a fourth embodiment;

BEST MODE FOR CARRYING OUT THE INVENTION Below, embodiments of the present invention will be described in detail with reference to the drawings.

[Configuration of power supply]
A flyback power supply device using the active clamp method of Example 1 will be described with reference to the drawings. FIG. 1 is a schematic circuit diagram of a switching power supply circuit using an active clamp system according to a first embodiment. In the flyback power supply device of this embodiment, an AC voltage is input from an AC power supply 10 such as a commercial power supply, and a voltage rectified by a bridge diode BD1 as full-wave rectifying means is input to a switching power supply circuit 100. In the switching power supply circuit 100, the smoothing capacitor C3 is used as means for smoothing the voltage rectified by the bridge diode BD1. DCL is the low potential of the smoothing capacitor C3 and DCH is the high potential. The switching power supply circuit 100 outputs the power supply voltage Vout from the input voltage Vin charged in the smoothing capacitor C3 to the insulated secondary side of the transformer T1.

The switching power supply circuit 100 has an insulated transformer T1 having a primary winding P1, an auxiliary winding P2 on the primary side, and a secondary winding S1 on the secondary side. Energy is supplied from the primary winding P1 to the secondary winding S1 of the transformer T1 by a switching operation described later with reference to FIG. The auxiliary winding P2 of the transformer T1 is used to rectify and smooth the forward voltage of the input voltage Vin applied to the primary winding P1 with a diode D4 and a capacitor C4 and supply the power supply voltage V1.

On the primary side of the switching power supply circuit 100, a field effect transistor (hereinafter referred to as FET) 1, which is a first switching element, is connected in series with the primary winding P1 of the transformer T1. A voltage clamping capacitor C2 and a second switching element FET2 are connected in series, and the voltage clamping capacitor C2 and FET2 connected in series are connected in parallel with the primary winding P1 of the transformer T1. It is Further, the primary side of the switching power supply circuit 100 is provided with a control section 101 that controls driving of the FET1 and the FET2.

A control unit 101, which is control means, drives FET1 by outputting a high-level control signal DRV-L, and drives FET2 by outputting a high-level control signal DRV-H. A power supply voltage V1 is supplied between the VC terminal and the G terminal of the control section 101 . In order to drive the FET2, a power supply voltage V1 is supplied between the VH terminal and the GH terminal of the control section 101 by a charge pump circuit composed of a capacitor C5 and a diode D5.

FET1 is connected in parallel with a resonant capacitor C11 as a first resonant capacitor, a circuit in which a resonant capacitor C12 as a second resonant capacitor, and an FET12 as a third switching element are connected in series. there is The resonance capacitors C11, C12, and FET12 form a resonance capacitor section, and the resonance capacitor C11 is selected to have a smaller capacitance than the resonance capacitor C12 (C11<C12). Also, the FET 12 is on/off controlled by the control signal DRV-C output from the control section 101 . When the FET12 is off, only the resonance capacitor C11 is connected in parallel with the FET1, and the capacitance of the resonance capacitor at this time is the capacitance of the resonance capacitor C11. On the other hand, when the FET12 is on, the resonance capacitors C11 and C12 are connected in parallel to the FET1, and the capacitance of the resonance capacitor at this time is the sum of the capacitances of the resonance capacitors C11 and C12. Note that the capacitance between the drain terminal and the source terminal of FET1 may be used without providing the resonance capacitor C11.

A diode D1 connected in parallel with FET1 in FIG. 1 is a body diode of FET1. Similarly, diode D2 connected in parallel with FET2 is also the body diode of FET2. Note that the control unit 101 may use, for example, an IC configured by an analog circuit, or may use an arithmetic control element (eg, CPU, ASIC, etc.) that operates with a clock signal generated by an oscillator or the like.

The secondary side of the switching power supply circuit 100 is provided with a rectifying/smoothing circuit 118 composed of a diode D21 and a capacitor C21, which is a secondary side rectifying means for the flyback voltage generated in the secondary winding S1 of the transformer T1. there is A voltage induced in the secondary winding S1 of the transformer T1 is rectified and smoothed by a diode D21 and a capacitor C21, and output as a power supply voltage Vout (also referred to as an output voltage Vout). Further, the secondary side of the switching power supply circuit 100 is provided with a feedback section 115 as feedback means for feeding back information corresponding to the power supply voltage Vout output to the secondary side to the primary side.

The feedback unit 115 is used to control the power supply voltage Vout to a predetermined constant voltage (hereinafter referred to as target voltage). The voltage value of the power supply voltage Vout is set by a reference voltage, which is the voltage input to the reference terminal REF of the shunt regulator IC5. That is, the power supply voltage Vout is set by the voltage dividing resistors R52, R53, and R54. When the voltage of the power supply voltage Vout becomes higher than the target voltage, current flows from the cathode terminal K of the shunt regulator IC5, and the secondary diode of the photocoupler PC5 becomes conductive via the pull-up resistor R51. As a result, the primary side phototransistor of the photocoupler PC5 is activated, and the capacitor C6 is discharged. Therefore, the input voltage of the FB terminal of the control section 101 is lowered. On the other hand, when the voltage of the power supply voltage Vout becomes lower than the target voltage, the secondary diode of the photocoupler PC5 becomes non-conductive. As a result, the primary-side phototransistor of the photocoupler PC5 is turned off, and current flows from the power supply voltage V1 through the resistor R2 to charge the capacitor C6. Therefore, the input voltage of the FB terminal of the control unit 101 (hereinafter referred to as FB terminal voltage) increases. In this way, the feedback section 115 changes the FB terminal voltage of the control section 101 in accordance with fluctuations in the power supply voltage Vout.

The control unit 101 detects the FB terminal voltage input from the feedback unit 115, thereby performing feedback control for controlling the power supply voltage Vout to the target voltage. Thus, the control unit 101 can indirectly feedback-control the power supply voltage Vout by monitoring the FB terminal voltage. Further, instead of the feedback section 115, the control section 101 may be provided on the secondary side and the power supply voltage Vout may be directly feedback-controlled by monitoring the power supply voltage Vout. Since the control unit 101 can grasp the state of the load by monitoring the FB terminal voltage, it can perform appropriate control according to the state of the load. In order to determine the state of the load more accurately, current detection means may be provided in the FET 1 or the path for supplying power to the load of the switching power supply circuit 100 . It is assumed that the FB terminal voltage of the control unit 101 is used as the means for determining the light load state in this embodiment.

The starter circuit 103 is a three-terminal regulator or a step-down switching power supply circuit, converts the input voltage Vin input between the VC terminal and the G terminal, and outputs the power supply voltage V1 from the OUT terminal. The startup circuit 103 is a circuit that operates only when the power supply voltage V1 supplied from the auxiliary winding P2 is equal to or lower than a predetermined voltage value, and is used to supply the power supply voltage V1 when the switching power supply circuit 100 is started.

[Control Method of Switching Power Supply Circuit]
FIG. 2 is a diagram for explaining a method of controlling the switching power supply circuit 100 using the active clamp method by the control section 101. As shown in FIG. FIG. 2 shows operation waveforms when the control signal DRV-C is set to a low level and the FET 12 is turned off. The switching power supply circuit 100 supplies power to the secondary side by alternately turning on/off the FET1 and the FET2 with a dead time during which the control unit 101 turns off both the FET1 and the FET2. A period in which the control unit 101 alternately turns on/off the FET1 and the FET2 with a dead time in which both the FET1 and the FET2 are turned off is called a switching period (first period). FIG. 2A is a diagram showing voltage waveforms and current waveforms at terminals of FET1 and FET2 divided into a plurality of periods [1] to [4], which will be described later. In FIG. 2A, (a) is a diagram showing the voltage between the gate terminal and the source terminal of FET1, which indicates the state of the control signal DRV-L, which is the input signal to the gate terminal of FET1. (b) is a diagram showing the voltage between the gate terminal and the source terminal of FET2 indicating the state of the control signal DRV-H which is the input signal to the gate terminal of FET2, and (c) is a diagram showing the voltage between the drain terminal and the source terminal of FET1. FIG. 10 is a diagram showing the voltage between (d) is a diagram showing the drain current of the FET1, and the drain current in this case includes the current flowing through the diode D1. (e) is a diagram showing the drain current of the FET2, and the drain current in this case includes the current flowing through the diode D2. (f) is a diagram showing a current waveform flowing through a diode D21 on the secondary side of the transformer T1. Note that the horizontal axis indicates time.

FIG. 2B is a simplified circuit diagram showing current flow in each of a plurality of periods [1] to [4]. The inductance Ls is shown divided into the ideal transformer TI. Further, in the circuit of FIG. 2B, the current flowing in each period is indicated by dark solid arrows.

(switching period)
First, period [1] is a period in which FET1 is on and FET2 is off (FIGS. 2(A)(a) and (b)). Energy is accumulated in the leakage inductance Lr and the exciting inductance Ls of the transformer T1 by the current flowing from the smoothing capacitor C3 to the primary winding P1 of the transformer T1. At this time, the voltage between the drain terminal and the source terminal of FET1 is almost zero (FIGS. 2(A)(c)), and the drain current flowing through FET1 increases linearly (FIGS. 2(A)(d)). .

Next, period [2] is a period in which both FET1 and FET2 are in an OFF state, that is, a period of dead time (FIGS. 2(A)(a) and (b)). When the FET1 is turned off, the current flowing through the primary winding P1 of the transformer T1 flows so as to charge the resonance capacitor C11. Then, as the resonance capacitor C11 is charged, the voltage between the drain terminal and the source terminal of FET1 rises (FIG. 2(A)(c)). When the voltage between the drain terminal and the source terminal of FET1 exceeds the voltage of the + terminal of the voltage clamping capacitor C2, the current flowing through the primary winding P1 of the transformer T1 is transferred to the voltage clamping capacitor via the diode D2. It begins to flow to charge C2. As a result, the kickback voltage due to the leakage inductance Lr is absorbed by the voltage clamping capacitor C2, so that the surge voltage applied between the drain terminal and the source terminal of the FET1 can be suppressed. In addition, since the voltage between the drain terminal and the source terminal of FET2 becomes almost zero, turning on FET2 in this state during period [3] realizes zero voltage switching of FET2.

Here, the period [2] should be set substantially equal to or slightly longer than the time from when FET1 is turned off until the voltage between the drain terminal and the source terminal of FET2 becomes substantially zero. If the period of [2] is long, the period in which the current flows through the diode D2 is lengthened, resulting in wasted power consumption. On the other hand, if the period [2] is short, the FET2 is turned on before the voltage between the drain terminal and the source terminal of the FET2 becomes zero, so zero voltage switching cannot be performed and power is wasted. be. Therefore, power consumption can be suppressed by setting the period [2] to an appropriate value.

Subsequently, the period [3] is a period in which the FET2 is on and the FET1 is off (FIGS. 2(A)(a) and (b)). When the FET2 is turned on, the current charging the voltage clamping capacitor C2 through the diode D2 starts to flow through the FET2. When the voltage of the voltage clamping capacitor C2 rises, the diode D21 on the secondary side is turned on, and power is supplied to the secondary side of the switching power supply circuit 100 via the secondary winding S1 of the transformer T1. become.

Here, in the drain current of the FET 2 shown in FIGS. 2A and 2E, the waveform indicated by the dotted line indicates the excitation current flowing through the excitation inductance Ls of the transformer T1, which decreases linearly. The sum of the exciting current flowing through the exciting inductance Ls and the current flowing through the ideal transformer TI is the drain current of the FET2. Also, the current flowing through the ideal transformer TI has a similar shape to the current flowing through the diode D21 (FIG. 2(A)(f)).

The period [3] is composed of [3] OFF period during which power is not supplied to the secondary side and [3] ON period during which power is supplied to the secondary side. [3] During the OFF period, a current flows through the FET2 mainly due to the resonance operation of the voltage clamping capacitor C2 and the leakage inductance Lr and exciting inductance Ls of the transformer T1. On the other hand, during the [3] ON period, a current flows through the FET2 mainly due to the resonance operation of the voltage clamping capacitor C2 and the leakage inductance Lr of the transformer T1. The inductance value of the leakage inductance Lr is smaller than the excitation inductance Ls. Therefore, the resonance frequency during the [3] ON period is higher than the resonance frequency during the [3] OFF period.

Zeroing of the exciting current flowing through the exciting inductance Ls of the transformer T1 means that all the energy accumulated in the exciting inductance Ls is released. If the FET2 continues to be turned on thereafter, a current begins to flow from the voltage clamping capacitor C2 toward the magnetizing inductance Ls, and opposite-phase energy is accumulated in the magnetizing inductance Ls. Become.

Subsequently, the period [4] is a period in which both FET1 and FET2 are off again, that is, a period of dead time. When the FET2 is turned off, the current flowing through the primary winding P1 of the transformer T1 flows so as to discharge the charge charged in the resonance capacitor C11. As the resonance capacitor C11 is discharged, the voltage between the drain terminal and the source terminal of FET1 decreases (FIG. 2(A)(c)). When the voltage between the drain terminal and the source terminal of FET1 falls below zero, the current flowing through the primary winding P1 of the transformer T1 is regenerated to the smoothing capacitor C3 via the diode D1. By returning to period [1] in this state and turning on FET1, zero voltage switching of FET1 can be realized. In the period [4], similarly to the period [2] described above, the time from when the FET2 is turned off until the drain-source voltage of the FET1 becomes almost zero, or set to be slightly longer. can reduce power consumption.

As described above, the flyback power supply device using the active clamp system, which is the switching power supply in this embodiment, repeats the control from period [1] to period [4]. As a result, it is possible to perform zero-voltage switching of FET1 and FET2 while suppressing the surge voltage due to the leakage inductance Lr, thereby supplying power to the secondary side. By the way, the switching power supply circuit 100 described above operates in a continuous operation state in which periods [1] to [4] are repeated. In a general switching power supply circuit, an intermittent operation is performed in which a switching period in which FET1 and FET2 perform switching operations alternately and a switching stop period (second period) in which switching of both FET1 and FET2 is stopped is provided. will be That is, by intermittently operating the switching power supply circuit, it is possible to improve the power conversion efficiency compared to continuous operation. However, in the intermittent operation state, ripples occur in the power supply voltage Vout, so it is common to set the intermittent operation state only when the output power is small. Even in the flyback power supply device using the active clamp method of this embodiment, it is possible to improve the power conversion efficiency by setting the intermittent operation state.

[Effect of Connecting Two Resonant Capacitors in Parallel]
In FIG. 2, the circuit operation waveforms when the FET 12 of FIG. Next, the effect when the FET12 is set to the ON state and the two resonance capacitors C11 and C12 are connected in parallel to the FET1 will be described. FIG. 3A is a diagram showing the voltage waveform and current waveform at each terminal of FET1 and FET2, and the switching loss when FET12 is turned on and off. 4]. In FIG. 3A, (a) is a diagram showing the voltage between the gate terminal and the source terminal of FET1, which indicates the state of the control signal DRV-L, which is the input signal to the gate terminal of FET1. (b) is a diagram showing the voltage between the gate terminal and the source terminal of FET2 indicating the state of the control signal DRV-H, which is the input signal to the gate terminal of FET2, and (c) is a diagram showing the drain current of FET1. is.

(d) is a diagram showing the voltage between the drain terminal and the source terminal of FET1, (e) is a diagram showing switching loss in FET1, and (f) is a diagram showing switching loss in FET2. (d) to (f) show the waveforms when FET12 is off, that is, when only resonance capacitor C11 is connected in parallel to FET1. (g) is a diagram showing the voltage between the drain terminal and the source terminal of FET1, (h) is a diagram showing switching loss in FET1, and (i) is a diagram showing switching loss in FET2. (g) to (i) show waveforms when the FET12 is on, that is, when the resonant capacitors C11 and C12 are connected in parallel to the FET1. Note that the horizontal axis indicates time. Also, the operation waveforms in periods [1] to [4] are the same as the operation waveforms described above, and descriptions thereof are omitted here.

When FET12 is turned on, the capacitance of the resonance capacitor connected in parallel with FET1 increases compared to when FET12 is turned off. Therefore, the rate of increase of the voltage between the drain terminal and the source terminal of FET1 when FET12 is in the ON state when FET1 is switched from the ON state to the OFF state (FIG. 3(A)(g)) is As compared with the rising speed in the state (FIG. 3(A)(d)), it becomes slower. As a result, the loss energy, which is the integrated value of the voltage x current of the FET1, that is, the switching loss is greater when the FET12 is in the ON state (Fig.3(A)(h)) than when it is in the OFF state (Fig.3(A) (e)). Similarly, when the FET 2 is switched from the ON state to the OFF state, the drop speed of the voltage between the drain terminal and the source terminal of the FET 2 when the FET 12 is in the ON state (FIG. 3 (A) (g)) is It is slower than the descending speed in the off state (FIGS. 3(A)(d)). As a result, the switching loss of the FET2 is smaller when the FET12 is on ((A)(i) in FIG. 3) than when it is off ((A)(f) in FIG. 3). Since this switching loss occurs in each switching cycle, the switching loss is greater during continuous operation than during intermittent operation.

On the other hand, when the switching power supply circuit 100 starts switching operation, electric charge is stored in the resonance capacitor C11. Therefore, when the FET1 is turned on, the energy corresponding to the charge, that is, the energy calculated by (1/2*capacitance of resonance capacitor C11*Vin*Vin) becomes switching loss. FIG. 3B is a diagram showing circuit waveforms when the switching operation of the switching power supply circuit 100 is started. In FIG. 3B, (a) is a diagram showing the voltage between the gate terminal and the source terminal of FET1 indicating the state of the control signal DRV-L, and (b) is a diagram showing the state of the control signal DRV-H. is a diagram showing the voltage between the gate terminal and the source terminal of the . Also, (c) is a diagram showing the voltage between the drain terminal and the source terminal of the FET1. The timing when the switching power supply circuit 100 described above starts the switching operation refers to timing [0] in FIG. 3B. At this time, if the FET 12 is in the ON state, the energy corresponding to the charge charged in the resonance capacitor C12, that is, (1/2*capacitance of the resonance capacitor C12*Vin*Vin) also becomes a switching loss. However, since this switching loss occurs only at the start of the switching operation, the loss can be almost ignored when the switching power supply circuit 100 is in continuous operation. Therefore, in this embodiment, in the switching power supply circuit 100, the controller 101 controls the FET 12 so that the FET 12 is turned on in the continuous operation state and turned off in the intermittent operation state.

[Relationship between output power and power conversion efficiency]
FIG. 4 is a graph showing the relationship between the output power supplied to the load from the switching power supply circuit 100 and the power conversion efficiency when the FET 12 is on and off. In FIG. 4 , the vertical axis indicates the power conversion efficiency [%], and the horizontal axis indicates the output power [W] of the switching power supply circuit 100 . The thick solid line is a graph showing the relationship between the output power and the power conversion efficiency when the FET 12 is on, and the thin solid line is a graph showing the relationship between the output power and the power conversion efficiency when the FET 12 is off. be. The switching power supply circuit 100 is in a continuous operation state when the output power is higher than the dashed line shown in FIG. 4, and is in an intermittent operation state when the output power is lower than the dashed line. As shown in FIG. 4, by setting the FET 12 to the ON state in the continuous operation state and setting the FET 12 to the OFF state in the intermittent operation state, a low-loss switching power supply circuit can be realized in both the continuous operation state and the intermittent operation state. can be done.

[Resonant Capacitor Switching Timing]
Next, the switching timing of the FET12 that switches the connection between the resonant capacitors C11 and C12 and the FET1 will be described with reference to FIG. FIG. 5 is a diagram showing voltage waveforms in FET1, FET2, and FET12, capacitances of resonant capacitors, and operating states of the switching power supply circuit 100, where the horizontal axis indicates time. In FIG. 5, (a) shows the voltage between the gate terminal and the source terminal of FET1 showing the state of the control signal DRV-L, and (b) shows the gate terminal of FET2 showing the state of the control signal DRV-H. and a voltage between the source terminals. (c) is a diagram showing the voltage between the drain terminal and the source terminal of FET1, and (d) is a diagram showing the state of the control signal DRV-C, which is the input signal to the gate terminal of FET12. It is a figure which shows the voltage between terminals. (e) is a diagram showing the capacity state (resonance capacitor small, resonance capacitor large) of the resonance capacitor connected in parallel to the FET 1, and (f) shows the operation state (continuous operation, intermittent operation) of the switching power supply circuit 100. FIG. 4 is a diagram showing;

First, when the switching power supply circuit 100 is in an intermittent operation state (FIG. 5(f)), the output power is small. This is the low level state (FIG. 5(d)). After that, when the operation state transitions from intermittent operation to continuous operation (FIG. 5(f)), during the period when the voltage between the drain terminal and the source terminal of FET1 after turning on FET1 is zero, the control unit 101 outputs the control signal The state of DRV-C is switched to high level (FIG. 5(d)). If the state of the control signal DRV-C is switched from low level to high level when the voltage between the drain terminal and the source terminal of FET1 is not zero, a sudden rush current flows into the resonance capacitor C12. As a result, noise is generated, causing the switching power supply circuit 100 to malfunction, or the charging voltage of the resonance capacitor C11 is lowered to make the switching operation unstable. Therefore, it is desirable to turn on/off the FET12 when the voltage between the drain terminal and the source terminal of the FET1 is zero.

Subsequently, the control unit 101 causes the switching power supply circuit 100 to transition from the continuous operation to the intermittent operation again (FIG. 5(f)). Then, after the switching operations of both FET1 and FET2 are stopped ((a) and (b) in FIG. 5), the control unit 101 switches the control signal DRV-C from the high level state to the low level state ((d) in FIG. 5). )). The timing of switching the control signal DRV-C from high level to low level is preferably when the voltage between the drain terminal and the source terminal of FET1 is stable. Further, if priority is given to simple control such that the switching of the control signal DRV-C is always the timing at which the voltage between the drain terminal and the source terminal of FET1 becomes zero, the switching may be performed at the following timing. . That is, immediately before the switching power supply circuit 100 transitions from continuous operation to intermittent operation, the control signal DRV-C is changed from the high level to the low level during the period in which the FET1 is in the ON state and the voltage between the drain terminal and the source terminal of the FET1 is zero. You can switch to By the way, in this switching control, the switching power supply circuit 100 performs switching in a state where the capacity of the resonance capacitor is small only once immediately before the switching power supply circuit 100 transitions from the continuous operation state to the intermittent operation state. Therefore, it is necessary to pay attention to the fact that a slight switching loss occurs accordingly.

As described above, the switching power supply circuit switches the capacitance of the resonance capacitor at appropriate timing depending on whether the operating state is the continuous operating state or the intermittent operating state. As a result, the switching power supply circuit can realize high power conversion efficiency from when the output power is small to when it is large while maintaining stable switching operation.
As described above, according to this embodiment, it is possible to improve the power efficiency in the active clamp type power supply device.

In Example 1, the capacitance of the resonance capacitor is switched by controlling the FET 12 depending on whether the switching operation is intermittent or continuous. In a second embodiment, an embodiment will be described in which the FET 12 is controlled to turn on and off depending on whether the target voltage supplied to the load by the switching power supply circuit is 24 VDC (direct current) or 5 VDC.

[Configuration of power supply]
FIG. 6 is a schematic circuit diagram of a switching power supply circuit 200 using an active clamp method according to the second embodiment. Compared to the switching power supply circuit 100 of the first embodiment shown in FIG. 1, the switching power supply circuit 200 shown in FIG.

The target voltage switching unit 117, which is an instruction unit, inputs a high level or low level to the 24SL terminal of the control unit 101 as a switching instruction signal for switching the power supply voltage Vout according to the state of the 24VSL signal input from the outside. do. When the switching power supply circuit 200 outputs a DC 24V voltage, which is the second voltage, as the power supply voltage Vout, a high-level 24VSL signal is input. On the other hand, when outputting the DC 5V voltage, which is the first voltage, as the power supply voltage Vout, a low-level 24VSL signal is input. When the 24VSL signal is in a high level state, the FET71 is turned on, and a current flows through the secondary diode of the photocoupler PC7 via the resistor R71. As a result, the primary-side phototransistor of the photocoupler PC7 is turned on, the electric charge stored in the capacitor C7 is discharged, and the input voltage of the 24SL terminal of the control section 101 becomes low level. On the other hand, when the 24VSL signal is in the low level state, the FET71 is turned off, the secondary diode of the photocoupler PC7 is turned off, and no current flows. As a result, the primary-side phototransistor of the photocoupler PC7 is turned off, the capacitor C7 is charged from the power supply voltage V1 through the resistor R1, and the input voltage of the 24SL terminal of the control unit 101 becomes high level. Become. Then, the control unit 101 detects whether the target voltage is DC24V or DC5V according to the input voltage of the 24SL terminal. A resistor R72 is a current limiting resistor.

Further, in FIG. 6, an FET51 connected in parallel to the voltage dividing resistor R54 of the feedback section 115 is added, and a resistor R55 is connected between the gate terminal and the drain terminal of the FET51. The 24VSL signal is also input to the gate terminal of the FET 51 of the feedback section 115 . When the 24VSL signal is at a high level, the FET51 is turned on and the voltage dividing resistor R54 is shorted. Therefore, the voltage input to the REF terminal of the shunt regulator IC5 is the voltage obtained by dividing the output voltage Vout by the voltage dividing resistors R52 and R53. As a result, the voltage dividing ratio of the reference voltage of the shunt regulator IC5 to the power supply voltage Vout decreases, and the feedback section 115 operates so that 24V DC is output to the power supply voltage Vout. On the other hand, when the 24VSL signal is low level, the FET51 is turned off, and the voltage dividing resistors R53 and R54 are connected in series. Therefore, the voltage input to the REF terminal of the shunt regulator IC5 is the voltage obtained by dividing the output voltage Vout by the voltage dividing resistors R52, R53, and R54. As a result, the voltage division ratio of the reference voltage of the shunt regulator IC5 to the power supply voltage Vout increases, and the feedback section 115 operates so that 5V DC is output to the power supply voltage Vout. In this way, when the power supply voltage Vout is switched, the feedback unit 115 switches the voltage dividing resistance value to a resistance value corresponding to the power supply voltage Vout by changing the combination of the voltage dividing resistances. As a result, the state of the load to which power is supplied from the switching power supply circuit 200 is notified from the feedback section 115 as the FB terminal voltage of the control section 101 .

As described above, in the intermittent operation state, the power conversion efficiency is higher than in the continuous operation state. Not suitable for large cases. Therefore, the switching power supply circuit 200 is always in the continuous operation state when the target voltage is DC 24V, which has a large output power fluctuation. On the other hand, when the target voltage at which output power fluctuation is small and the required power conversion efficiency is high is DC 5V, the switching power supply circuit 200 switches between the continuous operation state and the intermittent operation state according to the output power.

[Resonance capacitor switching]
FIG. 7 is a graph showing the relationship between the output power supplied to the load by the switching power supply circuit 200 and the power conversion efficiency when the FET 12 is on and off. FIG. 7A shows a case where the target voltage is 24V DC, and FIG. 7B shows a case where the target voltage is 5V DC. 7A and 7B, the vertical axis indicates the power conversion efficiency [%], and the horizontal axis indicates the output power [W] of the switching power supply circuit 200. FIG. 7A and 7B, the thick solid line is a graph showing the relationship between the output power and the power conversion efficiency when the FET 12 is on, and the thin solid line is the output power when the FET 12 is off. 4 is a graph showing the relationship between , and power conversion efficiency. When the target voltage is DC24V, the switching power supply circuit 200 is in a continuous operation state. On the other hand, when the target voltage is 5V DC, the switching power supply circuit 200 enters a continuous operation state when the output power is greater than the dashed line shown in FIG. It becomes operational.

FIG. 7A shows that when the FET 12 is on, the power conversion efficiency with respect to the output power is higher over the entire range of output power than when it is off. Therefore, when the target voltage is 24 VDC, the FET 12 should always be set to the ON state because it is always in the continuous operation state. On the other hand, when the target voltage is 5V DC, the FET 12 should be turned off in the intermittent operation state and turned on in the continuous operation state. However, if the intermittent operation state and the continuous operation state are frequently switched, the control of the FET 12 becomes complicated. Therefore, if the target voltage is DC5V and the required power conversion efficiency is not so high when the output voltage is high, it is easier to control by turning off the FET 12 even in the continuous operation state. Become. Therefore, in this embodiment, the control unit 101 controls the FET 12 so that the FET 12 is turned on when the target voltage is DC 24V, and is turned off when the target voltage is 5V.

Next, the ON/OFF switching timing of the FET 12 will be described with reference to FIG. FIG. 8 is a diagram showing voltage waveforms in FET1, FET2 and FET12, the state of the 24VSL signal, the capacity of the resonant capacitor, and the operating state of the switching power supply circuit 200, with the horizontal axis representing time. In FIG. 8, (a) shows the voltage between the gate terminal and the source terminal of FET1 indicating the state of the control signal DRV-L, and (b) shows the gate terminal of FET2 indicating the state of the control signal DRV-H. and a voltage between the source terminals. (c) is a diagram showing the voltage between the drain terminal and the source terminal of FET1, and (d) is a diagram showing the state of the control signal DRV-C, which is the input signal to the gate terminal of FET12. It is a figure which shows the voltage between terminals. (e) is a diagram showing the state (high level, low level) of the 24VSL signal, (f) is a diagram showing the capacity state of the resonance capacitor connected in parallel to FET1, (g) is a switching power supply FIG. 4 is a diagram showing target voltages (5V, 24V) of circuit 200;

Also in this embodiment, as in the first embodiment, it is desirable to switch the on/off state of the FET 12 when the voltage between the drain terminal and the source terminal of the FET 1 is zero. First, when the target voltage is 5V DC ((g) in FIG. 8), the control signal DRV-C is at low level ((d) in FIG. 8) and the 24VSL signal is also at low level ((e) in FIG. 8). )). Then, when the 24VSL signal switches from low level to high level (FIG. 8(e)), the control unit 101 switches the target voltage from DC 5V to DC 24V (FIG. 8(g)). After that, the FET1 is turned on, and during the period when the voltage between the drain terminal and the source terminal of the FET1 is zero, the control unit 101 switches the control signal DRV-C output to the FET12 from low level to high level (Fig. 8 (d )). On the other hand, when the 24VSL signal switches from high level to low level (FIG. 8(e)), the control unit 101 switches the target voltage from DC 24V to DC 5V (FIG. 8(g)). After that, FET1 is turned on, and during a period in which the voltage between the drain terminal and the source terminal of FET1 is zero, the control unit 101 switches the control signal DRV-C output to the FET12 from high level to low level (FIG. 8 ( d)).

As described above, by switching the capacitance of the resonance capacitor according to the target voltage, the switching power supply circuit 200 maintains a stable switching operation with simple control, and achieves high power conversion from when the output power is small to when it is large. can have efficiency.
As described above, according to this embodiment, it is possible to improve the power efficiency in the active clamp type power supply device.

In Example 2, the FET 12 is controlled to turn on/off depending on whether the target voltage supplied to the load by the switching power supply circuit is 24V DC (direct current) or 5V DC, thereby switching the capacity of the resonance capacitor. Embodiment 3 describes an embodiment characterized by the ON/OFF timing of the FET 12 in the configuration of Embodiment 2. FIG.

First, the difference in voltage waveform between the drain terminal and the source terminal of FET1 due to the difference in capacitance of the resonant capacitor will be described with reference to FIG. 9A shows waveforms when the resonance capacitor is small (FET 12 is off) and the power supply voltage Vout is 5V, and FIG. 9B shows waveforms when the resonance capacitor is small and the power supply voltage Vout is 24V. FIG. 9(c) shows the waveform when the resonance capacitor capacity is large (FET 12 is on) and the power supply voltage Vout is 5V, and FIG. 9(d) shows the waveform when the resonance capacitor capacity is large and the power supply voltage Vout is 24V. When the FET1 is turned off, the voltage between the drain terminal and the source terminal of the FET1 rises to the voltage charged in the clamp capacitor C2 and is clamped. However, in reality, a surge voltage (inside the dashed line in FIG. 9) is generated due to the influence of the resistance and inductance components of the pattern, and is superimposed on the voltage charged in the clamp capacitor C2 (the thick line in FIG. 9). The surge voltage depends on the rate of increase of the voltage between the drain terminal and the source terminal of FET1=DV/DT. If the DV/DT is large, the surge voltage will be large, and conversely, if the DV/DT is small, the surge voltage will be small. DV/DT depends on the capacitance of the resonant capacitor. If the capacity of the resonance capacitor is small, the resonance capacitor is charged quickly when the FET1 is turned off, so DV/DT increases and the surge voltage also increases as shown in FIGS. 9(a) and 9(b). Conversely, when the capacity of the resonance capacitor is large, DV/DT becomes small, and the surge voltage also becomes small as shown in FIGS. 9(c) and 9(d).

ここで、ＮｒはトランスＴ１の１次巻線Ｐ１の巻数ＮＰ１と２次巻線Ｓ１の巻数ＮＳ１の比（ＮＰ１／ＮＳ１）である。（式１）より、クランプコンデンサＣ２に充電されている電圧ＶＣ２は、電源電圧Ｖｏｕｔに比例する。即ち、目標電圧が５Ｖのときより２４Ｖのときの方が、クランプコンデンサＣ２に充電されている電圧ＶＣ２は大きくなる。 By the way, the voltage VC2 charged in the clamp capacitor C2 is expressed by the following (Equation 1) using the input voltage Vin and the power supply voltage Vout.

Here, Nr is the ratio (NP1/NS1) of the number of turns NP1 of the primary winding P1 of the transformer T1 and the number of turns NS1 of the secondary winding S1. From (Equation 1), the voltage VC2 charged in the clamp capacitor C2 is proportional to the power supply voltage Vout. That is, the voltage VC2 charged in the clamp capacitor C2 is higher when the target voltage is 24V than when the target voltage is 5V.

The voltage applied between the drain terminal and the source terminal of FET1 is, as described above, a voltage obtained by adding the surge voltage to the voltage charged in the clamp capacitor C2. Therefore, the voltage applied between the drain terminal and the source terminal of FET1 is the smallest when the resonance capacitor capacity is large and the power supply voltage Vout is 5 V (FIG. 9(c)). (FIG. 9(b)) is the largest.

In this embodiment, when the power supply voltage Vout is 5V, the resonance capacitor capacity is small (Fig. 9(a)), and when the power supply voltage Vout is 24V, the resonance capacitor capacity is large (Fig. 9(d)). be.

The ON/OFF switching timing of the FET 12 when switching the target voltage will be described with reference to FIGS. 10 and 11. FIG.

10 and 11, (a) shows the voltage between the drain terminal and the source terminal of FET1, and (b) shows the state of the control signal DRV-C, which is the input signal to the gate terminal of FET12. FIG. 4 is a diagram showing the voltage between the gate and source terminals of the FET 12 shown. (c) is a diagram showing the state (high level, low level) of the 24VSL signal, and (d) is a diagram showing the power supply voltage Vout. (e) is a diagram showing the capacitance state of a resonance capacitor connected in parallel to FET 1, and (f) is a diagram showing target voltages (5V, 24V) of the switching power supply circuit 200. FIG. (g) is the control state of the power supply voltage Vout, that is, the control state (normal control) in which the power supply voltage Vout is stably controlled to the target voltage, or the power supply voltage Vout has not reached the target voltage and has reached the target voltage. It is a figure which shows the approaching control state (switching control). It should be noted that the normal control in this embodiment indicates a state in which the power supply voltage Vout is controlled to the target voltage by detecting the FB terminal voltage, as described above. On the other hand, switching control indicates a state in which control is performed to gradually change the power supply voltage Vout regardless of the FB terminal voltage.

10 is a diagram showing each operation when switching the power supply voltage Vout from 5V to 24V, and FIG. 11 is a diagram showing each operation when switching the power supply voltage Vout from 24V to 5V.

First, when operating with the target voltage of 5V DC (FIG. 10(f)), the control signal DRV-C is at low level (FIG. 10(b)) and the 24VSL signal is also at low level (FIG. 10(c)). )). At this time, a large surge voltage is applied between the drain terminal and the source terminal of FET1 (FIG. 10(a)). When the 24VSL signal switches from low level to high level (FIG. 10(c)), the control section 101 switches the target voltage from DC5V to DC24V (FIG. 10(f)). The control state of the power supply voltage Vout switches from normal control to switching control (FIG. 10(g)), and the power supply voltage Vout starts to rise (FIG. 10(d)). After that, while the voltage between the drain terminal and the source terminal of FET1 is zero, the control section 101 switches the control signal DRV-C output to the FET12 from low level to high level (FIG. 10(b)). As a result, the capacitance of the resonant capacitor is switched from small to large (FIG. 10(e)), and the surge voltage applied between the drain terminal and the source terminal of FET1 is reduced (FIG. 10(a)). When the power supply voltage Vout eventually reaches the target voltage of 24 VDC (FIG. 10(d)), the control state of the power supply voltage Vout returns to normal control (FIG. 10(g)). Here, if the control signal DRV-C to be output to the FET 12 is switched at the earliest timing after the control state of the power supply voltage Vout shifts to switching control, the voltage applied between the drain terminal and the source terminal of the FET 1 can be kept low. .

On the other hand, when the 24VSL signal switches from high level to low level (FIG. 11(c)), the control section 101 switches the target voltage from DC24V to DC5V (FIG. 11(f)). The control state of the power supply voltage Vout switches again to switching control (FIG. 11(g)), and the power supply voltage Vout starts to drop (FIG. 11(d)). When the power supply voltage Vout eventually reaches the target voltage of DC 5V (FIG. 11(d)), the control state of the power supply voltage Vout returns to normal control (FIG. 11(g)). Up to this point, the surge voltage applied between the drain terminal and the source terminal of FET1 continues to be small (FIG. 11(a)). After that, while the voltage between the drain terminal and the source terminal of FET1 is zero, the control section 101 switches the control signal DRV-C output to the FET12 from high level to low level (FIG. 11(b)). As a result, the capacitance of the resonant capacitor changes from large to small (FIG. 11(e)), and the surge voltage applied between the drain terminal and the source terminal of FET1 increases (FIG. 11(a)). Here, by switching the control signal DRV-C output to FET12 after the control state of the power supply voltage Vout returns to normal control, the voltage applied between the drain terminal and the source terminal of FET1 can be kept low.

As described above, when the target voltage is switched from DC5V to DC24V, the capacity of the resonance capacitor is switched from small to large as soon as possible after the control state of the power supply voltage Vout shifts to switching control, and the target voltage is switched from DC24V to DC5V. By switching the capacity of the resonance capacitor from large to small after the control state of the power supply voltage Vout shifts from switching control to normal control, the voltage applied between the drain terminal and the source terminal of FET1 can be minimized. In other words, it becomes possible to use an FET with a low withstand voltage as the FET1.

The switching power supply circuit 200 maintains a stable switching operation with simple control, has high power conversion efficiency from when the output power is small to high, and can reduce the cost of the FET 1 .
As described above, according to this embodiment, it is possible to improve the power efficiency in the active clamp type power supply device.

The switching power supply circuit, which is the power supply device described in Embodiments 1, 2, and 3, can be applied, for example, as a low-voltage power supply for an image forming apparatus, that is, as a power supply for supplying electric power to a driving unit such as a controller (control unit) or a motor. . The configuration of an image forming apparatus to which the power supply devices of Embodiments 1, 2, and 3 are applied will be described below.

[Configuration of Image Forming Apparatus]
A laser beam printer will be described as an example of an image forming apparatus. FIG. 12 shows a schematic configuration of a laser beam printer, which is an example of an electrophotographic printer. The laser beam printer 300 includes a photosensitive drum 311 as an image carrier on which an electrostatic latent image is formed, a charging section 317 (charging means) that uniformly charges the photosensitive drum 311 , and an electrostatic latent image formed on the photosensitive drum 311 . A developing section 312 (developing means) for developing an image with toner is provided. Then, the toner image developed on the photosensitive drum 311 is transferred to a sheet (not shown) as a recording material supplied from a cassette 316 by a transfer unit 318 (transfer means), and the toner image transferred to the sheet is transferred to a fixing device 314 . , and is discharged to the tray 315 . The photosensitive drum 311, charging section 317, developing section 312, and transfer section 318 constitute an image forming section. The laser beam printer 300 also includes the power supply device 500 described in the first, second, and third embodiments. Note that the image forming apparatus to which the power supply device 500 of Embodiments 1, 2, and 3 can be applied is not limited to the one illustrated in FIG. 12, and may be an image forming apparatus including a plurality of image forming units, for example. Furthermore, the image forming apparatus may include a primary transfer section that transfers the toner image on the photosensitive drum 311 to the intermediate transfer belt, and a secondary transfer section that transfers the toner image on the intermediate transfer belt to a sheet.

The laser beam printer 300 includes a controller 320 that controls the image forming operation of the image forming unit and the sheet conveying operation. supply. Further, the power supply device 500 described in the first, second, and third embodiments supplies power to a drive unit such as a motor for rotating the photosensitive drum 311 or driving various rollers for conveying sheets. When the power supply device 500 of the present embodiment is the switching power supply circuit 100 of the first embodiment, the control unit 101 detects the state of the output power supplied to the load based on the FB terminal voltage, and detects the state of intermittent operation or continuous operation. switch to state. In this case, as described in the first embodiment, the control unit 101 switches the capacitance of the resonance capacitor at appropriate timing depending on whether the operating state is the continuous operating state or the intermittent operating state. As a result, the switching power supply circuit 100 can realize high power conversion efficiency from when the output power is small to when the output power is large while maintaining stable switching operation.

Also, the image forming apparatus of this embodiment can operate in a normal operation mode, a standby mode, or a sleep mode. The standby mode is a mode in which the image forming operation can be performed as soon as a print instruction is received while reducing the power consumption compared to the normal operation mode in which the image forming operation is performed. The sleep mode is a mode in which power consumption is further reduced than in the standby mode. When the power supply device 500 is the switching power supply circuit 200 of the second and third embodiments, the controller 320 outputs the 24VSL signal to the switching power supply circuit 200 . In the switching power supply circuit 200, as described in the second and third embodiments, the control unit 101 switches the target voltage to DC24V or DC5V based on the input voltage of the 24SL terminal and the FB terminal voltage, and switches the target voltage to an intermittent operation state or a continuous operation state. Switch to working state. In this case, as described in the second and third embodiments, the control unit 101 switches the capacitance of the resonance capacitor at appropriate timing according to the target voltage. As a result, the switching power supply circuit 200 can realize high power conversion efficiency from when the output power is small to when the output power is large while maintaining stable switching operation with simple control.

As described above, according to this embodiment, it is possible to improve the power efficiency in the active clamp type power supply device.

C11 resonance capacitor C12 resonance capacitor T transformer 1 FET
2 FETs
12 FETs
101 control unit 115 feedback unit

Claims (17)

a transformer having a primary winding and a secondary winding;
a first switching element connected in series with the primary winding of the transformer;
a resonant capacitor unit connected in parallel with the first switching element;
a second switching element connected in parallel to the primary winding of the transformer;
a capacitor connected in series with the second switching element and connected in parallel with the primary winding of the transformer together with the second switching element;
feedback means for outputting information according to an output voltage obtained by rectifying and smoothing the voltage induced in the secondary winding of the transformer;
Based on the information input from the feedback means, a first control signal controls ON or OFF of the first switching element, and a second control signal controls ON or OFF of the second switching element. a control means for controlling;
with
The control means alternately turns on or off the first switching element and the second switching element with a dead time for turning off both the first switching element and the second switching element. A power supply device capable of performing a continuous operation that repeats a period of performing the switching operation and an intermittent operation that alternately repeats a period of performing the switching operation and a period of stopping the switching operation,
The resonance capacitor section has a first resonance capacitor, a second resonance capacitor, and a third switching element connected in series with the second resonance capacitor,
the second resonant capacitor and the third switching element are connected in parallel with the first resonant capacitor;
The control means turns on the third switching element during the continuous operation, turns off the third switching element during the intermittent operation, and turns on the first switching element after transition from the intermittent operation to the continuous operation. is turned on, the third switching element is switched from off to on . 2. The power supply apparatus according to claim 1, wherein said control means performs said continuous operation or said intermittent operation based on said information output from said feedback means. The control means turns off the third switching element after the transition from the continuous operation to the intermittent operation, when the first switching element is in the ON state or in the OFF state. 3. The power supply device according to claim 1, wherein switching is performed. a transformer having a primary winding and a secondary winding;
a first switching element connected in series with the primary winding of the transformer;
a resonant capacitor unit connected in parallel with the first switching element;
a second switching element connected in parallel to the primary winding of the transformer;
a capacitor connected in series with the second switching element and connected in parallel with the primary winding of the transformer together with the second switching element;
feedback means for outputting information according to an output voltage obtained by rectifying and smoothing the voltage induced in the secondary winding of the transformer;
Based on the information input from the feedback means, a first control signal controls ON or OFF of the first switching element, and a second control signal controls ON or OFF of the second switching element. a control means for controlling;
with
The control means alternately turns on or off the first switching element and the second switching element with a dead time for turning off both the first switching element and the second switching element. A power supply device capable of performing a continuous operation that repeats a period of performing the switching operation and an intermittent operation that alternately repeats a period of performing the switching operation and a period of stopping the switching operation,
The resonance capacitor section has a first resonance capacitor, a second resonance capacitor, and a third switching element connected in series with the second resonance capacitor,
the second resonant capacitor and the third switching element are connected in parallel with the first resonant capacitor;
The control means turns on the third switching element during the continuous operation, turns off the third switching element during the intermittent operation, and turns off the first switching element after the continuous operation transitions to the intermittent operation. A power supply device, wherein the third switching element is switched from on to off when the switching element is on or off. 5. The power supply device according to claim 1, wherein said first switching element is a field effect transistor. an image forming means for forming an image on a recording material;
A power supply device according to any one of claims 1 to 5;
An image forming apparatus comprising: a transformer having a primary winding and a secondary winding;
a first switching element connected in series with the primary winding of the transformer;
a resonant capacitor unit connected in parallel with the first switching element;
a second switching element connected in parallel to the primary winding of the transformer;
a capacitor connected in series with the second switching element and connected in parallel with the primary winding of the transformer together with the second switching element;
feedback means for outputting information according to an output voltage obtained by rectifying and smoothing the voltage induced in the secondary winding of the transformer;
Based on the information input from the feedback means, a first control signal controls ON or OFF of the first switching element, and a second control signal controls ON or OFF of the second switching element. a control means for controlling;
instruction means for instructing switching of the target voltage of the output voltage to a first voltage or a second voltage higher than the first voltage in response to a signal from the outside;
with
The control means alternately turns on or off the first switching element and the second switching element with a dead time for turning off both the first switching element and the second switching element. a continuous operation that repeats a period of performing the switching operation, and an intermittent operation that alternately repeats a period of performing the switching operation and a period of stopping the switching operation,
The control means is a power supply device capable of switching the target voltage according to an instruction from the instruction means,
The resonance capacitor section has a first resonance capacitor, a second resonance capacitor, and a third switching element connected in series with the second resonance capacitor,
the second resonant capacitor and the third switching element are connected in parallel with the first resonant capacitor;
The control means turns on the third switching element when the target voltage is the second voltage, and turns off the third switching element when the target voltage is the first voltage. A power supply device characterized by: The control means performs the continuous operation when the target voltage is the second voltage, and based on the information output from the feedback means when the target voltage is the first voltage. 8. The power supply device according to claim 7 , wherein said continuous operation or said intermittent operation is performed. the feedback means has a plurality of voltage dividing resistors for dividing the output voltage;
9. The power supply device according to claim 7 , wherein the resistance value of said voltage dividing resistor is switched according to said target voltage. After switching the target voltage from the first voltage to the second voltage, the control means switches the third switching element from off when the first switching element is on. 10. A power supply device according to any one of claims 7 to 9 , characterized in that it is switched on. The control means controls the third switching after the instruction means switches the target voltage from the first voltage to the second voltage until the output voltage reaches the second voltage. 11. The power supply of claim 10 , wherein the device switches from off to on. The control means turns off the third switching element from on when the first switching element is on after switching the target voltage from the second voltage to the first voltage. 12. The power supply device according to any one of claims 7 to 11 , wherein the power supply device switches to . The control means controls the third switching after the instruction means switches the target voltage from the second voltage to the first voltage until the output voltage reaches the first voltage. 13. The power supply according to claim 12 , which turns on the element. 14. The power supply device according to any one of claims 7 to 13 , wherein said first switching element is a field effect transistor. an image forming means for forming an image on a recording material;
A power supply device according to any one of claims 7 to 14 ;
An image forming apparatus comprising: A control unit that controls the power supply device to output the first voltage or the second voltage,
The control means is
When the instruction means receives a signal from the outside from the control unit and instructs to output the second voltage, controlling to perform the continuous operation,
When the instruction means receives the signal from the outside from the control unit and instructs to output the first voltage, the 16. The image forming apparatus according to claim 15 , wherein control is performed so as to perform continuous operation or said intermittent operation. 17. The image forming apparatus according to claim 16 , wherein the control means determines the state of the load to which power is supplied by the power supply device based on the information input from the feedback means.

Images